[Pixman] [PATCH] MIPS: DSPr2: Basic infrastructure for MIPS architecture
siarhei.siamashka at gmail.com
Fri Feb 17 08:18:11 PST 2012
On Fri, Feb 17, 2012 at 5:38 PM, Lukic, Nemanja <nlukic at mips.com> wrote:
> Hi Siarhei,
> You are right, "cpu model" line from /proc/cpuinfo for MIPS doesn't provide nearly enough information.
> Main issue with run-time detection of the version of the DSP extensions and (as you pointed out) cache line size, is that this information is stored in status registers, which can't be read from user space (for cache line size, this is CP0 Register 16, Select 1, bits 12:10).
> And this information is not stored in /proc/cpuinfo and there is no system call to determine them either. So, at this point, we are not able to run time distinguish between DSPr1 and DSPr2, and retrieve cache line size.
Sorry for not being clear enough earlier.
What I mean is that according MIPS website  and pdf documents, 74K
always has 32 bytes cache line. Also if it has DSP ASE support (is it
optional or mandatory for 74K?), then it is likely DSPr2 and not
DSPr1. So if we find "MIPS 74K" substring in /proc/cpuinfo, then we
can be reasonably sure that your assembly optimizations will work
correctly on it. I guess it is possible to check all the MIPS cores
known by "arch/mips/kernel/cpu-probe.c" , make a list of the ones
which do support DSPr2 instructions and use this list in pixman
runtime detection code. Cache line sizes can be stored in this list
too. Yes, this is ugly, and can be used only a stop gap measure until
the kernel gets updated to provide the necessary information.
BTW, the information reported by the kernel used to be not perfect for
ARM either, see  and . But now this is fixed. The MIPS case is
better, because we don't even have to make any wrong assumptions if I
understand it correctly. Just the code gets ugly. But on a positive
side, showing this ugly code to the kernel people could probably
convince them that they are really lacking some necessary information
in /proc/cpuinfo ;)
Runtime detection may be useful because I read on the news that some
MIPS based Android tablets are going to use Ingenic JZ4770 SoC .
Yay for the "Ingenic’s own extension of SIMD instruction set". Looks
like there is no agreement between MIPS vendors about what kind of
SIMD ISA is preferable and this is going to be a big mess.
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