[Pixman] [PATCH 00/10] Cleanups to CPU detection

Søren Sandmann Pedersen sandmann at cs.au.dk
Fri Jun 29 13:44:45 PDT 2012


    in the branch "cpudetectfiles".


The following patches contains some cleanups to the CPU detection in
general, and some improvements to the x86 specific parts in particular.

I was looking at making use of some of the newer x86 SIMD instruction
sets and realized that (a) we don't ever call cpuid on x86-64, we just
assume that MMX and SSE2 are present, and (b) pixman-cpu.c is a royal

The following patches split pixman-cpu.c into four different files:
pixman-arm.c, pixman-mips.c, pixman-ppc.c, and pixman-x86.c. All the
files are still compiled on all arhicitectures, but they have #ifdefs
in them that make them no-ops on the ones that they are not specific
to. The remaining bits of pixman-cpu.c are moved into

There are also some cleanups to the logic for all architectures. In
particular, all the have_<feature>() functions are gone and replaced
with a single function that detects all the features that the CPU
offers. This function is implemented by each #ifdef variation, and
then this is called from shared code.

The changes to x86 are the most involved. There is now a
pixman_cpuid() function that uses inline assembly on GCC and the
cpuid__ intrinsic on MSVC. The assembly is written such that it will
work on both 32 and 64 bit; the main change required was the save %ebx
in %esi instead of on the stack.

There is also a have_cpuid() function that detects the presence of
cpuid. On MSVC, this simply returns TRUE, so the an MSVC-compiled
pixman will now not work on old 486s. I am very tempted to remove this
on GCC as well and just require cpuid to be present for pixman work.

These two functions together make it possible to write the CPU
detection code in plain C, rather than the #ifdef ridden mess of
assembly it used to be.

I have tested the patches on ppc64, x86-64, x86-32, and on an ARM
Cortex A8 running Linux, but more testing would definitely be
appreciated. In particular if you use MSVC, MIPS, XO-1, or ARM on


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