[Pixman] Basic infrastructure for MIPS32r2 and DSPr1 optimizations.

[Nemanja Lukic]

Some of the optimizations introduced in previous DSPr2 commits were not DSPr2 specific. Some of the fast-paths didn't used DSPr2 instructions at all, and rather utilized more generic MIPS32r2 instruction set or previous version of DSP instruction set (DSPr1) for optimizations.
Since Pixman's run-time CPU detection only added DSPr2 fast-paths on 74K MIPS cores, these optimizations couldn't be used on cores that don't support DSPr2, but do support MIPS32r2 or DSPr1 instructions (these are almost all newer MIPS CPU cores like 4K, 24K, 34K, 1004K, etc).
These patches extract those MIPS32r2 and DSPr1 specific optimizations into new fast-path sets, with appropriate build and run time infrastructure. With these pathes no new optimizations are introduced, only refactoring of previous DSPr2 optimizations into MIPS32r2-specific and DSPr1-specific.
Future commits will add more MIPS32r2 and DSPr1 specific fast paths.
For testing, lowlevel-blt benchmark is used and two different MIPS cores:
 - 24Kc - for MIPS32r2
 - 1004Kc - for DSPr1

This patch set should address all previous code review remarks.

Any comments are available.