[Pixman] [PATCH v2] pixman-general: Tighten up calculation of temporary buffer sizes

Pekka Paalanen ppaalanen at gmail.com
Fri Sep 25 04:21:31 PDT 2015

On Thu, 24 Sep 2015 23:12:42 +0200
soren.sandmann at gmail.com (Søren Sandmann) wrote:

> Pekka Paalanen <ppaalanen at gmail.com> writes:
> >> As a discussion point, wouldn't it be better for the ALIGN macro to
> >> assume 32-byte cache lines? Both 16-byte and 32-byte cachelines are
> >> currently in common use, but by aligning the buffers to 32-byte addresses
> >> we would simultaneously achieve 16-byte alignment.
> It's not the size of cache lines that is interesting; it's the width of
> SIMD instructions.
> > I think Ben's explanation as seen in
> > https://patchwork.freedesktop.org/patch/49898/
> > covers all Søren's concerns (it quotes everything Søren said about the
> > patch), and I see no reason to reject this.
> Well, the concern that SIMD destination fetchers (for example a 565
> destination iterator) can no longer do a full SIMD write to the buffer
> is still there. It's not just combiners that write to the destination
> buffer.
> But whatever, it's not really worth arguing about. Let's just push
> this. We can fix it if SIMD destination fetchers ever actually happen.

Cool. Pushed:
   8b49d4b..23525b4  master -> master

I wasn't sure if you wanted me to interpret that as an acked-by from
you, so I didn't.

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