[pulseaudio-discuss] Issue with multiple hdmi codecs in radeonhd, hacked to work

[Takashi Iwai]

At Mon, 09 Dec 2013 08:01:17 +0200,
Anssi Hannula wrote:
> 
> 09.12.2013 06:50, Raymond Yau kirjoitti:
> > 2013/12/9 John Ettedgui <john.ettedgui at gmail.com
> > <mailto:john.ettedgui at gmail.com>>
> > 
> > 
> >     I am using the gitcompile script to configure, compile... 
> >     There is no configure by default, I was able to autogen it, but then
> >     I had issues while building so I reverted back to gitcompile
> > 
> > [    4.841881] ALSA hda_intel.c:3170 0000:01:00.1: Handle VGA-switcheroo
> > audio client
> > [    4.841885] ALSA hda_intel.c:3364 0000:01:00.1: Using LPIB position fix
> > [    4.841886] ALSA hda_intel.c:3510 0000:01:00.1: Force to non-snoop mode
> > [    4.841920] snd_hda_intel 0000:01:00.1: irq 47 for MSI/MSI-X
> > [    4.841940] ALSA hda_intel.c:3635 0000:01:00.1: chipset global
> > capabilities = 0x0
> > 
> > seem the max number of playback streams is hardcoded in the driver
> 
> Indeed it is hardcoded to 1 (previous ATI/AMD codecs had a single HDMI
> pin). This is almost certainly not true anymore.
> 
> I wonder what the limit is now, maybe the amount of HDMI pins so that
> there can be 6 or 7 independent streams? Alex?

It's surprising that even the recent AMD chips don't set GCAPS
properly...

We can set it max 8 or 16 for AZX_DRIVER_ATIHDMI* cases.  You'd need a
bit more spaces for BDL and azx_dev structs, but it's small enough and
negligible.

An untested patch is attached below.


thanks,

Takashi

-- 8< --
From: Takashi Iwai <tiwai at suse.de>
Subject: [PATCH] ALSA: hda - Increment default stream numbers for AMD HDMI
 controllers

It turned out that some AMD HDMI controllers still don't provide
proper values in GCAP register (all zero), and the driver assigns only
one stream in that case, although the connected codec chip supports
more than one stream.

In this patch, the default max number of streams for AMD HDMI
controllers is increased to 8, which should suffice for most use
cases.  This is a default value that takes effect only when no GCAP
register is given.  The overhead by this increase is only azx_dev
struct and BDL allocations, so it's negligible.

Signed-off-by: Takashi Iwai <tiwai at suse.de>
---
 sound/pci/hda/hda_intel.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index af86c71f27bf..08d3a634bf42 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -297,9 +297,9 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define ULI_NUM_CAPTURE		5
 #define ULI_NUM_PLAYBACK	6
 
-/* ATI HDMI has 1 playback and 0 capture */
+/* ATI HDMI may have up to 8 playbacks and 0 capture */
 #define ATIHDMI_NUM_CAPTURE	0
-#define ATIHDMI_NUM_PLAYBACK	1
+#define ATIHDMI_NUM_PLAYBACK	8
 
 /* TERA has 4 playback and 3 capture */
 #define TERA_NUM_CAPTURE	3
-- 
1.8.5