[Spice-commits] 2 commits - hw/mips_malta.c target-mips/translate.c

[Gerd Hoffmann]

 hw/mips_malta.c         |    3 ++-
 target-mips/translate.c |    2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

New commits:
commit 6801038bc52d61f81ac8a25fbe392f1bad982887
Author: 陳韋任 (Wei-Ren Chen) <chenwj at iis.sinica.edu.tw>
Date:   Wed Nov 14 10:49:55 2012 +0800

    target-mips: fix wrong microMIPS opcode encoding
    
    While reading microMIPS decoding, I found a possible wrong opcode
    encoding. According to [1] page 166, the bits 13..12 for MULTU is
    0x01 rather than 0x00. Please review, thanks.
    
    [1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
        Application-Specific Extension to the microMIPS32 Architecture
    
    Signed-off-by: Chen Wei-Ren <chenwj at iis.sinica.edu.tw>
    Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>

diff --git a/target-mips/translate.c b/target-mips/translate.c
index f6fc0c2..01b48fa 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -10385,7 +10385,7 @@ enum {
 
     /* bits 13..12 for 0x32 */
     MULT_ACC = 0x0,
-    MULTU_ACC = 0x0,
+    MULTU_ACC = 0x1,
 
     /* bits 15..12 for 0x2c */
     SEB = 0x2,
commit 68d001928b151a0c50f367c0bdca645b3d5e9ed3
Author: Aurelien Jarno <aurelien at aurel32.net>
Date:   Wed Nov 14 15:04:42 2012 +0100

    mips/malta: fix CBUS UART interrupt pin
    
    According to the MIPS Malta Developement Platform User's Manual, the
    i8259 interrupt controller is supposed to be connected to the hardware
    IRQ0, and the CBUS UART to the hardware interrupt 2.
    
    In QEMU they are both connected to hardware interrupt 0, the CBUS UART
    interrupt being wrong. This patch fixes that. It should be noted that
    the irq array in QEMU includes the software interrupts, hence
    env->irq[2] is the first hardware interrupt.
    
    Cc: Ralf Baechle <ralf at linux-mips.org>
    Reviewed-by: Eric Johnson <ericj at mips.com>
    Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 0571d58..4d2464a 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args)
     be = 0;
 #endif
     /* FPGA */
-    malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]);
+    /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
+    malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]);
 
     /* Load firmware in flash / BIOS. */
     dinfo = drive_get(IF_PFLASH, 0, fl_idx);