[Spice-commits] 12 commits - target-mips/op_helper.c tcg/arm tcg/ia64
Gerd Hoffmann
kraxel at kemper.freedesktop.org
Wed Oct 17 01:26:49 PDT 2012
target-mips/op_helper.c | 63 +++++++++------
tcg/arm/tcg-target.c | 56 +++++++------
tcg/arm/tcg-target.h | 2
tcg/ia64/tcg-target.c | 194 ++++++++++++++++++++++++++++++++++++------------
tcg/ia64/tcg-target.h | 11 +-
5 files changed, 225 insertions(+), 101 deletions(-)
New commits:
commit 6f4d6b09088ee161ff4be0e4db4e4c0962c79070
Author: Andreas Färber <afaerber at suse.de>
Date: Fri Oct 12 00:56:37 2012 +0200
target-mips: Pass MIPSCPU to mips_vpe_sleep()
Needed for moving halted field to CPUState.
Signed-off-by: Andreas Färber <afaerber at suse.de>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 5710dd0..05b7730 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -731,8 +731,10 @@ static inline void mips_vpe_wake(CPUMIPSState *c)
cpu_interrupt(c, CPU_INTERRUPT_WAKE);
}
-static inline void mips_vpe_sleep(CPUMIPSState *c)
+static inline void mips_vpe_sleep(MIPSCPU *cpu)
{
+ CPUMIPSState *c = &cpu->env;
+
/* The VPE was shut off, really go to bed.
Reset any old _WAKE requests. */
c->halted = 1;
@@ -755,7 +757,7 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
/* FIXME: TC reschedule. */
if (!mips_vpe_active(c)) {
- mips_vpe_sleep(c);
+ mips_vpe_sleep(cpu);
}
}
@@ -1889,8 +1891,10 @@ target_ulong helper_dvpe(CPUMIPSState *env)
do {
/* Turn off all VPEs except the one executing the dvpe. */
if (other_cpu_env != env) {
+ MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
+
other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
- mips_vpe_sleep(other_cpu_env);
+ mips_vpe_sleep(other_cpu);
}
other_cpu_env = other_cpu_env->next_cpu;
} while (other_cpu_env);
commit c6679e9038027e28b0360039d2bb7d3aa55b934e
Author: Andreas Färber <afaerber at suse.de>
Date: Fri Oct 12 00:56:36 2012 +0200
target-mips: Pass MIPSCPU to mips_tc_sleep()
Needed for changing mips_vpe_sleep() argument type to MIPSCPU.
Signed-off-by: Andreas Färber <afaerber at suse.de>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 9770741..5710dd0 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -749,8 +749,10 @@ static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
}
}
-static inline void mips_tc_sleep(CPUMIPSState *c, int tc)
+static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
{
+ CPUMIPSState *c = &cpu->env;
+
/* FIXME: TC reschedule. */
if (!mips_vpe_active(c)) {
mips_vpe_sleep(c);
@@ -1352,7 +1354,7 @@ void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
// TODO: Halt TC / Restart (if allocated+active) TC.
if (env->active_tc.CP0_TCHalt & 1) {
- mips_tc_sleep(env, env->current_tc);
+ mips_tc_sleep(cpu, env->current_tc);
} else {
mips_tc_wake(cpu, env->current_tc);
}
@@ -1372,7 +1374,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
other->tcs[other_tc].CP0_TCHalt = arg1;
if (arg1 & 1) {
- mips_tc_sleep(other, other_tc);
+ mips_tc_sleep(other_cpu, other_tc);
} else {
mips_tc_wake(other_cpu, other_tc);
}
commit b35d77d73c0fc0b60c9937471a17d41c6fb32947
Author: Andreas Färber <afaerber at suse.de>
Date: Fri Oct 12 00:56:35 2012 +0200
target-mips: Pass MIPSCPU to mips_vpe_is_wfi()
Needed for moving halted field to CPUState.
The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState.
Also change return type to bool while at it.
Signed-off-by: Andreas Färber <afaerber at suse.de>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index e721a4d..9770741 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -714,11 +714,13 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
#ifndef CONFIG_USER_ONLY
/* SMP helpers. */
-static int mips_vpe_is_wfi(CPUMIPSState *c)
+static bool mips_vpe_is_wfi(MIPSCPU *c)
{
+ CPUMIPSState *env = &c->env;
+
/* If the VPE is halted but otherwise active, it means it's waiting for
an interrupt. */
- return c->halted && mips_vpe_active(c);
+ return env->halted && mips_vpe_active(env);
}
static inline void mips_vpe_wake(CPUMIPSState *c)
@@ -742,7 +744,7 @@ static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
CPUMIPSState *c = &cpu->env;
/* FIXME: TC reschedule. */
- if (mips_vpe_active(c) && !mips_vpe_is_wfi(c)) {
+ if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
mips_vpe_wake(c);
}
}
@@ -1899,9 +1901,11 @@ target_ulong helper_evpe(CPUMIPSState *env)
target_ulong prev = env->mvp->CP0_MVPControl;
do {
+ MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
+
if (other_cpu_env != env
/* If the VPE is WFI, don't disturb its sleep. */
- && !mips_vpe_is_wfi(other_cpu_env)) {
+ && !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
mips_vpe_wake(other_cpu_env); /* And wake it up. */
commit 135dd63a190a084fa5e9f1b4695397016bf0ce5a
Author: Andreas Färber <afaerber at suse.de>
Date: Fri Oct 12 00:56:34 2012 +0200
target-mips: Pass MIPSCPU to mips_tc_wake()
Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU.
Signed-off-by: Andreas Färber <afaerber at suse.de>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 1051c44..e721a4d 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -737,8 +737,10 @@ static inline void mips_vpe_sleep(CPUMIPSState *c)
cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
}
-static inline void mips_tc_wake(CPUMIPSState *c, int tc)
+static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
{
+ CPUMIPSState *c = &cpu->env;
+
/* FIXME: TC reschedule. */
if (mips_vpe_active(c) && !mips_vpe_is_wfi(c)) {
mips_vpe_wake(c);
@@ -1342,13 +1344,15 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
+
env->active_tc.CP0_TCHalt = arg1 & 0x1;
// TODO: Halt TC / Restart (if allocated+active) TC.
if (env->active_tc.CP0_TCHalt & 1) {
mips_tc_sleep(env, env->current_tc);
} else {
- mips_tc_wake(env, env->current_tc);
+ mips_tc_wake(cpu, env->current_tc);
}
}
@@ -1356,6 +1360,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
+ MIPSCPU *other_cpu = mips_env_get_cpu(other);
// TODO: Halt TC / Restart (if allocated+active) TC.
@@ -1367,7 +1372,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
if (arg1 & 1) {
mips_tc_sleep(other, other_tc);
} else {
- mips_tc_wake(other, other_tc);
+ mips_tc_wake(other_cpu, other_tc);
}
}
commit 81bad50ec40311797c38a7691844c7d2df9b3823
Author: Andreas Färber <afaerber at suse.de>
Date: Fri Oct 12 00:56:33 2012 +0200
target-mips: Clean up other_cpu in helper_{d,e}vpe()
Free the variable name "other_cpu" for later use for MIPSCPU.
Fix off-by-one indentation while at it.
Signed-off-by: Andreas Färber <afaerber at suse.de>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ce5ddaf..1051c44 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1874,35 +1874,35 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(CPUMIPSState *env)
{
- CPUMIPSState *other_cpu = first_cpu;
+ CPUMIPSState *other_cpu_env = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
do {
/* Turn off all VPEs except the one executing the dvpe. */
- if (other_cpu != env) {
- other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
- mips_vpe_sleep(other_cpu);
+ if (other_cpu_env != env) {
+ other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ mips_vpe_sleep(other_cpu_env);
}
- other_cpu = other_cpu->next_cpu;
- } while (other_cpu);
+ other_cpu_env = other_cpu_env->next_cpu;
+ } while (other_cpu_env);
return prev;
}
target_ulong helper_evpe(CPUMIPSState *env)
{
- CPUMIPSState *other_cpu = first_cpu;
+ CPUMIPSState *other_cpu_env = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
do {
- if (other_cpu != env
- /* If the VPE is WFI, don't disturb its sleep. */
- && !mips_vpe_is_wfi(other_cpu)) {
+ if (other_cpu_env != env
+ /* If the VPE is WFI, don't disturb its sleep. */
+ && !mips_vpe_is_wfi(other_cpu_env)) {
/* Enable the VPE. */
- other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- mips_vpe_wake(other_cpu); /* And wake it up. */
+ other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ mips_vpe_wake(other_cpu_env); /* And wake it up. */
}
- other_cpu = other_cpu->next_cpu;
- } while (other_cpu);
+ other_cpu_env = other_cpu_env->next_cpu;
+ } while (other_cpu_env);
return prev;
}
#endif /* !CONFIG_USER_ONLY */
commit c7d4475a701c61f964a593d6fe81a8ea7a33add7
Author: Richard Henderson <rth at twiddle.net>
Date: Wed Oct 10 16:01:35 2012 -0700
tcg-ia64: Implement deposit
Note that in the general reg=reg,reg case we're restricted
to 16-bit insertions. This makes it easy to allow "any"
constant as input, as post-truncation it will fit into the
constant load insn for which we have room in the bundle.
Signed-off-by: Richard Henderson <rth at twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 6f018f4..06570be 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -231,6 +231,7 @@ enum {
OPC_CMP4_LTU_A6 = 0x1a400000000ull,
OPC_CMP4_EQ_A6 = 0x1c400000000ull,
OPC_DEP_I14 = 0x0ae00000000ull,
+ OPC_DEP_I15 = 0x08000000000ull,
OPC_DEP_Z_I12 = 0x0a600000000ull,
OPC_EXTR_I11 = 0x0a400002000ull,
OPC_EXTR_U_I11 = 0x0a400000000ull,
@@ -514,6 +515,18 @@ static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
| (qp & 0x3f);
}
+static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
+ int r3, uint64_t pos, uint64_t len)
+{
+ return opc
+ | ((pos & 0x3f) << 31)
+ | ((len & 0x0f) << 27)
+ | ((r3 & 0x7f) << 20)
+ | ((r2 & 0x7f) << 13)
+ | ((r1 & 0x7f) << 6)
+ | (qp & 0x3f);
+}
+
static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
{
return opc
@@ -1325,6 +1338,37 @@ static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
}
+static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
+ TCGArg a2, int const_a2, int pos, int len)
+{
+ uint64_t i1 = 0, i2 = 0;
+ int cpos = 63 - pos, lm1 = len - 1;
+
+ if (const_a2) {
+ /* Truncate the value of a constant a2 to the width of the field. */
+ int mask = (1u << len) - 1;
+ a2 &= mask;
+
+ if (a2 == 0 || a2 == mask) {
+ /* 1-bit signed constant inserted into register. */
+ i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
+ } else {
+ /* Otherwise, load any constant into a temporary. Do this into
+ the first I slot to help out with cross-unit delays. */
+ i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
+ TCG_REG_R2, a2, TCG_REG_R0);
+ a2 = TCG_REG_R2;
+ }
+ }
+ if (i2 == 0) {
+ i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
+ }
+ tcg_out_bundle(s, (i1 ? mII : miI),
+ tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
+ i1 ? i1 : tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
+ i2);
+}
+
static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
TCGArg arg2, int cmp4)
{
@@ -2130,6 +2174,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_bswap64(s, args[0], args[1]);
break;
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
+ args[3], args[4]);
+ break;
+
case INDEX_op_brcond_i32:
tcg_out_brcond(s, args[2], args[0], const_args[0],
args[1], const_args[1], args[3], 1);
@@ -2294,6 +2344,9 @@ static const TCGTargetOpDef ia64_op_defs[] = {
{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
{ INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
+ { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
+ { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
+
{ INDEX_op_qemu_ld8u, { "r", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "r" } },
{ INDEX_op_qemu_ld16u, { "r", "r" } },
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 5e7d970..4255ca5 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -133,8 +133,11 @@ typedef enum {
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_movcond_i64 1
-#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_deposit_i64 0
+#define TCG_TARGET_HAS_deposit_i32 1
+#define TCG_TARGET_HAS_deposit_i64 1
+
+#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
+#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */
commit 63975ea7dfb3ec258433c782c2455bf64fab5e49
Author: Aurelien Jarno <aurelien at aurel32.net>
Date: Tue Oct 9 21:53:55 2012 +0200
tcg/ia64: slightly optimize TLB access code
It is possible to slightly optimize the TLB access code, by replacing
the movi + and instructions by a deposit instruction.
Reviewed-by: Richard Henderson <rth at twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 16edc1b..6f018f4 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -230,6 +230,7 @@ enum {
OPC_CMP4_LT_A6 = 0x18400000000ull,
OPC_CMP4_LTU_A6 = 0x1a400000000ull,
OPC_CMP4_EQ_A6 = 0x1c400000000ull,
+ OPC_DEP_I14 = 0x0ae00000000ull,
OPC_DEP_Z_I12 = 0x0a600000000ull,
OPC_EXTR_I11 = 0x0a400002000ull,
OPC_EXTR_U_I11 = 0x0a400000000ull,
@@ -501,6 +502,18 @@ static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
| (qp & 0x3f);
}
+static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
+ int r3, uint64_t pos, uint64_t len)
+{
+ return opc
+ | ((imm & 0x01) << 36)
+ | ((len & 0x3f) << 27)
+ | ((r3 & 0x7f) << 20)
+ | ((pos & 0x3f) << 14)
+ | ((r1 & 0x7f) << 6)
+ | (qp & 0x3f);
+}
+
static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
{
return opc
@@ -1444,9 +1457,7 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
uint64_t offset_addend)
{
tcg_out_bundle(s, mII,
- tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
- TARGET_PAGE_MASK | ((1 << s_bits) - 1),
- TCG_REG_R0),
+ tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
@@ -1468,8 +1479,9 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
(TARGET_LONG_BITS == 32
? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
TCG_REG_R2, offset_addend - offset_rw),
- tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
- TCG_REG_R3, TCG_REG_R57),
+ tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
+ TCG_REG_R57, 63 - s_bits,
+ TARGET_PAGE_BITS - s_bits - 1),
tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
}
commit 2174d1e1ff3522f6f64260bad460185b7ca5bd26
Author: Aurelien Jarno <aurelien at aurel32.net>
Date: Tue Oct 9 21:53:55 2012 +0200
tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops
Remove suboptimal register shifting in qemu_ld/st ops, introduced at the
CONFIG_TCG_PASS_AREG0 time.
As mem_idx is now loaded in register R58/R59 for the slow path, we have
to make sure to do it last, to not add additional register constraints.
Reviewed-by: Richard Henderson <rth at twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index d4d350f..16edc1b 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1438,7 +1438,7 @@ static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
/* Load and compare a TLB entry, and return the result in (p6, p7).
R2 is loaded with the address of the addend TLB entry.
- R56 is loaded with the address, zero extented on 32-bit targets. */
+ R57 is loaded with the address, zero extented on 32-bit targets. */
static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
int s_bits, uint64_t offset_rw,
uint64_t offset_addend)
@@ -1456,9 +1456,9 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
offset_rw, TCG_REG_R2),
#if TARGET_LONG_BITS == 32
- tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R56, addr_reg),
+ tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
#else
- tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R56,
+ tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
0, addr_reg),
#endif
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
@@ -1466,12 +1466,12 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
tcg_out_bundle(s, mII,
tcg_opc_m3 (TCG_REG_P0,
(TARGET_LONG_BITS == 32
- ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R57,
+ ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
TCG_REG_R2, offset_addend - offset_rw),
tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
- TCG_REG_R3, TCG_REG_R56),
+ TCG_REG_R3, TCG_REG_R57),
tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
- TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
+ TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
}
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
@@ -1508,8 +1508,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
/* P6 is the fast path, and P7 the slow path */
tcg_out_bundle(s, mLX,
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R57,
- mem_index, TCG_REG_R0),
+ tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
+ TCG_REG_R56, 0, TCG_AREG0),
tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
(tcg_target_long) qemu_ld_helpers[s_bits]));
@@ -1517,7 +1517,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
TCG_REG_R2, 8),
tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
- TCG_REG_R3, TCG_REG_R56),
+ TCG_REG_R3, TCG_REG_R57),
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
TCG_REG_R3, 0));
if (bswap && s_bits == 1) {
@@ -1541,23 +1541,17 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
}
- /* XXX/FIXME: suboptimal */
- tcg_out_bundle(s, mII,
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
- mem_index, TCG_REG_R0),
- tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
- TCG_REG_R57, 0, TCG_REG_R56),
- tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
- TCG_REG_R56, 0, TCG_AREG0));
if (!bswap || s_bits == 0) {
tcg_out_bundle(s, miB,
- tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
+ tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
+ mem_index, TCG_REG_R0),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
TCG_REG_B0, TCG_REG_B6));
} else {
tcg_out_bundle(s, miB,
- tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
+ tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
+ mem_index, TCG_REG_R0),
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R8, TCG_REG_R8, 0xb),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
@@ -1609,8 +1603,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
/* P6 is the fast path, and P7 the slow path */
tcg_out_bundle(s, mLX,
- tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R57,
- 0, data_reg),
+ tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
+ TCG_REG_R56, 0, TCG_AREG0),
tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
(tcg_target_long) qemu_st_helpers[opc]));
@@ -1618,31 +1612,42 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
TCG_REG_R2, 8),
tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
- TCG_REG_R3, TCG_REG_R56),
+ TCG_REG_R3, TCG_REG_R57),
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
TCG_REG_R3, 0));
if (!bswap || opc == 0) {
- tcg_out_bundle(s, mII,
+ tcg_out_bundle(s, mii,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2),
- tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
+ tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
+ 0, data_reg),
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
} else if (opc == 1) {
- tcg_out_bundle(s, mII,
+ tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2),
+ tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
- TCG_REG_R2, data_reg, 15, 15),
+ TCG_REG_R2, data_reg, 15, 15));
+ tcg_out_bundle(s, miI,
+ tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
+ 0, data_reg),
+ tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R2, TCG_REG_R2, 0xb));
data_reg = TCG_REG_R2;
} else if (opc == 2) {
- tcg_out_bundle(s, mII,
+ tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2),
+ tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
- TCG_REG_R2, data_reg, 31, 31),
+ TCG_REG_R2, data_reg, 31, 31));
+ tcg_out_bundle(s, miI,
+ tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
+ 0, data_reg),
+ tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R2, TCG_REG_R2, 0xb));
data_reg = TCG_REG_R2;
@@ -1650,25 +1655,18 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_out_bundle(s, miI,
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
TCG_REG_R1, TCG_REG_R2),
- tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
+ tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
+ 0, data_reg),
tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
TCG_REG_R2, data_reg, 0xb));
data_reg = TCG_REG_R2;
}
- /* XXX/FIXME: suboptimal */
- tcg_out_bundle(s, mII,
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
- mem_index, TCG_REG_R0),
- tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
- TCG_REG_R58, 0, TCG_REG_R57),
- tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
- TCG_REG_R57, 0, TCG_REG_R56));
tcg_out_bundle(s, miB,
tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
data_reg, TCG_REG_R3),
- tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
- TCG_REG_R56, 0, TCG_AREG0),
+ tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
+ mem_index, TCG_REG_R0),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
TCG_REG_B0, TCG_REG_B6));
}
commit b90cf716928d7934f4c1392f9097247a84b295d2
Author: Aurelien Jarno <aurelien at aurel32.net>
Date: Tue Oct 9 21:53:55 2012 +0200
tcg/ia64: implement movcond_i32/64
Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.
Reviewed-by: Richard Henderson <rth at twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 4cba344..d4d350f 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1404,6 +1404,34 @@ static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
}
+static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
+ TCGArg c1, TCGArg c2,
+ TCGArg v1, int const_v1,
+ TCGArg v2, int const_v2, int cmp4)
+{
+ uint64_t opc1, opc2;
+
+ if (const_v1) {
+ opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
+ } else if (ret == v1) {
+ opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
+ } else {
+ opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
+ }
+ if (const_v2) {
+ opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
+ } else if (ret == v2) {
+ opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
+ } else {
+ opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
+ }
+
+ tcg_out_bundle(s, MmI,
+ tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
+ opc1,
+ opc2);
+}
+
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
@@ -2106,6 +2134,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
break;
+ case INDEX_op_movcond_i32:
+ tcg_out_movcond(s, args[5], args[0], args[1], args[2],
+ args[3], const_args[3], args[4], const_args[4], 1);
+ break;
+ case INDEX_op_movcond_i64:
+ tcg_out_movcond(s, args[5], args[0], args[1], args[2],
+ args[3], const_args[3], args[4], const_args[4], 0);
+ break;
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
@@ -2196,6 +2232,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
{ INDEX_op_brcond_i32, { "rI", "rI" } },
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
+ { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
{ INDEX_op_mov_i64, { "r", "r" } },
{ INDEX_op_movi_i64, { "r" } },
@@ -2245,6 +2282,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
{ INDEX_op_brcond_i64, { "rI", "rI" } },
{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
{ INDEX_op_qemu_ld8u, { "r", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "r" } },
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 368aee4..5e7d970 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -131,10 +131,10 @@ typedef enum {
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_rot_i64 1
+#define TCG_TARGET_HAS_movcond_i32 1
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_movcond_i32 0
-#define TCG_TARGET_HAS_movcond_i64 0
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */
commit da897bf5ae2d0276dcabe941ba3a402aa718b740
Author: Blue Swirl <blauwirbel at gmail.com>
Date: Tue Oct 9 21:53:55 2012 +0200
tcg/ia64: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.
Signed-off-by: Blue Swirl <blauwirbel at gmail.com>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 705712f..4cba344 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -2269,9 +2269,12 @@ static void tcg_target_qemu_prologue(TCGContext *s)
int frame_size;
/* reserve some stack space */
- frame_size = TCG_STATIC_CALL_ARGS_SIZE;
+ frame_size = TCG_STATIC_CALL_ARGS_SIZE +
+ CPU_TEMP_BUF_NLONGS * sizeof(long);
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
~(TCG_TARGET_STACK_ALIGN - 1);
+ tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
/* First emit adhoc function descriptor */
*(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
@@ -2378,6 +2381,4 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
tcg_add_target_add_op_defs(ia64_op_defs);
- tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
- CPU_TEMP_BUF_NLONGS * sizeof(long));
}
commit 4a1d241e3cc0a0cacb5de9084a4edb543d529d51
Author: Peter Maydell <peter.maydell at linaro.org>
Date: Wed Sep 26 19:48:55 2012 +0100
tcg/arm: Implement movcond_i32
Implement movcond_i32 for ARM, as the sequence
mov dst, v2 (implicitly done by the tcg common code)
cmp c1, c2
movCC dst, v1
Signed-off-by: Peter Maydell <peter.maydell at linaro.org>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 3596bce..e790bf0 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1572,6 +1572,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_movi_i32:
tcg_out_movi32(s, COND_AL, args[0], args[1]);
break;
+ case INDEX_op_movcond_i32:
+ /* Constraints mean that v2 is always in the same register as dest,
+ * so we only need to do "if condition passed, move v1 to dest".
+ */
+ tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
+ args[1], args[2], const_args[2]);
+ tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]],
+ ARITH_MOV, args[0], 0, args[3], const_args[3]);
+ break;
case INDEX_op_add_i32:
c = ARITH_ADD;
goto gen_arith;
@@ -1782,6 +1791,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_brcond_i32, { "r", "rI" } },
{ INDEX_op_setcond_i32, { "r", "r", "rI" } },
+ { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } },
/* TODO: "r", "r", "r", "r", "ri", "ri" */
{ INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index e2299ca..0df3352 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -73,7 +73,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_GUEST_BASE
commit 7fc645bf7a313d75904f8901f4e231008e79999a
Author: Peter Maydell <peter.maydell at linaro.org>
Date: Wed Sep 26 19:48:54 2012 +0100
tcg/arm: Factor out code to emit immediate or reg-reg op
The code to emit either an immediate cmp or a register cmp insn is
duplicated in several places; factor it out into its own function.
Signed-off-by: Peter Maydell <peter.maydell at linaro.org>
Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 737200e..3596bce 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -467,6 +467,21 @@ static inline void tcg_out_movi32(TCGContext *s,
}
}
+static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,
+ TCGArg lhs, TCGArg rhs, int rhs_is_const)
+{
+ /* Emit either the reg,imm or reg,reg form of a data-processing insn.
+ * rhs must satisfy the "rI" constraint.
+ */
+ if (rhs_is_const) {
+ int rot = encode_imm(rhs);
+ assert(rot >= 0);
+ tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7));
+ } else {
+ tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
+ }
+}
+
static inline void tcg_out_mul32(TCGContext *s,
int cond, int rd, int rs, int rm)
{
@@ -1576,14 +1591,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
c = ARITH_EOR;
/* Fall through. */
gen_arith:
- if (const_args[2]) {
- int rot;
- rot = encode_imm(args[2]);
- tcg_out_dat_imm(s, COND_AL, c,
- args[0], args[1], rotl(args[2], rot) | (rot << 7));
- } else
- tcg_out_dat_reg(s, COND_AL, c,
- args[0], args[1], args[2], SHIFT_IMM_LSL(0));
+ tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
break;
case INDEX_op_add2_i32:
tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
@@ -1643,15 +1651,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_brcond_i32:
- if (const_args[1]) {
- int rot;
- rot = encode_imm(args[1]);
- tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
- args[0], rotl(args[1], rot) | (rot << 7));
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
- args[0], args[1], SHIFT_IMM_LSL(0));
- }
+ tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
+ args[0], args[1], const_args[1]);
tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
break;
case INDEX_op_brcond2_i32:
@@ -1670,15 +1671,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
break;
case INDEX_op_setcond_i32:
- if (const_args[2]) {
- int rot;
- rot = encode_imm(args[2]);
- tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
- args[1], rotl(args[2], rot) | (rot << 7));
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
- args[1], args[2], SHIFT_IMM_LSL(0));
- }
+ tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
+ args[1], args[2], const_args[2]);
tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
ARITH_MOV, args[0], 0, 1);
tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
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