[uim-commit] r1841 - in branches/r5rs/sigscheme: . experimental
experimental/imm-const
yamaken at freedesktop.org
yamaken at freedesktop.org
Sat Oct 15 12:58:33 PDT 2005
Author: yamaken
Date: 2005-10-15 12:58:29 -0700 (Sat, 15 Oct 2005)
New Revision: 1841
Added:
branches/r5rs/sigscheme/experimental/
branches/r5rs/sigscheme/experimental/imm-const/
branches/r5rs/sigscheme/experimental/imm-const/Makefile
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te-thumb.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-m68k.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips16.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh2.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh3.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh4.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-avr.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-i486.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro-i486.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro.txt
branches/r5rs/sigscheme/experimental/imm-const/imm-test.c
Log:
* experimental
* experimental/imm-const
- New directory
* experimental/imm-const/Makefile
* experimental/imm-const/imm-test.c
- New file
* experimental/imm-const/imm-test-gcc34-Os-i486.txt
* experimental/imm-const/imm-test-gcc34-Os-ppro.txt
* experimental/imm-const/imm-test-gcc34-Os-ppro-i486.txt
* experimental/imm-const/imm-test-gcc32-Os-armv5te.txt
* experimental/imm-const/imm-test-gcc32-Os-armv5te-thumb.txt
* experimental/imm-const/imm-test-gcc32-Os-mips.txt
* experimental/imm-const/imm-test-gcc32-Os-mips16.txt
* experimental/imm-const/imm-test-gcc32-Os-sh2.txt
* experimental/imm-const/imm-test-gcc32-Os-sh3.txt
* experimental/imm-const/imm-test-gcc32-Os-sh4.txt
* experimental/imm-const/imm-test-gcc32-Os-m68k.txt
* experimental/imm-const/imm-test-gcc34-Os-avr.txt
- New file produced by the imm-test
Added: branches/r5rs/sigscheme/experimental/imm-const/Makefile
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/Makefile 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/Makefile 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,72 @@
+GCCOPT=-c -Os -fomit-frame-pointer
+OBJDUMPOPT=-td
+
+PROG=imm-test
+TARGETS=imm-test-gcc34-Os-i486.txt imm-test-gcc34-Os-ppro.txt \
+ imm-test-gcc34-Os-ppro-i486.txt \
+ imm-test-gcc32-Os-armv5te.txt imm-test-gcc32-Os-armv5te-thumb.txt \
+ imm-test-gcc32-Os-mips.txt imm-test-gcc32-Os-mips16.txt \
+ imm-test-gcc32-Os-sh2.txt imm-test-gcc32-Os-sh3.txt \
+ imm-test-gcc32-Os-sh4.txt \
+ imm-test-gcc32-Os-m68k.txt \
+ imm-test-gcc34-Os-avr.txt
+
+# disabled
+# imm-test-gcc32-Os-sh5-compact.txt
+
+all: $(TARGETS)
+
+clean:
+ rm -f $(TARGETS) $(PROG).o
+
+imm-test-gcc34-Os-i486.txt:
+ gcc -march=i486 $(GCCOPT) $(PROG).c
+ objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc34-Os-ppro.txt:
+ gcc -march=pentiumpro $(GCCOPT) $(PROG).c
+ objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc34-Os-ppro-i486.txt:
+ gcc -march=pentiumpro -mtune=i486 $(GCCOPT) $(PROG).c
+ objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-armv5te.txt:
+ arm-rtems-gcc -march=armv5te $(GCCOPT) $(PROG).c
+ arm-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-armv5te-thumb.txt:
+ arm-rtems-gcc -march=armv5te -mthumb $(GCCOPT) $(PROG).c
+ arm-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-mips.txt:
+ mips-rtems-gcc $(GCCOPT) $(PROG).c
+ mips-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-mips16.txt:
+ mips-rtems-gcc -mips16 $(GCCOPT) $(PROG).c
+ mips-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-sh2.txt:
+ sh-rtems-gcc -m2 $(GCCOPT) $(PROG).c
+ sh-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-sh3.txt:
+ sh-rtems-gcc -m3 $(GCCOPT) $(PROG).c
+ sh-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-sh4.txt:
+ sh-rtems-gcc -m4 $(GCCOPT) $(PROG).c
+ sh-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-sh5-compact.txt:
+ sh-rtems-gcc -m5-compact $(GCCOPT) $(PROG).c
+ sh-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc32-Os-m68k.txt:
+ m68k-rtems-gcc $(GCCOPT) $(PROG).c
+ m68k-rtems-objdump $(OBJDUMPOPT) $(PROG).o >$@
+
+imm-test-gcc34-Os-avr.txt:
+ avr-gcc $(GCCOPT) $(PROG).c
+ avr-objdump $(OBJDUMPOPT) $(PROG).o >$@
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te-thumb.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te-thumb.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te-thumb.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,173 @@
+
+imm-test.o: file format elf32-littlearm
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .comment 00000000
+00000000 g .text 00000010 falsep
+00000010 g .text 00000010 ntc_falsep
+00000020 g .text 00000010 nullp
+00000030 g .text 00000010 ntc_nullp
+00000040 g .text 00000012 consp
+00000054 g .text 00000016 ntc_consp
+0000006c g .text 00000022 memq
+00000090 g .text 0000002a ntc_memq
+000000bc g .text 00000020 and
+000000dc g .text 00000028 ntc_and
+00000004 O *COM* 00000020 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: b500 push {lr}
+ 2: 2300 mov r3, #0
+ 4: 2806 cmp r0, #6
+ 6: d001 beq c <falsep+0xc>
+ 8: 1c18 mov r0, r3 (add r0, r3, #0)
+ a: bd00 pop {pc}
+ c: 2301 mov r3, #1
+ e: e7fb b 8 <falsep+0x8>
+
+00000010 <ntc_falsep>:
+ 10: b500 push {lr}
+ 12: 2300 mov r3, #0
+ 14: 2800 cmp r0, #0
+ 16: d001 beq 1c <ntc_falsep+0xc>
+ 18: 1c18 mov r0, r3 (add r0, r3, #0)
+ 1a: bd00 pop {pc}
+ 1c: 2301 mov r3, #1
+ 1e: e7fb b 18 <ntc_falsep+0x8>
+
+00000020 <nullp>:
+ 20: b500 push {lr}
+ 22: 2300 mov r3, #0
+ 24: 2826 cmp r0, #38
+ 26: d001 beq 2c <nullp+0xc>
+ 28: 1c18 mov r0, r3 (add r0, r3, #0)
+ 2a: bd00 pop {pc}
+ 2c: 2301 mov r3, #1
+ 2e: e7fb b 28 <nullp+0x8>
+
+00000030 <ntc_nullp>:
+ 30: b500 push {lr}
+ 32: 2300 mov r3, #0
+ 34: 2802 cmp r0, #2
+ 36: d001 beq 3c <ntc_nullp+0xc>
+ 38: 1c18 mov r0, r3 (add r0, r3, #0)
+ 3a: bd00 pop {pc}
+ 3c: 2301 mov r3, #1
+ 3e: e7fb b 38 <ntc_nullp+0x8>
+
+00000040 <consp>:
+ 40: b500 push {lr}
+ 42: 2306 mov r3, #6
+ 44: 4018 and r0, r3
+ 46: 2200 mov r2, #0
+ 48: 2800 cmp r0, #0
+ 4a: d100 bne 4e <consp+0xe>
+ 4c: 2201 mov r2, #1
+ 4e: 1c10 mov r0, r2 (add r0, r2, #0)
+ 50: bd00 pop {pc}
+ ...
+
+00000054 <ntc_consp>:
+ 54: b500 push {lr}
+ 56: 2306 mov r3, #6
+ 58: 4003 and r3, r0
+ 5a: 2200 mov r2, #0
+ 5c: 2b00 cmp r3, #0
+ 5e: d102 bne 66 <ntc_consp+0x12>
+ 60: 2800 cmp r0, #0
+ 62: d000 beq 66 <ntc_consp+0x12>
+ 64: 2201 mov r2, #1
+ 66: 1c10 mov r0, r2 (add r0, r2, #0)
+ 68: bd00 pop {pc}
+ ...
+
+0000006c <memq>:
+ 6c: b500 push {lr}
+ 6e: 2306 mov r3, #6
+ 70: 400b and r3, r1
+ 72: 1c02 mov r2, r0 (add r2, r0, #0)
+ 74: 1c08 mov r0, r1 (add r0, r1, #0)
+ 76: 2b00 cmp r3, #0
+ 78: d107 bne 8a <memq+0x1e>
+ 7a: 6803 ldr r3, [r0, #0]
+ 7c: 4293 cmp r3, r2
+ 7e: d005 beq 8c <memq+0x20>
+ 80: 6840 ldr r0, [r0, #4]
+ 82: 2306 mov r3, #6
+ 84: 4003 and r3, r0
+ 86: 2b00 cmp r3, #0
+ 88: d0f7 beq 7a <memq+0xe>
+ 8a: 2006 mov r0, #6
+ 8c: bd00 pop {pc}
+ ...
+
+00000090 <ntc_memq>:
+ 90: b500 push {lr}
+ 92: 2306 mov r3, #6
+ 94: 400b and r3, r1
+ 96: 1c02 mov r2, r0 (add r2, r0, #0)
+ 98: 1c08 mov r0, r1 (add r0, r1, #0)
+ 9a: 2b00 cmp r3, #0
+ 9c: d10b bne b6 <ntc_memq+0x26>
+ 9e: 2900 cmp r1, #0
+ a0: d009 beq b6 <ntc_memq+0x26>
+ a2: 6803 ldr r3, [r0, #0]
+ a4: 4293 cmp r3, r2
+ a6: d007 beq b8 <ntc_memq+0x28>
+ a8: 6840 ldr r0, [r0, #4]
+ aa: 2306 mov r3, #6
+ ac: 4003 and r3, r0
+ ae: 2b00 cmp r3, #0
+ b0: d101 bne b6 <ntc_memq+0x26>
+ b2: 2800 cmp r0, #0
+ b4: d1f5 bne a2 <ntc_memq+0x12>
+ b6: 2000 mov r0, #0
+ b8: bd00 pop {pc}
+ ...
+
+000000bc <and>:
+ bc: b500 push {lr}
+ be: 2306 mov r3, #6
+ c0: 4003 and r3, r0
+ c2: 2b00 cmp r3, #0
+ c4: d106 bne d4 <and+0x18>
+ c6: 2806 cmp r0, #6
+ c8: d006 beq d8 <and+0x1c>
+ ca: 6840 ldr r0, [r0, #4]
+ cc: 2306 mov r3, #6
+ ce: 4003 and r3, r0
+ d0: 2b00 cmp r3, #0
+ d2: d0f8 beq c6 <and+0xa>
+ d4: 20a6 mov r0, #166
+ d6: bd00 pop {pc}
+ d8: 2006 mov r0, #6
+ da: e7fc b d6 <and+0x1a>
+
+000000dc <ntc_and>:
+ dc: b500 push {lr}
+ de: 2306 mov r3, #6
+ e0: 4003 and r3, r0
+ e2: 2b00 cmp r3, #0
+ e4: d108 bne f8 <ntc_and+0x1c>
+ e6: 2800 cmp r0, #0
+ e8: d006 beq f8 <ntc_and+0x1c>
+ ea: 6840 ldr r0, [r0, #4]
+ ec: 2306 mov r3, #6
+ ee: 4003 and r3, r0
+ f0: 2b00 cmp r3, #0
+ f2: d101 bne f8 <ntc_and+0x1c>
+ f4: 2800 cmp r0, #0
+ f6: d1f8 bne ea <ntc_and+0xe>
+ f8: 4b01 ldr r3, [pc, #4] (100 <ntc_and+0x24>)
+ fa: 6818 ldr r0, [r3, #0]
+ fc: bd00 pop {pc}
+ fe: 0000 lsl r0, r0, #0
+ 100: 0000 lsl r0, r0, #0
+ ...
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-armv5te.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,137 @@
+
+imm-test.o: file format elf32-littlearm
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .comment 00000000
+00000000 g F .text 00000010 falsep
+00000010 g F .text 00000010 ntc_falsep
+00000020 g F .text 00000010 nullp
+00000030 g F .text 00000010 ntc_nullp
+00000040 g F .text 00000010 consp
+00000050 g F .text 00000020 ntc_consp
+00000070 g F .text 0000002c memq
+0000009c g F .text 0000005c ntc_memq
+000000f8 g F .text 00000024 and
+0000011c g F .text 0000005c ntc_and
+00000004 O *COM* 00000020 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: e3500006 cmp r0, #6 ; 0x6
+ 4: 13a00000 movne r0, #0 ; 0x0
+ 8: 03a00001 moveq r0, #1 ; 0x1
+ c: e12fff1e bx lr
+
+00000010 <ntc_falsep>:
+ 10: e3500000 cmp r0, #0 ; 0x0
+ 14: 13a00000 movne r0, #0 ; 0x0
+ 18: 03a00001 moveq r0, #1 ; 0x1
+ 1c: e12fff1e bx lr
+
+00000020 <nullp>:
+ 20: e3500026 cmp r0, #38 ; 0x26
+ 24: 13a00000 movne r0, #0 ; 0x0
+ 28: 03a00001 moveq r0, #1 ; 0x1
+ 2c: e12fff1e bx lr
+
+00000030 <ntc_nullp>:
+ 30: e3500002 cmp r0, #2 ; 0x2
+ 34: 13a00000 movne r0, #0 ; 0x0
+ 38: 03a00001 moveq r0, #1 ; 0x1
+ 3c: e12fff1e bx lr
+
+00000040 <consp>:
+ 40: e3100006 tst r0, #6 ; 0x6
+ 44: 13a00000 movne r0, #0 ; 0x0
+ 48: 03a00001 moveq r0, #1 ; 0x1
+ 4c: e12fff1e bx lr
+
+00000050 <ntc_consp>:
+ 50: e3100006 tst r0, #6 ; 0x6
+ 54: e1a03000 mov r3, r0
+ 58: 13a00000 movne r0, #0 ; 0x0
+ 5c: 03a00001 moveq r0, #1 ; 0x1
+ 60: e3530000 cmp r3, #0 ; 0x0
+ 64: 03a00000 moveq r0, #0 ; 0x0
+ 68: 12000001 andne r0, r0, #1 ; 0x1
+ 6c: e12fff1e bx lr
+
+00000070 <memq>:
+ 70: e3110006 tst r1, #6 ; 0x6
+ 74: 1a000023 bne 94 <memq+0x24>
+ 78: e5913000 ldr r3, [r1]
+ 7c: e1530000 cmp r3, r0
+ 80: 01a00001 moveq r0, r1
+ 84: 012fff1e bxeq lr
+ 88: e5911004 ldr r1, [r1, #4]
+ 8c: e3110006 tst r1, #6 ; 0x6
+ 90: 0a00001c beq 78 <memq+0x8>
+ 94: e3a00006 mov r0, #6 ; 0x6
+ 98: e12fff1e bx lr
+
+0000009c <ntc_memq>:
+ 9c: e3110006 tst r1, #6 ; 0x6
+ a0: 13a03000 movne r3, #0 ; 0x0
+ a4: 03a03001 moveq r3, #1 ; 0x1
+ a8: e3510000 cmp r1, #0 ; 0x0
+ ac: 03a03000 moveq r3, #0 ; 0x0
+ b0: 12033001 andne r3, r3, #1 ; 0x1
+ b4: e3530000 cmp r3, #0 ; 0x0
+ b8: 0a00003a beq f0 <ntc_memq+0x54>
+ bc: e5913000 ldr r3, [r1]
+ c0: e1530000 cmp r3, r0
+ c4: 01a00001 moveq r0, r1
+ c8: 012fff1e bxeq lr
+ cc: e5911004 ldr r1, [r1, #4]
+ d0: e3110006 tst r1, #6 ; 0x6
+ d4: 13a03000 movne r3, #0 ; 0x0
+ d8: 03a03001 moveq r3, #1 ; 0x1
+ dc: e3510000 cmp r1, #0 ; 0x0
+ e0: 03a03000 moveq r3, #0 ; 0x0
+ e4: 12033001 andne r3, r3, #1 ; 0x1
+ e8: e3530000 cmp r3, #0 ; 0x0
+ ec: 1a00002d bne bc <ntc_memq+0x20>
+ f0: e3a00000 mov r0, #0 ; 0x0
+ f4: e12fff1e bx lr
+
+000000f8 <and>:
+ f8: e3100006 tst r0, #6 ; 0x6
+ fc: 1a000043 bne 114 <and+0x1c>
+ 100: e3500006 cmp r0, #6 ; 0x6
+ 104: 012fff1e bxeq lr
+ 108: e5900004 ldr r0, [r0, #4]
+ 10c: e3100006 tst r0, #6 ; 0x6
+ 110: 0a00003e beq 100 <and+0x8>
+ 114: e3a000a6 mov r0, #166 ; 0xa6
+ 118: e12fff1e bx lr
+
+0000011c <ntc_and>:
+ 11c: e3100006 tst r0, #6 ; 0x6
+ 120: 13a03000 movne r3, #0 ; 0x0
+ 124: 03a03001 moveq r3, #1 ; 0x1
+ 128: e3500000 cmp r0, #0 ; 0x0
+ 12c: 03a03000 moveq r3, #0 ; 0x0
+ 130: 12033001 andne r3, r3, #1 ; 0x1
+ 134: e3530000 cmp r3, #0 ; 0x0
+ 138: 0a000058 beq 168 <ntc_and+0x4c>
+ 13c: e3500000 cmp r0, #0 ; 0x0
+ 140: 012fff1e bxeq lr
+ 144: e5900004 ldr r0, [r0, #4]
+ 148: e3100006 tst r0, #6 ; 0x6
+ 14c: 13a03000 movne r3, #0 ; 0x0
+ 150: 03a03001 moveq r3, #1 ; 0x1
+ 154: e3500000 cmp r0, #0 ; 0x0
+ 158: 03a03000 moveq r3, #0 ; 0x0
+ 15c: 12033001 andne r3, r3, #1 ; 0x1
+ 160: e3530000 cmp r3, #0 ; 0x0
+ 164: 1a00004d bne 13c <ntc_and+0x20>
+ 168: e59f3004 ldr r3, [pc, #4] ; 174 <ntc_and+0x58>
+ 16c: e5930000 ldr r0, [r3]
+ 170: e12fff1e bx lr
+ 174: 00000000 andeq r0, r0, r0
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-m68k.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-m68k.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-m68k.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,158 @@
+
+imm-test.o: file format elf32-m68k
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .comment 00000000
+00000000 g F .text 0000000e falsep
+0000000e g F .text 0000000c ntc_falsep
+0000001a g F .text 0000000e nullp
+00000028 g F .text 0000000e ntc_nullp
+00000036 g F .text 0000000e consp
+00000044 g F .text 00000018 ntc_consp
+0000005c g F .text 0000002a memq
+00000086 g F .text 00000032 ntc_memq
+000000b8 g F .text 00000026 and
+000000de g F .text 0000002e ntc_and
+00000004 O *COM* 00000002 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 7006 moveq #6,%d0
+ 2: b0af 0004 cmpl %sp@(4),%d0
+ 6: 57c0 seq %d0
+ 8: 49c0 extbl %d0
+ a: 4480 negl %d0
+ c: 4e75 rts
+
+0000000e <ntc_falsep>:
+ e: 4aaf 0004 tstl %sp@(4)
+ 12: 57c0 seq %d0
+ 14: 49c0 extbl %d0
+ 16: 4480 negl %d0
+ 18: 4e75 rts
+
+0000001a <nullp>:
+ 1a: 7026 moveq #38,%d0
+ 1c: b0af 0004 cmpl %sp@(4),%d0
+ 20: 57c0 seq %d0
+ 22: 49c0 extbl %d0
+ 24: 4480 negl %d0
+ 26: 4e75 rts
+
+00000028 <ntc_nullp>:
+ 28: 7002 moveq #2,%d0
+ 2a: b0af 0004 cmpl %sp@(4),%d0
+ 2e: 57c0 seq %d0
+ 30: 49c0 extbl %d0
+ 32: 4480 negl %d0
+ 34: 4e75 rts
+
+00000036 <consp>:
+ 36: 7006 moveq #6,%d0
+ 38: c0af 0004 andl %sp@(4),%d0
+ 3c: 57c0 seq %d0
+ 3e: 49c0 extbl %d0
+ 40: 4480 negl %d0
+ 42: 4e75 rts
+
+00000044 <ntc_consp>:
+ 44: 222f 0004 movel %sp@(4),%d1
+ 48: 91c8 subal %a0,%a0
+ 4a: 7006 moveq #6,%d0
+ 4c: c081 andl %d1,%d0
+ 4e: 6608 bnes 58 <ntc_consp+0x14>
+ 50: 4a81 tstl %d1
+ 52: 6704 beqs 58 <ntc_consp+0x14>
+ 54: 307c 0001 moveaw #1,%a0
+ 58: 2008 movel %a0,%d0
+ 5a: 4e75 rts
+
+0000005c <memq>:
+ 5c: 206f 0004 moveal %sp@(4),%a0
+ 60: 222f 0008 movel %sp@(8),%d1
+ 64: 7006 moveq #6,%d0
+ 66: c081 andl %d1,%d0
+ 68: 6612 bnes 7c <memq+0x20>
+ 6a: 2241 moveal %d1,%a1
+ 6c: b1d1 cmpal %a1@,%a0
+ 6e: 6710 beqs 80 <memq+0x24>
+ 70: 2241 moveal %d1,%a1
+ 72: 2229 0004 movel %a1@(4),%d1
+ 76: 7006 moveq #6,%d0
+ 78: c081 andl %d1,%d0
+ 7a: 67ee beqs 6a <memq+0xe>
+ 7c: 7006 moveq #6,%d0
+ 7e: 4e75 rts
+ 80: 2001 movel %d1,%d0
+ 82: 4e75 rts
+ 84: 4e71 nop
+
+00000086 <ntc_memq>:
+ 86: 206f 0004 moveal %sp@(4),%a0
+ 8a: 222f 0008 movel %sp@(8),%d1
+ 8e: 7006 moveq #6,%d0
+ 90: c081 andl %d1,%d0
+ 92: 661a bnes ae <ntc_memq+0x28>
+ 94: 4a81 tstl %d1
+ 96: 6716 beqs ae <ntc_memq+0x28>
+ 98: 2241 moveal %d1,%a1
+ 9a: b1d1 cmpal %a1@,%a0
+ 9c: 6714 beqs b2 <ntc_memq+0x2c>
+ 9e: 2241 moveal %d1,%a1
+ a0: 2229 0004 movel %a1@(4),%d1
+ a4: 7006 moveq #6,%d0
+ a6: c081 andl %d1,%d0
+ a8: 6604 bnes ae <ntc_memq+0x28>
+ aa: 4a81 tstl %d1
+ ac: 66ea bnes 98 <ntc_memq+0x12>
+ ae: 4280 clrl %d0
+ b0: 4e75 rts
+ b2: 2001 movel %d1,%d0
+ b4: 4e75 rts
+ b6: 4e71 nop
+
+000000b8 <and>:
+ b8: 2f02 movel %d2,%sp at -
+ ba: 222f 0008 movel %sp@(8),%d1
+ be: 7006 moveq #6,%d0
+ c0: c081 andl %d1,%d0
+ c2: 6612 bnes d6 <and+0x1e>
+ c4: 7006 moveq #6,%d0
+ c6: b081 cmpl %d1,%d0
+ c8: 6710 beqs da <and+0x22>
+ ca: 2041 moveal %d1,%a0
+ cc: 2228 0004 movel %a0@(4),%d1
+ d0: 7006 moveq #6,%d0
+ d2: c081 andl %d1,%d0
+ d4: 67ee beqs c4 <and+0xc>
+ d6: 7059 moveq #89,%d0
+ d8: 4600 notb %d0
+ da: 241f movel %sp at +,%d2
+ dc: 4e75 rts
+
+000000de <ntc_and>:
+ de: 222f 0004 movel %sp@(4),%d1
+ e2: 7006 moveq #6,%d0
+ e4: c081 andl %d1,%d0
+ e6: 661a bnes 102 <ntc_and+0x24>
+ e8: 4a81 tstl %d1
+ ea: 6716 beqs 102 <ntc_and+0x24>
+ ec: 4280 clrl %d0
+ ee: 4a81 tstl %d1
+ f0: 6716 beqs 108 <ntc_and+0x2a>
+ f2: 2041 moveal %d1,%a0
+ f4: 2228 0004 movel %a0@(4),%d1
+ f8: 7006 moveq #6,%d0
+ fa: c081 andl %d1,%d0
+ fc: 6604 bnes 102 <ntc_and+0x24>
+ fe: 4a81 tstl %d1
+ 100: 66ea bnes ec <ntc_and+0xe>
+ 102: 2039 0000 0000 movel 0 <falsep>,%d0
+ 108: 4e75 rts
+ 10a: 4e71 nop
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,129 @@
+
+imm-test.o: file format elf32-bigmips
+
+SYMBOL TABLE:
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .mdebug.abi32 00000000
+00000000 l d .reginfo 00000000
+00000000 l d .pdr 00000000
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 g F .text 00000000 falsep
+0000000c g F .text 00000000 ntc_falsep
+00000014 g F .text 00000000 nullp
+00000020 g F .text 00000000 ntc_nullp
+0000002c g F .text 00000000 consp
+00000038 g F .text 00000000 ntc_consp
+00000058 g F .text 00000000 memq
+00000090 g F .text 00000000 ntc_memq
+000000dc g F .text 00000000 and
+00000110 g F .text 00000000 ntc_and
+00000004 O *COM* 00000004 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 38820006 xori v0,a0,0x6
+ 4: 03e00008 jr ra
+ 8: 2c420001 sltiu v0,v0,1
+
+0000000c <ntc_falsep>:
+ c: 03e00008 jr ra
+ 10: 2c820001 sltiu v0,a0,1
+
+00000014 <nullp>:
+ 14: 38820026 xori v0,a0,0x26
+ 18: 03e00008 jr ra
+ 1c: 2c420001 sltiu v0,v0,1
+
+00000020 <ntc_nullp>:
+ 20: 38820002 xori v0,a0,0x2
+ 24: 03e00008 jr ra
+ 28: 2c420001 sltiu v0,v0,1
+
+0000002c <consp>:
+ 2c: 30820006 andi v0,a0,0x6
+ 30: 03e00008 jr ra
+ 34: 2c420001 sltiu v0,v0,1
+
+00000038 <ntc_consp>:
+ 38: 30820006 andi v0,a0,0x6
+ 3c: 14400004 bnez v0,50 <ntc_consp+0x18>
+ 40: 00001821 move v1,zero
+ 44: 10800002 beqz a0,50 <ntc_consp+0x18>
+ 48: 00000000 nop
+ 4c: 24030001 li v1,1
+ 50: 03e00008 jr ra
+ 54: 00601021 move v0,v1
+
+00000058 <memq>:
+ 58: 30a20006 andi v0,a1,0x6
+ 5c: 1440000a bnez v0,88 <memq+0x30>
+ 60: 24030006 li v1,6
+ 64: 8ca20000 lw v0,0(a1)
+ 68: 00000000 nop
+ 6c: 10440006 beq v0,a0,88 <memq+0x30>
+ 70: 00a01821 move v1,a1
+ 74: 8ca50004 lw a1,4(a1)
+ 78: 00000000 nop
+ 7c: 30a20006 andi v0,a1,0x6
+ 80: 1040fff8 beqz v0,64 <memq+0xc>
+ 84: 24030006 li v1,6
+ 88: 03e00008 jr ra
+ 8c: 00601021 move v0,v1
+
+00000090 <ntc_memq>:
+ 90: 30a20006 andi v0,a1,0x6
+ 94: 1440000f bnez v0,d4 <ntc_memq+0x44>
+ 98: 00001821 move v1,zero
+ 9c: 10a0000d beqz a1,d4 <ntc_memq+0x44>
+ a0: 00000000 nop
+ a4: 8ca20000 lw v0,0(a1)
+ a8: 00000000 nop
+ ac: 10440009 beq v0,a0,d4 <ntc_memq+0x44>
+ b0: 00a01821 move v1,a1
+ b4: 8ca50004 lw a1,4(a1)
+ b8: 00000000 nop
+ bc: 30a20006 andi v0,a1,0x6
+ c0: 14400003 bnez v0,d0 <ntc_memq+0x40>
+ c4: 00000000 nop
+ c8: 14a0fff6 bnez a1,a4 <ntc_memq+0x14>
+ cc: 00000000 nop
+ d0: 00001821 move v1,zero
+ d4: 03e00008 jr ra
+ d8: 00601021 move v0,v1
+
+000000dc <and>:
+ dc: 30820006 andi v0,a0,0x6
+ e0: 14400009 bnez v0,108 <and+0x2c>
+ e4: 240300a6 li v1,166
+ e8: 24020006 li v0,6
+ ec: 10820006 beq a0,v0,108 <and+0x2c>
+ f0: 24030006 li v1,6
+ f4: 8c840004 lw a0,4(a0)
+ f8: 00000000 nop
+ fc: 30820006 andi v0,a0,0x6
+ 100: 1040fff9 beqz v0,e8 <and+0xc>
+ 104: 240300a6 li v1,166
+ 108: 03e00008 jr ra
+ 10c: 00601021 move v0,v1
+
+00000110 <ntc_and>:
+ 110: 30820006 andi v0,a0,0x6
+ 114: 1440000a bnez v0,140 <ntc_and+0x30>
+ 118: 00000000 nop
+ 11c: 10800008 beqz a0,140 <ntc_and+0x30>
+ 120: 00000000 nop
+ 124: 8c840004 lw a0,4(a0)
+ 128: 00000000 nop
+ 12c: 30820006 andi v0,a0,0x6
+ 130: 14400003 bnez v0,140 <ntc_and+0x30>
+ 134: 00000000 nop
+ 138: 1480fffa bnez a0,124 <ntc_and+0x14>
+ 13c: 00000000 nop
+ 140: 8f820000 lw v0,0(gp)
+ 144: 03e00008 jr ra
+ 148: 00000000 nop
+ 14c: 00000000 nop
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips16.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips16.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-mips16.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,140 @@
+
+imm-test.o: file format elf32-bigmips
+
+SYMBOL TABLE:
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .mdebug.abi32 00000000
+00000000 l d .reginfo 00000000
+00000000 l d .pdr 00000000
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 g F .text 00000000 0xf0 falsep
+0000000c g F .text 00000000 0xf0 ntc_falsep
+00000014 g F .text 00000000 0xf0 nullp
+00000020 g F .text 00000000 0xf0 ntc_nullp
+0000002c g F .text 00000000 0xf0 consp
+00000038 g F .text 00000000 0xf0 ntc_consp
+00000048 g F .text 00000000 0xf0 memq
+00000064 g F .text 00000000 0xf0 ntc_memq
+00000084 g F .text 00000000 0xf0 and
+000000a0 g F .text 00000000 0xf0 ntc_and
+00000004 O *COM* 00000004 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 6a06 li v0,6
+ 2: ec4e xor a0,v0
+ 4: 5c01 sltiu a0,1
+ 6: e820 jr ra
+ 8: 6758 move v0,t8
+ ...
+
+0000000c <ntc_falsep>:
+ c: 5c01 sltiu a0,1
+ e: e820 jr ra
+ 10: 6758 move v0,t8
+ ...
+
+00000014 <nullp>:
+ 14: 6a26 li v0,38
+ 16: ec4e xor a0,v0
+ 18: 5c01 sltiu a0,1
+ 1a: e820 jr ra
+ 1c: 6758 move v0,t8
+ ...
+
+00000020 <ntc_nullp>:
+ 20: 6a02 li v0,2
+ 22: ec4e xor a0,v0
+ 24: 5c01 sltiu a0,1
+ 26: e820 jr ra
+ 28: 6758 move v0,t8
+ ...
+
+0000002c <consp>:
+ 2c: 6a06 li v0,6
+ 2e: ea8c and v0,a0
+ 30: 5a01 sltiu v0,1
+ 32: e820 jr ra
+ 34: 6758 move v0,t8
+ ...
+
+00000038 <ntc_consp>:
+ 38: 6a06 li v0,6
+ 3a: ea8c and v0,a0
+ 3c: 6b00 li v1,0
+ 3e: 2a02 bnez v0,44 <ntc_consp+0xc>
+ 40: 2401 beqz a0,44 <ntc_consp+0xc>
+ 42: 6b01 li v1,1
+ 44: e820 jr ra
+ 46: 6743 move v0,v1
+
+00000048 <memq>:
+ 48: 6a06 li v0,6
+ 4a: eaac and v0,a1
+ 4c: 2a08 bnez v0,5e <memq+0x16>
+ 4e: 9d40 lw v0,0(a1)
+ 50: 6765 move v1,a1
+ 52: ea8e xor v0,a0
+ 54: 2205 beqz v0,60 <memq+0x18>
+ 56: 9da1 lw a1,4(a1)
+ 58: 6a06 li v0,6
+ 5a: eaac and v0,a1
+ 5c: 22f8 beqz v0,4e <memq+0x6>
+ 5e: 6b06 li v1,6
+ 60: e820 jr ra
+ 62: 6743 move v0,v1
+
+00000064 <ntc_memq>:
+ 64: 6a06 li v0,6
+ 66: eaac and v0,a1
+ 68: 2a0a bnez v0,7e <ntc_memq+0x1a>
+ 6a: 2509 beqz a1,7e <ntc_memq+0x1a>
+ 6c: 9d40 lw v0,0(a1)
+ 6e: 6765 move v1,a1
+ 70: ea8e xor v0,a0
+ 72: 2206 beqz v0,80 <ntc_memq+0x1c>
+ 74: 9da1 lw a1,4(a1)
+ 76: 6a06 li v0,6
+ 78: eaac and v0,a1
+ 7a: 2a01 bnez v0,7e <ntc_memq+0x1a>
+ 7c: 2df7 bnez a1,6c <ntc_memq+0x8>
+ 7e: 6b00 li v1,0
+ 80: e820 jr ra
+ 82: 6743 move v0,v1
+
+00000084 <and>:
+ 84: 6a06 li v0,6
+ 86: ea8c and v0,a0
+ 88: 2a07 bnez v0,98 <and+0x14>
+ 8a: 7406 cmpi a0,6
+ 8c: 6a06 li v0,6
+ 8e: 6005 bteqz 9a <and+0x16>
+ 90: 9c81 lw a0,4(a0)
+ 92: 6a06 li v0,6
+ 94: ea8c and v0,a0
+ 96: 22f9 beqz v0,8a <and+0x6>
+ 98: 6aa6 li v0,166
+ 9a: e820 jr ra
+ 9c: 6500 nop
+ ...
+
+000000a0 <ntc_and>:
+ a0: 6a06 li v0,6
+ a2: ea8c and v0,a0
+ a4: 2a06 bnez v0,b2 <ntc_and+0x12>
+ a6: 2405 beqz a0,b2 <ntc_and+0x12>
+ a8: 9c81 lw a0,4(a0)
+ aa: 6a06 li v0,6
+ ac: ea8c and v0,a0
+ ae: 2a01 bnez v0,b2 <ntc_and+0x12>
+ b0: 2cfb bnez a0,a8 <ntc_and+0x8>
+ b2: 675c move v0,gp
+ b4: f000 9a40 lw v0,0(v0)
+ b8: e820 jr ra
+ ba: 6500 nop
+ bc: 6500 nop
+ be: 6500 nop
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh2.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh2.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh2.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,136 @@
+
+imm-test.o: file format coff-sh
+
+SYMBOL TABLE:
+[ 0](sec -2)(fl 0x00)(ty 0)(scl 103) (nx 1) 0x00000000 imm-test.c
+File
+[ 2](sec 1)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x00000000 .text
+AUX scnlen 0xb0 nreloc 1 nlnno 0
+[ 4](sec 2)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000b0 .data
+AUX scnlen 0x0 nreloc 0 nlnno 0
+[ 6](sec 3)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000b0 .bss
+AUX scnlen 0x0 nreloc 0 nlnno 0
+[ 8](sec 4)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000b0 .comment
+AUX scnlen 0x20 nreloc 0 nlnno 0
+[ 10](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _falsep
+[ 11](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000008 _ntc_falsep
+[ 12](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000000e _nullp
+[ 13](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000016 _ntc_nullp
+[ 14](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000001e _consp
+[ 15](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000026 _ntc_consp
+[ 16](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000038 _memq
+[ 17](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000052 _ntc_memq
+[ 18](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000074 _and
+[ 19](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000090 _ntc_and
+[ 20](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000004 _scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <_falsep>:
+ 0: 60 43 mov r4,r0
+ 2: 88 06 cmp/eq #6,r0
+ 4: 00 0b rts
+ 6: 00 29 movt r0
+
+00000008 <_ntc_falsep>:
+ 8: 24 48 tst r4,r4
+ a: 00 0b rts
+ c: 00 29 movt r0
+
+0000000e <_nullp>:
+ e: 60 43 mov r4,r0
+ 10: 88 26 cmp/eq #38,r0
+ 12: 00 0b rts
+ 14: 00 29 movt r0
+
+00000016 <_ntc_nullp>:
+ 16: 60 43 mov r4,r0
+ 18: 88 02 cmp/eq #2,r0
+ 1a: 00 0b rts
+ 1c: 00 29 movt r0
+
+0000001e <_consp>:
+ 1e: 60 43 mov r4,r0
+ 20: c8 06 tst #6,r0
+ 22: 00 0b rts
+ 24: 00 29 movt r0
+
+00000026 <_ntc_consp>:
+ 26: 60 43 mov r4,r0
+ 28: c8 06 tst #6,r0
+ 2a: 8f 03 bf.s 34 <_ntc_consp+0xe>
+ 2c: e1 00 mov #0,r1
+ 2e: 24 48 tst r4,r4
+ 30: 89 00 bt 34 <_ntc_consp+0xe>
+ 32: e1 01 mov #1,r1
+ 34: 00 0b rts
+ 36: 60 13 mov r1,r0
+
+00000038 <_memq>:
+ 38: 60 53 mov r5,r0
+ 3a: c8 06 tst #6,r0
+ 3c: 8b 06 bf 4c <_memq+0x14>
+ 3e: 61 02 mov.l @r0,r1
+ 40: 31 40 cmp/eq r4,r1
+ 42: 8d 04 bt.s 4e <_memq+0x16>
+ 44: 61 03 mov r0,r1
+ 46: 50 01 mov.l @(4,r0),r0
+ 48: c8 06 tst #6,r0
+ 4a: 89 f8 bt 3e <_memq+0x6>
+ 4c: e1 06 mov #6,r1
+ 4e: 00 0b rts
+ 50: 60 13 mov r1,r0
+
+00000052 <_ntc_memq>:
+ 52: 60 53 mov r5,r0
+ 54: c8 06 tst #6,r0
+ 56: 8f 0a bf.s 6e <_ntc_memq+0x1c>
+ 58: 25 58 tst r5,r5
+ 5a: 89 08 bt 6e <_ntc_memq+0x1c>
+ 5c: 61 02 mov.l @r0,r1
+ 5e: 31 40 cmp/eq r4,r1
+ 60: 8d 06 bt.s 70 <_ntc_memq+0x1e>
+ 62: 61 03 mov r0,r1
+ 64: 50 01 mov.l @(4,r0),r0
+ 66: c8 06 tst #6,r0
+ 68: 8f 01 bf.s 6e <_ntc_memq+0x1c>
+ 6a: 20 08 tst r0,r0
+ 6c: 8b f6 bf 5c <_ntc_memq+0xa>
+ 6e: e1 00 mov #0,r1
+ 70: 00 0b rts
+ 72: 60 13 mov r1,r0
+
+00000074 <_and>:
+ 74: 60 43 mov r4,r0
+ 76: c8 06 tst #6,r0
+ 78: 8f 06 bf.s 88 <_and+0x14>
+ 7a: 88 06 cmp/eq #6,r0
+ 7c: 8d 05 bt.s 8a <_and+0x16>
+ 7e: e1 06 mov #6,r1
+ 80: 50 01 mov.l @(4,r0),r0
+ 82: c8 06 tst #6,r0
+ 84: 8d fa bt.s 7c <_and+0x8>
+ 86: 88 06 cmp/eq #6,r0
+ 88: 91 01 mov.w 8e <_and+0x1a>,r1 ! 0xa6
+ 8a: 00 0b rts
+ 8c: 60 13 mov r1,r0
+ 8e: 00 a6 mov.l r10,@(r0,r0)
+
+00000090 <_ntc_and>:
+ 90: 60 43 mov r4,r0
+ 92: c8 06 tst #6,r0
+ 94: 8f 06 bf.s a4 <_ntc_and+0x14>
+ 96: 24 48 tst r4,r4
+ 98: 89 04 bt a4 <_ntc_and+0x14>
+ 9a: 50 01 mov.l @(4,r0),r0
+ 9c: c8 06 tst #6,r0
+ 9e: 8f 01 bf.s a4 <_ntc_and+0x14>
+ a0: 20 08 tst r0,r0
+ a2: 8b fa bf 9a <_ntc_and+0xa>
+ a4: d1 01 mov.l ac <_ntc_and+0x1c>,r1 ! 0x0
+ a6: 00 0b rts
+ a8: 60 12 mov.l @r1,r0
+ aa: 00 09 nop
+ ac: 00 00 .word 0x0000
+ ...
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh3.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh3.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh3.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,136 @@
+
+imm-test.o: file format coff-sh
+
+SYMBOL TABLE:
+[ 0](sec -2)(fl 0x00)(ty 0)(scl 103) (nx 1) 0x00000000 imm-test.c
+File
+[ 2](sec 1)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x00000000 .text
+AUX scnlen 0xb0 nreloc 1 nlnno 0
+[ 4](sec 2)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000b0 .data
+AUX scnlen 0x0 nreloc 0 nlnno 0
+[ 6](sec 3)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000b0 .bss
+AUX scnlen 0x0 nreloc 0 nlnno 0
+[ 8](sec 4)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000b0 .comment
+AUX scnlen 0x20 nreloc 0 nlnno 0
+[ 10](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _falsep
+[ 11](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000008 _ntc_falsep
+[ 12](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000000e _nullp
+[ 13](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000016 _ntc_nullp
+[ 14](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000001e _consp
+[ 15](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000026 _ntc_consp
+[ 16](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000038 _memq
+[ 17](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000052 _ntc_memq
+[ 18](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000074 _and
+[ 19](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000090 _ntc_and
+[ 20](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000004 _scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <_falsep>:
+ 0: 60 43 mov r4,r0
+ 2: 88 06 cmp/eq #6,r0
+ 4: 00 0b rts
+ 6: 00 29 movt r0
+
+00000008 <_ntc_falsep>:
+ 8: 24 48 tst r4,r4
+ a: 00 0b rts
+ c: 00 29 movt r0
+
+0000000e <_nullp>:
+ e: 60 43 mov r4,r0
+ 10: 88 26 cmp/eq #38,r0
+ 12: 00 0b rts
+ 14: 00 29 movt r0
+
+00000016 <_ntc_nullp>:
+ 16: 60 43 mov r4,r0
+ 18: 88 02 cmp/eq #2,r0
+ 1a: 00 0b rts
+ 1c: 00 29 movt r0
+
+0000001e <_consp>:
+ 1e: 60 43 mov r4,r0
+ 20: c8 06 tst #6,r0
+ 22: 00 0b rts
+ 24: 00 29 movt r0
+
+00000026 <_ntc_consp>:
+ 26: 60 43 mov r4,r0
+ 28: c8 06 tst #6,r0
+ 2a: 8f 03 bf.s 34 <_ntc_consp+0xe>
+ 2c: e1 00 mov #0,r1
+ 2e: 24 48 tst r4,r4
+ 30: 89 00 bt 34 <_ntc_consp+0xe>
+ 32: e1 01 mov #1,r1
+ 34: 00 0b rts
+ 36: 60 13 mov r1,r0
+
+00000038 <_memq>:
+ 38: 60 53 mov r5,r0
+ 3a: c8 06 tst #6,r0
+ 3c: 8b 06 bf 4c <_memq+0x14>
+ 3e: 61 02 mov.l @r0,r1
+ 40: 31 40 cmp/eq r4,r1
+ 42: 8d 04 bt.s 4e <_memq+0x16>
+ 44: 61 03 mov r0,r1
+ 46: 50 01 mov.l @(4,r0),r0
+ 48: c8 06 tst #6,r0
+ 4a: 89 f8 bt 3e <_memq+0x6>
+ 4c: e1 06 mov #6,r1
+ 4e: 00 0b rts
+ 50: 60 13 mov r1,r0
+
+00000052 <_ntc_memq>:
+ 52: 60 53 mov r5,r0
+ 54: c8 06 tst #6,r0
+ 56: 8f 0a bf.s 6e <_ntc_memq+0x1c>
+ 58: 25 58 tst r5,r5
+ 5a: 89 08 bt 6e <_ntc_memq+0x1c>
+ 5c: 61 02 mov.l @r0,r1
+ 5e: 31 40 cmp/eq r4,r1
+ 60: 8d 06 bt.s 70 <_ntc_memq+0x1e>
+ 62: 61 03 mov r0,r1
+ 64: 50 01 mov.l @(4,r0),r0
+ 66: c8 06 tst #6,r0
+ 68: 8f 01 bf.s 6e <_ntc_memq+0x1c>
+ 6a: 20 08 tst r0,r0
+ 6c: 8b f6 bf 5c <_ntc_memq+0xa>
+ 6e: e1 00 mov #0,r1
+ 70: 00 0b rts
+ 72: 60 13 mov r1,r0
+
+00000074 <_and>:
+ 74: 60 43 mov r4,r0
+ 76: c8 06 tst #6,r0
+ 78: 8f 06 bf.s 88 <_and+0x14>
+ 7a: 88 06 cmp/eq #6,r0
+ 7c: 8d 05 bt.s 8a <_and+0x16>
+ 7e: e1 06 mov #6,r1
+ 80: 50 01 mov.l @(4,r0),r0
+ 82: c8 06 tst #6,r0
+ 84: 8d fa bt.s 7c <_and+0x8>
+ 86: 88 06 cmp/eq #6,r0
+ 88: 91 01 mov.w 8e <_and+0x1a>,r1 ! 0xa6
+ 8a: 00 0b rts
+ 8c: 60 13 mov r1,r0
+ 8e: 00 a6 mov.l r10,@(r0,r0)
+
+00000090 <_ntc_and>:
+ 90: 60 43 mov r4,r0
+ 92: c8 06 tst #6,r0
+ 94: 8f 06 bf.s a4 <_ntc_and+0x14>
+ 96: 24 48 tst r4,r4
+ 98: 89 04 bt a4 <_ntc_and+0x14>
+ 9a: 50 01 mov.l @(4,r0),r0
+ 9c: c8 06 tst #6,r0
+ 9e: 8f 01 bf.s a4 <_ntc_and+0x14>
+ a0: 20 08 tst r0,r0
+ a2: 8b fa bf 9a <_ntc_and+0xa>
+ a4: d1 01 mov.l ac <_ntc_and+0x1c>,r1 ! 0x0
+ a6: 00 0b rts
+ a8: 60 12 mov.l @r1,r0
+ aa: 00 09 nop
+ ac: 00 00 .word 0x0000
+ ...
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh4.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh4.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc32-Os-sh4.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,160 @@
+
+imm-test.o: file format coff-sh
+
+SYMBOL TABLE:
+[ 0](sec -2)(fl 0x00)(ty 0)(scl 103) (nx 1) 0x00000000 imm-test.c
+File
+[ 2](sec 1)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x00000000 .text
+AUX scnlen 0xe0 nreloc 1 nlnno 0
+[ 4](sec 2)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000e0 .data
+AUX scnlen 0x0 nreloc 0 nlnno 0
+[ 6](sec 3)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000e0 .bss
+AUX scnlen 0x0 nreloc 0 nlnno 0
+[ 8](sec 4)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x000000e0 .comment
+AUX scnlen 0x20 nreloc 0 nlnno 0
+[ 10](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _falsep
+[ 11](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000008 _ntc_falsep
+[ 12](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000000e _nullp
+[ 13](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000016 _ntc_nullp
+[ 14](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000001e _consp
+[ 15](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000026 _ntc_consp
+[ 16](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000036 _memq
+[ 17](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000050 _ntc_memq
+[ 18](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000082 _and
+[ 19](sec 1)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x0000009e _ntc_and
+[ 20](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000004 _scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <_falsep>:
+ 0: 60 43 mov r4,r0
+ 2: 88 06 cmp/eq #6,r0
+ 4: 00 0b rts
+ 6: 00 29 movt r0
+
+00000008 <_ntc_falsep>:
+ 8: 24 48 tst r4,r4
+ a: 00 0b rts
+ c: 00 29 movt r0
+
+0000000e <_nullp>:
+ e: 60 43 mov r4,r0
+ 10: 88 26 cmp/eq #38,r0
+ 12: 00 0b rts
+ 14: 00 29 movt r0
+
+00000016 <_ntc_nullp>:
+ 16: 60 43 mov r4,r0
+ 18: 88 02 cmp/eq #2,r0
+ 1a: 00 0b rts
+ 1c: 00 29 movt r0
+
+0000001e <_consp>:
+ 1e: 60 43 mov r4,r0
+ 20: c8 06 tst #6,r0
+ 22: 00 0b rts
+ 24: 00 29 movt r0
+
+00000026 <_ntc_consp>:
+ 26: 60 43 mov r4,r0
+ 28: c8 06 tst #6,r0
+ 2a: 01 29 movt r1
+ 2c: e0 ff mov #-1,r0
+ 2e: 24 48 tst r4,r4
+ 30: 60 0a negc r0,r0
+ 32: 00 0b rts
+ 34: 20 19 and r1,r0
+
+00000036 <_memq>:
+ 36: 60 53 mov r5,r0
+ 38: c8 06 tst #6,r0
+ 3a: 8b 06 bf 4a <_memq+0x14>
+ 3c: 61 02 mov.l @r0,r1
+ 3e: 31 40 cmp/eq r4,r1
+ 40: 8d 04 bt.s 4c <_memq+0x16>
+ 42: 61 03 mov r0,r1
+ 44: 50 01 mov.l @(4,r0),r0
+ 46: c8 06 tst #6,r0
+ 48: 89 f8 bt 3c <_memq+0x6>
+ 4a: e1 06 mov #6,r1
+ 4c: 00 0b rts
+ 4e: 60 13 mov r1,r0
+
+00000050 <_ntc_memq>:
+ 50: 60 53 mov r5,r0
+ 52: e1 ff mov #-1,r1
+ 54: c8 06 tst #6,r0
+ 56: 02 29 movt r2
+ 58: 25 58 tst r5,r5
+ 5a: 61 1a negc r1,r1
+ 5c: 21 29 and r2,r1
+ 5e: 21 18 tst r1,r1
+ 60: 89 0c bt 7c <_ntc_memq+0x2c>
+ 62: 61 02 mov.l @r0,r1
+ 64: 31 40 cmp/eq r4,r1
+ 66: 8d 0a bt.s 7e <_ntc_memq+0x2e>
+ 68: 61 03 mov r0,r1
+ 6a: 50 01 mov.l @(4,r0),r0
+ 6c: e1 ff mov #-1,r1
+ 6e: c8 06 tst #6,r0
+ 70: 02 29 movt r2
+ 72: 20 08 tst r0,r0
+ 74: 61 1a negc r1,r1
+ 76: 21 29 and r2,r1
+ 78: 21 18 tst r1,r1
+ 7a: 8b f2 bf 62 <_ntc_memq+0x12>
+ 7c: e1 00 mov #0,r1
+ 7e: 00 0b rts
+ 80: 60 13 mov r1,r0
+
+00000082 <_and>:
+ 82: 60 43 mov r4,r0
+ 84: c8 06 tst #6,r0
+ 86: 8f 06 bf.s 96 <_and+0x14>
+ 88: 88 06 cmp/eq #6,r0
+ 8a: 8d 05 bt.s 98 <_and+0x16>
+ 8c: e1 06 mov #6,r1
+ 8e: 50 01 mov.l @(4,r0),r0
+ 90: c8 06 tst #6,r0
+ 92: 8d fa bt.s 8a <_and+0x8>
+ 94: 88 06 cmp/eq #6,r0
+ 96: 91 01 mov.w 9c <_and+0x1a>,r1 ! 0xa6
+ 98: 00 0b rts
+ 9a: 60 13 mov r1,r0
+ 9c: 00 a6 mov.l r10,@(r0,r0)
+
+0000009e <_ntc_and>:
+ 9e: 60 43 mov r4,r0
+ a0: e1 ff mov #-1,r1
+ a2: c8 06 tst #6,r0
+ a4: 02 29 movt r2
+ a6: 24 48 tst r4,r4
+ a8: 61 1a negc r1,r1
+ aa: 21 29 and r2,r1
+ ac: 21 18 tst r1,r1
+ ae: 8d 0c bt.s ca <_ntc_and+0x2c>
+ b0: 20 08 tst r0,r0
+ b2: 8d 0c bt.s ce <_ntc_and+0x30>
+ b4: e1 00 mov #0,r1
+ b6: 50 01 mov.l @(4,r0),r0
+ b8: e1 ff mov #-1,r1
+ ba: c8 06 tst #6,r0
+ bc: 02 29 movt r2
+ be: 20 08 tst r0,r0
+ c0: 61 1a negc r1,r1
+ c2: 21 29 and r2,r1
+ c4: 21 18 tst r1,r1
+ c6: 8f f4 bf.s b2 <_ntc_and+0x14>
+ c8: 20 08 tst r0,r0
+ ca: d1 02 mov.l d4 <_ntc_and+0x36>,r1 ! 0x0
+ cc: 61 12 mov.l @r1,r1
+ ce: 00 0b rts
+ d0: 60 13 mov r1,r0
+ d2: 00 09 nop
+ d4: 00 00 .word 0x0000
+ d6: 00 00 .word 0x0000
+ d8: 00 09 nop
+ da: 00 09 nop
+ dc: 00 09 nop
+ de: 00 09 nop
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-avr.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-avr.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-avr.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,210 @@
+
+imm-test.o: file format elf32-avr
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000 .text
+00000000 l d .data 00000000 .data
+00000000 l d .bss 00000000 .bss
+0000003f l *ABS* 00000000 __SREG__
+0000003e l *ABS* 00000000 __SP_H__
+0000003d l *ABS* 00000000 __SP_L__
+00000000 l *ABS* 00000000 __tmp_reg__
+00000001 l *ABS* 00000000 __zero_reg__
+00000000 *UND* 00000000 __do_copy_data
+00000000 *UND* 00000000 __do_clear_bss
+00000000 g F .text 00000012 falsep
+00000012 g F .text 00000012 ntc_falsep
+00000024 g F .text 00000012 nullp
+00000036 g F .text 00000012 ntc_nullp
+00000048 g F .text 00000016 consp
+0000005e g F .text 0000001e ntc_consp
+0000007c g F .text 00000036 memq
+000000b2 g F .text 0000003a ntc_memq
+000000ec g F .text 0000002a and
+00000116 g F .text 00000030 ntc_and
+00000002 O *COM* 00000001 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 20 e0 ldi r18, 0x00 ; 0
+ 2: 30 e0 ldi r19, 0x00 ; 0
+ 4: 06 97 sbiw r24, 0x06 ; 6
+ 6: 11 f4 brne .+4 ; 0xc <falsep+0xc>
+ 8: 21 e0 ldi r18, 0x01 ; 1
+ a: 30 e0 ldi r19, 0x00 ; 0
+ c: 93 2f mov r25, r19
+ e: 82 2f mov r24, r18
+ 10: 08 95 ret
+
+00000012 <ntc_falsep>:
+ 12: 20 e0 ldi r18, 0x00 ; 0
+ 14: 30 e0 ldi r19, 0x00 ; 0
+ 16: 89 2b or r24, r25
+ 18: 11 f4 brne .+4 ; 0x1e <ntc_falsep+0xc>
+ 1a: 21 e0 ldi r18, 0x01 ; 1
+ 1c: 30 e0 ldi r19, 0x00 ; 0
+ 1e: 93 2f mov r25, r19
+ 20: 82 2f mov r24, r18
+ 22: 08 95 ret
+
+00000024 <nullp>:
+ 24: 20 e0 ldi r18, 0x00 ; 0
+ 26: 30 e0 ldi r19, 0x00 ; 0
+ 28: 86 97 sbiw r24, 0x26 ; 38
+ 2a: 11 f4 brne .+4 ; 0x30 <nullp+0xc>
+ 2c: 21 e0 ldi r18, 0x01 ; 1
+ 2e: 30 e0 ldi r19, 0x00 ; 0
+ 30: 93 2f mov r25, r19
+ 32: 82 2f mov r24, r18
+ 34: 08 95 ret
+
+00000036 <ntc_nullp>:
+ 36: 20 e0 ldi r18, 0x00 ; 0
+ 38: 30 e0 ldi r19, 0x00 ; 0
+ 3a: 02 97 sbiw r24, 0x02 ; 2
+ 3c: 11 f4 brne .+4 ; 0x42 <ntc_nullp+0xc>
+ 3e: 21 e0 ldi r18, 0x01 ; 1
+ 40: 30 e0 ldi r19, 0x00 ; 0
+ 42: 93 2f mov r25, r19
+ 44: 82 2f mov r24, r18
+ 46: 08 95 ret
+
+00000048 <consp>:
+ 48: 20 e0 ldi r18, 0x00 ; 0
+ 4a: 30 e0 ldi r19, 0x00 ; 0
+ 4c: 86 70 andi r24, 0x06 ; 6
+ 4e: 90 70 andi r25, 0x00 ; 0
+ 50: 89 2b or r24, r25
+ 52: 11 f4 brne .+4 ; 0x58 <consp+0x10>
+ 54: 21 e0 ldi r18, 0x01 ; 1
+ 56: 30 e0 ldi r19, 0x00 ; 0
+ 58: 93 2f mov r25, r19
+ 5a: 82 2f mov r24, r18
+ 5c: 08 95 ret
+
+0000005e <ntc_consp>:
+ 5e: 28 2f mov r18, r24
+ 60: 39 2f mov r19, r25
+ 62: 40 e0 ldi r20, 0x00 ; 0
+ 64: 50 e0 ldi r21, 0x00 ; 0
+ 66: 86 70 andi r24, 0x06 ; 6
+ 68: 90 70 andi r25, 0x00 ; 0
+ 6a: 89 2b or r24, r25
+ 6c: 21 f4 brne .+8 ; 0x76 <ntc_consp+0x18>
+ 6e: 23 2b or r18, r19
+ 70: 11 f0 breq .+4 ; 0x76 <ntc_consp+0x18>
+ 72: 41 e0 ldi r20, 0x01 ; 1
+ 74: 50 e0 ldi r21, 0x00 ; 0
+ 76: 95 2f mov r25, r21
+ 78: 84 2f mov r24, r20
+ 7a: 08 95 ret
+
+0000007c <memq>:
+ 7c: 28 2f mov r18, r24
+ 7e: 39 2f mov r19, r25
+ 80: f7 2f mov r31, r23
+ 82: e6 2f mov r30, r22
+ 84: 8e 2f mov r24, r30
+ 86: 9f 2f mov r25, r31
+ 88: 86 70 andi r24, 0x06 ; 6
+ 8a: 90 70 andi r25, 0x00 ; 0
+ 8c: 89 2b or r24, r25
+ 8e: 61 f4 brne .+24 ; 0xa8 <memq+0x2c>
+ 90: 80 81 ld r24, Z
+ 92: 91 81 ldd r25, Z+1 ; 0x01
+ 94: 82 17 cp r24, r18
+ 96: 93 07 cpc r25, r19
+ 98: 19 f4 brne .+6 ; 0xa0 <memq+0x24>
+ 9a: 6e 2f mov r22, r30
+ 9c: 7f 2f mov r23, r31
+ 9e: 06 c0 rjmp .+12 ; 0xac <memq+0x30>
+ a0: 02 80 ldd r0, Z+2 ; 0x02
+ a2: f3 81 ldd r31, Z+3 ; 0x03
+ a4: e0 2d mov r30, r0
+ a6: ee cf rjmp .-36 ; 0x84 <memq+0x8>
+ a8: 66 e0 ldi r22, 0x06 ; 6
+ aa: 70 e0 ldi r23, 0x00 ; 0
+ ac: 97 2f mov r25, r23
+ ae: 86 2f mov r24, r22
+ b0: 08 95 ret
+
+000000b2 <ntc_memq>:
+ b2: 28 2f mov r18, r24
+ b4: 39 2f mov r19, r25
+ b6: f7 2f mov r31, r23
+ b8: e6 2f mov r30, r22
+ ba: 0d c0 rjmp .+26 ; 0xd6 <ntc_memq+0x24>
+ bc: 30 97 sbiw r30, 0x00 ; 0
+ be: 89 f0 breq .+34 ; 0xe2 <ntc_memq+0x30>
+ c0: 80 81 ld r24, Z
+ c2: 91 81 ldd r25, Z+1 ; 0x01
+ c4: 82 17 cp r24, r18
+ c6: 93 07 cpc r25, r19
+ c8: 19 f4 brne .+6 ; 0xd0 <ntc_memq+0x1e>
+ ca: 6e 2f mov r22, r30
+ cc: 7f 2f mov r23, r31
+ ce: 0b c0 rjmp .+22 ; 0xe6 <ntc_memq+0x34>
+ d0: 02 80 ldd r0, Z+2 ; 0x02
+ d2: f3 81 ldd r31, Z+3 ; 0x03
+ d4: e0 2d mov r30, r0
+ d6: 8e 2f mov r24, r30
+ d8: 9f 2f mov r25, r31
+ da: 86 70 andi r24, 0x06 ; 6
+ dc: 90 70 andi r25, 0x00 ; 0
+ de: 89 2b or r24, r25
+ e0: 69 f3 breq .-38 ; 0xbc <ntc_memq+0xa>
+ e2: 60 e0 ldi r22, 0x00 ; 0
+ e4: 70 e0 ldi r23, 0x00 ; 0
+ e6: 97 2f mov r25, r23
+ e8: 86 2f mov r24, r22
+ ea: 08 95 ret
+
+000000ec <and>:
+ ec: f9 2f mov r31, r25
+ ee: e8 2f mov r30, r24
+ f0: 8e 2f mov r24, r30
+ f2: 9f 2f mov r25, r31
+ f4: 86 70 andi r24, 0x06 ; 6
+ f6: 90 70 andi r25, 0x00 ; 0
+ f8: 89 2b or r24, r25
+ fa: 51 f4 brne .+20 ; 0x110 <and+0x24>
+ fc: e6 30 cpi r30, 0x06 ; 6
+ fe: f1 05 cpc r31, r1
+ 100: 19 f4 brne .+6 ; 0x108 <and+0x1c>
+ 102: 8e 2f mov r24, r30
+ 104: 9f 2f mov r25, r31
+ 106: 08 95 ret
+ 108: 02 80 ldd r0, Z+2 ; 0x02
+ 10a: f3 81 ldd r31, Z+3 ; 0x03
+ 10c: e0 2d mov r30, r0
+ 10e: f0 cf rjmp .-32 ; 0xf0 <and+0x4>
+ 110: 86 ea ldi r24, 0xA6 ; 166
+ 112: 90 e0 ldi r25, 0x00 ; 0
+ 114: 08 95 ret
+
+00000116 <ntc_and>:
+ 116: f9 2f mov r31, r25
+ 118: e8 2f mov r30, r24
+ 11a: 0a c0 rjmp .+20 ; 0x130 <ntc_and+0x1a>
+ 11c: 30 97 sbiw r30, 0x00 ; 0
+ 11e: 71 f0 breq .+28 ; 0x13c <ntc_and+0x26>
+ 120: 30 97 sbiw r30, 0x00 ; 0
+ 122: 19 f4 brne .+6 ; 0x12a <ntc_and+0x14>
+ 124: 8e 2f mov r24, r30
+ 126: 9f 2f mov r25, r31
+ 128: 08 95 ret
+ 12a: 02 80 ldd r0, Z+2 ; 0x02
+ 12c: f3 81 ldd r31, Z+3 ; 0x03
+ 12e: e0 2d mov r30, r0
+ 130: 8e 2f mov r24, r30
+ 132: 9f 2f mov r25, r31
+ 134: 86 70 andi r24, 0x06 ; 6
+ 136: 90 70 andi r25, 0x00 ; 0
+ 138: 89 2b or r24, r25
+ 13a: 81 f3 breq .-32 ; 0x11c <ntc_and+0x6>
+ 13c: 80 91 00 00 lds r24, 0x0000
+ 140: 90 91 00 00 lds r25, 0x0000
+ 144: 08 95 ret
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-i486.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-i486.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-i486.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,111 @@
+
+imm-test.o: file format elf32-i386-freebsd
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .comment 00000000
+00000000 g F .text 0000000b falsep
+0000000b g F .text 0000000b ntc_falsep
+00000016 g F .text 0000000b nullp
+00000021 g F .text 0000000b ntc_nullp
+0000002c g F .text 0000000b consp
+00000037 g F .text 00000012 ntc_consp
+00000049 g F .text 0000001b memq
+00000064 g F .text 0000001c ntc_memq
+00000080 g F .text 00000018 and
+00000098 g F .text 00000017 ntc_and
+00000004 O *COM* 00000004 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 31 c0 xor %eax,%eax
+ 2: 83 7c 24 04 06 cmpl $0x6,0x4(%esp)
+ 7: 0f 94 c0 sete %al
+ a: c3 ret
+
+0000000b <ntc_falsep>:
+ b: 31 c0 xor %eax,%eax
+ d: 83 7c 24 04 00 cmpl $0x0,0x4(%esp)
+ 12: 0f 94 c0 sete %al
+ 15: c3 ret
+
+00000016 <nullp>:
+ 16: 31 c0 xor %eax,%eax
+ 18: 83 7c 24 04 26 cmpl $0x26,0x4(%esp)
+ 1d: 0f 94 c0 sete %al
+ 20: c3 ret
+
+00000021 <ntc_nullp>:
+ 21: 31 c0 xor %eax,%eax
+ 23: 83 7c 24 04 02 cmpl $0x2,0x4(%esp)
+ 28: 0f 94 c0 sete %al
+ 2b: c3 ret
+
+0000002c <consp>:
+ 2c: 31 c0 xor %eax,%eax
+ 2e: f6 44 24 04 06 testb $0x6,0x4(%esp)
+ 33: 0f 94 c0 sete %al
+ 36: c3 ret
+
+00000037 <ntc_consp>:
+ 37: 8b 54 24 04 mov 0x4(%esp),%edx
+ 3b: 31 c0 xor %eax,%eax
+ 3d: f6 c2 06 test $0x6,%dl
+ 40: 75 06 jne 48 <ntc_consp+0x11>
+ 42: 85 d2 test %edx,%edx
+ 44: 74 02 je 48 <ntc_consp+0x11>
+ 46: b0 01 mov $0x1,%al
+ 48: c3 ret
+
+00000049 <memq>:
+ 49: 8b 54 24 04 mov 0x4(%esp),%edx
+ 4d: 8b 44 24 08 mov 0x8(%esp),%eax
+ 51: a8 06 test $0x6,%al
+ 53: 75 09 jne 5e <memq+0x15>
+ 55: 39 10 cmp %edx,(%eax)
+ 57: 74 0a je 63 <memq+0x1a>
+ 59: 8b 40 04 mov 0x4(%eax),%eax
+ 5c: eb f3 jmp 51 <memq+0x8>
+ 5e: b8 06 00 00 00 mov $0x6,%eax
+ 63: c3 ret
+
+00000064 <ntc_memq>:
+ 64: 8b 54 24 04 mov 0x4(%esp),%edx
+ 68: 8b 44 24 08 mov 0x8(%esp),%eax
+ 6c: eb 0b jmp 79 <ntc_memq+0x15>
+ 6e: 85 c0 test %eax,%eax
+ 70: 74 0b je 7d <ntc_memq+0x19>
+ 72: 39 10 cmp %edx,(%eax)
+ 74: 74 09 je 7f <ntc_memq+0x1b>
+ 76: 8b 40 04 mov 0x4(%eax),%eax
+ 79: a8 06 test $0x6,%al
+ 7b: 74 f1 je 6e <ntc_memq+0xa>
+ 7d: 31 c0 xor %eax,%eax
+ 7f: c3 ret
+
+00000080 <and>:
+ 80: 8b 44 24 04 mov 0x4(%esp),%eax
+ 84: a8 06 test $0x6,%al
+ 86: 75 0a jne 92 <and+0x12>
+ 88: 83 f8 06 cmp $0x6,%eax
+ 8b: 74 0a je 97 <and+0x17>
+ 8d: 8b 40 04 mov 0x4(%eax),%eax
+ 90: eb f2 jmp 84 <and+0x4>
+ 92: b8 a6 00 00 00 mov $0xa6,%eax
+ 97: c3 ret
+
+00000098 <ntc_and>:
+ 98: 8b 44 24 04 mov 0x4(%esp),%eax
+ 9c: eb 07 jmp a5 <ntc_and+0xd>
+ 9e: 85 c0 test %eax,%eax
+ a0: 74 07 je a9 <ntc_and+0x11>
+ a2: 8b 40 04 mov 0x4(%eax),%eax
+ a5: a8 06 test $0x6,%al
+ a7: 74 f5 je 9e <ntc_and+0x6>
+ a9: a1 00 00 00 00 mov 0x0,%eax
+ ae: c3 ret
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro-i486.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro-i486.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro-i486.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,112 @@
+
+imm-test.o: file format elf32-i386-freebsd
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .comment 00000000
+00000000 g F .text 0000000b falsep
+0000000b g F .text 0000000b ntc_falsep
+00000016 g F .text 0000000b nullp
+00000021 g F .text 0000000b ntc_nullp
+0000002c g F .text 0000000b consp
+00000037 g F .text 00000017 ntc_consp
+0000004e g F .text 0000001b memq
+00000069 g F .text 0000001c ntc_memq
+00000085 g F .text 00000018 and
+0000009d g F .text 00000017 ntc_and
+00000004 O *COM* 00000004 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 31 c0 xor %eax,%eax
+ 2: 83 7c 24 04 06 cmpl $0x6,0x4(%esp)
+ 7: 0f 94 c0 sete %al
+ a: c3 ret
+
+0000000b <ntc_falsep>:
+ b: 31 c0 xor %eax,%eax
+ d: 83 7c 24 04 00 cmpl $0x0,0x4(%esp)
+ 12: 0f 94 c0 sete %al
+ 15: c3 ret
+
+00000016 <nullp>:
+ 16: 31 c0 xor %eax,%eax
+ 18: 83 7c 24 04 26 cmpl $0x26,0x4(%esp)
+ 1d: 0f 94 c0 sete %al
+ 20: c3 ret
+
+00000021 <ntc_nullp>:
+ 21: 31 c0 xor %eax,%eax
+ 23: 83 7c 24 04 02 cmpl $0x2,0x4(%esp)
+ 28: 0f 94 c0 sete %al
+ 2b: c3 ret
+
+0000002c <consp>:
+ 2c: 31 c0 xor %eax,%eax
+ 2e: f6 44 24 04 06 testb $0x6,0x4(%esp)
+ 33: 0f 94 c0 sete %al
+ 36: c3 ret
+
+00000037 <ntc_consp>:
+ 37: 8b 44 24 04 mov 0x4(%esp),%eax
+ 3b: 31 d2 xor %edx,%edx
+ 3d: a8 06 test $0x6,%al
+ 3f: 75 0a jne 4b <ntc_consp+0x14>
+ 41: 85 c0 test %eax,%eax
+ 43: b8 01 00 00 00 mov $0x1,%eax
+ 48: 0f 45 d0 cmovne %eax,%edx
+ 4b: 89 d0 mov %edx,%eax
+ 4d: c3 ret
+
+0000004e <memq>:
+ 4e: 8b 54 24 04 mov 0x4(%esp),%edx
+ 52: 8b 44 24 08 mov 0x8(%esp),%eax
+ 56: a8 06 test $0x6,%al
+ 58: 75 09 jne 63 <memq+0x15>
+ 5a: 39 10 cmp %edx,(%eax)
+ 5c: 74 0a je 68 <memq+0x1a>
+ 5e: 8b 40 04 mov 0x4(%eax),%eax
+ 61: eb f3 jmp 56 <memq+0x8>
+ 63: b8 06 00 00 00 mov $0x6,%eax
+ 68: c3 ret
+
+00000069 <ntc_memq>:
+ 69: 8b 54 24 04 mov 0x4(%esp),%edx
+ 6d: 8b 44 24 08 mov 0x8(%esp),%eax
+ 71: eb 0b jmp 7e <ntc_memq+0x15>
+ 73: 85 c0 test %eax,%eax
+ 75: 74 0b je 82 <ntc_memq+0x19>
+ 77: 39 10 cmp %edx,(%eax)
+ 79: 74 09 je 84 <ntc_memq+0x1b>
+ 7b: 8b 40 04 mov 0x4(%eax),%eax
+ 7e: a8 06 test $0x6,%al
+ 80: 74 f1 je 73 <ntc_memq+0xa>
+ 82: 31 c0 xor %eax,%eax
+ 84: c3 ret
+
+00000085 <and>:
+ 85: 8b 44 24 04 mov 0x4(%esp),%eax
+ 89: a8 06 test $0x6,%al
+ 8b: 75 0a jne 97 <and+0x12>
+ 8d: 83 f8 06 cmp $0x6,%eax
+ 90: 74 0a je 9c <and+0x17>
+ 92: 8b 40 04 mov 0x4(%eax),%eax
+ 95: eb f2 jmp 89 <and+0x4>
+ 97: b8 a6 00 00 00 mov $0xa6,%eax
+ 9c: c3 ret
+
+0000009d <ntc_and>:
+ 9d: 8b 44 24 04 mov 0x4(%esp),%eax
+ a1: eb 07 jmp aa <ntc_and+0xd>
+ a3: 85 c0 test %eax,%eax
+ a5: 74 07 je ae <ntc_and+0x11>
+ a7: 8b 40 04 mov 0x4(%eax),%eax
+ aa: a8 06 test $0x6,%al
+ ac: 74 f5 je a3 <ntc_and+0x6>
+ ae: a1 00 00 00 00 mov 0x0,%eax
+ b3: c3 ret
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro.txt
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro.txt 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test-gcc34-Os-ppro.txt 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,125 @@
+
+imm-test.o: file format elf32-i386-freebsd
+
+SYMBOL TABLE:
+00000000 l df *ABS* 00000000 imm-test.c
+00000000 l d .text 00000000
+00000000 l d .data 00000000
+00000000 l d .bss 00000000
+00000000 l d .comment 00000000
+00000000 g F .text 0000000b falsep
+0000000b g F .text 0000000b ntc_falsep
+00000016 g F .text 0000000b nullp
+00000021 g F .text 0000000b ntc_nullp
+0000002c g F .text 0000000b consp
+00000037 g F .text 00000014 ntc_consp
+0000004b g F .text 0000001b memq
+00000066 g F .text 0000002b ntc_memq
+00000091 g F .text 00000018 and
+000000a9 g F .text 00000027 ntc_and
+00000004 O *COM* 00000004 scm_ntc_true
+
+
+Disassembly of section .text:
+
+00000000 <falsep>:
+ 0: 31 c0 xor %eax,%eax
+ 2: 83 7c 24 04 06 cmpl $0x6,0x4(%esp)
+ 7: 0f 94 c0 sete %al
+ a: c3 ret
+
+0000000b <ntc_falsep>:
+ b: 31 c0 xor %eax,%eax
+ d: 83 7c 24 04 00 cmpl $0x0,0x4(%esp)
+ 12: 0f 94 c0 sete %al
+ 15: c3 ret
+
+00000016 <nullp>:
+ 16: 31 c0 xor %eax,%eax
+ 18: 83 7c 24 04 26 cmpl $0x26,0x4(%esp)
+ 1d: 0f 94 c0 sete %al
+ 20: c3 ret
+
+00000021 <ntc_nullp>:
+ 21: 31 c0 xor %eax,%eax
+ 23: 83 7c 24 04 02 cmpl $0x2,0x4(%esp)
+ 28: 0f 94 c0 sete %al
+ 2b: c3 ret
+
+0000002c <consp>:
+ 2c: 31 c0 xor %eax,%eax
+ 2e: f6 44 24 04 06 testb $0x6,0x4(%esp)
+ 33: 0f 94 c0 sete %al
+ 36: c3 ret
+
+00000037 <ntc_consp>:
+ 37: 8b 44 24 04 mov 0x4(%esp),%eax
+ 3b: a8 06 test $0x6,%al
+ 3d: 0f 94 c2 sete %dl
+ 40: 85 c0 test %eax,%eax
+ 42: 0f 95 c0 setne %al
+ 45: 0f b6 c0 movzbl %al,%eax
+ 48: 21 d0 and %edx,%eax
+ 4a: c3 ret
+
+0000004b <memq>:
+ 4b: 8b 54 24 04 mov 0x4(%esp),%edx
+ 4f: 8b 44 24 08 mov 0x8(%esp),%eax
+ 53: a8 06 test $0x6,%al
+ 55: 75 09 jne 60 <memq+0x15>
+ 57: 39 10 cmp %edx,(%eax)
+ 59: 74 0a je 65 <memq+0x1a>
+ 5b: 8b 40 04 mov 0x4(%eax),%eax
+ 5e: eb f3 jmp 53 <memq+0x8>
+ 60: b8 06 00 00 00 mov $0x6,%eax
+ 65: c3 ret
+
+00000066 <ntc_memq>:
+ 66: 53 push %ebx
+ 67: 8b 5c 24 08 mov 0x8(%esp),%ebx
+ 6b: 8b 4c 24 0c mov 0xc(%esp),%ecx
+ 6f: f6 c1 06 test $0x6,%cl
+ 72: 0f 94 c0 sete %al
+ 75: 31 d2 xor %edx,%edx
+ 77: 85 c9 test %ecx,%ecx
+ 79: 0f 95 c2 setne %dl
+ 7c: 85 d0 test %edx,%eax
+ 7e: 74 0d je 8d <ntc_memq+0x27>
+ 80: 39 19 cmp %ebx,(%ecx)
+ 82: 75 04 jne 88 <ntc_memq+0x22>
+ 84: 89 c8 mov %ecx,%eax
+ 86: eb 07 jmp 8f <ntc_memq+0x29>
+ 88: 8b 49 04 mov 0x4(%ecx),%ecx
+ 8b: eb e2 jmp 6f <ntc_memq+0x9>
+ 8d: 31 c0 xor %eax,%eax
+ 8f: 5b pop %ebx
+ 90: c3 ret
+
+00000091 <and>:
+ 91: 8b 44 24 04 mov 0x4(%esp),%eax
+ 95: a8 06 test $0x6,%al
+ 97: 75 0a jne a3 <and+0x12>
+ 99: 83 f8 06 cmp $0x6,%eax
+ 9c: 74 0a je a8 <and+0x17>
+ 9e: 8b 40 04 mov 0x4(%eax),%eax
+ a1: eb f2 jmp 95 <and+0x4>
+ a3: b8 a6 00 00 00 mov $0xa6,%eax
+ a8: c3 ret
+
+000000a9 <ntc_and>:
+ a9: 8b 4c 24 04 mov 0x4(%esp),%ecx
+ ad: f6 c1 06 test $0x6,%cl
+ b0: 0f 94 c0 sete %al
+ b3: 31 d2 xor %edx,%edx
+ b5: 85 c9 test %ecx,%ecx
+ b7: 0f 95 c2 setne %dl
+ ba: 85 d0 test %edx,%eax
+ bc: 74 0c je ca <ntc_and+0x21>
+ be: 85 c9 test %ecx,%ecx
+ c0: 75 03 jne c5 <ntc_and+0x1c>
+ c2: 31 c0 xor %eax,%eax
+ c4: c3 ret
+ c5: 8b 49 04 mov 0x4(%ecx),%ecx
+ c8: eb e3 jmp ad <ntc_and+0x4>
+ ca: a1 00 00 00 00 mov 0x0,%eax
+ cf: c3 ret
Added: branches/r5rs/sigscheme/experimental/imm-const/imm-test.c
===================================================================
--- branches/r5rs/sigscheme/experimental/imm-const/imm-test.c 2005-10-15 15:05:03 UTC (rev 1840)
+++ branches/r5rs/sigscheme/experimental/imm-const/imm-test.c 2005-10-15 19:58:29 UTC (rev 1841)
@@ -0,0 +1,179 @@
+/*===========================================================================
+ * FileName : imm-test.c
+ * About : Efficiency evaluation for immediate constant values (temporary)
+ *
+ * Copyright (C) 2005 by YamaKen
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of authors nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+===========================================================================*/
+
+#define NULL ((void *)0)
+
+#define SCM_VALUE_MASK (~0 ^ (SCM_GCBIT_MASK | SCM_TAG_MASK))
+
+#define SCM_GCBIT_MASK 0x1
+#define SCM_GCBIT_UNMARKED 0x0
+#define SCM_GCBIT_MARKED 0x1
+
+#define SCM_TAG_MASK 0x6
+#define SCM_TAG_CONS 0x0
+#define SCM_TAG_CLOSURE 0x2
+#define SCM_TAG_OTHERS 0x4
+#define SCM_TAG_IMM 0x6
+
+#define SCM_IMM_TAG_MASK 0x18
+#define SCM_IMM_TAG_CONST 0x00
+#define SCM_IMM_TAG_CHAR 0x10
+#define SCM_IMM_TAG_INT_EVEN 0x08
+#define SCM_IMM_TAG_INT_ODD 0x18
+
+#define SCM_IMM_CONST_OFFSET 5
+
+#define SCM_IMMCONST(id) \
+ ((ScmObj)((id << SCM_IMM_CONST_OFFSET) | SCM_IMM_TAG_CONST | SCM_TAG_IMM))
+
+#define SCM_FALSE SCM_IMMCONST(0x0)
+#define SCM_NULL SCM_IMMCONST(0x1)
+#define SCM_UNBOUND SCM_IMMCONST(0x2)
+#define SCM_EOF SCM_IMMCONST(0x3)
+#define SCM_UNDEF SCM_IMMCONST(0x4)
+#define SCM_TRUE SCM_IMMCONST(0x5)
+
+/* NULL|tag style const representation */
+#define SCM_NULLTAG_CONST_FALSE ((ScmObj)((int)NULL | SCM_TAG_CONS))
+#define SCM_NULLTAG_CONST_NULL ((ScmObj)((int)NULL | SCM_TAG_CLOSURE))
+#define SCM_NULLTAG_CONST_UNBOUND ((ScmObj)((int)NULL | SCM_TAG_OTHERS))
+#define SCM_NULLTAG_CONST_TRUE scm_ntc_true
+
+#define FALSEP(obj) (obj == SCM_FALSE)
+#define NULLTAG_CONST_FALSEP(obj) (obj == SCM_NULLTAG_CONST_FALSE)
+
+#define NULLP(obj) (obj == SCM_NULL)
+#define NULLTAG_CONST_NULLP(obj) (obj == SCM_NULLTAG_CONST_NULL)
+
+#define CONSP(obj) ((((int)obj) & SCM_TAG_MASK) == SCM_TAG_CONS)
+#define NULLTAG_CONST_CONSP(obj) \
+ (((((int)obj) & SCM_TAG_MASK) == SCM_TAG_CONS) \
+ && (obj != SCM_NULLTAG_CONST_FALSE))
+
+#define CAR(cell) (((ScmCell *)cell)->car)
+#define CDR(cell) (((ScmCell *)cell)->cdr)
+
+typedef struct ScmCell_ ScmCell;
+struct ScmCell_ {
+ void *car;
+ void *cdr;
+};
+
+typedef ScmCell *ScmObj;
+
+ScmObj scm_ntc_true;
+
+int
+falsep(ScmObj obj)
+{
+ return (obj == SCM_FALSE);
+}
+
+int
+ntc_falsep(ScmObj obj)
+{
+ return (obj == SCM_NULLTAG_CONST_FALSE);
+}
+
+int
+nullp(ScmObj obj)
+{
+ return (obj == SCM_NULL);
+}
+
+int
+ntc_nullp(ScmObj obj)
+{
+ return (obj == SCM_NULLTAG_CONST_NULL);
+}
+
+int
+consp(ScmObj obj)
+{
+ return CONSP(obj);
+}
+
+int
+ntc_consp(ScmObj obj)
+{
+ return NULLTAG_CONST_CONSP(obj);
+}
+
+ScmObj
+memq(ScmObj key, ScmObj lst)
+{
+ ScmObj rest;
+
+ for (rest = lst; CONSP(rest); rest = CDR(rest)) {
+ if (CAR(rest) == key)
+ return rest;
+ }
+ return SCM_FALSE;
+}
+
+ScmObj
+ntc_memq(ScmObj key, ScmObj lst)
+{
+ ScmObj rest;
+
+ for (rest = lst; NULLTAG_CONST_CONSP(rest); rest = CDR(rest)) {
+ if (CAR(rest) == key)
+ return rest;
+ }
+ return SCM_NULLTAG_CONST_FALSE;
+}
+
+ScmObj
+and(ScmObj lst)
+{
+ ScmObj rest;
+
+ for (rest = lst; CONSP(rest); rest = CDR(rest)) {
+ if (FALSEP(rest))
+ return SCM_FALSE;
+ }
+ return SCM_TRUE;
+}
+
+ScmObj
+ntc_and(ScmObj lst)
+{
+ ScmObj rest;
+
+ for (rest = lst; NULLTAG_CONST_CONSP(rest); rest = CDR(rest)) {
+ if (NULLTAG_CONST_FALSEP(rest))
+ return SCM_NULLTAG_CONST_FALSE;
+ }
+ return SCM_NULLTAG_CONST_TRUE;
+}
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