[virglrenderer-devel] [PATCH 07/12] arb_gpu_shader5: add extra gpu shader instructions.

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

This adds the bitfield and multiplies and barrier.
---
 src/vrend_shader.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/src/vrend_shader.c b/src/vrend_shader.c
index f54efb1..2585155 100644
--- a/src/vrend_shader.c
+++ b/src/vrend_shader.c
@@ -152,6 +152,7 @@ struct dump_ctx {
    bool vs_has_pervertex;
    bool uses_sample_shading;
    bool uses_gpu_shader5;
+   bool write_mul_temp;
 };
 
 static inline const char *tgsi_proc_to_prefix(int shader_type)
@@ -2342,6 +2343,62 @@ iter_instruction(struct tgsi_iterate_context *iter,
       EMIT_BUF_WITH_RET(ctx, buf);
       break;
    }
+   case TGSI_OPCODE_UMUL_HI:
+      snprintf(buf, 255, "umulExtended(%s, %s, umul_temp, mul_temp);\n", srcs[0], srcs[1]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      snprintf(buf, 255, "%s = %s(%s(umul_temp));\n", dsts[0], dstconv, dtypeprefix);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      ctx->write_mul_temp = true;
+      break;
+   case TGSI_OPCODE_IMUL_HI:
+      snprintf(buf, 255, "imulExtended(%s, %s, imul_temp, mul_temp);\n", srcs[0], srcs[1]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      snprintf(buf, 255, "%s = %s(%s(imul_temp));\n", dsts[0], dstconv, dtypeprefix);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      ctx->write_mul_temp = true;
+      break;
+
+   case TGSI_OPCODE_IBFE:
+      snprintf(buf, 255, "%s = %s(%s(bitfieldExtract(%s, int(%s.x), int(%s.x))));\n", dsts[0], dstconv, dtypeprefix, srcs[0], srcs[1], srcs[2]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_UBFE:
+      snprintf(buf, 255, "%s = %s(%s(bitfieldExtract(%s, int(%s.x), int(%s.x))));\n", dsts[0], dstconv, dtypeprefix, srcs[0], srcs[1], srcs[2]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_BFI:
+      snprintf(buf, 255, "%s = %s(uintBitsToFloat(bitfieldInsert(%s, %s, int(%s), int(%s))));\n", dsts[0], dstconv, srcs[0], srcs[1], srcs[2], srcs[3]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_BREV:
+      snprintf(buf, 255, "%s = %s(%s(bitfieldReverse(%s)));\n", dsts[0], dstconv, dtypeprefix, srcs[0]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_POPC:
+      snprintf(buf, 255, "%s = %s(%s(bitCount(%s)));\n", dsts[0], dstconv, dtypeprefix, srcs[0]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_LSB:
+      snprintf(buf, 255, "%s = %s(%s(findLSB(%s)));\n", dsts[0], dstconv, dtypeprefix, srcs[0]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_IMSB:
+   case TGSI_OPCODE_UMSB:
+      snprintf(buf, 255, "%s = %s(%s(findMSB(%s)));\n", dsts[0], dstconv, dtypeprefix, srcs[0]);
+      EMIT_BUF_WITH_RET(ctx, buf);
+      ctx->uses_gpu_shader5 = true;
+      break;
+   case TGSI_OPCODE_BARRIER:
+      snprintf(buf, 255, "barrier();\n");
+      break;
    default:
       fprintf(stderr,"failed to convert opcode %d\n", inst->Instruction.Opcode);
       break;
@@ -2709,6 +2766,15 @@ static char *emit_ios(struct dump_ctx *ctx, char *glsl_hdr)
       STRCAT_WITH_RET(glsl_hdr, buf);
    }
 
+   if (ctx->write_mul_temp) {
+      snprintf(buf, 255, "uvec4 mul_temp;\n");
+      STRCAT_WITH_RET(glsl_hdr, buf);
+      snprintf(buf, 255, "uvec4 umul_temp;\n");
+      STRCAT_WITH_RET(glsl_hdr, buf);
+      snprintf(buf, 255, "ivec4 imul_temp;\n");
+      STRCAT_WITH_RET(glsl_hdr, buf);
+   }
+
    for (i = 0; i < ctx->num_address; i++) {
       snprintf(buf, 255, "int addr%d;\n", i);
       STRCAT_WITH_RET(glsl_hdr, buf);
-- 
2.14.3