[virglrenderer-devel] coherent memory access for virgl

[Gerd Hoffmann]

  Hi,

> > Using the pci bar also for non-coherent buffers becomes tricky.  The
> > buffer is out-of-reach for the guest.  We can ask the host gbm_bo_map()
> > the buffer and place it in the pci bar for access.  But it's not
> > permanent (unless we can change libgbm as outlined above).  I'm not sure
> > how to model that best in ttm ...
> 
> There are three possible cases:
> 
> 1) Coherent -- guest can keep the resource mapped (most Intel, ARM
> display drivers since they primarily use uncached / write_combine
> memory)
> 2) Non-coherent, but sync-able (non-LLC Intel platorms, MSM)
> 3) Non-coherent and no-flush/invalidate mechanism exposed yet (AMD)
> 
> We should make these realities explicit to guest user space through
> the flags (i.e, REQUIRES_SYNC, MEMORY_COHERENT etc.).

Hmm, sounds like coherency is more a property of the hardware, not of
the buffer.  Or does hardware exist which supports both (coherent and
non-coherent) kinds of buffers, and you have to ask for the coherent
variant if you need it?

> gbm.h doesn't expose these capabilities yet, but I can imagine a
> virglrenderer function that queries for this information in response
> to the resource_info ioctl.

Well, for now I'm looking at the virtio protocol level.  resource_info
simply doesn't exist there, so that must be tackled first before we can
figure the best way to tell userspace.

cheers,
  Gerd