[RFC 16/33] drm/i915/color: Add color pipeline for HDR planes

[Uma Shankar]

Add color pipeline for HDR planes. It consists of the following
hardware blocks.

* Pre-CSC : This block can used to linearize the input frame buffer data.
 	     The linear data then can be further acted on by the following
            color hardware blocks in the display hardware pipeline

* CSC/CTM: Used to program color transformation matrix, this block is used
           to perform color space conversions like BT2020 to BT709 or BT601
           etc. This block acts on the linearized data coming from the
           Pre-CSC HW block.

* Post-CSC: This HW block can be used to non-linearize frame buffer data to
            match the sink. Another use case of it could be to perform Tone
            mapping for HDR use-cases.

Co-developed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah at intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah at intel.com>
Signed-off-by: Uma Shankar <uma.shankar at intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 58b6d70043ca..8c2a858fc452 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3941,6 +3941,24 @@ static const struct drm_color_lut_range xelpd_post_csc_hdr[] = {
 	},
 };
 
+struct drm_color_op color_pipeline_hdr[] = {
+	{
+		.name = DRM_CB_PRE_CSC,
+		.type = CURVE_1D,
+		.blob_id = 0, /* To be updated during plane initialization */
+	},
+	{
+		.name = DRM_CB_CSC,
+		.type = MATRIX,
+		.blob_id = 0,
+	},
+	{
+		.name = DRM_CB_POST_CSC,
+		.type = CURVE_1D,
+		.blob_id = 0,
+	},
+};
+
 void intel_color_crtc_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-- 
2.38.1