xf86-video-ati: Branch 'master' - 3 commits
Michel Daenzer
daenzer at kemper.freedesktop.org
Thu Dec 7 19:42:25 EET 2006
src/radeon.h | 12 ++
src/radeon_display.c | 9 -
src/radeon_dri.c | 46 ---------
src/radeon_driver.c | 237 +++++++++++++++++++++++++--------------------------
src/radeon_reg.h | 3
5 files changed, 135 insertions(+), 172 deletions(-)
New commits:
diff-tree ccd37b3e88cdcfe03b7c707b6082339eb8f11e6b (from 02be8c04a268eaa71bdfe891331758715fef4e71)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Thu Dec 7 18:41:48 2006 +0100
radeon: Move Xv option handling code into RADEONPreInitXv().
This unclutters RADEONPreInit() somewhat, but more importantly moves comparison
against info->ChipFamily after that's initialized.
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index f529629..566197c 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -2750,6 +2750,119 @@ static Bool RADEONPreInitXv(ScrnInfoPtr
CARD16 mm_table;
CARD16 bios_header;
CARD16 pll_info_block;
+#ifdef XvExtension
+ char* microc_path = NULL;
+ char* microc_type = NULL;
+ MessageType from;
+
+ if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY,
+ &(info->videoKey))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n",
+ info->videoKey);
+ } else {
+ info->videoKey = 0x1E;
+ }
+
+ if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n",
+ info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100);
+ } else {
+ info->RageTheatreCrystal=-1;
+ }
+
+ if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n",
+ info->RageTheatreTunerPort);
+ } else {
+ info->RageTheatreTunerPort=-1;
+ }
+
+ if(info->RageTheatreTunerPort>5){
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n");
+ info->RageTheatreTunerPort=-1;
+ }
+
+ if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n",
+ info->RageTheatreCompositePort);
+ } else {
+ info->RageTheatreCompositePort=-1;
+ }
+
+ if(info->RageTheatreCompositePort>6){
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n");
+ info->RageTheatreCompositePort=-1;
+ }
+
+ if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n",
+ info->RageTheatreSVideoPort);
+ } else {
+ info->RageTheatreSVideoPort=-1;
+ }
+
+ if(info->RageTheatreSVideoPort>6){
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n");
+ info->RageTheatreSVideoPort=-1;
+ }
+
+ if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n",
+ info->tunerType);
+ } else {
+ info->tunerType=-1;
+ }
+
+ if(info->tunerType>31){
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n");
+ info->tunerType=-1;
+ }
+
+ if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL)
+ {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path);
+ info->RageTheatreMicrocPath = microc_path;
+ } else {
+ info->RageTheatreMicrocPath= NULL;
+ }
+
+ if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL)
+ {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type);
+ info->RageTheatreMicrocType = microc_type;
+ } else {
+ info->RageTheatreMicrocType= NULL;
+ }
+
+ if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) {
+ if ((info->overlay_scaler_buffer_width < 1024) ||
+ (info->overlay_scaler_buffer_width > 2048) ||
+ ((info->overlay_scaler_buffer_width % 64) != 0)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n");
+ from = X_DEFAULT;
+ info->overlay_scaler_buffer_width = 0;
+ } else
+ from = X_CONFIG;
+ } else {
+ from = X_DEFAULT;
+ info->overlay_scaler_buffer_width = 0;
+ }
+ if (!info->overlay_scaler_buffer_width) {
+ /* overlay scaler line length differs for different revisions
+ this needs to be maintained by hand */
+ switch(info->ChipFamily){
+ case CHIP_FAMILY_R200:
+ case CHIP_FAMILY_R300:
+ case CHIP_FAMILY_RV350:
+ info->overlay_scaler_buffer_width = 1920;
+ break;
+ default:
+ info->overlay_scaler_buffer_width = 1536;
+ }
+ }
+ xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n",
+ info->overlay_scaler_buffer_width);
+#endif
/* Rescue MM_TABLE before VBIOS is freed */
info->MM_TABLE_valid = FALSE;
@@ -2860,8 +2973,6 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr
xf86Int10InfoPtr pInt10 = NULL;
void *int10_save = NULL;
const char *s;
- char* microc_path = NULL;
- char* microc_type = NULL;
MessageType from;
RADEONTRACE(("RADEONPreInit\n"));
@@ -3007,117 +3118,6 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr
if (!RADEONPreInitWeight(pScrn))
goto fail;
-#ifdef XvExtension
- if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY,
- &(info->videoKey))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n",
- info->videoKey);
- } else {
- info->videoKey = 0x1E;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n",
- info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100);
- } else {
- info->RageTheatreCrystal=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n",
- info->RageTheatreTunerPort);
- } else {
- info->RageTheatreTunerPort=-1;
- }
-
- if(info->RageTheatreTunerPort>5){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n");
- info->RageTheatreTunerPort=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n",
- info->RageTheatreCompositePort);
- } else {
- info->RageTheatreCompositePort=-1;
- }
-
- if(info->RageTheatreCompositePort>6){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n");
- info->RageTheatreCompositePort=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n",
- info->RageTheatreSVideoPort);
- } else {
- info->RageTheatreSVideoPort=-1;
- }
-
- if(info->RageTheatreSVideoPort>6){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n");
- info->RageTheatreSVideoPort=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n",
- info->tunerType);
- } else {
- info->tunerType=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) {
- if ((info->overlay_scaler_buffer_width < 1024) ||
- (info->overlay_scaler_buffer_width > 2048) ||
- ((info->overlay_scaler_buffer_width % 64) != 0)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n");
- from = X_DEFAULT;
- info->overlay_scaler_buffer_width = 0;
- } else
- from = X_CONFIG;
- } else {
- from = X_DEFAULT;
- info->overlay_scaler_buffer_width = 0;
- }
- if (!info->overlay_scaler_buffer_width) {
- /* overlay scaler line length differs for different revisions
- this needs to be maintained by hand */
- switch(info->ChipFamily){
- case CHIP_FAMILY_R200:
- case CHIP_FAMILY_R300:
- case CHIP_FAMILY_RV350:
- info->overlay_scaler_buffer_width = 1920;
- break;
- default:
- info->overlay_scaler_buffer_width = 1536;
- }
- }
- xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n",
- info->overlay_scaler_buffer_width);
-
- if(info->tunerType>31){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n");
- info->tunerType=-1;
- }
-
- if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path);
- info->RageTheatreMicrocPath = microc_path;
- } else {
- info->RageTheatreMicrocPath= NULL;
- }
-
- if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type);
- info->RageTheatreMicrocType = microc_type;
- } else {
- info->RageTheatreMicrocType= NULL;
- }
-
-#endif
-
info->DispPriority = 1;
if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) {
if (strcmp(s, "AUTO") == 0) {
diff-tree 02be8c04a268eaa71bdfe891331758715fef4e71 (from be46f7b6f7a729695a0affe2328077666283af12)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Thu Dec 7 18:31:58 2006 +0100
radeon: Make cache flushing for R300 series less invasive.
Instead of calling the DRM CP idle ioctl, just emit the cache flush commands
into the CP stream.
diff --git a/src/radeon.h b/src/radeon.h
index d13beeb..4c3cbcc 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -621,6 +621,7 @@ typedef struct {
int CPMode; /* CP mode that server/clients use */
int CPFifoSize; /* Size of the CP command FIFO */
int CPusecTimeout; /* CP timeout in usecs */
+ Bool needCacheFlush;
/* CP ring buffer data */
unsigned long ringStart; /* Offset into GART space */
@@ -986,6 +987,11 @@ do { \
#define RADEONCP_REFRESH(pScrn, info) \
do { \
if (!info->CPInUse) { \
+ if (info->needCacheFlush) { \
+ RADEON_PURGE_CACHE(); \
+ RADEON_PURGE_ZCACHE(); \
+ info->needCacheFlush = FALSE; \
+ } \
RADEON_WAIT_UNTIL_IDLE(); \
BEGIN_RING(6); \
OUT_RING_REG(RADEON_RE_TOP_LEFT, info->re_top_left); \
@@ -1132,6 +1138,12 @@ do { \
ADVANCE_RING(); \
} while (0)
+#define RADEON_PURGE_ZCACHE() \
+do { \
+ OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
+ OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
+} while (0)
+
#endif /* XF86DRI */
static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 70ff288..e223825 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -357,50 +357,10 @@ static void RADEONEnterServer(ScreenPtr
RADEON_MARK_SYNC(info, pScrn);
pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen))
+ if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen)) {
info->XInited3D = FALSE;
-
-
- /* TODO: Fix this more elegantly.
- * Sometimes (especially with multiple DRI clients), this code
- * runs immediately after a DRI client issues a rendering command.
- *
- * The accel code regularly inserts WAIT_UNTIL_IDLE into the
- * command buffer that is sent with the indirect buffer below.
- * The accel code fails to set the 3D cache flush registers for
- * the R300 before sending WAIT_UNTIL_IDLE. Sending a cache flush
- * on these new registers is not necessary for pure 2D functionality,
- * but it *is* necessary after 3D operations.
- * Without the cache flushes before WAIT_UNTIL_IDLE, the R300 locks up.
- *
- * The CP_IDLE call into the DRM indirectly flushes all caches and
- * thus avoids the lockup problem, but the solution is far from ideal.
- * Better solutions could be:
- * - always flush caches when entering the X server
- * - track the type of rendering commands somewhere and issue
- * cache flushes when they change
- * However, I don't feel confident enough with the control flow
- * inside the X server to implement either fix. -- nh
- */
-
- /* On my computer (Radeon Mobility M10)
- The fix below results in x11perf -shmput500 rate of 245.0/sec
- which is lower than 264.0/sec I get without it.
-
- Doing the same each time before indirect buffer is submitted
- results in x11perf -shmput500 rate of 225.0/sec.
-
- On the other hand, not using CP acceleration at all benchmarks
- at 144.0/sec.
-
- For now let us accept this as a lesser evil, especially as the
- DRM driver for R300 is still in flux.
-
- Once the code is more stable this should probably be moved into DRM driver.
- */
-
- if (info->ChipFamily>=CHIP_FAMILY_R300)
- drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE);
+ info->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
+ }
#ifdef DAMAGE
if (!info->pDamage && info->allowPageFlip) {
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 9503dde..a6bbe69 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1280,6 +1280,9 @@
# define RADEON_RB2D_DC_BUSY (1 << 31)
#define RADEON_RB2D_DSTCACHE_MODE 0x3428
+#define RADEON_RB3D_ZCACHE_MODE 0x3250
+#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
+# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
#define RADEON_RB3D_DSTCACHE_MODE 0x3258
# define RADEON_RB3D_DC_CACHE_ENABLE (0)
# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
diff-tree be46f7b6f7a729695a0affe2328077666283af12 (from 59c5b4f69c97fb233144677ab18095f88aed006b)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Thu Dec 7 16:27:10 2006 +0100
Fix radeon compile warnings.
diff --git a/src/radeon_display.c b/src/radeon_display.c
index a248428..3679e4f 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -1143,7 +1143,6 @@ void RADEONSetupConnectors(ScrnInfoPtr p
static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, int connector)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
if (info->IsMobility) {
@@ -1170,7 +1169,6 @@ static RADEONMonitorType RADEONPortCheck
/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, int connector)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONConnector *pPort = pRADEONEnt->PortInfo[connector];
@@ -1189,7 +1187,6 @@ static void RADEONQueryConnectedDisplays
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
const char *s;
Bool ignore_edid = FALSE;
@@ -2010,7 +2007,6 @@ static void RADEONBlankSet(ScrnInfoPtr p
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
switch(pPort->MonType) {
case MT_LCD:
@@ -2093,7 +2089,6 @@ static void RADEONUnblankSet(ScrnInfoPtr
{
RADEONInfoPtr info = RADEONPTR (pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
switch(pPort->MonType) {
case MT_LCD:
@@ -2161,7 +2156,6 @@ void RADEONUnblank(ScrnInfoPtr pScrn)
static void RADEONDPMSSetOn(ScrnInfoPtr pScrn, RADEONConnector *pPort)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
RADEONMonitorType MonType;
RADEONTmdsType TmdsType;
@@ -2199,7 +2193,6 @@ static void RADEONDPMSSetOn(ScrnInfoPtr
static void RADEONDPMSSetOff(ScrnInfoPtr pScrn, RADEONConnector *pPort)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
RADEONMonitorType MonType;
RADEONTmdsType TmdsType;
@@ -2358,7 +2351,6 @@ void RADEONDisplayPowerManagementSet(Scr
Bool RADEONAllocateControllers(ScrnInfoPtr pScrn)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- int num_crtc;
if (pRADEONEnt->Controller[0])
return TRUE;
@@ -2383,7 +2375,6 @@ Bool RADEONAllocateControllers(ScrnInfoP
Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- int num_connectors;
int i;
if (pRADEONEnt->PortInfo[0])
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 0ba4427..f529629 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -816,7 +816,6 @@ static int RADEONDiv(int n, int d)
static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONPLLPtr pll = &info->pll;
unsigned char *RADEONMMIO = info->MMIO;
unsigned char ppll_div_sel;
@@ -5846,7 +5845,6 @@ static Bool RADEONInitCrtcRegisters(Scrn
int hsync_wid;
int vsync_wid;
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- RADEONConnector *connector;
pRADEONEnt->Controller[0]->IsUsed = TRUE;
pRADEONEnt->Controller[0]->IsActive = TRUE;
@@ -7014,7 +7012,6 @@ static void
RADEONGetMergedFBOptions(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONConnector *connector;
char *strptr;
char *default_hsync = "28-33";
@@ -7213,10 +7210,10 @@ RADEONGetMergedFBOptions(ScrnInfoPtr pSc
}
/* xf86SetDDCproperties(info->CRT2pScrn, pRADEONEnt->MonInfo2); */
- if (connector = RADEONGetCrtcConnector(pScrn, 2))
- info->CRT2pScrn->monitor->DDC = connector->MonInfo;
- else
- info->CRT2pScrn->monitor->DDC = NULL;
+
+ connector = RADEONGetCrtcConnector(pScrn, 2);
+ info->CRT2pScrn->monitor->DDC = connector ? connector->MonInfo : NULL;
+
if (default_range) {
RADEONStrToRanges(info->CRT2pScrn->monitor->hsync, default_hsync, MAX_HSYNC);
RADEONStrToRanges(info->CRT2pScrn->monitor->vrefresh, default_vrefresh, MAX_VREFRESH);
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