xf86-video-intel: Branch 'modesetting' - 2 commits - src/i830_display.c
Eric Anholt
anholt at kemper.freedesktop.org
Wed Dec 13 22:05:16 EET 2006
src/i830_display.c | 16 ++++++++++++++++
1 files changed, 16 insertions(+)
New commits:
diff-tree 3fa5b3998353518c40e2fb0c28b425ee22c8d625 (from e27372e85a007d8a7e31678dbdb62755c22918bf)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 13 11:54:36 2006 -0800
Add magic double-write of the dpll register to fix mac mini cold boot.
diff --git a/src/i830_display.c b/src/i830_display.c
index c111145..37a6e32 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -758,6 +758,15 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
OUTREG(fp_reg, fp);
OUTREG(dpll_reg, dpll);
+
+ /* Magic re-write of the register for the Mac Mini. Without this, the
+ * first X invocation after a cold boot will stick in 4x pixel multiply
+ * mode. Alternatives that don't work include sleeping and doing an
+ * INREG for presumable pci write posting magic before and after the dpll
+ * write above.
+ */
+ OUTREG(dpll_reg, dpll);
+
if (IS_I965G(pI830)) {
int sdvo_pixel_multiply = adjusted_mode->Clock / mode->Clock;
OUTREG(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
diff-tree e27372e85a007d8a7e31678dbdb62755c22918bf (from df0a5a25aa72563a33731f8063602dd7faad8459)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 13 00:26:27 2006 -0800
Add some caution with PCI write posting and DPLL delays to i830_crtc_dpms.
While it doesn't specifically help/hurt my test case, we've seen enough
mysterious behavior that caution is probably warranted.
diff --git a/src/i830_display.c b/src/i830_display.c
index e4d8e9f..c111145 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -507,6 +507,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
/* Enable the DPLL */
temp = INREG(dpll_reg);
OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
+ (void)INREG(dpll_reg); /* write posting */
/* Wait for the clocks to stabilize. */
usleep(150);
@@ -538,6 +539,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
/* Flush the plane changes */
OUTREG(dspbase_reg, INREG(dspbase_reg));
+ (void)INREG(dspbase_reg); /* write posting */
if (!IS_I9XX(pI830)) {
/* Wait for vblank for the disable to take effect */
@@ -547,12 +549,17 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
/* Next, disable display pipes */
temp = INREG(pipeconf_reg);
OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
+ (void)INREG(pipeconf_reg); /* write posting */
/* Wait for vblank for the disable to take effect. */
i830WaitForVblank(pScrn);
temp = INREG(dpll_reg);
OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
+ (void)INREG(dpll_reg); /* write posting */
+
+ /* Wait for the clocks to turn off. */
+ usleep(150);
break;
}
}
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