xf86-video-intel: Branch 'modesetting' - 3 commits - src/ch7xxx/ch7xxx.c src/i810_reg.h src/i830_debug.c
Keith Packard
keithp at kemper.freedesktop.org
Thu Nov 2 21:57:37 EET 2006
src/ch7xxx/ch7xxx.c | 6 +-
src/i810_reg.h | 66 +++++++++++++++++++++++++
src/i830_debug.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 202 insertions(+), 4 deletions(-)
New commits:
diff-tree 2636d68663a02f6d9eaf36971706b67036ebf56c (from 786ec54c4c1540f4aced63ef21d567c3b9f3282e)
Author: Keith Packard <keithp at mandolin.keithp.com>
Date: Thu Nov 2 11:57:11 2006 -0800
Dump more registers for debug purposes
diff --git a/src/i830_debug.c b/src/i830_debug.c
index a48e9f2..802330e 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -41,6 +41,26 @@ static struct i830SnapshotRec {
char *name;
CARD32 regval;
} i830_snapshot[] = {
+ DEFINEREG(VCLK_DIVISOR_VGA0),
+ DEFINEREG(VCLK_DIVISOR_VGA1),
+ DEFINEREG(VCLK_POST_DIV),
+ DEFINEREG(DPLL_TEST),
+ DEFINEREG(D_STATE),
+ DEFINEREG(DSPCLK_GATE_D),
+ DEFINEREG(RENCLK_GATE_D1),
+ DEFINEREG(RENCLK_GATE_D2),
+/* DEFINEREG(RAMCLK_GATE_D), CRL only */
+ DEFINEREG(SDVOB),
+ DEFINEREG(SDVOC),
+/* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */
+/* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */
+ DEFINEREG(SDVOUDI),
+ DEFINEREG(DSPARB),
+ DEFINEREG(DSPFW1),
+ DEFINEREG(DSPFW2),
+ DEFINEREG(DSPFW3),
+
+
DEFINEREG(ADPA),
DEFINEREG(LVDS),
DEFINEREG(DVOA),
@@ -62,36 +82,46 @@ static struct i830SnapshotRec {
DEFINEREG(DSPAPOS),
DEFINEREG(DSPASIZE),
DEFINEREG(DSPABASE),
+ DEFINEREG(DSPASURF),
+ DEFINEREG(DSPATILEOFF),
DEFINEREG(PIPEACONF),
DEFINEREG(PIPEASRC),
DEFINEREG(FPA0),
DEFINEREG(FPA1),
DEFINEREG(DPLL_A),
+ DEFINEREG(DPLLAMD),
DEFINEREG(HTOTAL_A),
DEFINEREG(HBLANK_A),
DEFINEREG(HSYNC_A),
DEFINEREG(VTOTAL_A),
DEFINEREG(VBLANK_A),
DEFINEREG(VSYNC_A),
+ DEFINEREG(BCLRPAT_A),
+ DEFINEREG(VSYNCSHIFT_A),
DEFINEREG(DSPBCNTR),
DEFINEREG(DSPBSTRIDE),
DEFINEREG(DSPBPOS),
DEFINEREG(DSPBSIZE),
DEFINEREG(DSPBBASE),
+ DEFINEREG(DSPBSURF),
+ DEFINEREG(DSPBTILEOFF),
DEFINEREG(PIPEBCONF),
DEFINEREG(PIPEBSRC),
DEFINEREG(FPB0),
DEFINEREG(FPB1),
DEFINEREG(DPLL_B),
+ DEFINEREG(DPLLBMD),
DEFINEREG(HTOTAL_B),
DEFINEREG(HBLANK_B),
DEFINEREG(HSYNC_B),
DEFINEREG(VTOTAL_B),
DEFINEREG(VBLANK_B),
DEFINEREG(VSYNC_B),
+ DEFINEREG(BCLRPAT_B),
+ DEFINEREG(VSYNCSHIFT_B),
DEFINEREG(VCLK_DIVISOR_VGA0),
DEFINEREG(VCLK_DIVISOR_VGA1),
@@ -129,13 +159,115 @@ void i830CompareRegsToSnapshot(ScrnInfoP
}
}
+static void i830DumpIndexed (ScrnInfoPtr pScrn, char *name, int id, int val, int min, int max)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int i;
+
+ for (i = min; i <= max; i++) {
+ OUTREG8 (id, i);
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%18.18s%02x: 0x%02x\n",
+ name, i, INREG8(val));
+ }
+}
+
void i830DumpRegs (ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int i;
+ int fp, dpll;
+ int pipe;
+ int n, m1, m2, m, p1, p2;
+ int ref;
+ int dot;
+ int phase;
+ int msr;
+ int crt;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "DumpRegsBegin\n");
for (i = 0; i < NUM_I830_SNAPSHOTREGS; i++) {
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%10.10s: 0x%08x\n",
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%20.20s: 0x%08x\n",
i830_snapshot[i].name, (unsigned int) INREG(i830_snapshot[i].reg));
}
+ i830DumpIndexed (pScrn, "SR", 0x3c4, 0x3c5, 0, 7);
+ msr = INREG8(0x3cc);
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "%20.20s: 0x%02x\n",
+ "MSR", (unsigned int) msr);
+
+ if (msr & 1)
+ crt = 0x3d0;
+ else
+ crt = 0x3b0;
+ i830DumpIndexed (pScrn, "CR", crt + 4, crt + 5, 0, 0x24);
+ for (pipe = 0; pipe <= 1; pipe++)
+ {
+ fp = INREG(pipe == 0 ? FPA0 : FPB0);
+ dpll = INREG(pipe == 0 ? DPLL_A : DPLL_B);
+ switch ((dpll >> 24) & 0x3) {
+ case 0:
+ p2 = 10;
+ break;
+ case 1:
+ p2 = 5;
+ break;
+ default:
+ p2 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "p2 out of range\n");
+ break;
+ }
+ switch ((dpll >> 16) & 0xff) {
+ case 1:
+ p1 = 1; break;
+ case 2:
+ p1 = 2; break;
+ case 4:
+ p1 = 3; break;
+ case 8:
+ p1 = 4; break;
+ case 16:
+ p1 = 5; break;
+ case 32:
+ p1 = 6; break;
+ case 64:
+ p1 = 7; break;
+ case 128:
+ p1 = 8; break;
+ default:
+ p1 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "p1 out of range\n");
+ break;
+ }
+ switch ((dpll >> 13) & 0x3) {
+ case 0:
+ ref = 96000;
+ break;
+ default:
+ ref = 0;
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "ref out of range\n");
+ break;
+ }
+ phase = (dpll >> 9) & 0xf;
+ switch (phase) {
+ case 6:
+ break;
+ default:
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "phase %d out of range\n", phase);
+ break;
+ }
+ switch ((dpll >> 8) & 1) {
+ case 0:
+ break;
+ default:
+ xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "fp select out of range\n");
+ break;
+ }
+ n = ((fp >> 16) & 0x3f);
+ m1 = ((fp >> 8) & 0x3f);
+ m2 = ((fp >> 0) & 0x3f);
+ m = 5 * (m1 + 2) + (m2 + 2);
+ dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "pipe %s dot %d n %d m1 %d m2 %d p1 %d p2 %d\n",
+ pipe == 0 ? "A" : "B", dot, n, m1, m2, p1, p2);
+ }
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "DumpRegsEnd\n");
}
diff-tree 786ec54c4c1540f4aced63ef21d567c3b9f3282e (from 85e32ad2dadcce1134fcadb14ece8ff30f3925f2)
Author: Keith Packard <keithp at mandolin.keithp.com>
Date: Thu Nov 2 11:56:50 2006 -0800
Add a few more registers from the 965 spec
diff --git a/src/i810_reg.h b/src/i810_reg.h
index 34e6e53..31f8885 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -739,6 +739,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define VSYNC_A 0x60014
#define PIPEASRC 0x6001c
#define BCLRPAT_A 0x60020
+#define VSYNCSHIFT_A 0x60028
#define HTOTAL_B 0x61000
#define HBLANK_B 0x61004
@@ -748,6 +749,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define VSYNC_B 0x61014
#define PIPEBSRC 0x6101c
#define BCLRPAT_B 0x61020
+#define VSYNCSHIFT_B 0x61028
#define PP_STATUS 0x61200
# define PP_ON (1 << 31)
@@ -849,6 +851,28 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
/** @} */
+/* SDVO/UDI Multiplier/Divisor register */
+#define DPLLAMD 0x601c
+#define DPLLBMD 0x6020
+
+/* Hi res source UDI divider (-1), non-zeor for UDI fixed freq mode */
+# define DPLLMD_UDI_DIVIDER_HIRES_MASK (0x3f << 24)
+# define DPLLMD_UDI_DIVIDER_HIRES_SHIFT 24
+# define DPLLMD_UDI_DIVIDER_VGA_MASK (0x3f << 16)
+# define DPLLMD_UDI_DIVIDER_VGA_SHIFT 16
+# define DPLLMD_SDVOUDI_MULTIPLIER_HIRES_MASK (0x3f << 8)
+# define DPLLMD_SDVOUDI_MULTIPLIER_HIRES_SHIFT 8
+# define DPLLMD_SDVOUDI_MULTIPLIER_VGA_MASK (0x3f << 0)
+# define DPLLMD_SDVOUDI_MULTIPLIER_VGA_SHIFT 0
+
+#define DPLL_TEST 0x606c
+
+#define D_STATE 0x6104
+#define DSPCLK_GATE_D 0x6200
+#define RENCLK_GATE_D1 0x6204
+#define RENCLK_GATE_D2 0x6208
+#define RAMCLK_GATE_D 0x6210 /* CRL only */
+
#define BLC_PWM_CTL 0x61254
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
@@ -856,6 +880,21 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
+#define BLM_CTL 0x61260
+#define BLM_THRESHOLD_0 0x61270
+#define BLM_THRESHOLD_1 0x61274
+#define BLM_THRESHOLD_2 0x61278
+#define BLM_THRESHOLD_3 0x6127c
+#define BLM_THRESHOLD_4 0x61280
+#define BLM_THRESHOLD_5 0x61284
+
+#define BLM_ACCUMULATOR_0 0x61290
+#define BLM_ACCUMULATOR_1 0x61294
+#define BLM_ACCUMULATOR_2 0x61298
+#define BLM_ACCUMULATOR_3 0x6129c
+#define BLM_ACCUMULATOR_4 0x612a0
+#define BLM_ACCUMULATOR_5 0x612a4
+
#define FPA0 0x06040
#define FPA1 0x06044
#define FPB0 0x06048
@@ -907,6 +946,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
#define SDVOC_PRESERVE_MASK (1 << 17)
+#define UDIB_SVB_SHB_CODES 0x61144
+#define UDIB_SHA_BLANK_CODES 0x61148
+#define UDIB_START_END_FILL_CODES 0x6114c
+
+
+#define SDVOUDI 0x61150
+
#define I830_HTOTAL_MASK 0xfff0000
#define I830_HACTIVE_MASK 0x7ff
@@ -1554,6 +1600,19 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define PIPEACONF_GAMMA (1<<24)
#define PIPECONF_FORCE_BORDER (1<<25)
+#define PIPEAGCMAXRED 0x70010
+#define PIPEAGCMAXGREEN 0x70014
+#define PIPEAGCMAXBLUE 0x70018
+#define PIPEASTAT 0x70024
+
+#define DSPARB 0x70030
+#define DSPFW1 0x70034
+#define DSPFW2 0x70038
+#define DSPFW3 0x7003c
+#define PIPEAFRAMEHIGH 0x70040
+#define PIPEAFRAMEPIXEL 0x70044
+
+
#define PIPEBCONF 0x71008
#define PIPEBCONF_ENABLE (1<<31)
#define PIPEBCONF_DISABLE 0
@@ -1562,6 +1621,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#define PIPEBCONF_GAMMA (1<<24)
#define PIPEBCONF_PALETTE 0
+#define PIPEBGCMAXRED 0x71010
+#define PIPEBGCMAXGREEN 0x71014
+#define PIPEBGCMAXBLUE 0x71018
+#define PIPEBSTAT 0x71024
+#define PIPEBFRAMEHIGH 0x71040
+#define PIPEBFRAMEPIXEL 0x71044
+
#define DSPACNTR 0x70180
#define DSPBCNTR 0x71180
#define DISPLAY_PLANE_ENABLE (1<<31)
diff-tree 85e32ad2dadcce1134fcadb14ece8ff30f3925f2 (from ffbd6ca09bc2300bf967d7c248a559d85b8706e0)
Author: Keith Packard <keithp at mandolin.keithp.com>
Date: Thu Nov 2 11:56:12 2006 -0800
ch7xxxSaveRegs receives real type instead of void *
diff --git a/src/ch7xxx/ch7xxx.c b/src/ch7xxx/ch7xxx.c
index fdc96d0..d11c355 100644
--- a/src/ch7xxx/ch7xxx.c
+++ b/src/ch7xxx/ch7xxx.c
@@ -38,7 +38,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#include "ch7xxx.h"
#include "ch7xxx_reg.h"
-static void ch7xxxSaveRegs(void *d);
+static void ch7xxxSaveRegs(I2CDevPtr d);
static CARD8 ch7xxxFreqRegs[][7] =
{ { 0, 0x23, 0x08, 0x16, 0x30, 0x60, 0x00 },
@@ -243,9 +243,9 @@ static void ch7xxxPrintRegs(I2CDevPtr d)
}
}
-static void ch7xxxSaveRegs(void *d)
+static void ch7xxxSaveRegs(I2CDevPtr d)
{
- CH7xxxPtr ch7xxx = CH7PTR(((I2CDevPtr)d));
+ CH7xxxPtr ch7xxx = CH7PTR(d);
int ret;
int i;
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