xf86-video-intel: Branch 'fbc' - src/i830_display.c src/i830_driver.c src/i830.h src/i830_memory.c src/i830_reg.h
Jesse Barnes
jbarnes at kemper.freedesktop.org
Mon Jul 2 15:45:16 PDT 2007
src/i830.h | 4 ++++
src/i830_display.c | 26 +-------------------------
src/i830_driver.c | 11 +++++++++++
src/i830_memory.c | 10 +++++++++-
src/i830_reg.h | 23 +++++++++++++++++++++++
5 files changed, 48 insertions(+), 26 deletions(-)
New commits:
diff-tree f02036aedcd7866c567a6adc070eda3dad872105 (from b384c608978dcd3d2ea6c0018179673cb4735f4c)
Author: Jesse Barnes <jbarnes at nietzche.virtuousgeek.org>
Date: Mon Jul 2 15:42:02 2007 -0700
Framebuffer compression changes:
- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
diff --git a/src/i830.h b/src/i830.h
index 29982ec..1358e3e 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -530,6 +530,10 @@ typedef struct _I830Rec {
CARD32 savePaletteB[256];
CARD32 saveSWF[17];
CARD32 saveBLC_PWM_CTL;
+ CARD32 saveFBC_CFB_BASE;
+ CARD32 saveFBC_LL_BASE;
+ CARD32 saveFBC_CONTROL2;
+ CARD32 saveFBC_CONTROL;
enum last_3d *last_3d;
diff --git a/src/i830_display.c b/src/i830_display.c
index f3b24b2..5b1d6ea 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -38,6 +38,7 @@
#include "xf86.h"
#include "i830.h"
+#include "i830_reg.h"
#include "i830_bios.h"
#include "i830_display.h"
#include "i830_debug.h"
@@ -653,28 +654,6 @@ i830_crtc_unlock (xf86CrtcPtr crtc)
#endif
}
-#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
-#define FBC_LL_BASE 0x03204 /* 4k page aligned */
-#define FBC_CONTROL 0x03208
-#define FBC_CTL_EN (1<<31)
-#define FBC_CTL_PERIODIC (1<<30)
-#define FBC_CTL_INTERVAL_SHIFT (16)
-#define FBC_CTL_STRIDE_SHIFT (5)
-#define FBC_CTL_FENCENO (1<<0)
-#define FBC_COMMAND 0x0320c
-#define FBC_CMD_COMPRESS (1<<0)
-#define FBC_STATUS 0x03210
-#define FBC_STAT_COMPRESSING (1<<31)
-#define FBC_STAT_COMPRESSED (1<<30)
-#define FBC_STAT_MODIFIED (1<<29)
-#define FBC_STAT_CURRENT_LINE (1<<0)
-#define FBC_CONTROL2 0x03214
-#define FBC_CTL_CPU_FENCE (1<<1)
-#define FBC_CTL_PIPEA (0<<0)
-#define FBC_CTL_PIPEB (1<<0)
-
-#define FBC_COMPRESSED_LINES (1536+32)
-
/*
* Several restrictions:
* - DSP[AB]CNTR - no line duplication && no pixel multiplier
@@ -718,9 +697,6 @@ i830_enable_fb_compression(xf86CrtcPtr c
fbc_ctl |= (compressed_stride & 0xff) << FBC_CTL_STRIDE_SHIFT;
fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
OUTREG(FBC_CONTROL, fbc_ctl);
-
- /* and request immediate compression */
- OUTREG(FBC_COMMAND, FBC_CMD_COMPRESS);
}
static void
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 42d0f87..5f934fe 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -192,6 +192,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "vbe.h"
#include "shadow.h"
#include "i830.h"
+#include "i830_reg.h"
#include "i830_display.h"
#include "i830_debug.h"
#include "i830_bios.h"
@@ -1750,6 +1751,11 @@ SaveHWState(ScrnInfoPtr pScrn)
vgaRegPtr vgaReg = &hwp->SavedReg;
int i;
+ pI830->saveFBC_CFB_BASE = INREG(FBC_CFB_BASE);
+ pI830->saveFBC_LL_BASE = INREG(FBC_LL_BASE);
+ pI830->saveFBC_CONTROL2 = INREG(FBC_CONTROL2);
+ pI830->saveFBC_CONTROL = INREG(FBC_CONTROL);
+
/* Save video mode information for native mode-setting. */
pI830->saveDSPACNTR = INREG(DSPACNTR);
pI830->savePIPEACONF = INREG(PIPEACONF);
@@ -1974,6 +1980,11 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(SWF31, pI830->saveSWF[15]);
OUTREG(SWF32, pI830->saveSWF[16]);
+ OUTREG(FBC_CFB_BASE, pI830->saveFBC_CFB_BASE);
+ OUTREG(FBC_LL_BASE, pI830->saveFBC_LL_BASE);
+ OUTREG(FBC_CONTROL2, pI830->saveFBC_CONTROL2);
+ OUTREG(FBC_CONTROL, pI830->saveFBC_CONTROL);
+
vgaHWRestore(pScrn, vgaReg, VGA_SR_FONTS);
vgaHWLock(hwp);
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 5e553f1..8703f2d 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -104,6 +104,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN
#include "i830.h"
#include "i810_reg.h"
+#include "i830_reg.h"
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
@@ -1032,6 +1033,12 @@ static void i830_setup_fb_compression(Sc
goto out;
}
+ /* Clear out any stale state */
+ OUTREG(FBC_CFB_BASE, 0);
+ OUTREG(FBC_LL_BASE, 0);
+ OUTREG(FBC_CONTROL2, 0);
+ OUTREG(FBC_CONTROL, 0);
+
/*
* Compressed framebuffer limitations:
* - contiguous, physical, uncached memory
@@ -1302,7 +1309,8 @@ i830_allocate_depthbuffer(ScrnInfoPtr pS
i830_allocate_memory_tiled(pScrn, "depth buffer", size, pitch,
GTT_PAGE_SIZE, ALIGN_BOTH_ENDS,
tile_format);
- pI830->depth_tiled = FENCE_XMAJOR;
+ pI830->depth_tiled = (tile_format == TILING_YMAJOR) ? FENCE_YMAJOR :
+ FENCE_XMAJOR;
}
/* Otherwise, allocate it linear. */
diff --git a/src/i830_reg.h b/src/i830_reg.h
index 7a8df9f..b5fa1b9 100644
--- a/src/i830_reg.h
+++ b/src/i830_reg.h
@@ -29,6 +29,29 @@
#ifndef _I830_REG_H_
#define _I830_REG_H_
+/* Framebuffer compression */
+#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
+#define FBC_LL_BASE 0x03204 /* 4k page aligned */
+#define FBC_CONTROL 0x03208
+#define FBC_CTL_EN (1<<31)
+#define FBC_CTL_PERIODIC (1<<30)
+#define FBC_CTL_INTERVAL_SHIFT (16)
+#define FBC_CTL_STRIDE_SHIFT (5)
+#define FBC_CTL_FENCENO (1<<0)
+#define FBC_COMMAND 0x0320c
+#define FBC_CMD_COMPRESS (1<<0)
+#define FBC_STATUS 0x03210
+#define FBC_STAT_COMPRESSING (1<<31)
+#define FBC_STAT_COMPRESSED (1<<30)
+#define FBC_STAT_MODIFIED (1<<29)
+#define FBC_STAT_CURRENT_LINE (1<<0)
+#define FBC_CONTROL2 0x03214
+#define FBC_CTL_CPU_FENCE (1<<1)
+#define FBC_CTL_PIPEA (0<<0)
+#define FBC_CTL_PIPEB (1<<0)
+
+#define FBC_COMPRESSED_LINES (1536+32)
+
#define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value)
#define CMD_3D (0x3<<29)
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