xf86-video-intel: Branch 'fbc' - 3 commits - src/i830_display.c src/i830_memory.c

[Jesse Barnes]

 src/i830_display.c |   43 ++++++++++++++++++++++++++++++++++---------
 src/i830_memory.c  |    2 --
 2 files changed, 34 insertions(+), 11 deletions(-)

New commits:
diff-tree 407b124af8f7bb42abe4eecc87476c4c3e555cd0 (from 7a87b9d2a2eb4d281dce67586756ff5653b2805a)
Author: Jesse Barnes <jbarnes at nietzche.virtuousgeek.org>
Date:   Thu Jul 5 11:31:34 2007 -0700

    Remove tiling kludge.  May need more fixes for 965.

diff --git a/src/i830_memory.c b/src/i830_memory.c
index f4271ef..904476a 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1444,8 +1444,6 @@ i830_set_fence(ScrnInfoPtr pScrn, int nr
     CARD32 fence_mask = 0;
     unsigned int fence_pitch;
 
-    pitch = 512;
-
     DPRINTF(PFX, "i830_set_fence(): %d, 0x%08x, %d, %d kByte\n",
 	    nr, offset, pitch, size / 1024);
 
diff-tree 7a87b9d2a2eb4d281dce67586756ff5653b2805a (from fecf964534f5ba6d40480cb13adc89094946a51e)
Author: Jesse Barnes <jbarnes at nietzche.virtuousgeek.org>
Date:   Thu Jul 5 11:23:06 2007 -0700

    Revert discard alpha change, requires other fixes to work.

diff --git a/src/i830_display.c b/src/i830_display.c
index 6bfa7e6..db02402 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1032,10 +1032,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
 	    dspcntr |= DISPPLANE_16BPP;
 	break;
     case 32:
-	if (pI830->fb_compression)
-	    dspcntr |= DISPPLANE_32BPP;
-	else
-	    dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+	dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 	break;
     default:
 	FatalError("unknown display bpp\n");
diff-tree fecf964534f5ba6d40480cb13adc89094946a51e (from 60ee7b6a91b2b8c447130c60cd8b19eb68119777)
Author: Jesse Barnes <jbarnes at nietzche.virtuousgeek.org>
Date:   Thu Jul 5 10:59:23 2007 -0700

    FBC fixes:
      - properly check several FBC enablement constraints
      - don't use alpha discard if FBC is in use

diff --git a/src/i830_display.c b/src/i830_display.c
index 1feb13b..6bfa7e6 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -654,6 +654,34 @@ i830_crtc_unlock (xf86CrtcPtr crtc)
 #endif
 }
 
+static Bool
+i830_use_fb_compression(xf86CrtcPtr crtc)
+{
+    ScrnInfoPtr pScrn = crtc->scrn;
+    I830Ptr pI830 = I830PTR(pScrn);
+    I830CrtcPrivatePtr	intel_crtc = crtc->driver_private;
+    int pipe = intel_crtc->pipe;
+    int plane = (pipe == 0 ? FBC_CTL_PIPEA : FBC_CTL_PIPEB);
+
+    if (!pI830->fb_compression)
+	return FALSE;
+
+    /* Pre-965 only supports plane A, which is synonymous with pipe A for now */
+    if (!IS_I965GM(pI830) && plane != FBC_CTL_PIPEA)
+	return FALSE;
+
+    /* Need 15, 16, or 32 (w/alpha) pixel format */
+    if (!(pScrn->bitsPerPixel == 16 || /* covers 15 bit mode as well */
+	  pScrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */
+	return FALSE;
+
+    /*
+     * No checks for pixel multiply, incl. horizontal, or interlaced modes
+     * since they're currently unused.
+     */
+    return TRUE;
+}
+
 /*
  * Several restrictions:
  *   - DSP[AB]CNTR - no line duplication && no pixel multiplier
@@ -661,6 +689,9 @@ i830_crtc_unlock (xf86CrtcPtr crtc)
  *   - no alpha buffer discard
  *   - no dual wide display
  *   - progressive mode only (DSP[AB]CNTR)
+ *   - uncompressed fb is <= 2048 in width, 0 mod 8
+ *   - uncompressed fb is <= 1536 in height, 0 mod 2
+ *   - SR display watermarks must be equal between 16bpp and 32bpp?
  *
  * FIXME: verify above conditions are true
  */
@@ -719,20 +750,14 @@ i830_disable_fb_compression(xf86CrtcPtr 
 static void
 i830_crtc_prepare (xf86CrtcPtr crtc)
 {
-    ScrnInfoPtr pScrn = crtc->scrn;
-    I830Ptr pI830 = I830PTR(pScrn);
-    crtc->funcs->dpms (crtc, DPMSModeOff);
-
     /* Temporarily turn off FB compression during modeset */
-    if (pI830->fb_compression)
-	i830_disable_fb_compression(crtc);
+    i830_disable_fb_compression(crtc);
+    crtc->funcs->dpms (crtc, DPMSModeOff);
 }
 
 static void
 i830_crtc_commit (xf86CrtcPtr crtc)
 {
-    ScrnInfoPtr pScrn = crtc->scrn;
-    I830Ptr pI830 = I830PTR(pScrn);
     I830CrtcPrivatePtr	intel_crtc = crtc->driver_private;
     Bool		deactivate = FALSE;
 
@@ -748,7 +773,7 @@ i830_crtc_commit (xf86CrtcPtr crtc)
 	i830_pipe_a_require_deactivate (crtc->scrn);
 
     /* Reenable FB compression if possible */
-    if (pI830->fb_compression)
+    if (i830_use_fb_compression(crtc))
 	i830_enable_fb_compression(crtc);
 }
 
@@ -1007,7 +1032,10 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
 	    dspcntr |= DISPPLANE_16BPP;
 	break;
     case 32:
-	dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+	if (pI830->fb_compression)
+	    dspcntr |= DISPPLANE_32BPP;
+	else
+	    dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 	break;
     default:
 	FatalError("unknown display bpp\n");