xf86-video-intel: Branch 'fbc' - src/i830_display.c src/i830_reg.h

[Jesse Barnes]

 src/i830_display.c |    8 ++++----
 src/i830_reg.h     |    4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

New commits:
diff-tree 377c58373daa6bef5d37ead2b6f9a769a905b6fa (from 9c0388dc8d4c6495fae21af6da644b34e20173d1)
Author: Jesse Barnes <jesse.barnes at intel.com>
Date:   Fri Jul 6 20:39:19 2007 -0700

    Fix naming of FBC plane enable bits (mistakenly called them pipes earlier).

diff --git a/src/i830_display.c b/src/i830_display.c
index dc52c0b..853f4e4 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -661,13 +661,13 @@ i830_use_fb_compression(xf86CrtcPtr crtc
     I830Ptr pI830 = I830PTR(pScrn);
     I830CrtcPrivatePtr	intel_crtc = crtc->driver_private;
     int pipe = intel_crtc->pipe;
-    int plane = (pipe == 0 ? FBC_CTL_PIPEA : FBC_CTL_PIPEB);
+    int plane = (pipe == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
 
     if (!pI830->fb_compression)
 	return FALSE;
 
-    /* Pre-965 only supports plane A, which is synonymous with pipe A for now */
-    if (!IS_I965GM(pI830) && plane != FBC_CTL_PIPEA)
+    /* Pre-965 only supports plane A */
+    if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
 	return FALSE;
 
     /* Need 15, 16, or 32 (w/alpha) pixel format */
@@ -704,7 +704,7 @@ i830_enable_fb_compression(xf86CrtcPtr c
     uint32_t fbc_ctl;
     unsigned long compressed_stride;
     int pipe = intel_crtc->pipe;
-    int plane = (pipe == 0 ? FBC_CTL_PIPEA : FBC_CTL_PIPEB);
+    int plane = (pipe == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
     unsigned long uncompressed_stride = pScrn->displayWidth * pI830->cpp;
     unsigned long interval = 1000;
 
diff --git a/src/i830_reg.h b/src/i830_reg.h
index d1670c3..8a2a98a 100644
--- a/src/i830_reg.h
+++ b/src/i830_reg.h
@@ -47,8 +47,8 @@
 #define   FBC_STAT_CURRENT_LINE	(1<<0)
 #define FBC_CONTROL2		0x03214
 #define   FBC_CTL_CPU_FENCE	(1<<1)
-#define   FBC_CTL_PIPEA		(0<<0)
-#define   FBC_CTL_PIPEB		(1<<0)
+#define   FBC_CTL_PLANEA	(0<<0)
+#define   FBC_CTL_PLANEB	(1<<0)
 
 #define FBC_LL_SIZE		(1536)
 #define FBC_LL_PAD		(32)