xf86-video-intel: 2 commits - src/i830_debug.c src/i830_display.c
Keith Packard
keithp at kemper.freedesktop.org
Thu Jun 28 15:29:45 PDT 2007
src/i830_debug.c | 116 ++++++++++++++++++++++++++++++++++++++---------------
src/i830_display.c | 7 +--
2 files changed, 87 insertions(+), 36 deletions(-)
New commits:
diff-tree 5257e36f502676fd6a44bbb8e747d9138ed3bc5c (from 16bfcb8042519f24b4494fd621814f39949ceeb6)
Author: Keith Packard <keithp at neko.keithp.com>
Date: Thu Jun 28 15:29:52 2007 -0700
Handle dual-channel LVDS on i855.
Just as with i9xx LVDS, the i855 LVDS can operate in dual-channel mode with
a modified P2 divisor value (7 instead of 14). Just using the existing 9xx
code for 855 appears to work fine.
diff --git a/src/i830_display.c b/src/i830_display.c
index f6e99be..16ef2cc 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -92,7 +92,7 @@ typedef struct {
#define I8XX_P2_SLOW 4
#define I8XX_P2_FAST 2
#define I8XX_P2_LVDS_SLOW 14
-#define I8XX_P2_LVDS_FAST 14 /* No fast option */
+#define I8XX_P2_LVDS_FAST 7
#define I8XX_P2_SLOW_LIMIT 165000
#define I9XX_DOT_MIN 20000
@@ -311,8 +311,7 @@ i830FindBestPLL(xf86CrtcPtr crtc, int ta
const intel_limit_t *limit = intel_limit (crtc);
int err = target;
- if (IS_I9XX(pI830) && i830PipeHasType(crtc, I830_OUTPUT_LVDS) &&
- (INREG(LVDS) & LVDS_PORT_EN) != 0)
+ if (i830PipeHasType(crtc, I830_OUTPUT_LVDS))
{
/* For LVDS, if the panel is on, just rely on its current settings for
* dual-channel. We haven't figured out how to reliably set up
@@ -1006,7 +1005,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
*/
- if (clock.p2 == 7)
+ if (clock.p2 == I9XX_P2_LVDS_FAST)
lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
else
lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
diff-tree 16bfcb8042519f24b4494fd621814f39949ceeb6 (from 9675ccb30818bf831ac4c634751ab4bfe35f7bfe)
Author: Keith Packard <keithp at neko.keithp.com>
Date: Thu Jun 28 15:27:56 2007 -0700
Decode PLL registers in LVDS mode a bit better in debug code.
LVDS mode changes how the PLL works in fairly dramatic ways; the debug code
wasn't properly accounting for those differences resulting in fairly bogus
debug output.
diff --git a/src/i830_debug.c b/src/i830_debug.c
index bda263c..055ca93 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -571,39 +571,91 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
{
fp = INREG(pipe == 0 ? FPA0 : FPB0);
dpll = INREG(pipe == 0 ? DPLL_A : DPLL_B);
- switch ((dpll >> 24) & 0x3) {
- case 0:
- p2 = 10;
- break;
- case 1:
- p2 = 5;
- break;
- default:
- p2 = 1;
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p2 out of range\n");
- break;
+ if (IS_I9XX(pI830))
+ {
+ CARD32 lvds = INREG(LVDS);
+ if ((lvds & LVDS_PORT_EN) &&
+ (lvds & LVDS_PIPEB_SELECT) == (pipe << 30))
+ {
+ if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ p2 = 7;
+ else
+ p2 = 14;
+ }
+ else
+ {
+ switch ((dpll >> 24) & 0x3) {
+ case 0:
+ p2 = 10;
+ break;
+ case 1:
+ p2 = 5;
+ break;
+ default:
+ p2 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p2 out of range\n");
+ break;
+ }
+ }
+ switch ((dpll >> 16) & 0xff) {
+ case 1:
+ p1 = 1; break;
+ case 2:
+ p1 = 2; break;
+ case 4:
+ p1 = 3; break;
+ case 8:
+ p1 = 4; break;
+ case 16:
+ p1 = 5; break;
+ case 32:
+ p1 = 6; break;
+ case 64:
+ p1 = 7; break;
+ case 128:
+ p1 = 8; break;
+ default:
+ p1 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
+ break;
+ }
}
- switch ((dpll >> 16) & 0xff) {
- case 1:
- p1 = 1; break;
- case 2:
- p1 = 2; break;
- case 4:
- p1 = 3; break;
- case 8:
- p1 = 4; break;
- case 16:
- p1 = 5; break;
- case 32:
- p1 = 6; break;
- case 64:
- p1 = 7; break;
- case 128:
- p1 = 8; break;
- default:
- p1 = 1;
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
- break;
+ else
+ {
+ CARD32 lvds = INREG(LVDS);
+ if (IS_I85X (pI830) &&
+ (lvds & LVDS_PORT_EN) &&
+ (lvds & LVDS_PIPEB_SELECT) == (pipe << 30))
+ {
+ if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ p2 = 7;
+ else
+ p2 = 14;
+ switch ((dpll >> 16) & 0x3f) {
+ case 0x01: p1 = 1; break;
+ case 0x02: p1 = 2; break;
+ case 0x04: p1 = 3; break;
+ case 0x08: p1 = 4; break;
+ case 0x10: p1 = 5; break;
+ case 0x20: p1 = 6; break;
+ default:
+ p1 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "LVDS P1 0x%x invalid encoding\n",
+ (dpll >> 16) & 0x3f);
+ break;
+ }
+ }
+ else
+ {
+ if (dpll & (1 << 23))
+ p2 = 4;
+ else
+ p2 = 2;
+ if (dpll & PLL_P1_DIVIDE_BY_TWO)
+ p1 = 2;
+ else
+ p1 = ((dpll >> 16) & 0x3f) + 2;
+ }
}
switch ((dpll >> 13) & 0x3) {
case 0:
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