xf86-video-ati: Branch 'master' - 3 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Thu Sep 20 20:56:03 PDT 2007
src/radeon_display.c | 7 ++++++-
src/radeon_driver.c | 6 +-----
src/radeon_output.c | 23 ++++++++++-------------
src/radeon_vip.c | 7 +++++++
4 files changed, 24 insertions(+), 19 deletions(-)
New commits:
diff-tree 5a6f74103f0ec0d451d0e2573442efe5922848af (from c72a365386e19f9257db041d44b09ad499cc9f6a)
Author: Maciej Cencora <m.cencora at gmail.com>
Date: Thu Sep 20 23:56:08 2007 -0400
RADEON: fix video in on RV380 (tested on X600 VIVO)
diff --git a/src/radeon_vip.c b/src/radeon_vip.c
index abcba06..7ee4ab5 100644
--- a/src/radeon_vip.c
+++ b/src/radeon_vip.c
@@ -331,6 +331,13 @@ void RADEONVIP_reset(ScrnInfoPtr pScrn,
OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
break;
+ case CHIP_FAMILY_RV380:
+ OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */
+ OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
+ OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
+ OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
+ OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
+ break;
default:
OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
diff-tree c72a365386e19f9257db041d44b09ad499cc9f6a (from 5e4d98470b6412a686883c554e7eb7badbe78c4d)
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Sep 20 23:49:57 2007 -0400
RADEON: fix up dvo support (still no external chip init)
diff --git a/src/radeon_display.c b/src/radeon_display.c
index fa80e10..7f599e6 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -289,6 +289,7 @@ void RADEONDisableDisplays(ScrnInfoPtr p
/* FP 2 */
tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= RADEON_FP2_BLANK_EN;
tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
OUTREG(RADEON_FP2_GEN_CNTL, tmp);
@@ -355,10 +356,12 @@ void RADEONEnableDisplay(xf86OutputPtr o
save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
} else if (radeon_output->TMDSType == TMDS_EXT) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~RADEON_FP2_BLANK_EN;
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
OUTREG(RADEON_FP2_GEN_CNTL, tmp);
save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- }
+ save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
+ }
} else if (radeon_output->MonType == MT_LCD) {
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
@@ -406,9 +409,11 @@ void RADEONEnableDisplay(xf86OutputPtr o
save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
} else if (radeon_output->TMDSType == TMDS_EXT) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= RADEON_FP2_BLANK_EN;
tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
OUTREG(RADEON_FP2_GEN_CNTL, tmp);
save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
}
} else if (radeon_output->MonType == MT_LCD) {
unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
diff --git a/src/radeon_output.c b/src/radeon_output.c
index f9a21bb..8b7ae08 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -766,7 +766,7 @@ static void RADEONInitFP2Registers(xf86O
DisplayModePtr mode, BOOL IsPrimary)
{
ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
if (pScrn->rgbBits == 8)
@@ -776,26 +776,23 @@ static void RADEONInitFP2Registers(xf86O
save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl &
~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON |
+ RADEON_FP2_DVO_EN |
+ RADEON_FP2_DVO_RATE_SEL_SDR);
if (IsPrimary) {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_EN |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- if (mode->Flags & RADEON_USE_RMX)
- save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
+ save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
+ if (mode->Flags & RADEON_USE_RMX)
+ save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
} else {
- save->fp2_gen_cntl &= ~(RADEON_FP2_SRC_SEL_CRTC2 |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- }
+ save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
+ }
} else {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
+ save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
} else {
- save->fp2_gen_cntl &= ~(RADEON_FP2_DVO_RATE_SEL_SDR);
save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
}
}
diff-tree 5e4d98470b6412a686883c554e7eb7badbe78c4d (from c5e2a2f09af807006c7ea493a8e90ff77abe207c)
Author: Alex Deucher <alex at botch2.(none)>
Date: Thu Sep 20 23:22:48 2007 -0400
RADEON: round 3 on the PLLs. should fix the LVDS issues
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 8f6e8f0..3b8454f 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4662,9 +4662,7 @@ void RADEONRestorePLLRegisters(ScrnInfoP
RADEON_VCLK_SRC_SEL_PPLLCLK,
~(RADEON_VCLK_SRC_SEL_MASK));
- usleep(50000);
-
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);
+ /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/
ErrorF("finished PLL1\n");
@@ -4739,8 +4737,6 @@ void RADEONRestorePLL2Registers(ScrnInfo
RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
~(RADEON_PIX2CLK_SRC_SEL_MASK));
- usleep(5000);
-
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);
ErrorF("finished PLL2\n");
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