xf86-video-intel: 2 commits - src/i830_display.c src/i830_driver.c src/i830_dvo.c src/i830.h

[Jesse Barnes]

 src/i830.h         |    1 +
 src/i830_display.c |    1 +
 src/i830_driver.c  |    2 ++
 src/i830_dvo.c     |    2 +-
 4 files changed, 5 insertions(+), 1 deletion(-)

New commits:
commit f79a585d57c61fbe9af5684a336918e1fe3e8416
Author: liuhong <liuhong at devlinux-hong.sh.intel.com>
Date:   Tue Feb 5 11:04:34 2008 +0800

    xf86-video-intel: fix ivch using wrong dvo register
    
    We use the wrong DVO output register for ivch which is used for DVO LVDS.
    Vbios enables DVOB and driver never touches it, so everything seems
    working correctly now.

diff --git a/src/i830_dvo.c b/src/i830_dvo.c
index e6ff6af..e7342b0 100644
--- a/src/i830_dvo.c
+++ b/src/i830_dvo.c
@@ -83,7 +83,7 @@ struct _I830DVODriver i830_dvo_drivers[] =
 	.type = I830_OUTPUT_DVO_LVDS,
 	.modulename = "ivch",
 	.fntablename = "ivch_methods",
-	.dvo_reg = DVOA,
+	.dvo_reg = DVOB,
 	.address = 0x04, /* Might also be 0x44, 0x84, 0xc4 */
 	.symbols = ivch_symbols
     },
commit cabed67b6a0e4dd408eeb8d2083269100a65933c
Author: Jesse Barnes <jbarnes at hobbes.virtuousgeek.org>
Date:   Tue Feb 5 11:36:24 2008 -0800

    Program FBC fence offset register
    
    Just a partial fix for some of the FBC issues people have been seeing.  The
    other half is to disable FBC if both pipes are running.

diff --git a/src/i830.h b/src/i830.h
index e55e110..05b0358 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -616,6 +616,7 @@ typedef struct _I830Rec {
    CARD32 saveFBC_LL_BASE;
    CARD32 saveFBC_CONTROL2;
    CARD32 saveFBC_CONTROL;
+   CARD32 saveFBC_FENCE_OFF;
 
    enum last_3d *last_3d;
 
diff --git a/src/i830_display.c b/src/i830_display.c
index a4916d0..274a07d 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -612,6 +612,7 @@ i830_enable_fb_compression_8xx(xf86CrtcPtr crtc)
     OUTREG(FBC_LL_BASE, pI830->compressed_ll_buffer->bus_addr + 6);
     OUTREG(FBC_CONTROL2, FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_FULL |
 	   FBC_CTL_CPU_FENCE | plane);
+    OUTREG(FBC_FENCE_OFF, crtc->y);
 
     /* Zero buffers */
     memset(pI830->FbBase + pI830->compressed_front_buffer->offset, 0,
diff --git a/src/i830_driver.c b/src/i830_driver.c
index a3c64de..01418ab 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1932,6 +1932,7 @@ SaveHWState(ScrnInfoPtr pScrn)
        pI830->saveFBC_LL_BASE = INREG(FBC_LL_BASE);
        pI830->saveFBC_CONTROL2 = INREG(FBC_CONTROL2);
        pI830->saveFBC_CONTROL = INREG(FBC_CONTROL);
+       pI830->saveFBC_FENCE_OFF = INREG(FBC_FENCE_OFF);
    }
 
    /* Save video mode information for native mode-setting. */
@@ -2212,6 +2213,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
    if (pI830->fb_compression) {
        OUTREG(FBC_CFB_BASE, pI830->saveFBC_CFB_BASE);
        OUTREG(FBC_LL_BASE, pI830->saveFBC_LL_BASE);
+       OUTREG(FBC_FENCE_OFF, pI830->saveFBC_FENCE_OFF);
        OUTREG(FBC_CONTROL2, pI830->saveFBC_CONTROL2);
        OUTREG(FBC_CONTROL, pI830->saveFBC_CONTROL);
    }