xf86-video-ati: Branch 'master'
Alex Deucher
agd5f at kemper.freedesktop.org
Tue Feb 26 09:25:21 PST 2008
src/radeon_exa_render.c | 9 +-
src/radeon_reg.h | 22 +++++
src/radeon_textured_videofuncs.c | 157 ++++++++++++++++++++++++++++-----------
3 files changed, 143 insertions(+), 45 deletions(-)
New commits:
commit 823d8bf49e4c0a8c839354179942c5a1944c178d
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Feb 26 12:25:14 2008 -0500
R300/R500: clean up magic numbers in textured video
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index b00c013..30e3329 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1111,7 +1111,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
+ OUT_ACCEL_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_COL_PTR(0) |
+ R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 893fca4..b8a63d7 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -4032,6 +4032,28 @@
# define R300_RS_COUNT_HIRES_EN (1 << 18)
#define R300_RS_IP_0 0x4310
+# define R300_RS_TEX_PTR(x) (x << 0)
+# define R300_RS_COL_PTR(x) (x << 6)
+# define R300_RS_COL_FMT(x) (x << 9)
+# define R300_RS_COL_FMT_RGBA 0
+# define R300_RS_COL_FMT_RGB0 2
+# define R300_RS_COL_FMT_RGB1 3
+# define R300_RS_COL_FMT_000A 4
+# define R300_RS_COL_FMT_0000 5
+# define R300_RS_COL_FMT_0001 6
+# define R300_RS_COL_FMT_111A 8
+# define R300_RS_COL_FMT_1110 9
+# define R300_RS_COL_FMT_1111 10
+# define R300_RS_SEL_S(x) (x << 13)
+# define R300_RS_SEL_T(x) (x << 16)
+# define R300_RS_SEL_R(x) (x << 19)
+# define R300_RS_SEL_Q(x) (x << 22)
+# define R300_RS_SEL_C0 0
+# define R300_RS_SEL_C1 1
+# define R300_RS_SEL_C2 2
+# define R300_RS_SEL_C3 3
+# define R300_RS_SEL_K0 4
+# define R300_RS_SEL_K1 5
#define R300_RS_INST_COUNT 0x4304
# define R300_INST_COUNT_RS(x) (x << 0)
# define R300_RS_W_EN (1 << 4)
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 36951d5..1c9b7e8 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -21,7 +21,7 @@
* SOFTWARE.
*
*
- * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt
+ * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al.
*
*/
@@ -128,7 +128,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
+ int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
+
switch (pPixmap->drawable.bitsPerPixel) {
case 16:
if (pPixmap->drawable.depth == 15)
@@ -174,7 +175,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_VIDEO(6);
OUT_VIDEO_REG(R300_TX_FILTER0_0, txfilter);
- OUT_VIDEO_REG(R300_TX_FILTER1_0, 0x0);
+ OUT_VIDEO_REG(R300_TX_FILTER1_0, 0);
OUT_VIDEO_REG(R300_TX_FORMAT0_0, txformat0);
OUT_VIDEO_REG(R300_TX_FORMAT1_0, txformat1);
OUT_VIDEO_REG(R300_TX_FORMAT2_0, txpitch);
@@ -183,32 +184,85 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txenable = R300_TEX_0_ENABLE;
- /* setup vertex shader */
+ /* setup the VAP */
if (has_tcl) {
BEGIN_VIDEO(26);
- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0x0);
- OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
- OUT_VIDEO_REG(R300_VAP_CNTL, 0x300456);
+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0);
+ OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+ OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
} else {
BEGIN_VIDEO(8);
- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 1<<8);
- OUT_VIDEO_REG(R300_VAP_CNTL, 0x14045a);
+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+ OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
}
- OUT_VIDEO_REG(R300_VAP_VTE_CNTL, 0x300);
- OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0);
-
+ OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+ OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
+
if (has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x6a014001);
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (10 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_LAST_VEC_1 |
+ R300_SIGNED_1));
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_1_SHIFT)));
} else {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x66014001);
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0x3b083b08);
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_LAST_VEC_1 |
+ R300_SIGNED_1));
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ << R300_WRITE_ENA_1_SHIFT)));
}
+ /* setup vertex shader */
if (has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (1 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
@@ -218,33 +272,46 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
+ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, 0x10000);
+ OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
}
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, 0x1);
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, 0x2);
+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
FINISH_VIDEO();
/* setup pixel shader */
if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
BEGIN_VIDEO(16);
- OUT_VIDEO_REG(R300_RS_COUNT, 0x40002);
- OUT_VIDEO_REG(R300_RS_IP_0, 0x1610000);
- OUT_VIDEO_REG(R300_RS_INST_COUNT, 0xC0);
+ OUT_VIDEO_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ OUT_VIDEO_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_COL_PTR(0) |
+ R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
- OUT_VIDEO_REG(R300_US_CONFIG, 0x8);
- OUT_VIDEO_REG(R300_US_PIXSIZE, 0x0);
- OUT_VIDEO_REG(R300_US_CODE_OFFSET, 0x40040);
- OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0x0);
- OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0x0);
- OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0x0);
+ OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
+ OUT_VIDEO_REG(R300_US_CODE_OFFSET,
+ (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(1) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(1)));
+ OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0);
+ OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0);
+ OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0);
OUT_VIDEO_REG(R300_US_CODE_ADDR_3, 0x400000);
OUT_VIDEO_REG(R300_US_TEX_INST_0, 0x8000);
OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
@@ -254,19 +321,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
} else {
BEGIN_VIDEO(22);
- OUT_VIDEO_REG(R300_RS_COUNT, 0x40002);
+ OUT_VIDEO_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
OUT_VIDEO_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
-
- OUT_VIDEO_REG(R300_RS_INST_COUNT, 0x0);
+
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, 0);
OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
- OUT_VIDEO_REG(R300_US_CONFIG, 0x2);
- OUT_VIDEO_REG(R300_US_PIXSIZE, 0x0);
- OUT_VIDEO_REG(R500_US_FC_CTRL, 0x0);
- OUT_VIDEO_REG(R500_US_CODE_ADDR, 0x10000);
- OUT_VIDEO_REG(R500_US_CODE_RANGE, 0x10000);
- OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0x0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0x0);
+ OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
+ OUT_VIDEO_REG(R500_US_FC_CTRL, 0);
+ OUT_VIDEO_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
+ OUT_VIDEO_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
+ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00007807);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x06400000);
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0xe4000400);
@@ -283,7 +352,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
}
BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_INVALTAGS, 0x0);
+ OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
@@ -291,7 +360,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
- OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0x0);
+ OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0);
FINISH_VIDEO();
BEGIN_VIDEO(1);
@@ -503,7 +572,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
}
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