xf86-video-ati: Branch 'master' - 7 commits
George Sapountzis
gsap7 at kemper.freedesktop.org
Wed Feb 27 08:52:31 PST 2008
Makefile.am | 6
README.r128 | 160
README.r128.sgml | 138
configure.ac | 12
man/Makefile.am | 4
man/ati.man | 34
man/r128.man | 156
man/radeon.man | 514 ---
src/AtomBios/CD_Operations.c | 954 -----
src/AtomBios/Decoder.c | 235 -
src/AtomBios/hwserv_drv.c | 348 --
src/AtomBios/includes/CD_Common_Types.h | 154
src/AtomBios/includes/CD_Definitions.h | 49
src/AtomBios/includes/CD_Opcodes.h | 181 -
src/AtomBios/includes/CD_Structs.h | 464 --
src/AtomBios/includes/CD_binding.h | 46
src/AtomBios/includes/CD_hw_services.h | 318 -
src/AtomBios/includes/Decoder.h | 86
src/AtomBios/includes/ObjectID.h | 484 --
src/AtomBios/includes/atombios.h | 4436 -------------------------
src/AtomBios/includes/regsdef.h | 25
src/Makefile.am | 23
src/ati.c | 348 --
src/ati_pciids_gen.h | 358 --
src/atimisc.c | 2
src/atimodule.c | 79
src/atipciids.h | 46
src/ativersion.h | 54
src/atombios_crtc.c | 426 --
src/atombios_output.c | 703 ----
src/generic_bus.h | 35
src/legacy_crtc.c | 1793 ----------
src/legacy_output.c | 1763 ----------
src/local_xf86Rename.h | 23
src/pcidb/ati_pciids.csv | 359 --
src/pcidb/parse_pci_ids.pl | 102
src/r128.h | 606 ---
src/r128_accel.c | 1880 ----------
src/r128_common.h | 169
src/r128_cursor.c | 311 -
src/r128_dga.c | 402 --
src/r128_dri.c | 1499 --------
src/r128_dri.h | 100
src/r128_dripriv.h | 57
src/r128_driver.c | 4463 --------------------------
src/r128_misc.c | 79
src/r128_probe.c | 378 --
src/r128_probe.h | 73
src/r128_reg.h | 1533 --------
src/r128_sarea.h | 194 -
src/r128_version.h | 59
src/r128_video.c | 1028 ------
src/radeon.h | 1187 ------
src/radeon_accel.c | 1254 -------
src/radeon_accelfuncs.c | 1346 -------
src/radeon_atombios.c | 2884 ----------------
src/radeon_atombios.h | 253 -
src/radeon_atomwrapper.c | 101
src/radeon_atomwrapper.h | 31
src/radeon_bios.c | 1469 --------
src/radeon_chipinfo_gen.h | 279 -
src/radeon_chipset_gen.h | 280 -
src/radeon_common.h | 494 --
src/radeon_commonfuncs.c | 351 --
src/radeon_crtc.c | 721 ----
src/radeon_cursor.c | 360 --
src/radeon_dga.c | 463 --
src/radeon_dri.c | 2216 ------------
src/radeon_dri.h | 100
src/radeon_dripriv.h | 63
src/radeon_driver.c | 5478 --------------------------------
src/radeon_exa.c | 525 ---
src/radeon_exa_funcs.c | 592 ---
src/radeon_exa_render.c | 1439 --------
src/radeon_macros.h | 163
src/radeon_misc.c | 78
src/radeon_mm_i2c.c | 642 ---
src/radeon_modes.c | 310 -
src/radeon_output.c | 2803 ----------------
src/radeon_pci_chipset_gen.h | 280 -
src/radeon_pci_device_match_gen.h | 280 -
src/radeon_probe.c | 227 -
src/radeon_probe.h | 595 ---
src/radeon_reg.h | 4812 ----------------------------
src/radeon_render.c | 1052 ------
src/radeon_sarea.h | 231 -
src/radeon_textured_video.c | 383 --
src/radeon_textured_videofuncs.c | 596 ---
src/radeon_tv.c | 1164 ------
src/radeon_tv.h | 51
src/radeon_version.h | 63
src/radeon_video.c | 3985 -----------------------
src/radeon_video.h | 145
src/radeon_vip.c | 362 --
src/theatre.c | 2209 ------------
src/theatre.h | 79
src/theatre200.c | 2275 -------------
src/theatre200.h | 140
src/theatre200_module.c | 33
src/theatre_detect.c | 129
src/theatre_detect.h | 46
src/theatre_detect_module.c | 37
src/theatre_module.c | 33
src/theatre_reg.h | 876 -----
104 files changed, 13 insertions(+), 73701 deletions(-)
New commits:
commit 56a1c9f07886d40c25baa31b6d02f5ee0efd749a
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:49:50 2008 +0200
add warning message
diff --git a/configure.ac b/configure.ac
index 7c20d7d..5e8be38 100644
--- a/configure.ac
+++ b/configure.ac
@@ -221,6 +221,12 @@ XORG_MANPAGE_SECTIONS
XORG_RELEASE_VERSION
XORG_CHECK_LINUXDOC
+AC_MSG_NOTICE(
+[Please change the Driver line in xorg.conf from "ati" to "mach64" or install]
+[the ati wrapper as well:]
+[ git://anongit.freedesktop.org/git/xorg/driver/xf86-video-ati]
+)
+
AC_OUTPUT([
Makefile
src/Makefile
commit 10127a10841ec211a92b2a59d6db716343caf018
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:49:31 2008 +0200
change module name and version
module gets package version, driver keeps its own version
diff --git a/configure.ac b/configure.ac
index b244c55..7c20d7d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -21,10 +21,10 @@
# Process this file with autoconf to produce a configure script
AC_PREREQ(2.57)
-AC_INIT([xf86-video-ati],
+AC_INIT([xf86-video-mach64],
6.8.0,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
- xf86-video-ati)
+ xf86-video-mach64)
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
@@ -214,7 +214,7 @@ AC_SUBST([XORG_CFLAGS])
AC_SUBST([DRI_CFLAGS])
AC_SUBST([moduledir])
-DRIVER_NAME=ati
+DRIVER_NAME=mach64
AC_SUBST([DRIVER_NAME])
XORG_MANPAGE_SECTIONS
diff --git a/src/atimisc.c b/src/atimisc.c
index ebfde54..24897c3 100644
--- a/src/atimisc.c
+++ b/src/atimisc.c
@@ -37,7 +37,7 @@ static XF86ModuleVersionInfo ATIVersionRec =
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
- MACH64_VERSION_MAJOR, MACH64_VERSION_MINOR, MACH64_VERSION_PATCH,
+ PACKAGE_VERSION_MAJOR, PACKAGE_VERSION_MINOR, PACKAGE_VERSION_PATCHLEVEL,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_VIDEODRV,
commit e8260479e8c9f0445d160e991104b3a749035a7b
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:49:02 2008 +0200
drop r128
diff --git a/README.r128 b/README.r128
deleted file mode 100644
index dcc2715..0000000
--- a/README.r128
+++ /dev/null
@@ -1,160 +0,0 @@
- Information for ATI Rage 128 Users
- Precision Insight, Inc., SuSE GmbH
- 13 June 2000
- ____________________________________________________________
-
- Table of Contents
-
-
- 1. Supported Hardware
- 2. Features
- 3. Technical Notes
- 4. Reported Working Video Cards
- 5. Configuration
- 6. Driver Options
- 7. Known Limitations
- 8. Authors
-
-
- ______________________________________________________________________
-
- [1m1. Supported Hardware[0m
-
-
- +o ATI Rage 128 based cards
-
-
-
- [1m2. Features[0m
-
-
- +o Full support (including hardware accelerated 2D drawing) for 8, 15,
- 16, 24 bit pixel depths.
-
- +o Hardware cursor support to reduce sprite flicker.
-
- +o Support for high resolution video modes up to 1800x1440 @ 70Hz.
-
- +o Support for doublescan video modes (e.g., 320x200 and 320x240).
-
- +o Support for gamma correction at all pixel depths.
-
- +o Fully programmable clock supported.
-
- +o Robust text mode restore for VT switching.
-
-
-
- [1m3. Technical Notes[0m
-
-
- +o None
-
-
-
- [1m4. Reported Working Video Cards[0m
-
-
- +o Rage Fury AGP 32MB
-
- +o XPERT 128 AGP 16MB
-
- +o XPERT 99 AGP 8MB
-
-
-
- [1m5. Configuration[0m
-
- The driver auto-detects all device information necessary to initialize
- the card. The only lines you need in the "Device" section of your
- xorg.conf file are:
-
- Section "Device"
- Identifier "Rage 128"
- Driver "r128"
- EndSection
-
-
- or let xorgconfig do this for you.
-
- However, if you have problems with auto-detection, you can specify:
-
- +o VideoRam - in kilobytes
-
- +o MemBase - physical address of the linear framebuffer
-
- +o IOBase - physical address of the memory mapped IO registers
-
- +o ChipID - PCI DEVICE ID
-
-
-
- [1m6. Driver Options[0m
-
-
- +o "hw_cursor" - request hardware cursor (default)
-
- +o "sw_cursor" - software cursor only
-
- +o "no_accel" - software rendering only
-
- +o "dac_8_bit" - use color weight 888 in 8 bpp mode (default)
-
- +o "dac_6_bit" - use color weight 666 in 8 bpp mode (VGA emulation)
-
-
-
- [1m7. Known Limitations[0m
-
-
- +o None
-
-
-
- [1m8. Authors[0m
-
- The X11R6.8 driver was originally part of XFree86 4.4 rc2.
-
- The XFree86 4 driver was ported from XFree86 3.3.x and enhanced by:
-
- +o Rickard E. (Rik) Faith <faith at precisioninsight.com>
-
- +o Kevin E. Martin <kevin at precisioninsight.com>
-
- The XFree86 4 driver was funded by ATI and was donated to The XFree86
- Project by:
-
- Precision Insight, Inc.
- Cedar Park, TX
- USA
-
-
- The XFree86 3.3.x driver used for the port was written by:
-
- +o Rickard E. (Rik) Faith <faith at precisioninsight.com>
-
- +o Kevin E. Martin <kevin at precisioninsight.com>
-
- The XFree86 3.3.x driver was funded by ATI and was donated to The
- XFree86 Project by Precision Insight, Inc. It was based in part on
- an earlier driver that was written by:
-
- +o Alan Hourihane <alanh at fairlite.demon.co.uk>
-
- +o Dirk Hohndel <hohndel at suse.de>
-
- This early driver was funded and donated to The XFree86 Project by:
-
- SuSE GmbH
- Schanzaekerstr. 10
- 90443 Nuernberg
- Germany
-
-
-
- http://www.precisioninsight.com
-
- http://www.suse.com
-
-
-
diff --git a/README.r128.sgml b/README.r128.sgml
deleted file mode 100644
index 8d7f448..0000000
--- a/README.r128.sgml
+++ /dev/null
@@ -1,138 +0,0 @@
-<!DOCTYPE linuxdoc PUBLIC "-//Xorg//DTD linuxdoc//EN"[
-<!ENTITY % defs SYSTEM "defs.ent"> %defs;
-]>
-
-<article>
-<title>Information for ATI Rage 128 Users
-<author>Precision Insight, Inc., SuSE GmbH
-<date>13 June 2000
-
-<ident>
-</ident>
-
-<toc>
-
-<sect>Supported Hardware
-<p>
-<itemize>
- <item>ATI Rage 128 based cards
-</itemize>
-
-
-<sect>Features
-<p>
-<itemize>
- <item>Full support (including hardware accelerated 2D drawing) for 8, 15,
- 16, 24 bit pixel depths.
- <item>Hardware cursor support to reduce sprite flicker.
- <item>Support for high resolution video modes up to 1800x1440 @ 70Hz.
- <item>Support for doublescan video modes (e.g., 320x200 and 320x240).
- <item>Support for gamma correction at all pixel depths.
- <item>Fully programmable clock supported.
- <item>Robust text mode restore for VT switching.
-</itemize>
-
-
-<sect>Technical Notes
-<p>
-<itemize>
- <item>None
-</itemize>
-
-
-<sect>Reported Working Video Cards
-<p>
-<itemize>
- <item>Rage Fury AGP 32MB
- <item>XPERT 128 AGP 16MB
- <item>XPERT 99 AGP 8MB
-</itemize>
-
-
-<sect>Configuration
-<p>
-The driver auto-detects all device information necessary to
-initialize the card. The only lines you need in the "Device"
-section of your xorg.conf file are:
-<verb>
- Section "Device"
- Identifier "Rage 128"
- Driver "r128"
- EndSection
-</verb>
-or let <tt>xorgconfig</tt> do this for you.
-
-However, if you have problems with auto-detection, you can specify:
-<itemize>
- <item>VideoRam - in kilobytes
- <item>MemBase - physical address of the linear framebuffer
- <item>IOBase - physical address of the memory mapped IO registers
- <item>ChipID - PCI DEVICE ID
-</itemize>
-
-
-<sect>Driver Options
-<p>
-<itemize>
- <item>"hw_cursor" - request hardware cursor (default)
- <item>"sw_cursor" - software cursor only
- <item>"no_accel" - software rendering only
- <item>"dac_8_bit" - use color weight 888 in 8 bpp mode (default)
- <item>"dac_6_bit" - use color weight 666 in 8 bpp mode (VGA emulation)
-</itemize>
-
-
-<sect>Known Limitations
-<p>
-<itemize>
- <item>None
-</itemize>
-
-
-<sect>Authors
-<p>
-The X11R&relvers; driver was originally part of XFree86 4.4 rc2.
-
-The XFree86 4 driver was ported from XFree86 3.3.x and enhanced by:
-<itemize>
- <item>Rickard E. (Rik) Faith <email>faith at precisioninsight.com</email>
- <item>Kevin E. Martin <email>kevin at precisioninsight.com</email>
-</itemize>
-<p>
-The XFree86 4 driver was funded by ATI and was donated to The XFree86
-Project by:
-<verb>
- Precision Insight, Inc.
- Cedar Park, TX
- USA
-</verb>
-<p>
-The XFree86 3.3.x driver used for the port was written by:
-<itemize>
- <item>Rickard E. (Rik) Faith <email>faith at precisioninsight.com</email>
- <item>Kevin E. Martin <email>kevin at precisioninsight.com</email>
-</itemize>
-The XFree86 3.3.x driver was funded by ATI and was donated to The XFree86
-Project by Precision Insight, Inc. It was based in part on an earlier
-driver that was written by:
-<itemize>
- <item>Alan Hourihane <email>alanh at fairlite.demon.co.uk</email>
- <item>Dirk Hohndel <email>hohndel at suse.de</email>
-</itemize>
-<p>This early driver was funded and donated to The XFree86 Project by:
-<verb>
- SuSE GmbH
- Schanzaekerstr. 10
- 90443 Nuernberg
- Germany
-</verb>
-
-<p>
-<htmlurl name="http://www.precisioninsight.com"
- url="http://www.precisioninsight.com">
-<p>
-<htmlurl name="http://www.suse.com"
- url="http://www.suse.com">
-
-
-</article>
diff --git a/man/r128.man b/man/r128.man
deleted file mode 100644
index 709c2fe..0000000
--- a/man/r128.man
+++ /dev/null
@@ -1,156 +0,0 @@
-.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man,v 1.3 2001/06/01 02:10:05 dawes Exp $
-.\" shorthand for double quote that works everywhere.
-.ds q \N'34'
-.TH R128 __drivermansuffix__ __vendorversion__
-.SH NAME
-r128 \- ATI Rage 128 video driver
-.SH SYNOPSIS
-.nf
-.B "Section \*qDevice\*q"
-.BI " Identifier \*q" devname \*q
-.B " Driver \*qr128\*q"
-\ \ ...
-.B EndSection
-.fi
-.SH DESCRIPTION
-.B r128
-is an __xservername__ driver for ATI Rage 128 based video cards. It contains
-full support for 8, 15, 16 and 24 bit pixel depths, hardware
-acceleration of drawing primitives, hardware cursor, video modes up to
-1800x1440 @ 70Hz, doublescan modes (e.g., 320x200 and 320x240), gamma
-correction at all pixel depths, a fully programming dot clock and robust
-text mode restoration for VT switching. Dualhead is supported on M3/M4
-mobile chips.
-.SH SUPPORTED HARDWARE
-The
-.B r128
-driver supports all ATI Rage 128 based video cards including the Rage
-Fury AGP 32MB, the XPERT 128 AGP 16MB and the XPERT 99 AGP 8MB.
-.SH CONFIGURATION DETAILS
-Please refer to __xconfigfile__(__filemansuffix__) for general configuration
-details. This section only covers configuration details specific to this
-driver.
-.PP
-The driver auto-detects all device information necessary to initialize
-the card. However, if you have problems with auto-detection, you can
-specify:
-.PP
-.RS 4
-VideoRam - in kilobytes
-.br
-MemBase - physical address of the linear framebuffer
-.br
-IOBase - physical address of the MMIO registers
-.br
-ChipID - PCI DEVICE ID
-.RE
-.PP
-In addition, the following driver
-.B Options
-are supported:
-.TP
-.BI "Option \*qSWcursor\*q \*q" boolean \*q
-Selects software cursor. The default is
-.B off.
-.TP
-.BI "Option \*qNoAccel\*q \*q" boolean \*q
-Enables or disables all hardware acceleration. The default is to
-.B enable
-hardware acceleration.
-.TP
-.BI "Option \*qDac6Bit\*q \*q" boolean \*q
-Enables or disables the use of 6 bits per color component when in 8 bpp
-mode (emulates VGA mode). By default, all 8 bits per color component
-are used. The default is
-.B off.
-.TP
-.BI "Option \*qVideoKey\*q \*q" integer \*q
-This overrides the default pixel value for the YUV video overlay key.
-The default value is
-.B undefined.
-.TP
-.BI "Option \*qDisplay\*q \*q" string \*q
-Select display mode for devices which support flat panels. Supported modes are:
-
-.B \*qFP\*q
-- use flat panel;
-
-.B \*qCRT\*q
-- use cathode ray tube;
-
-.B \*qMirror\*q
-- use both FP and CRT;
-
-.B \*qBIOS\*q
-- use mode as configured in the BIOS.
-
-The default is
-.B FP.
-
-.PP
-The following
-.B Options
-are mostly important for non-x86 architectures:
-.TP
-.BI "Option \*qProgramFPRegs\*q \*q" boolean \*q
-Enable or disable programming of the flat panel registers.
-Beware that this may damage your panel, so use this
-.B at your own risk.
-The default depends on the device.
-.TP
-.BI "Option \*qPanelWidth\*q \*q" integer \*q
-.TP
-.BI "Option \*qPanelHeight\*q \*q" integer \*q
-Override the flat panel dimensions in pixels. They are used to program the flat panel
-registers and normally determined using the video card BIOS. If the wrong dimensions
-are used, the system may hang.
-.TP
-.BI "Option \*qUseFBDev\*q \*q" boolean \*q
-Enable or disable use of an OS-specific framebuffer device interface
-(which is not supported on all OSs). See fbdevhw(__drivermansuffix__)
-for further information.
-Default:
-.BI on
-for PowerPC,
-.BI off
-for other architectures.
-.TP
-.BI "Option \*qDMAForXv\*q \*q" boolean \*q
-Try or don't try to use DMA for Xv image transfers. This will reduce CPU
-usage when playing big videos like DVDs, but may cause instabilities.
-Default: off.
-
-.PP
-The following additional
-.B Options
-are supported:
-.TP
-.BI "Option \*qShowCache\*q \*q" boolean \*q
-Enable or disable viewing offscreen cache memory. A
-development debug option. Default: off.
-.TP
-.BI "Option \*qVGAAccess\*q \*q" boolean \*q
-Tell the driver if it can do legacy VGA IOs to the card. This is
-necessary for properly resuming consoles when in VGA text mode, but
-shouldn't be if the console is using radeonfb or some other graphic
-mode driver. Some platforms like PowerPC have issues with those, and they aren't
-necessary unless you have a real text mode in console. The default is
-.B off
-on PowerPC and SPARC and
-.B on
-on other architectures.
-
-.PP
-.B Dualhead Note:
-The video BIOS on some laptops interacts strangely with dualhead.
-This can result in flickering and problems changing modes on crtc2.
-If you experience these problems try toggling your laptop's video
-output switch (e.g., fn-f7, etc.) prior to starting X or switch to
-another VT and back.
-
-.SH "SEE ALSO"
-__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
-.SH AUTHORS
-.nf
-Rickard E. (Rik) Faith \fIfaith at precisioninsight.com\fP
-Kevin E. Martin \fIkevin at precisioninsight.com\fP
diff --git a/src/r128.h b/src/r128.h
deleted file mode 100644
index 1205245..0000000
--- a/src/r128.h
+++ /dev/null
@@ -1,606 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- *
- */
-
-#ifndef _R128_H_
-#define _R128_H_
-
-#include <unistd.h>
-#include "xf86str.h"
-
- /* PCI support */
-#include "xf86Pci.h"
-
- /* XAA and Cursor Support */
-#include "xaa.h"
-#include "xf86Cursor.h"
-
- /* DDC support */
-#include "xf86DDC.h"
-
- /* Xv support */
-#include "xf86xv.h"
-
-#include "r128_probe.h"
-
- /* DRI support */
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "r128_dripriv.h"
-#include "dri.h"
-#include "GL/glxint.h"
-#endif
-
-#include "atipcirename.h"
-
-#define R128_DEBUG 0 /* Turn off debugging output */
-#define R128_IDLE_RETRY 32 /* Fall out of idle loops after this count */
-#define R128_TIMEOUT 2000000 /* Fall out of wait loops after this count */
-#define R128_MMIOSIZE 0x4000
-
-#define R128_VBIOS_SIZE 0x00010000
-
-#if R128_DEBUG
-#define R128TRACE(x) \
- do { \
- ErrorF("(**) %s(%d): ", R128_NAME, pScrn->scrnIndex); \
- ErrorF x; \
- } while (0);
-#else
-#define R128TRACE(x)
-#endif
-
-
-/* Other macros */
-#define R128_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
-#define R128_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
-#define R128PTR(pScrn) ((R128InfoPtr)(pScrn)->driverPrivate)
-
-typedef struct { /* All values in XCLKS */
- int ML; /* Memory Read Latency */
- int MB; /* Memory Burst Length */
- int Trcd; /* RAS to CAS delay */
- int Trp; /* RAS percentage */
- int Twr; /* Write Recovery */
- int CL; /* CAS Latency */
- int Tr2w; /* Read to Write Delay */
- int Rloop; /* Loop Latency */
- int Rloop_fudge; /* Add to ML to get Rloop */
- char *name;
-} R128RAMRec, *R128RAMPtr;
-
-typedef struct {
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 config_cntl;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 gen_reset_cntl;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 tmds_crc;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int post_div;
-
- /* PLL registers */
- CARD32 ppll_ref_div;
- CARD32 ppll_div_3;
- CARD32 htotal_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
-
- /* DDA register */
- CARD32 dda_config;
- CARD32 dda_on_off;
-
- /* DDA2 register */
- CARD32 dda2_config;
- CARD32 dda2_on_off;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-} R128SaveRec, *R128SavePtr;
-
-typedef struct {
- CARD16 reference_freq;
- CARD16 reference_div;
- unsigned min_pll_freq;
- unsigned max_pll_freq;
- CARD16 xclk;
-} R128PLLRec, *R128PLLPtr;
-
-typedef struct {
- int bitsPerPixel;
- int depth;
- int displayWidth;
- int pixel_code;
- int pixel_bytes;
- DisplayModePtr mode;
-} R128FBLayout;
-
-typedef enum
-{
- MT_NONE,
- MT_CRT,
- MT_LCD,
- MT_DFP,
- MT_CTV,
- MT_STV
-} R128MonitorType;
-
-typedef struct {
- EntityInfoPtr pEnt;
- pciVideoPtr PciInfo;
- PCITAG PciTag;
- int Chipset;
- Bool Primary;
-
- Bool FBDev;
-
- unsigned long LinearAddr; /* Frame buffer physical address */
- unsigned long MMIOAddr; /* MMIO region physical address */
- unsigned long BIOSAddr; /* BIOS physical address */
-
- void *MMIO; /* Map of MMIO region */
- void *FB; /* Map of frame buffer */
-
- CARD32 MemCntl;
- CARD32 BusCntl;
- unsigned long FbMapSize; /* Size of frame buffer, in bytes */
- int Flags; /* Saved copy of mode flags */
-
- CARD8 BIOSDisplay; /* Device the BIOS is set to display to */
-
- Bool HasPanelRegs; /* Current chip can connect to a FP */
- CARD8 *VBIOS; /* Video BIOS for mode validation on FPs */
- int FPBIOSstart; /* Start of the flat panel info */
-
- /* Computed values for FPs */
- int PanelXRes;
- int PanelYRes;
- int HOverPlus;
- int HSyncWidth;
- int HBlank;
- int VOverPlus;
- int VSyncWidth;
- int VBlank;
- int PanelPwrDly;
-
- R128PLLRec pll;
- R128RAMPtr ram;
-
- R128SaveRec SavedReg; /* Original (text) mode */
- R128SaveRec ModeReg; /* Current mode */
- Bool (*CloseScreen)(int, ScreenPtr);
- void (*BlockHandler)(int, pointer, pointer, pointer);
-
- Bool PaletteSavedOnVT; /* Palette saved on last VT switch */
-
- XAAInfoRecPtr accel;
- Bool accelOn;
- xf86CursorInfoPtr cursor;
- unsigned long cursor_start;
- unsigned long cursor_end;
-
- /*
- * XAAForceTransBlit is used to change the behavior of the XAA
- * SetupForScreenToScreenCopy function, to make it DGA-friendly.
- */
- Bool XAAForceTransBlit;
-
- int fifo_slots; /* Free slots in the FIFO (64 max) */
- int pix24bpp; /* Depth of pixmap for 24bpp framebuffer */
- Bool dac6bits; /* Use 6 bit DAC? */
-
- /* Computed values for Rage 128 */
- int pitch;
- int datatype;
- CARD32 dp_gui_master_cntl;
-
- /* Saved values for ScreenToScreenCopy */
- int xdir;
- int ydir;
-
- /* ScanlineScreenToScreenColorExpand support */
- unsigned char *scratch_buffer[1];
- unsigned char *scratch_save;
- int scanline_x;
- int scanline_y;
- int scanline_w;
- int scanline_h;
-#ifdef XF86DRI
- int scanline_hpass;
- int scanline_x1clip;
- int scanline_x2clip;
- int scanline_rop;
- int scanline_fg;
- int scanline_bg;
-#endif /* XF86DRI */
- int scanline_words;
- int scanline_direct;
- int scanline_bpp; /* Only used for ImageWrite */
-
- DGAModePtr DGAModes;
- int numDGAModes;
- Bool DGAactive;
- int DGAViewportStatus;
- DGAFunctionRec DGAFuncs;
-
- R128FBLayout CurrentLayout;
-#ifdef XF86DRI
- Bool directRenderingEnabled;
- DRIInfoPtr pDRIInfo;
- int drmFD;
- drm_context_t drmCtx;
- int numVisualConfigs;
- __GLXvisualConfig *pVisualConfigs;
- R128ConfigPrivPtr pVisualConfigsPriv;
-
- drm_handle_t fbHandle;
-
- drmSize registerSize;
- drm_handle_t registerHandle;
-
- Bool IsPCI; /* Current card is a PCI card */
- drmSize pciSize;
- drm_handle_t pciMemHandle;
- drmAddress PCI; /* Map */
-
- Bool allowPageFlip; /* Enable 3d page flipping */
- Bool have3DWindows; /* Are there any 3d clients? */
- int drmMinor;
-
- drmSize agpSize;
- drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */
- unsigned long agpOffset;
- drmAddress AGP; /* Map */
- int agpMode;
-
- Bool CCEInUse; /* CCE is currently active */
- int CCEMode; /* CCE mode that server/clients use */
- int CCEFifoSize; /* Size of the CCE command FIFO */
- Bool CCESecure; /* CCE security enabled */
- int CCEusecTimeout; /* CCE timeout in usecs */
-
- /* CCE ring buffer data */
- unsigned long ringStart; /* Offset into AGP space */
- drm_handle_t ringHandle; /* Handle from drmAddMap */
- drmSize ringMapSize; /* Size of map */
- int ringSize; /* Size of ring (in MB) */
- drmAddress ring; /* Map */
- int ringSizeLog2QW;
-
- unsigned long ringReadOffset; /* Offset into AGP space */
- drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */
- drmSize ringReadMapSize; /* Size of map */
- drmAddress ringReadPtr; /* Map */
-
- /* CCE vertex/indirect buffer data */
- unsigned long bufStart; /* Offset into AGP space */
- drm_handle_t bufHandle; /* Handle from drmAddMap */
- drmSize bufMapSize; /* Size of map */
- int bufSize; /* Size of buffers (in MB) */
- drmAddress buf; /* Map */
- int bufNumBufs; /* Number of buffers */
- drmBufMapPtr buffers; /* Buffer map */
-
- /* CCE AGP Texture data */
- unsigned long agpTexStart; /* Offset into AGP space */
- drm_handle_t agpTexHandle; /* Handle from drmAddMap */
- drmSize agpTexMapSize; /* Size of map */
- int agpTexSize; /* Size of AGP tex space (in MB) */
- drmAddress agpTex; /* Map */
- int log2AGPTexGran;
-
- /* CCE 2D accleration */
- drmBufPtr indirectBuffer;
- int indirectStart;
-
- /* DRI screen private data */
- int fbX;
- int fbY;
- int backX;
- int backY;
- int depthX;
- int depthY;
-
- int frontOffset;
- int frontPitch;
- int backOffset;
- int backPitch;
- int depthOffset;
- int depthPitch;
- int spanOffset;
- int textureOffset;
- int textureSize;
- int log2TexGran;
-
- /* Saved scissor values */
- CARD32 sc_left;
- CARD32 sc_right;
- CARD32 sc_top;
- CARD32 sc_bottom;
-
- CARD32 re_top_left;
- CARD32 re_width_height;
-
- CARD32 aux_sc_cntl;
-
- int irq;
- CARD32 gen_int_cntl;
-
- Bool DMAForXv;
-#endif
-
- XF86VideoAdaptorPtr adaptor;
- void (*VideoTimerCallback)(ScrnInfoPtr, Time);
- int videoKey;
- Bool showCache;
- OptionInfoPtr Options;
-
- Bool isDFP;
- Bool isPro2;
- I2CBusPtr pI2CBus;
- CARD32 DDCReg;
-
- Bool VGAAccess;
-
- /****** Added for dualhead support *******************/
- BOOL HasCRTC2; /* M3/M4 */
- BOOL IsSecondary; /* second Screen */
- BOOL IsPrimary; /* primary Screen */
- BOOL UseCRT; /* force use CRT port as primary */
- BOOL SwitchingMode;
- R128MonitorType DisplayType; /* Monitor connected on*/
-
-} R128InfoRec, *R128InfoPtr;
-
-#define R128WaitForFifo(pScrn, entries) \
-do { \
- if (info->fifo_slots < entries) R128WaitForFifoFunction(pScrn, entries); \
- info->fifo_slots -= entries; \
-} while (0)
-
-extern R128EntPtr R128EntPriv(ScrnInfoPtr pScrn);
-extern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
-extern void R128WaitForIdle(ScrnInfoPtr pScrn);
-extern void R128EngineReset(ScrnInfoPtr pScrn);
-extern void R128EngineFlush(ScrnInfoPtr pScrn);
-
-extern unsigned R128INPLL(ScrnInfoPtr pScrn, int addr);
-extern void R128WaitForVerticalSync(ScrnInfoPtr pScrn);
-
-extern Bool R128AccelInit(ScreenPtr pScreen);
-extern void R128EngineInit(ScrnInfoPtr pScrn);
-extern Bool R128CursorInit(ScreenPtr pScreen);
-extern Bool R128DGAInit(ScreenPtr pScreen);
-
-extern int R128MinBits(int val);
-
-extern void R128InitVideo(ScreenPtr pScreen);
-
-#ifdef XF86DRI
-extern Bool R128DRIScreenInit(ScreenPtr pScreen);
-extern void R128DRICloseScreen(ScreenPtr pScreen);
-extern Bool R128DRIFinishScreenInit(ScreenPtr pScreen);
-
-#define R128CCE_START(pScrn, info) \
-do { \
- int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_START); \
- if (_ret) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "%s: CCE start %d\n", __FUNCTION__, _ret); \
- } \
-} while (0)
-
-#define R128CCE_STOP(pScrn, info) \
-do { \
- int _ret = R128CCEStop(pScrn); \
- if (_ret) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "%s: CCE stop %d\n", __FUNCTION__, _ret); \
- } \
-} while (0)
-
-#define R128CCE_RESET(pScrn, info) \
-do { \
- if (info->directRenderingEnabled \
- && R128CCE_USE_RING_BUFFER(info->CCEMode)) { \
- int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_RESET); \
- if (_ret) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "%s: CCE reset %d\n", __FUNCTION__, _ret); \
- } \
- } \
-} while (0)
-
-extern drmBufPtr R128CCEGetBuffer(ScrnInfoPtr pScrn);
-#endif
-
-extern void R128CCEFlushIndirect(ScrnInfoPtr pScrn, int discard);
-extern void R128CCEReleaseIndirect(ScrnInfoPtr pScrn);
-extern void R128CCEWaitForIdle(ScrnInfoPtr pScrn);
-extern int R128CCEStop(ScrnInfoPtr pScrn);
-
-
-#define CCE_PACKET0( reg, n ) \
- (R128_CCE_PACKET0 | ((n) << 16) | ((reg) >> 2))
-#define CCE_PACKET1( reg0, reg1 ) \
- (R128_CCE_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
-#define CCE_PACKET2() \
- (R128_CCE_PACKET2)
-#define CCE_PACKET3( pkt, n ) \
- (R128_CCE_PACKET3 | (pkt) | ((n) << 16))
-
-
-#define R128_VERBOSE 0
-
-#define RING_LOCALS CARD32 *__head; int __count;
-
-#define R128CCE_REFRESH(pScrn, info) \
-do { \
- if ( R128_VERBOSE ) { \
- xf86DrvMsg( pScrn->scrnIndex, X_INFO, "REFRESH( %d ) in %s\n", \
- !info->CCEInUse , __FUNCTION__ ); \
- } \
- if ( !info->CCEInUse ) { \
- R128CCEWaitForIdle(pScrn); \
- BEGIN_RING( 6 ); \
- OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \
- OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \
- OUT_RING_REG( R128_AUX_SC_CNTL, info->aux_sc_cntl ); \
- ADVANCE_RING(); \
- info->CCEInUse = TRUE; \
- } \
-} while (0)
-
-#define BEGIN_RING( n ) do { \
- if ( R128_VERBOSE ) { \
- xf86DrvMsg( pScrn->scrnIndex, X_INFO, \
- "BEGIN_RING( %d ) in %s\n", n, __FUNCTION__ ); \
- } \
- if ( !info->indirectBuffer ) { \
- info->indirectBuffer = R128CCEGetBuffer( pScrn ); \
- info->indirectStart = 0; \
- } else if ( (info->indirectBuffer->used + 4*(n)) > \
- info->indirectBuffer->total ) { \
- R128CCEFlushIndirect( pScrn, 1 ); \
- } \
- __head = (pointer)((char *)info->indirectBuffer->address + \
- info->indirectBuffer->used); \
- __count = 0; \
-} while (0)
-
-#define ADVANCE_RING() do { \
- if ( R128_VERBOSE ) { \
- xf86DrvMsg( pScrn->scrnIndex, X_INFO, \
- "ADVANCE_RING() used: %d+%d=%d/%d\n", \
- info->indirectBuffer->used - info->indirectStart, \
- __count * (int)sizeof(CARD32), \
- info->indirectBuffer->used - info->indirectStart + \
- __count * (int)sizeof(CARD32), \
- info->indirectBuffer->total - info->indirectStart ); \
- } \
- info->indirectBuffer->used += __count * (int)sizeof(CARD32); \
-} while (0)
-
-#define OUT_RING( x ) do { \
- if ( R128_VERBOSE ) { \
- xf86DrvMsg( pScrn->scrnIndex, X_INFO, \
- " OUT_RING( 0x%08x )\n", (unsigned int)(x) ); \
- } \
- MMIO_OUT32(&__head[__count++], 0, (x)); \
-} while (0)
-
-#define OUT_RING_REG( reg, val ) \
-do { \
- OUT_RING( CCE_PACKET0( reg, 0 ) ); \
- OUT_RING( val ); \
-} while (0)
-
-#define FLUSH_RING() \
-do { \
- if ( R128_VERBOSE ) \
- xf86DrvMsg( pScrn->scrnIndex, X_INFO, \
- "FLUSH_RING in %s\n", __FUNCTION__ ); \
- if ( info->indirectBuffer ) { \
- R128CCEFlushIndirect( pScrn, 0 ); \
- } \
-} while (0)
-
-#endif
diff --git a/src/r128_accel.c b/src/r128_accel.c
deleted file mode 100644
index 8870682..0000000
--- a/src/r128_accel.c
+++ /dev/null
@@ -1,1880 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- *
- * Credits:
- *
- * Thanks to Alan Hourihane <alanh at fairlite.demon..co.uk> and SuSE for
- * providing source code to their 3.3.x Rage 128 driver. Portions of
- * this file are based on the acceleration code for that driver.
- *
- * References:
- *
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- * Notes on unimplemented XAA optimizations:
- *
- * SetClipping: The Rage128 doesn't support the full 16bit registers needed
- * for XAA clip rect support.
- * SolidFillTrap: This will probably work if we can compute the correct
- * Bresenham error values.
- * TwoPointLine: The Rage 128 supports Bresenham lines instead.
- * DashedLine with non-power-of-two pattern length: Apparently, there is
- * no way to set the length of the pattern -- it is always
- * assumed to be 8 or 32 (or 1024?).
- * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference
- * Manual where it states that monochrome expansion of frame
- * buffer data is not supported.
- * CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid
- * direct/indirect method. If we had more data registers,
- * then we could do better. If XAA supported a trigger write
- * address, the code would be simpler.
- * (Alan Hourihane) Update. We now use purely indirect and clip the full
- * rectangle. Seems as the direct method has some problems
- * with this, although this indirect method is much faster
- * than the old method of setting up the engine per scanline.
- * This code was the basis of the Radeon work we did.
- * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8
- * pattern from frame buffer memory.
- * ImageWrites: See CPUToScreenColorExpandFill.
- *
- */
-
-#define R128_TRAPEZOIDS 0 /* Trapezoids don't work */
-
- /* Driver data structures */
-#include <errno.h>
-
-#include "r128.h"
-#include "r128_reg.h"
-#include "r128_probe.h"
-#ifdef XF86DRI
-#include "r128_sarea.h"
-#define _XF86DRI_SERVER_
-#include "r128_dri.h"
-#include "r128_common.h"
-#endif
-
- /* Line support */
-#include "miline.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-
-static struct {
- int rop;
- int pattern;
-} R128_ROP[] = {
- { R128_ROP3_ZERO, R128_ROP3_ZERO }, /* GXclear */
- { R128_ROP3_DSa, R128_ROP3_DPa }, /* Gxand */
- { R128_ROP3_SDna, R128_ROP3_PDna }, /* GXandReverse */
- { R128_ROP3_S, R128_ROP3_P }, /* GXcopy */
- { R128_ROP3_DSna, R128_ROP3_DPna }, /* GXandInverted */
- { R128_ROP3_D, R128_ROP3_D }, /* GXnoop */
- { R128_ROP3_DSx, R128_ROP3_DPx }, /* GXxor */
- { R128_ROP3_DSo, R128_ROP3_DPo }, /* GXor */
- { R128_ROP3_DSon, R128_ROP3_DPon }, /* GXnor */
- { R128_ROP3_DSxn, R128_ROP3_PDxn }, /* GXequiv */
- { R128_ROP3_Dn, R128_ROP3_Dn }, /* GXinvert */
- { R128_ROP3_SDno, R128_ROP3_PDno }, /* GXorReverse */
- { R128_ROP3_Sn, R128_ROP3_Pn }, /* GXcopyInverted */
- { R128_ROP3_DSno, R128_ROP3_DPno }, /* GXorInverted */
- { R128_ROP3_DSan, R128_ROP3_DPan }, /* GXnand */
- { R128_ROP3_ONE, R128_ROP3_ONE } /* GXset */
-};
-
-extern int getR128EntityIndex(void);
-
-/* Flush all dirty data in the Pixel Cache to memory. */
-void R128EngineFlush(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i;
-
- OUTREGP(R128_PC_NGUI_CTLSTAT, R128_PC_FLUSH_ALL, ~R128_PC_FLUSH_ALL);
- for (i = 0; i < R128_TIMEOUT; i++) {
- if (!(INREG(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) break;
- }
-}
-
-/* Reset graphics card to known state. */
-void R128EngineReset(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- CARD32 clock_cntl_index;
- CARD32 mclk_cntl;
- CARD32 gen_reset_cntl;
-
- R128EngineFlush(pScrn);
-
- clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX);
- mclk_cntl = INPLL(pScrn, R128_MCLK_CNTL);
-
- OUTPLL(R128_MCLK_CNTL, mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
-
- gen_reset_cntl = INREG(R128_GEN_RESET_CNTL);
-
- OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
- INREG(R128_GEN_RESET_CNTL);
- OUTREG(R128_GEN_RESET_CNTL,
- gen_reset_cntl & (CARD32)(~R128_SOFT_RESET_GUI));
- INREG(R128_GEN_RESET_CNTL);
-
- OUTPLL(R128_MCLK_CNTL, mclk_cntl);
- OUTREG(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
- OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl);
-}
-
-/* The FIFO has 64 slots. This routines waits until at least `entries' of
- these slots are empty. */
-void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i;
-
- for (;;) {
- for (i = 0; i < R128_TIMEOUT; i++) {
- info->fifo_slots = INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
- if (info->fifo_slots >= entries) return;
- }
- R128TRACE(("FIFO timed out: %d entries, stat=0x%08x, probe=0x%08x\n",
- INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
- INREG(R128_GUI_STAT),
- INREG(R128_GUI_PROBE)));
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "FIFO timed out, resetting engine...\n");
- R128EngineReset(pScrn);
-#ifdef XF86DRI
- R128CCE_RESET(pScrn, info);
- if (info->directRenderingEnabled) {
- R128CCE_START(pScrn, info);
- }
-#endif
- }
-}
-
-/* Wait for the graphics engine to be completely idle: the FIFO has
- drained, the Pixel Cache is flushed, and the engine is idle. This is a
- standard "sync" function that will make the hardware "quiescent". */
-void R128WaitForIdle(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i;
-
- R128WaitForFifoFunction(pScrn, 64);
-
- for (;;) {
- for (i = 0; i < R128_TIMEOUT; i++) {
- if (!(INREG(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
- R128EngineFlush(pScrn);
- return;
- }
- }
- R128TRACE(("Idle timed out: %d entries, stat=0x%08x, probe=0x%08x\n",
- INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
- INREG(R128_GUI_STAT),
- INREG(R128_GUI_PROBE)));
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Idle timed out, resetting engine...\n");
-#ifdef XF86DRI
- R128CCE_STOP(pScrn, info);
-#endif
- R128EngineReset(pScrn);
-#ifdef XF86DRI
- R128CCE_RESET(pScrn, info);
- if (info->directRenderingEnabled) {
- R128CCE_START(pScrn, info);
- }
-#endif
- }
-}
-
-#ifdef XF86DRI
-/* Wait until the CCE is completely idle: the FIFO has drained and the
- * CCE is idle.
- */
-void R128CCEWaitForIdle(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int ret, i;
-
- FLUSH_RING();
-
- for (;;) {
- i = 0;
- do {
- ret = drmCommandNone(info->drmFD, DRM_R128_CCE_IDLE);
- } while ( ret && errno == EBUSY && i++ < (R128_IDLE_RETRY * R128_IDLE_RETRY) );
-
- if (ret && ret != -EBUSY) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: CCE idle %d\n", __FUNCTION__, ret);
- }
-
- if (i > R128_IDLE_RETRY) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: (DEBUG) CCE idle took i = %d\n", __FUNCTION__, i);
- }
-
- if (ret == 0) return;
-
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Idle timed out, resetting engine...\n");
- R128CCE_STOP(pScrn, info);
- R128EngineReset(pScrn);
-
- /* Always restart the engine when doing CCE 2D acceleration */
- R128CCE_RESET(pScrn, info);
- R128CCE_START(pScrn, info);
- }
-}
-
-int R128CCEStop(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- drmR128CCEStop stop;
- int ret, i;
-
- stop.flush = 1;
- stop.idle = 1;
-
- ret = drmCommandWrite( info->drmFD, DRM_R128_CCE_STOP,
- &stop, sizeof(drmR128CCEStop) );
-
- if ( ret == 0 ) {
- return 0;
- } else if ( errno != EBUSY ) {
- return -errno;
- }
-
- stop.flush = 0;
-
- i = 0;
- do {
- ret = drmCommandWrite( info->drmFD, DRM_R128_CCE_STOP,
- &stop, sizeof(drmR128CCEStop) );
- } while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
-
- if ( ret == 0 ) {
- return 0;
- } else if ( errno != EBUSY ) {
- return -errno;
- }
-
- stop.idle = 0;
-
- if ( drmCommandWrite( info->drmFD, DRM_R128_CCE_STOP,
- &stop, sizeof(drmR128CCEStop) )) {
- return -errno;
- } else {
- return 0;
- }
-}
-
-#endif
-
-/* Setup for XAA SolidFill. */
-static void R128SetupForSolidFill(ScrnInfoPtr pScrn,
- int color, int rop, unsigned int planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 4);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_SOLID_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].pattern));
- OUTREG(R128_DP_BRUSH_FRGD_CLR, color);
- OUTREG(R128_DP_WRITE_MASK, planemask);
- OUTREG(R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT
- | R128_DST_Y_TOP_TO_BOTTOM));
-}
-
-/* Subsequent XAA SolidFillRect.
-
- Tests: xtest CH06/fllrctngl, xterm
-*/
-static void R128SubsequentSolidFillRect(ScrnInfoPtr pScrn,
- int x, int y, int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 2);
- OUTREG(R128_DST_Y_X, (y << 16) | x);
- OUTREG(R128_DST_WIDTH_HEIGHT, (w << 16) | h);
-}
-
-/* Setup for XAA solid lines. */
-static void R128SetupForSolidLine(ScrnInfoPtr pScrn,
- int color, int rop, unsigned int planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_SOLID_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].pattern));
- OUTREG(R128_DP_BRUSH_FRGD_CLR, color);
- OUTREG(R128_DP_WRITE_MASK, planemask);
-}
-
-
-/* Subsequent XAA solid Bresenham line.
-
- Tests: xtest CH06/drwln, ico, Mark Vojkovich's linetest program
-
- [See http://www.xfree86.org/devel/archives/devel/1999-Jun/0102.shtml for
- Mark Vojkovich's linetest program, posted 2Jun99 to devel at xfree86.org.]
-
- x11perf -line500
- 1024x768 at 76Hz 1024x768 at 76Hz
- 8bpp 32bpp
- not used: 39700.0/sec 34100.0/sec
- used: 47600.0/sec 36800.0/sec
-*/
-static void R128SubsequentSolidBresenhamLine(ScrnInfoPtr pScrn,
- int x, int y,
- int major, int minor,
- int err, int len, int octant)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int flags = 0;
-
- if (octant & YMAJOR) flags |= R128_DST_Y_MAJOR;
- if (!(octant & XDECREASING)) flags |= R128_DST_X_DIR_LEFT_TO_RIGHT;
- if (!(octant & YDECREASING)) flags |= R128_DST_Y_DIR_TOP_TO_BOTTOM;
-
- R128WaitForFifo(pScrn, 6);
- OUTREG(R128_DP_CNTL_XDIR_YDIR_YMAJOR, flags);
- OUTREG(R128_DST_Y_X, (y << 16) | x);
- OUTREG(R128_DST_BRES_ERR, err);
- OUTREG(R128_DST_BRES_INC, minor);
- OUTREG(R128_DST_BRES_DEC, -major);
- OUTREG(R128_DST_BRES_LNTH, len);
-}
-
-/* Subsequent XAA solid horizontal and vertical lines
-
- 1024x768 at 76Hz 8bpp
- Without With
- x11perf -hseg500 87600.0/sec 798000.0/sec
- x11perf -vseg500 38100.0/sec 38000.0/sec
-*/
-static void R128SubsequentSolidHorVertLine(ScrnInfoPtr pScrn,
- int x, int y, int len, int dir )
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 1);
- OUTREG(R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT
- | R128_DST_Y_TOP_TO_BOTTOM));
-
- if (dir == DEGREES_0) {
- R128SubsequentSolidFillRect(pScrn, x, y, len, 1);
- } else {
- R128SubsequentSolidFillRect(pScrn, x, y, 1, len);
- }
-}
-
-/* Setup for XAA dashed lines.
-
- Tests: xtest CH05/stdshs, XFree86/drwln
-
- NOTE: Since we can only accelerate lines with power-of-2 patterns of
- length <= 32, these x11perf numbers are not representative of the
- speed-up on appropriately-sized patterns.
-
- 1024x768 at 76Hz 8bpp
- Without With
- x11perf -dseg100 218000.0/sec 222000.0/sec
- x11perf -dline100 215000.0/sec 221000.0/sec
- x11perf -ddline100 178000.0/sec 180000.0/sec
-*/
-static void R128SetupForDashedLine(ScrnInfoPtr pScrn,
- int fg, int bg,
- int rop, unsigned int planemask,
- int length, unsigned char *pattern)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- CARD32 pat = *(CARD32 *)(pointer)pattern;
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
-# define PAT_SHIFT(pat,n) pat << n
-#else
-# define PAT_SHIFT(pat,n) pat >> n
-#endif
-
- switch (length) {
- case 2: pat |= PAT_SHIFT(pat,2); /* fall through */
- case 4: pat |= PAT_SHIFT(pat,4); /* fall through */
- case 8: pat |= PAT_SHIFT(pat,8); /* fall through */
- case 16: pat |= PAT_SHIFT(pat,16);
- }
-
- R128WaitForFifo(pScrn, 5);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | (bg == -1
- ? R128_GMC_BRUSH_32x1_MONO_FG_LA
- : R128_GMC_BRUSH_32x1_MONO_FG_BG)
- | R128_ROP[rop].pattern
- | R128_GMC_BYTE_LSB_TO_MSB));
- OUTREG(R128_DP_WRITE_MASK, planemask);
- OUTREG(R128_DP_BRUSH_FRGD_CLR, fg);
- OUTREG(R128_DP_BRUSH_BKGD_CLR, bg);
- OUTREG(R128_BRUSH_DATA0, pat);
-}
-
-/* Subsequent XAA dashed line. */
-static void R128SubsequentDashedBresenhamLine(ScrnInfoPtr pScrn,
- int x, int y,
- int major, int minor,
- int err, int len, int octant,
- int phase)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int flags = 0;
-
- if (octant & YMAJOR) flags |= R128_DST_Y_MAJOR;
- if (!(octant & XDECREASING)) flags |= R128_DST_X_DIR_LEFT_TO_RIGHT;
- if (!(octant & YDECREASING)) flags |= R128_DST_Y_DIR_TOP_TO_BOTTOM;
-
- R128WaitForFifo(pScrn, 7);
- OUTREG(R128_DP_CNTL_XDIR_YDIR_YMAJOR, flags);
- OUTREG(R128_DST_Y_X, (y << 16) | x);
- OUTREG(R128_BRUSH_Y_X, (phase << 16) | phase);
- OUTREG(R128_DST_BRES_ERR, err);
- OUTREG(R128_DST_BRES_INC, minor);
- OUTREG(R128_DST_BRES_DEC, -major);
- OUTREG(R128_DST_BRES_LNTH, len);
-}
-
-#if R128_TRAPEZOIDS
- /* This doesn't work. Except in the
- lower-left quadrant, all of the pixel
- errors appear to be because eL and eR
- are not correct. Drawing from right to
- left doesn't help. Be aware that the
- non-_SUB registers set the sub-pixel
- values to 0.5 (0x08), which isn't what
- XAA wants. */
-/* Subsequent XAA SolidFillTrap. XAA always passes data that assumes we
- fill from top to bottom, so dyL and dyR are always non-negative. */
-static void R128SubsequentSolidFillTrap(ScrnInfoPtr pScrn, int y, int h,
- int left, int dxL, int dyL, int eL,
- int right, int dxR, int dyR, int eR)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int flags = 0;
- int Lymajor = 0;
- int Rymajor = 0;
- int origdxL = dxL;
- int origdxR = dxR;
-
- R128TRACE(("Trap %d %d; L %d %d %d %d; R %d %d %d %d\n",
- y, h,
- left, dxL, dyL, eL,
- right, dxR, dyR, eR));
-
- if (dxL < 0) dxL = -dxL; else flags |= (1 << 0) /* | (1 << 8) */;
- if (dxR < 0) dxR = -dxR; else flags |= (1 << 6);
-
- R128WaitForFifo(pScrn, 11);
-
-#if 1
- OUTREG(R128_DP_CNTL, flags | (1 << 1) | (1 << 7));
- OUTREG(R128_DST_Y_SUB, ((y) << 4) | 0x0 );
- OUTREG(R128_DST_X_SUB, ((left) << 4)|0x0);
- OUTREG(R128_TRAIL_BRES_ERR, eR-dxR);
- OUTREG(R128_TRAIL_BRES_INC, dxR);
- OUTREG(R128_TRAIL_BRES_DEC, -dyR);
- OUTREG(R128_TRAIL_X_SUB, ((right) << 4) | 0x0);
- OUTREG(R128_LEAD_BRES_ERR, eL-dxL);
- OUTREG(R128_LEAD_BRES_INC, dxL);
- OUTREG(R128_LEAD_BRES_DEC, -dyL);
- OUTREG(R128_LEAD_BRES_LNTH_SUB, ((h) << 4) | 0x00);
-#else
- OUTREG(R128_DP_CNTL, flags | (1 << 1) );
- OUTREG(R128_DST_Y_SUB, (y << 4));
- OUTREG(R128_DST_X_SUB, (right << 4));
- OUTREG(R128_TRAIL_BRES_ERR, eL);
- OUTREG(R128_TRAIL_BRES_INC, dxL);
- OUTREG(R128_TRAIL_BRES_DEC, -dyL);
- OUTREG(R128_TRAIL_X_SUB, (left << 4) | 0);
- OUTREG(R128_LEAD_BRES_ERR, eR);
- OUTREG(R128_LEAD_BRES_INC, dxR);
- OUTREG(R128_LEAD_BRES_DEC, -dyR);
- OUTREG(R128_LEAD_BRES_LNTH_SUB, h << 4);
-#endif
-}
-#endif
-
-/* Setup for XAA screen-to-screen copy.
-
- Tests: xtest CH06/fllrctngl (also tests transparency).
-*/
-static void R128SetupForScreenToScreenCopy(ScrnInfoPtr pScrn,
- int xdir, int ydir, int rop,
- unsigned int planemask,
- int trans_color)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- info->xdir = xdir;
- info->ydir = ydir;
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_SOLID_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].rop
- | R128_DP_SRC_SOURCE_MEMORY));
- OUTREG(R128_DP_WRITE_MASK, planemask);
- OUTREG(R128_DP_CNTL, ((xdir >= 0 ? R128_DST_X_LEFT_TO_RIGHT : 0)
- | (ydir >= 0
- ? R128_DST_Y_TOP_TO_BOTTOM
- : 0)));
-
- if ((trans_color != -1) || (info->XAAForceTransBlit == TRUE)) {
- /* Set up for transparency */
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_CLR_CMP_CLR_SRC, trans_color);
- OUTREG(R128_CLR_CMP_MASK, R128_CLR_CMP_MSK);
- OUTREG(R128_CLR_CMP_CNTL, (R128_SRC_CMP_NEQ_COLOR
- | R128_CLR_CMP_SRC_SOURCE));
- }
-}
-
-/* Subsequent XAA screen-to-screen copy. */
-static void R128SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb,
- int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if (info->xdir < 0) xa += w - 1, xb += w - 1;
- if (info->ydir < 0) ya += h - 1, yb += h - 1;
-
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_SRC_Y_X, (ya << 16) | xa);
- OUTREG(R128_DST_Y_X, (yb << 16) | xb);
- OUTREG(R128_DST_HEIGHT_WIDTH, (h << 16) | w);
-}
-
-/* Setup for XAA mono 8x8 pattern color expansion. Patterns with
- transparency use `bg == -1'. This routine is only used if the XAA
- pixmap cache is turned on.
-
- Tests: xtest XFree86/fllrctngl (no other test will test this routine with
- both transparency and non-transparency)
-
- 1024x768 at 76Hz 8bpp
- Without With
- x11perf -srect100 38600.0/sec 85700.0/sec
- x11perf -osrect100 38600.0/sec 85700.0/sec
-*/
-static void R128SetupForMono8x8PatternFill(ScrnInfoPtr pScrn,
- int patternx, int patterny,
- int fg, int bg, int rop,
- unsigned int planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 6);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | (bg == -1
- ? R128_GMC_BRUSH_8X8_MONO_FG_LA
- : R128_GMC_BRUSH_8X8_MONO_FG_BG)
- | R128_ROP[rop].pattern
- | R128_GMC_BYTE_LSB_TO_MSB));
- OUTREG(R128_DP_WRITE_MASK, planemask);
- OUTREG(R128_DP_BRUSH_FRGD_CLR, fg);
- OUTREG(R128_DP_BRUSH_BKGD_CLR, bg);
- OUTREG(R128_BRUSH_DATA0, patternx);
- OUTREG(R128_BRUSH_DATA1, patterny);
-}
-
-/* Subsequent XAA 8x8 pattern color expansion. Because they are used in
- the setup function, `patternx' and `patterny' are not used here. */
-static void R128SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn,
- int patternx, int patterny,
- int x, int y, int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_BRUSH_Y_X, (patterny << 8) | patternx);
- OUTREG(R128_DST_Y_X, (y << 16) | x);
- OUTREG(R128_DST_HEIGHT_WIDTH, (h << 16) | w);
-}
-
-#if 0
-/* Setup for XAA color 8x8 pattern fill.
-
- Tests: xtest XFree86/fllrctngl (with Mono8x8PatternFill off)
-*/
-static void R128SetupForColor8x8PatternFill(ScrnInfoPtr pScrn,
- int patx, int paty,
- int rop, unsigned int planemask,
- int trans_color)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128TRACE(("Color8x8 %d %d %d\n", trans_color, patx, paty));
-
- R128WaitForFifo(pScrn, 2);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_8x8_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].rop
- | R128_DP_SRC_SOURCE_MEMORY));
- OUTREG(R128_DP_WRITE_MASK, planemask);
-
- if (trans_color != -1) {
- /* Set up for transparency */
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_CLR_CMP_CLR_SRC, trans_color);
- OUTREG(R128_CLR_CMP_MASK, R128_CLR_CMP_MSK);
- OUTREG(R128_CLR_CMP_CNTL, (R128_SRC_CMP_NEQ_COLOR
- | R128_CLR_CMP_SRC_SOURCE));
- }
-}
-
-/* Subsequent XAA 8x8 pattern color expansion. */
-static void R128SubsequentColor8x8PatternFillRect( ScrnInfoPtr pScrn,
- int patx, int paty,
- int x, int y, int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128TRACE(("Color8x8 %d,%d %d,%d %d %d\n", patx, paty, x, y, w, h));
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_SRC_Y_X, (paty << 16) | patx);
- OUTREG(R128_DST_Y_X, (y << 16) | x);
- OUTREG(R128_DST_HEIGHT_WIDTH, (h << 16) | w);
-}
-#endif
-
-/* Setup for XAA indirect CPU-to-screen color expansion (indirect).
- Because of how the scratch buffer is initialized, this is really a
- mainstore-to-screen color expansion. Transparency is supported when `bg
- == -1'.
-
- x11perf -ftext (pure indirect):
- 1024x768 at 76Hz 1024x768 at 76Hz
- 8bpp 32bpp
- not used: 685000.0/sec 794000.0/sec
- used: 1070000.0/sec 1080000.0/sec
-
- We could improve this indirect routine by about 10% if the hardware
- could accept DWORD padded scanlines, or if XAA could provide bit-packed
- data. We might also be able to move to a direct routine if there were
- more HOST_DATA registers.
-
- Implementing the hybrid indirect/direct scheme improved performance in a
- few areas:
-
- 1024x768 at 76 8bpp
- Indirect Hybrid
- x11perf -oddsrect10 50100.0/sec 71700.0/sec
- x11perf -oddsrect100 4240.0/sec 6660.0/sec
- x11perf -bigsrect10 50300.0/sec 71100.0/sec
- x11perf -bigsrect100 4190.0/sec 6800.0/sec
- x11perf -polytext 584000.0/sec 714000.0/sec
- x11perf -polytext16 154000.0/sec 172000.0/sec
- x11perf -seg1 1780000.0/sec 1880000.0/sec
- x11perf -copyplane10 42900.0/sec 58300.0/sec
- x11perf -copyplane100 4400.0/sec 6710.0/sec
- x11perf -putimagexy10 5090.0/sec 6670.0/sec
- x11perf -putimagexy100 424.0/sec 575.0/sec
-
- 1024x768 at 76 -depth 24 -fbbpp 32
- Indirect Hybrid
- x11perf -oddsrect100 4240.0/sec 6670.0/sec
- x11perf -bigsrect100 4190.0/sec 6800.0/sec
- x11perf -polytext 585000.0/sec 719000.0/sec
- x11perf -seg1 2960000.0/sec 2990000.0/sec
- x11perf -copyplane100 4400.0/sec 6700.0/sec
- x11perf -putimagexy100 138.0/sec 191.0/sec
-
-*/
-static void R128SetupForScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrn,
- int fg, int bg,
- int rop,
- unsigned int
- planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 4);
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_DST_CLIPPING
- | R128_GMC_BRUSH_NONE
- | (bg == -1
- ? R128_GMC_SRC_DATATYPE_MONO_FG_LA
- : R128_GMC_SRC_DATATYPE_MONO_FG_BG)
- | R128_ROP[rop].rop
- | R128_GMC_BYTE_LSB_TO_MSB
- | R128_DP_SRC_SOURCE_HOST_DATA));
-#else /* X_BYTE_ORDER == X_BIG_ENDIAN */
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_DST_CLIPPING
- | R128_GMC_BRUSH_NONE
- | (bg == -1
- ? R128_GMC_SRC_DATATYPE_MONO_FG_LA
- : R128_GMC_SRC_DATATYPE_MONO_FG_BG)
- | R128_ROP[rop].rop
- | R128_DP_SRC_SOURCE_HOST_DATA));
-#endif
- OUTREG(R128_DP_WRITE_MASK, planemask);
- OUTREG(R128_DP_SRC_FRGD_CLR, fg);
- OUTREG(R128_DP_SRC_BKGD_CLR, bg);
-}
-
-/* Subsequent XAA indirect CPU-to-screen color expansion. This is only
- called once for each rectangle. */
-static void R128SubsequentScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrn,
- int x, int y,
- int w, int h,
- int skipleft)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int x1clip = x+skipleft;
- int x2clip = x+w;
-
- info->scanline_h = h;
- info->scanline_words = (w + 31) >> 5;
-
-#if 0
- /* Seems as though the Rage128's doesn't like blitting directly
- * as we must be overwriting something too quickly, therefore we
- * render to the buffer first and then blit */
- if ((info->scanline_words * h) <= 9) {
- /* Turn on direct for less than 9 dword colour expansion */
- info->scratch_buffer[0]
- = (unsigned char *)(ADDRREG(R128_HOST_DATA_LAST)
- - (info->scanline_words - 1));
- info->scanline_direct = 1;
- } else
-#endif
- {
- /* Use indirect for anything else */
- info->scratch_buffer[0] = info->scratch_save;
- info->scanline_direct = 0;
- }
-
- if (pScrn->bitsPerPixel == 24) {
- x1clip *= 3;
- x2clip *= 3;
- }
-
- R128WaitForFifo(pScrn, 4 + (info->scanline_direct ?
- (info->scanline_words * h) : 0) );
- OUTREG(R128_SC_TOP_LEFT, (y << 16) | (x1clip & 0xffff));
- OUTREG(R128_SC_BOTTOM_RIGHT, ((y+h-1) << 16) | ((x2clip-1) & 0xffff));
- OUTREG(R128_DST_Y_X, (y << 16) | (x & 0xffff));
- /* Have to pad the width here and use clipping engine */
- OUTREG(R128_DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
-}
-
-/* Subsequent XAA indirect CPU-to-screen color expansion. This is called
- once for each scanline. */
-static void R128SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- CARD32 *p = (pointer)info->scratch_buffer[bufno];
- int i;
- int left = info->scanline_words;
- volatile CARD32 *d;
-
- if (info->scanline_direct) return;
- --info->scanline_h;
- while (left) {
- write_mem_barrier();
- if (left <= 8) {
- /* Last scanline - finish write to DATA_LAST */
- if (info->scanline_h == 0) {
- R128WaitForFifo(pScrn, left);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(R128_HOST_DATA_LAST) - (left - 1); left; --left)
- *d++ = *p++;
- return;
- } else {
- R128WaitForFifo(pScrn, left);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(R128_HOST_DATA7) - (left - 1); left; --left)
- *d++ = *p++;
- }
- } else {
- R128WaitForFifo(pScrn, 8);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(R128_HOST_DATA0), i = 0; i < 8; i++)
- *d++ = *p++;
- left -= 8;
- }
- }
-}
-
-/* Setup for XAA indirect image write.
-
- 1024x768 at 76Hz 8bpp
- Without With
- x11perf -putimage10 37500.0/sec 39300.0/sec
- x11perf -putimage100 2150.0/sec 1170.0/sec
- x11perf -putimage500 108.0/sec 49.8/sec
- */
-static void R128SetupForScanlineImageWrite(ScrnInfoPtr pScrn,
- int rop,
- unsigned int planemask,
- int trans_color,
- int bpp,
- int depth)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- info->scanline_bpp = bpp;
-
- R128WaitForFifo(pScrn, 2);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_DST_CLIPPING
- | R128_GMC_BRUSH_1X8_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].rop
- | R128_GMC_BYTE_LSB_TO_MSB
- | R128_DP_SRC_SOURCE_HOST_DATA));
- OUTREG(R128_DP_WRITE_MASK, planemask);
-
- if (trans_color != -1) {
- /* Set up for transparency */
- R128WaitForFifo(pScrn, 3);
- OUTREG(R128_CLR_CMP_CLR_SRC, trans_color);
- OUTREG(R128_CLR_CMP_MASK, R128_CLR_CMP_MSK);
- OUTREG(R128_CLR_CMP_CNTL, (R128_SRC_CMP_NEQ_COLOR
- | R128_CLR_CMP_SRC_SOURCE));
- }
-}
-
-/* Subsequent XAA indirect image write. This is only called once for each
- rectangle. */
-static void R128SubsequentScanlineImageWriteRect(ScrnInfoPtr pScrn,
- int x, int y,
- int w, int h,
- int skipleft)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int x1clip = x+skipleft;
- int x2clip = x+w;
-
- int shift = 0; /* 32bpp */
-
- if (pScrn->bitsPerPixel == 8) shift = 3;
- else if (pScrn->bitsPerPixel == 16) shift = 1;
-
- info->scanline_h = h;
- info->scanline_words = (w * info->scanline_bpp + 31) >> 5;
-
-#if 0
- /* Seeing as the CPUToScreen doesn't like this, I've done this
- * here too, as it uses pretty much the same path. */
- if ((info->scanline_words * h) <= 9) {
- /* Turn on direct for less than 9 dword colour expansion */
- info->scratch_buffer[0]
- = (unsigned char *)(ADDRREG(R128_HOST_DATA_LAST)
- - (info->scanline_words - 1));
- info->scanline_direct = 1;
- } else
-#endif
- {
- /* Use indirect for anything else */
- info->scratch_buffer[0] = info->scratch_save;
- info->scanline_direct = 0;
- }
-
- if (pScrn->bitsPerPixel == 24) {
- x1clip *= 3;
- x2clip *= 3;
- }
-
- R128WaitForFifo(pScrn, 4 + (info->scanline_direct ?
- (info->scanline_words * h) : 0) );
- OUTREG(R128_SC_TOP_LEFT, (y << 16) | (x1clip & 0xffff));
- OUTREG(R128_SC_BOTTOM_RIGHT, ((y+h-1) << 16) | ((x2clip-1) & 0xffff));
- OUTREG(R128_DST_Y_X, (y << 16) | (x & 0xffff));
- /* Have to pad the width here and use clipping engine */
- OUTREG(R128_DST_HEIGHT_WIDTH, (h << 16) | ((w + shift) & ~shift));
-}
-
-/* Subsequent XAA indirect iamge write. This is called once for each
- scanline. */
-static void R128SubsequentImageWriteScanline(ScrnInfoPtr pScrn, int bufno)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- CARD32 *p = (pointer)info->scratch_buffer[bufno];
- int i;
- int left = info->scanline_words;
- volatile CARD32 *d;
-
- if (info->scanline_direct) return;
- --info->scanline_h;
- while (left) {
- write_mem_barrier();
- if (left <= 8) {
- /* Last scanline - finish write to DATA_LAST */
- if (info->scanline_h == 0) {
- R128WaitForFifo(pScrn, left);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(R128_HOST_DATA_LAST) - (left - 1); left; --left)
- *d++ = *p++;
- return;
- } else {
- R128WaitForFifo(pScrn, left);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(R128_HOST_DATA7) - (left - 1); left; --left)
- *d++ = *p++;
- }
- } else {
- R128WaitForFifo(pScrn, 8);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(R128_HOST_DATA0), i = 0; i < 8; i++)
- *d++ = *p++;
- left -= 8;
- }
- }
-}
-
-/* Initialize the acceleration hardware. */
-void R128EngineInit(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128TRACE(("EngineInit (%d/%d)\n", info->CurrentLayout.pixel_code, info->CurrentLayout.bitsPerPixel));
-
- OUTREG(R128_SCALE_3D_CNTL, 0);
- R128EngineReset(pScrn);
-
- switch (info->CurrentLayout.pixel_code) {
- case 8: info->datatype = 2; break;
- case 15: info->datatype = 3; break;
- case 16: info->datatype = 4; break;
- case 24: info->datatype = 5; break;
- case 32: info->datatype = 6; break;
- default:
- R128TRACE(("Unknown depth/bpp = %d/%d (code = %d)\n",
- info->CurrentLayout.depth, info->CurrentLayout.bitsPerPixel,
- info->CurrentLayout.pixel_code));
- }
- info->pitch = (info->CurrentLayout.displayWidth / 8) * (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1);
-
- R128TRACE(("Pitch for acceleration = %d\n", info->pitch));
-
- R128WaitForFifo(pScrn, 2);
- OUTREG(R128_DEFAULT_OFFSET, pScrn->fbOffset);
- OUTREG(R128_DEFAULT_PITCH, info->pitch);
-
- R128WaitForFifo(pScrn, 4);
- OUTREG(R128_AUX_SC_CNTL, 0);
- OUTREG(R128_DEFAULT_SC_BOTTOM_RIGHT, (R128_DEFAULT_SC_RIGHT_MAX
- | R128_DEFAULT_SC_BOTTOM_MAX));
- OUTREG(R128_SC_TOP_LEFT, 0);
- OUTREG(R128_SC_BOTTOM_RIGHT, (R128_DEFAULT_SC_RIGHT_MAX
- | R128_DEFAULT_SC_BOTTOM_MAX));
-
- info->dp_gui_master_cntl = ((info->datatype << R128_GMC_DST_DATATYPE_SHIFT)
- | R128_GMC_CLR_CMP_CNTL_DIS
- | R128_GMC_AUX_CLIP_DIS);
- R128WaitForFifo(pScrn, 1);
- OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_SOLID_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR));
-
- R128WaitForFifo(pScrn, 8);
- OUTREG(R128_DST_BRES_ERR, 0);
- OUTREG(R128_DST_BRES_INC, 0);
- OUTREG(R128_DST_BRES_DEC, 0);
- OUTREG(R128_DP_BRUSH_FRGD_CLR, 0xffffffff);
- OUTREG(R128_DP_BRUSH_BKGD_CLR, 0x00000000);
- OUTREG(R128_DP_SRC_FRGD_CLR, 0xffffffff);
- OUTREG(R128_DP_SRC_BKGD_CLR, 0x00000000);
- OUTREG(R128_DP_WRITE_MASK, 0xffffffff);
-
- R128WaitForFifo(pScrn, 1);
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* FIXME: this is a kludge for texture uploads in the 3D driver. Look at
- * how the radeon driver handles HOST_DATA_SWAP if you want to implement
- * CCE ImageWrite acceleration or anything needing this bit */
-#ifdef XF86DRI
- if (info->directRenderingEnabled)
- OUTREGP(R128_DP_DATATYPE, 0, ~R128_HOST_BIG_ENDIAN_EN);
- else
-#endif
- OUTREGP(R128_DP_DATATYPE,
- R128_HOST_BIG_ENDIAN_EN, ~R128_HOST_BIG_ENDIAN_EN);
-#else /* X_LITTLE_ENDIAN */
- OUTREGP(R128_DP_DATATYPE, 0, ~R128_HOST_BIG_ENDIAN_EN);
-#endif
-
-#ifdef XF86DRI
- info->sc_left = 0x00000000;
- info->sc_right = R128_DEFAULT_SC_RIGHT_MAX;
- info->sc_top = 0x00000000;
- info->sc_bottom = R128_DEFAULT_SC_BOTTOM_MAX;
-
- info->re_top_left = 0x00000000;
- info->re_width_height = ((0x7ff << R128_RE_WIDTH_SHIFT) |
- (0x7ff << R128_RE_HEIGHT_SHIFT));
-
- info->aux_sc_cntl = 0x00000000;
-#endif
-
- R128WaitForIdle(pScrn);
-}
-
-#ifdef XF86DRI
-
-/* Setup for XAA SolidFill. */
-static void R128CCESetupForSolidFill(ScrnInfoPtr pScrn,
- int color, int rop,
- unsigned int planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 8 );
-
- OUT_RING_REG( R128_DP_GUI_MASTER_CNTL,
- (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_SOLID_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].pattern) );
-
- OUT_RING_REG( R128_DP_BRUSH_FRGD_CLR, color );
- OUT_RING_REG( R128_DP_WRITE_MASK, planemask );
- OUT_RING_REG( R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT |
- R128_DST_Y_TOP_TO_BOTTOM));
- ADVANCE_RING();
-}
-
-/* Subsequent XAA SolidFillRect.
-
- Tests: xtest CH06/fllrctngl, xterm
-*/
-static void R128CCESubsequentSolidFillRect(ScrnInfoPtr pScrn,
- int x, int y, int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 4 );
-
- OUT_RING_REG( R128_DST_Y_X, (y << 16) | x );
- OUT_RING_REG( R128_DST_WIDTH_HEIGHT, (w << 16) | h );
-
- ADVANCE_RING();
-}
-
-/* Setup for XAA screen-to-screen copy.
-
- Tests: xtest CH06/fllrctngl (also tests transparency).
-*/
-static void R128CCESetupForScreenToScreenCopy(ScrnInfoPtr pScrn,
- int xdir, int ydir, int rop,
- unsigned int planemask,
- int trans_color)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- info->xdir = xdir;
- info->ydir = ydir;
-
- BEGIN_RING( 6 );
-
- OUT_RING_REG( R128_DP_GUI_MASTER_CNTL,
- (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_NONE
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].rop
- | R128_DP_SRC_SOURCE_MEMORY) );
-
- OUT_RING_REG( R128_DP_WRITE_MASK, planemask );
- OUT_RING_REG( R128_DP_CNTL,
- ((xdir >= 0 ? R128_DST_X_LEFT_TO_RIGHT : 0) |
- (ydir >= 0 ? R128_DST_Y_TOP_TO_BOTTOM : 0)) );
-
- ADVANCE_RING();
-
- if ((trans_color != -1) || (info->XAAForceTransBlit == TRUE)) {
- BEGIN_RING( 6 );
-
- OUT_RING_REG( R128_CLR_CMP_CLR_SRC, trans_color );
- OUT_RING_REG( R128_CLR_CMP_MASK, R128_CLR_CMP_MSK );
- OUT_RING_REG( R128_CLR_CMP_CNTL, (R128_SRC_CMP_NEQ_COLOR |
- R128_CLR_CMP_SRC_SOURCE) );
-
- ADVANCE_RING();
- }
-}
-
-/* Subsequent XAA screen-to-screen copy. */
-static void R128CCESubsequentScreenToScreenCopy(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb,
- int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- if (info->xdir < 0) xa += w - 1, xb += w - 1;
- if (info->ydir < 0) ya += h - 1, yb += h - 1;
-
- BEGIN_RING( 6 );
-
- OUT_RING_REG( R128_SRC_Y_X, (ya << 16) | xa );
- OUT_RING_REG( R128_DST_Y_X, (yb << 16) | xb );
- OUT_RING_REG( R128_DST_HEIGHT_WIDTH, (h << 16) | w );
-
- ADVANCE_RING();
-}
-
-
-/*
- * XAA scanline color expansion
- *
- * We use HOSTDATA_BLT CCE packets, dividing the image in chunks that fit into
- * the indirect buffer if necessary.
- */
-static void R128CCESetupForScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrn,
- int fg, int bg,
- int rop,
- unsigned int
- planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 2 );
- OUT_RING_REG(R128_DP_WRITE_MASK, planemask);
- ADVANCE_RING();
-
- info->scanline_rop = rop;
- info->scanline_fg = fg;
- info->scanline_bg = bg;
-}
-
-/* Helper function to write out a HOSTDATA_BLT packet into the indirect buffer
- and set the XAA scratch buffer address appropriately */
-static void R128CCEScanlineCPUToScreenColorExpandFillPacket(ScrnInfoPtr pScrn,
- int bufno)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int chunk_words = info->scanline_hpass * info->scanline_words;
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( chunk_words+9 );
-
- OUT_RING( CCE_PACKET3( R128_CCE_PACKET3_CNTL_HOSTDATA_BLT, chunk_words+9-2 ) );
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- OUT_RING( (info->dp_gui_master_cntl
- | R128_GMC_DST_CLIPPING
- | R128_GMC_BRUSH_NONE
- | (info->scanline_bg == -1
- ? R128_GMC_SRC_DATATYPE_MONO_FG_LA
- : R128_GMC_SRC_DATATYPE_MONO_FG_BG)
- | R128_ROP[info->scanline_rop].rop
- | R128_GMC_BYTE_LSB_TO_MSB
- | R128_DP_SRC_SOURCE_HOST_DATA));
-#else /* X_BYTE_ORDER == X_BIG_ENDIAN */
- OUT_RING( (info->dp_gui_master_cntl
- | R128_GMC_DST_CLIPPING
- | R128_GMC_BRUSH_NONE
- | (info->scanline_bg == -1
- ? R128_GMC_SRC_DATATYPE_MONO_FG_LA
- : R128_GMC_SRC_DATATYPE_MONO_FG_BG)
- | R128_ROP[info->scanline_rop].rop
- | R128_DP_SRC_SOURCE_HOST_DATA));
-#endif
- OUT_RING( (info->scanline_y << 16) | (info->scanline_x1clip & 0xffff) );
- OUT_RING( ((info->scanline_y+info->scanline_hpass-1) << 16) | ((info->scanline_x2clip-1) & 0xffff) );
- OUT_RING( info->scanline_fg );
- OUT_RING( info->scanline_bg );
- OUT_RING( (info->scanline_y << 16) | (info->scanline_x & 0xffff));
-
- /* Have to pad the width here and use clipping engine */
- OUT_RING( (info->scanline_hpass << 16) | ((info->scanline_w + 31) & ~31));
-
- OUT_RING( chunk_words );
-
- info->scratch_buffer[bufno] = (unsigned char *) &__head[__count];
- __count += chunk_words;
-
- ADVANCE_RING();
-
- info->scanline_y += info->scanline_hpass;
- info->scanline_h -= info->scanline_hpass;
-
- if ( R128_VERBOSE )
- xf86DrvMsg( pScrn->scrnIndex, X_INFO,
- "%s: hpass=%d, words=%d => chunk_words=%d, y=%d, h=%d\n",
- __FUNCTION__, info->scanline_hpass, info->scanline_words,
- chunk_words, info->scanline_y, info->scanline_h );
-}
-
-/* Subsequent XAA indirect CPU-to-screen color expansion. This is only
- called once for each rectangle. */
-static void R128CCESubsequentScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrn,
- int x, int y,
- int w, int h,
- int skipleft)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
-#define BUFSIZE ( R128_BUFFER_SIZE/4-9 )
-
- info->scanline_x = x;
- info->scanline_y = y;
- info->scanline_w = w;
- info->scanline_h = h;
-
- info->scanline_x1clip = x+skipleft;
- info->scanline_x2clip = x+w;
-
- info->scanline_words = (w + 31) >> 5;
- info->scanline_hpass = min(h,(BUFSIZE/info->scanline_words));
-
- if ( R128_VERBOSE )
- xf86DrvMsg( pScrn->scrnIndex, X_INFO,
- "%s: x=%d, y=%d, w=%d, h=%d, skipleft=%d => x1clip=%d, x2clip=%d, hpass=%d, words=%d\n",
- __FUNCTION__, x, y, w, h, skipleft, info->scanline_x1clip, info->scanline_x2clip,
- info->scanline_hpass, info->scanline_words );
-
- R128CCEScanlineCPUToScreenColorExpandFillPacket(pScrn, 0);
-}
-
-/* Subsequent XAA indirect CPU-to-screen color expansion. This is called
- once for each scanline. */
-static void R128CCESubsequentColorExpandScanline(ScrnInfoPtr pScrn,
- int bufno)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if ( R128_VERBOSE )
- xf86DrvMsg( pScrn->scrnIndex, X_INFO,
- "%s enter: scanline_hpass=%d, scanline_h=%d\n",
- __FUNCTION__, info->scanline_hpass, info->scanline_h );
-
- if (--info->scanline_hpass) {
- info->scratch_buffer[bufno] += 4 * info->scanline_words;
- }
- else if(info->scanline_h) {
- info->scanline_hpass = min(info->scanline_h,(BUFSIZE/info->scanline_words));
- R128CCEScanlineCPUToScreenColorExpandFillPacket(pScrn, bufno);
- }
-
- if ( R128_VERBOSE )
- xf86DrvMsg( pScrn->scrnIndex, X_INFO,
- "%s exit: scanline_hpass=%d, scanline_h=%d\n",
- __FUNCTION__, info->scanline_hpass, info->scanline_h );
-}
-
-/* Solid lines */
-static void R128CCESetupForSolidLine(ScrnInfoPtr pScrn,
- int color, int rop, unsigned int planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 6 );
-
- OUT_RING_REG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | R128_GMC_BRUSH_SOLID_COLOR
- | R128_GMC_SRC_DATATYPE_COLOR
- | R128_ROP[rop].pattern));
- OUT_RING_REG(R128_DP_BRUSH_FRGD_CLR, color);
- OUT_RING_REG(R128_DP_WRITE_MASK, planemask);
-
- ADVANCE_RING();
-}
-
-static void R128CCESubsequentSolidBresenhamLine(ScrnInfoPtr pScrn,
- int x, int y,
- int major, int minor,
- int err, int len, int octant)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int flags = 0;
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- if (octant & YMAJOR) flags |= R128_DST_Y_MAJOR;
- if (!(octant & XDECREASING)) flags |= R128_DST_X_DIR_LEFT_TO_RIGHT;
- if (!(octant & YDECREASING)) flags |= R128_DST_Y_DIR_TOP_TO_BOTTOM;
-
- BEGIN_RING( 12 );
-
- OUT_RING_REG(R128_DP_CNTL_XDIR_YDIR_YMAJOR, flags);
- OUT_RING_REG(R128_DST_Y_X, (y << 16) | x);
- OUT_RING_REG(R128_DST_BRES_ERR, err);
- OUT_RING_REG(R128_DST_BRES_INC, minor);
- OUT_RING_REG(R128_DST_BRES_DEC, -major);
- OUT_RING_REG(R128_DST_BRES_LNTH, len);
-
- ADVANCE_RING();
-}
-
-static void R128CCESubsequentSolidHorVertLine(ScrnInfoPtr pScrn,
- int x, int y, int len, int dir )
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 2 );
-
- OUT_RING_REG(R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT
- | R128_DST_Y_TOP_TO_BOTTOM));
-
- ADVANCE_RING();
-
- if (dir == DEGREES_0) {
- R128CCESubsequentSolidFillRect(pScrn, x, y, len, 1);
- } else {
- R128CCESubsequentSolidFillRect(pScrn, x, y, 1, len);
- }
-}
-
-/* Dashed lines */
-static void R128CCESetupForDashedLine(ScrnInfoPtr pScrn,
- int fg, int bg,
- int rop, unsigned int planemask,
- int length, unsigned char *pattern)
-{
- R128InfoPtr info = R128PTR(pScrn);
- CARD32 pat = *(CARD32 *)(pointer)pattern;
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
-# define PAT_SHIFT(pat,n) pat << n
-#else
-# define PAT_SHIFT(pat,n) pat >> n
-#endif
-
- switch (length) {
- case 2: pat |= PAT_SHIFT(pat,2); /* fall through */
- case 4: pat |= PAT_SHIFT(pat,4); /* fall through */
- case 8: pat |= PAT_SHIFT(pat,8); /* fall through */
- case 16: pat |= PAT_SHIFT(pat,16);
- }
-
- BEGIN_RING( 10 );
-
- OUT_RING_REG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | (bg == -1
- ? R128_GMC_BRUSH_32x1_MONO_FG_LA
- : R128_GMC_BRUSH_32x1_MONO_FG_BG)
- | R128_ROP[rop].pattern
- | R128_GMC_BYTE_LSB_TO_MSB));
- OUT_RING_REG(R128_DP_WRITE_MASK, planemask);
- OUT_RING_REG(R128_DP_BRUSH_FRGD_CLR, fg);
- OUT_RING_REG(R128_DP_BRUSH_BKGD_CLR, bg);
- OUT_RING_REG(R128_BRUSH_DATA0, pat);
-
- ADVANCE_RING();
-}
-
-static void R128CCESubsequentDashedBresenhamLine(ScrnInfoPtr pScrn,
- int x, int y,
- int major, int minor,
- int err, int len, int octant,
- int phase)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int flags = 0;
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- if (octant & YMAJOR) flags |= R128_DST_Y_MAJOR;
- if (!(octant & XDECREASING)) flags |= R128_DST_X_DIR_LEFT_TO_RIGHT;
- if (!(octant & YDECREASING)) flags |= R128_DST_Y_DIR_TOP_TO_BOTTOM;
-
- BEGIN_RING( 14 );
-
- OUT_RING_REG(R128_DP_CNTL_XDIR_YDIR_YMAJOR, flags);
- OUT_RING_REG(R128_DST_Y_X, (y << 16) | x);
- OUT_RING_REG(R128_BRUSH_Y_X, (phase << 16) | phase);
- OUT_RING_REG(R128_DST_BRES_ERR, err);
- OUT_RING_REG(R128_DST_BRES_INC, minor);
- OUT_RING_REG(R128_DST_BRES_DEC, -major);
- OUT_RING_REG(R128_DST_BRES_LNTH, len);
-
- ADVANCE_RING();
-}
-
-/* Mono 8x8 pattern color expansion */
-static void R128CCESetupForMono8x8PatternFill(ScrnInfoPtr pScrn,
- int patternx, int patterny,
- int fg, int bg, int rop,
- unsigned int planemask)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 12 );
-
- OUT_RING_REG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | (bg == -1
- ? R128_GMC_BRUSH_8X8_MONO_FG_LA
- : R128_GMC_BRUSH_8X8_MONO_FG_BG)
- | R128_ROP[rop].pattern
- | R128_GMC_BYTE_LSB_TO_MSB));
- OUT_RING_REG(R128_DP_WRITE_MASK, planemask);
- OUT_RING_REG(R128_DP_BRUSH_FRGD_CLR, fg);
- OUT_RING_REG(R128_DP_BRUSH_BKGD_CLR, bg);
- OUT_RING_REG(R128_BRUSH_DATA0, patternx);
- OUT_RING_REG(R128_BRUSH_DATA1, patterny);
-
- ADVANCE_RING();
-}
-
-static void R128CCESubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn,
- int patternx, int patterny,
- int x, int y, int w, int h)
-{
- R128InfoPtr info = R128PTR(pScrn);
- RING_LOCALS;
-
- R128CCE_REFRESH( pScrn, info );
-
- BEGIN_RING( 6 );
-
- OUT_RING_REG(R128_BRUSH_Y_X, (patterny << 8) | patternx);
- OUT_RING_REG(R128_DST_Y_X, (y << 16) | x);
- OUT_RING_REG(R128_DST_HEIGHT_WIDTH, (h << 16) | w);
-
- ADVANCE_RING();
-}
-
-/* Get an indirect buffer for the CCE 2D acceleration commands.
- */
-drmBufPtr R128CCEGetBuffer( ScrnInfoPtr pScrn )
-{
- R128InfoPtr info = R128PTR(pScrn);
- drmDMAReq dma;
- drmBufPtr buf = NULL;
- int indx = 0;
- int size = 0;
- int ret, i = 0;
-
-#if 0
- /* FIXME: pScrn->pScreen has not been initialized when this is first
- called from RADEONSelectBuffer via RADEONDRICPInit. We could use
- the screen index from pScrn, which is initialized, and then get
- the screen from screenInfo.screens[index], but that is a hack. */
- dma.context = DRIGetContext(pScrn->pScreen);
-#else
- dma.context = 0x00000001; /* This is the X server's context */
-#endif
- dma.send_count = 0;
- dma.send_list = NULL;
- dma.send_sizes = NULL;
- dma.flags = 0;
- dma.request_count = 1;
- dma.request_size = R128_BUFFER_SIZE;
- dma.request_list = &indx;
- dma.request_sizes = &size;
- dma.granted_count = 0;
-
- while ( 1 ) {
- do {
- ret = drmDMA( info->drmFD, &dma );
- if ( ret && ret != -EAGAIN ) {
- xf86DrvMsg( pScrn->scrnIndex, X_ERROR,
- "%s: CCE GetBuffer %d\n", __FUNCTION__, ret );
- }
- } while ( ( ret == -EAGAIN ) && ( i++ < R128_TIMEOUT ) );
-
- if ( ret == 0 ) {
- buf = &info->buffers->list[indx];
- buf->used = 0;
- if ( R128_VERBOSE ) {
- xf86DrvMsg( pScrn->scrnIndex, X_INFO,
- " GetBuffer returning %d\n", buf->idx );
- }
- return buf;
- }
-
- xf86DrvMsg( pScrn->scrnIndex, X_ERROR,
- "GetBuffer timed out, resetting engine...\n");
- R128EngineReset( pScrn );
- /* R128EngineRestore( pScrn ); FIXME ??? */
-
- /* Always restart the engine when doing CCE 2D acceleration */
- R128CCE_RESET( pScrn, info );
- R128CCE_START( pScrn, info );
- }
-}
-
-/* Flush the indirect buffer to the kernel for submission to the card.
- */
-void R128CCEFlushIndirect( ScrnInfoPtr pScrn, int discard )
-{
- R128InfoPtr info = R128PTR(pScrn);
- drmBufPtr buffer = info->indirectBuffer;
- int start = info->indirectStart;
- drmR128Indirect indirect;
-
- if ( !buffer )
- return;
-
- if ( (start == buffer->used) && !discard )
- return;
-
- indirect.idx = buffer->idx;
- indirect.start = start;
- indirect.end = buffer->used;
- indirect.discard = discard;
-
- drmCommandWriteRead( info->drmFD, DRM_R128_INDIRECT,
- &indirect, sizeof(drmR128Indirect));
-
- if ( discard )
- buffer = info->indirectBuffer = R128CCEGetBuffer( pScrn );
-
- /* pad to an even number of dwords */
- if (buffer->used & 7)
- buffer->used = ( buffer->used+7 ) & ~7;
-
- info->indirectStart = buffer->used;
-}
-
-/* Flush and release the indirect buffer.
- */
-void R128CCEReleaseIndirect( ScrnInfoPtr pScrn )
-{
- R128InfoPtr info = R128PTR(pScrn);
- drmBufPtr buffer = info->indirectBuffer;
- int start = info->indirectStart;
- drmR128Indirect indirect;
-
- info->indirectBuffer = NULL;
- info->indirectStart = 0;
-
- if ( !buffer )
- return;
-
- indirect.idx = buffer->idx;
- indirect.start = start;
- indirect.end = buffer->used;
- indirect.discard = 1;
-
- drmCommandWriteRead( info->drmFD, DRM_R128_INDIRECT,
- &indirect, sizeof(drmR128Indirect));
-}
-
-/* This callback is required for multihead cards using XAA */
-static
-void R128RestoreCCEAccelState(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-/* unsigned char *R128MMIO = info->MMIO; needed for OUTREG below */
- /*xf86DrvMsg(pScrn->scrnIndex, X_INFO, "===>RestoreCP\n");*/
-
- R128WaitForFifo(pScrn, 1);
-/* is this needed on r128
- OUTREG( R128_DEFAULT_OFFSET, info->frontPitchOffset);
-*/
- R128WaitForIdle(pScrn);
-
- /* FIXME: May need to restore other things,
- like BKGD_CLK FG_CLK...*/
-
-}
-
-static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- a->Flags = (PIXMAP_CACHE
- | OFFSCREEN_PIXMAPS
- | LINEAR_FRAMEBUFFER);
-
- /* Sync */
- a->Sync = R128CCEWaitForIdle;
-
- /* Solid Filled Rectangle */
- a->PolyFillRectSolidFlags = 0;
- a->SetupForSolidFill = R128CCESetupForSolidFill;
- a->SubsequentSolidFillRect = R128CCESubsequentSolidFillRect;
-
- /* Screen-to-screen Copy */
- /* Transparency uses the wrong colors for
- 24 bpp mode -- the transparent part is
- correct, but the opaque color is wrong.
- This can be seen with netscape's I-bar
- cursor when editing in the URL location
- box. */
- a->ScreenToScreenCopyFlags = ((pScrn->bitsPerPixel == 24)
- ? NO_TRANSPARENCY
- : 0);
- a->SetupForScreenToScreenCopy = R128CCESetupForScreenToScreenCopy;
- a->SubsequentScreenToScreenCopy = R128CCESubsequentScreenToScreenCopy;
-
- /* Indirect CPU-To-Screen Color Expand */
- a->ScanlineCPUToScreenColorExpandFillFlags = LEFT_EDGE_CLIPPING
- | LEFT_EDGE_CLIPPING_NEGATIVE_X;
- a->NumScanlineColorExpandBuffers = 1;
- a->ScanlineColorExpandBuffers = info->scratch_buffer;
- info->scratch_buffer[0] = NULL;
- a->SetupForScanlineCPUToScreenColorExpandFill
- = R128CCESetupForScanlineCPUToScreenColorExpandFill;
- a->SubsequentScanlineCPUToScreenColorExpandFill
- = R128CCESubsequentScanlineCPUToScreenColorExpandFill;
- a->SubsequentColorExpandScanline = R128CCESubsequentColorExpandScanline;
-
- /* Bresenham Solid Lines */
- a->SetupForSolidLine = R128CCESetupForSolidLine;
- a->SubsequentSolidBresenhamLine = R128CCESubsequentSolidBresenhamLine;
- a->SubsequentSolidHorVertLine = R128CCESubsequentSolidHorVertLine;
-
- /* Bresenham Dashed Lines*/
- a->SetupForDashedLine = R128CCESetupForDashedLine;
- a->SubsequentDashedBresenhamLine = R128CCESubsequentDashedBresenhamLine;
- a->DashPatternMaxLength = 32;
- a->DashedLineFlags = (LINE_PATTERN_LSBFIRST_LSBJUSTIFIED
- | LINE_PATTERN_POWER_OF_2_ONLY);
-
- /* Mono 8x8 Pattern Fill (Color Expand) */
- a->SetupForMono8x8PatternFill = R128CCESetupForMono8x8PatternFill;
- a->SubsequentMono8x8PatternFillRect = R128CCESubsequentMono8x8PatternFillRect;
- a->Mono8x8PatternFillFlags = (HARDWARE_PATTERN_PROGRAMMED_BITS
- | HARDWARE_PATTERN_PROGRAMMED_ORIGIN
- | HARDWARE_PATTERN_SCREEN_ORIGIN
- | BIT_ORDER_IN_BYTE_LSBFIRST);
-
- if(!info->IsSecondary && xf86IsEntityShared(pScrn->entityList[0]))
- a->RestoreAccelState = R128RestoreCCEAccelState;
-
-}
-#endif
-
-/* This callback is required for multihead cards using XAA */
-static
-void R128RestoreAccelState(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- R128WaitForFifo(pScrn, 2);
- OUTREG(R128_DEFAULT_OFFSET, pScrn->fbOffset);
- OUTREG(R128_DEFAULT_PITCH, info->pitch);
-
- /* FIXME: May need to restore other things,
- like BKGD_CLK FG_CLK...*/
-
- R128WaitForIdle(pScrn);
-
-}
-
-static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- a->Flags = (PIXMAP_CACHE
- | OFFSCREEN_PIXMAPS
- | LINEAR_FRAMEBUFFER);
-
- /* Sync */
- a->Sync = R128WaitForIdle;
-
- /* Solid Filled Rectangle */
- a->PolyFillRectSolidFlags = 0;
- a->SetupForSolidFill = R128SetupForSolidFill;
- a->SubsequentSolidFillRect = R128SubsequentSolidFillRect;
-
- /* Screen-to-screen Copy */
- /* Transparency uses the wrong colors for
- 24 bpp mode -- the transparent part is
- correct, but the opaque color is wrong.
- This can be seen with netscape's I-bar
- cursor when editing in the URL location
- box. */
- a->ScreenToScreenCopyFlags = ((pScrn->bitsPerPixel == 24)
- ? NO_TRANSPARENCY
- : 0);
- a->SetupForScreenToScreenCopy = R128SetupForScreenToScreenCopy;
- a->SubsequentScreenToScreenCopy = R128SubsequentScreenToScreenCopy;
-
- /* Mono 8x8 Pattern Fill (Color Expand) */
- a->SetupForMono8x8PatternFill = R128SetupForMono8x8PatternFill;
- a->SubsequentMono8x8PatternFillRect = R128SubsequentMono8x8PatternFillRect;
- a->Mono8x8PatternFillFlags = (HARDWARE_PATTERN_PROGRAMMED_BITS
- | HARDWARE_PATTERN_PROGRAMMED_ORIGIN
- | HARDWARE_PATTERN_SCREEN_ORIGIN
- | BIT_ORDER_IN_BYTE_LSBFIRST);
-
- /* Indirect CPU-To-Screen Color Expand */
- a->ScanlineCPUToScreenColorExpandFillFlags = LEFT_EDGE_CLIPPING
- | LEFT_EDGE_CLIPPING_NEGATIVE_X;
- a->NumScanlineColorExpandBuffers = 1;
- a->ScanlineColorExpandBuffers = info->scratch_buffer;
- info->scratch_save = xalloc(((pScrn->virtualX+31)/32*4)
- + (pScrn->virtualX
- * info->CurrentLayout.pixel_bytes));
- info->scratch_buffer[0] = info->scratch_save;
- a->SetupForScanlineCPUToScreenColorExpandFill
- = R128SetupForScanlineCPUToScreenColorExpandFill;
- a->SubsequentScanlineCPUToScreenColorExpandFill
- = R128SubsequentScanlineCPUToScreenColorExpandFill;
- a->SubsequentColorExpandScanline = R128SubsequentColorExpandScanline;
-
- /* Bresenham Solid Lines */
- a->SetupForSolidLine = R128SetupForSolidLine;
- a->SubsequentSolidBresenhamLine = R128SubsequentSolidBresenhamLine;
- a->SubsequentSolidHorVertLine = R128SubsequentSolidHorVertLine;
-
- /* Bresenham Dashed Lines*/
- a->SetupForDashedLine = R128SetupForDashedLine;
- a->SubsequentDashedBresenhamLine = R128SubsequentDashedBresenhamLine;
- a->DashPatternMaxLength = 32;
- a->DashedLineFlags = (LINE_PATTERN_LSBFIRST_LSBJUSTIFIED
- | LINE_PATTERN_POWER_OF_2_ONLY);
-
- /* ImageWrite */
- a->NumScanlineImageWriteBuffers = 1;
- a->ScanlineImageWriteBuffers = info->scratch_buffer;
- info->scratch_buffer[0] = info->scratch_save;
- a->SetupForScanlineImageWrite = R128SetupForScanlineImageWrite;
- a->SubsequentScanlineImageWriteRect= R128SubsequentScanlineImageWriteRect;
- a->SubsequentImageWriteScanline = R128SubsequentImageWriteScanline;
- a->ScanlineImageWriteFlags = CPU_TRANSFER_PAD_DWORD
- /* Performance tests show that we shouldn't use GXcopy for
- * uploads as a memcpy is faster */
- | NO_GXCOPY
- | LEFT_EDGE_CLIPPING
- | LEFT_EDGE_CLIPPING_NEGATIVE_X
- | SCANLINE_PAD_DWORD;
-
- if(xf86IsEntityShared(pScrn->entityList[0]))
- {
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
-
- /*if there are more than one devices sharing this entity, we
- have to assign this call back, otherwise the XAA will be
- disabled */
- if(pR128Ent->HasSecondary || pR128Ent->BypassSecondary)
- a->RestoreAccelState = R128RestoreAccelState;
- }
-
-}
-
-/* Initialize XAA for supported acceleration and also initialize the
- graphics hardware for acceleration. */
-Bool R128AccelInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- XAAInfoRecPtr a;
-
- if (!(a = info->accel = XAACreateInfoRec())) return FALSE;
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled)
- R128CCEAccelInit(pScrn, a);
- else
-#endif
- R128MMIOAccelInit(pScrn, a);
-
- R128EngineInit(pScrn);
- return XAAInit(pScreen, a);
-}
diff --git a/src/r128_common.h b/src/r128_common.h
deleted file mode 100644
index b60efe9..0000000
--- a/src/r128_common.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* r128_common.h -- common header definitions for R128 2D/3D/DRM suite
- * Created: Sun Apr 9 18:16:28 2000 by kevin at precisioninsight.com
- *
- * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Author:
- * Gareth Hughes <gareth at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- *
- * Converted to common header format:
- * Jens Owen <jens at tungstengraphics.com>
- *
- */
-
-#ifndef _R128_COMMON_H_
-#define _R128_COMMON_H_
-
-#include <X11/Xmd.h>
-
-/*
- * WARNING: If you change any of these defines, make sure to change
- * the kernel include file as well (r128_drm.h)
- */
-
-/* Driver specific DRM command indices
- * NOTE: these are not OS specific, but they are driver specific
- */
-#define DRM_R128_INIT 0x00
-#define DRM_R128_CCE_START 0x01
-#define DRM_R128_CCE_STOP 0x02
-#define DRM_R128_CCE_RESET 0x03
-#define DRM_R128_CCE_IDLE 0x04
-#define DRM_R128_UNDEFINED1 0x05
-#define DRM_R128_RESET 0x06
-#define DRM_R128_SWAP 0x07
-#define DRM_R128_CLEAR 0x08
-#define DRM_R128_VERTEX 0x09
-#define DRM_R128_INDICES 0x0a
-#define DRM_R128_BLIT 0x0b
-#define DRM_R128_DEPTH 0x0c
-#define DRM_R128_STIPPLE 0x0d
-#define DRM_R128_UNDEFINED2 0x0e
-#define DRM_R128_INDIRECT 0x0f
-#define DRM_R128_FULLSCREEN 0x10
-#define DRM_R128_CLEAR2 0x11
-#define DRM_R128_GETPARAM 0x12
-#define DRM_R128_FLIP 0x13
-
-#define DRM_R128_FRONT_BUFFER 0x1
-#define DRM_R128_BACK_BUFFER 0x2
-#define DRM_R128_DEPTH_BUFFER 0x4
-
-typedef struct {
- enum {
- DRM_R128_INIT_CCE = 0x01,
- DRM_R128_CLEANUP_CCE = 0x02
- } func;
- unsigned long sarea_priv_offset;
- int is_pci;
- int cce_mode;
- int cce_secure; /* FIXME: Deprecated, we should remove this */
- int ring_size;
- int usec_timeout;
-
- unsigned int fb_bpp;
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_bpp;
- unsigned int depth_offset, depth_pitch;
- unsigned int span_offset;
-
- unsigned long fb_offset;
- unsigned long mmio_offset;
- unsigned long ring_offset;
- unsigned long ring_rptr_offset;
- unsigned long buffers_offset;
- unsigned long agp_textures_offset;
-} drmR128Init;
-
-typedef struct {
- int flush;
- int idle;
-} drmR128CCEStop;
-
-typedef struct {
- int idx;
- int start;
- int end;
- int discard;
-} drmR128Indirect;
-
-typedef struct {
- int idx;
- int pitch;
- int offset;
- int format;
- unsigned short x, y;
- unsigned short width, height;
-} drmR128Blit;
-
-typedef struct {
- enum {
- DRM_R128_WRITE_SPAN = 0x01,
- DRM_R128_WRITE_PIXELS = 0x02,
- DRM_R128_READ_SPAN = 0x03,
- DRM_R128_READ_PIXELS = 0x04
- } func;
- int n;
- int *x;
- int *y;
- unsigned int *buffer;
- unsigned char *mask;
-} drmR128Depth;
-
-typedef struct {
- int prim;
- int idx; /* Index of vertex buffer */
- int count; /* Number of vertices in buffer */
- int discard; /* Client finished with buffer? */
-} drmR128Vertex;
-
-typedef struct {
- unsigned int *mask;
-} drmR128Stipple;
-
-typedef struct {
- unsigned int flags;
- unsigned int clear_color;
- unsigned int clear_depth;
- unsigned int color_mask;
- unsigned int depth_mask;
-} drmR128Clear;
-
-typedef struct {
- enum {
- DRM_R128_INIT_FULLSCREEN = 0x01,
- DRM_R128_CLEANUP_FULLSCREEN = 0x02
- } func;
-} drmR128Fullscreen;
-
-typedef struct drm_r128_getparam {
- int param;
- int *value;
-} drmR128GetParam;
-
-#define R128_PARAM_IRQ_NR 1
-
-#endif
diff --git a/src/r128_cursor.c b/src/r128_cursor.c
deleted file mode 100644
index 8321284..0000000
--- a/src/r128_cursor.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- *
- * References:
- *
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
- /* Driver data structures */
-#include "r128.h"
-#include "r128_reg.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-#define P_SWAP32( a , b ) \
- ((char *)a)[0] = ((char *)b)[3]; \
- ((char *)a)[1] = ((char *)b)[2]; \
- ((char *)a)[2] = ((char *)b)[1]; \
- ((char *)a)[3] = ((char *)b)[0]
-
-#define P_SWAP16( a , b ) \
- ((char *)a)[0] = ((char *)b)[1]; \
- ((char *)a)[1] = ((char *)b)[0]; \
- ((char *)a)[2] = ((char *)b)[3]; \
- ((char *)a)[3] = ((char *)b)[2]
-#endif
-
-
-/* Set cursor foreground and background colors. */
-static void R128SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if(info->IsSecondary)
- {
- OUTREG(R128_CUR2_CLR0, bg);
- OUTREG(R128_CUR2_CLR1, fg);
- }
- else
- {
- OUTREG(R128_CUR_CLR0, bg);
- OUTREG(R128_CUR_CLR1, fg);
- }
-}
-
-/* Set cursor position to (x,y) with offset into cursor bitmap at
- (xorigin,yorigin). */
-static void R128SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- xf86CursorInfoPtr cursor = info->cursor;
- int xorigin = 0;
- int yorigin = 0;
- int total_y = pScrn->frameY1 - pScrn->frameY0;
-
- if (x < 0) xorigin = -x;
- if (y < 0) yorigin = -y;
- if (y > total_y) y = total_y;
- if (info->Flags & V_DBLSCAN) y *= 2;
- if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1;
- if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1;
-
- if(!info->IsSecondary)
- {
- OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xorigin << 16) | yorigin);
- OUTREG(R128_CUR_HORZ_VERT_POSN, (R128_CUR_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- OUTREG(R128_CUR_OFFSET, info->cursor_start + yorigin * 16);
- }
- else
- {
- OUTREG(R128_CUR2_HORZ_VERT_OFF, (R128_CUR2_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(R128_CUR2_HORZ_VERT_POSN, (R128_CUR2_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- OUTREG(R128_CUR2_OFFSET,
- info->cursor_start + pScrn->fbOffset + yorigin * 16);
- }
-}
-
-/* Copy cursor image from `image' to video memory. R128SetCursorPosition
- will be called after this, so we can ignore xorigin and yorigin. */
-static void R128LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *image)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- CARD32 *s = (pointer)image;
- CARD32 *d = (pointer)((CARD8*)info->FB + info->cursor_start);
- int y;
- CARD32 save;
-
- if(!info->IsSecondary)
- {
- save = INREG(R128_CRTC_GEN_CNTL);
- OUTREG(R128_CRTC_GEN_CNTL, save & (CARD32)~R128_CRTC_CUR_EN);
- }
- else
- {
- save = INREG(R128_CRTC2_GEN_CNTL);
- OUTREG(R128_CRTC2_GEN_CNTL, save & (CARD32)~R128_CRTC2_CUR_EN);
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- switch(info->CurrentLayout.pixel_bytes) {
- case 4:
- case 3:
- for (y = 0; y < 64; y++) {
- P_SWAP32(d,s);
- d++; s++;
- P_SWAP32(d,s);
- d++; s++;
- P_SWAP32(d,s);
- d++; s++;
- P_SWAP32(d,s);
- d++; s++;
- }
- break;
- case 2:
- for (y = 0; y < 64; y++) {
- P_SWAP16(d,s);
- d++; s++;
- P_SWAP16(d,s);
- d++; s++;
- P_SWAP16(d,s);
- d++; s++;
- P_SWAP16(d,s);
- d++; s++;
- }
- break;
- default:
- for (y = 0; y < 64; y++) {
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- }
- }
-#else
- for (y = 0; y < 64; y++) {
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- }
-#endif
-
- /* Set the area after the cursor to be all transparent so that we
- won't display corrupted cursors on the screen */
- for (y = 0; y < 64; y++) {
- *d++ = 0xffffffff; /* The AND bits */
- *d++ = 0xffffffff;
- *d++ = 0x00000000; /* The XOR bits */
- *d++ = 0x00000000;
- }
-
-
- if(!info->IsSecondary)
- OUTREG(R128_CRTC_GEN_CNTL, save);
- else
- OUTREG(R128_CRTC2_GEN_CNTL, save);
-
-}
-
-/* Hide hardware cursor. */
-static void R128HideCursor(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if(info->IsSecondary)
- OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~R128_CRTC2_CUR_EN);
- else
- OUTREGP(R128_CRTC_GEN_CNTL, 0, ~R128_CRTC_CUR_EN);
-}
-
-/* Show hardware cursor. */
-static void R128ShowCursor(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if(info->IsSecondary)
- {
- OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_CUR_EN,
- ~R128_CRTC2_CUR_EN);
- }
- else
- {
- OUTREGP(R128_CRTC_GEN_CNTL, R128_CRTC_CUR_EN, ~R128_CRTC_CUR_EN);
- }
-}
-
-/* Determine if hardware cursor is in use. */
-static Bool R128UseHWCursor(ScreenPtr pScreen, CursorPtr pCurs)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
-
- return info->cursor_start ? TRUE : FALSE;
-}
-
-/* Initialize hardware cursor support. */
-Bool R128CursorInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- xf86CursorInfoPtr cursor;
- FBAreaPtr fbarea;
- int width;
- int height;
- int size;
-
-
- if (!(cursor = info->cursor = xf86CreateCursorInfoRec())) return FALSE;
-
- cursor->MaxWidth = 64;
- cursor->MaxHeight = 64;
- cursor->Flags = (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP
- | HARDWARE_CURSOR_SHOW_TRANSPARENT
- | HARDWARE_CURSOR_UPDATE_UNHIDDEN
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- | HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
-#endif
- | HARDWARE_CURSOR_INVERT_MASK
- | HARDWARE_CURSOR_AND_SOURCE_WITH_MASK
- | HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_64
- | HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK);
-
- cursor->SetCursorColors = R128SetCursorColors;
- cursor->SetCursorPosition = R128SetCursorPosition;
- cursor->LoadCursorImage = R128LoadCursorImage;
- cursor->HideCursor = R128HideCursor;
- cursor->ShowCursor = R128ShowCursor;
- cursor->UseHWCursor = R128UseHWCursor;
-
- size = (cursor->MaxWidth/4) * cursor->MaxHeight;
- width = pScrn->displayWidth;
- height = (size*2 + 1023) / pScrn->displayWidth;
- fbarea = xf86AllocateOffscreenArea(pScreen,
- width,
- height,
- 16,
- NULL,
- NULL,
- NULL);
-
- if (!fbarea) {
- info->cursor_start = 0;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Hardware cursor disabled"
- " due to insufficient offscreen memory\n");
- } else {
- info->cursor_start = R128_ALIGN((fbarea->box.x1
- + width * fbarea->box.y1)
- * info->CurrentLayout.pixel_bytes, 16);
- info->cursor_end = info->cursor_start + size;
- }
-
- R128TRACE(("R128CursorInit (0x%08x-0x%08x)\n",
- info->cursor_start, info->cursor_end));
-
- return xf86InitCursor(pScreen, cursor);
-}
diff --git a/src/r128_dga.c b/src/r128_dga.c
deleted file mode 100644
index 7dd03aa..0000000
--- a/src/r128_dga.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * Authors:
- * Ove KÃ¥ven <ovek at transgaming.com>,
- * borrowing some code from the Chips and MGA drivers.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
- /* Driver data structures */
-#include "r128.h"
-#include "r128_probe.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-
- /* DGA support */
-#include "dgaproc.h"
-
-#ifdef XF86DRI
-#include "r128_common.h"
-#endif
-
-static Bool R128_OpenFramebuffer(ScrnInfoPtr, char **, unsigned char **,
- int *, int *, int *);
-static Bool R128_SetMode(ScrnInfoPtr, DGAModePtr);
-static int R128_GetViewport(ScrnInfoPtr);
-static void R128_SetViewport(ScrnInfoPtr, int, int, int);
-static void R128_FillRect(ScrnInfoPtr, int, int, int, int, unsigned long);
-static void R128_BlitRect(ScrnInfoPtr, int, int, int, int, int, int);
-static void R128_BlitTransRect(ScrnInfoPtr, int, int, int, int, int, int,
- unsigned long);
-
-static DGAModePtr R128SetupDGAMode(ScrnInfoPtr pScrn,
- DGAModePtr modes,
- int *num,
- int bitsPerPixel,
- int depth,
- Bool pixmap,
- int secondPitch,
- unsigned long red,
- unsigned long green,
- unsigned long blue,
- short visualClass)
-{
- R128InfoPtr info = R128PTR(pScrn);
- DGAModePtr newmodes = NULL;
- DGAModePtr currentMode;
- DisplayModePtr pMode;
- DisplayModePtr firstMode;
- unsigned int size;
- int pitch;
- int Bpp = bitsPerPixel >> 3;
-
-SECOND_PASS:
-
- pMode = firstMode = pScrn->modes;
-
- while (1) {
- pitch = pScrn->displayWidth;
- size = pitch * Bpp * pMode->VDisplay;
-
- if ((!secondPitch || (pitch != secondPitch)) &&
- (size <= info->FbMapSize)) {
-
- if (secondPitch)
- pitch = secondPitch;
-
- if (!(newmodes = xrealloc(modes, (*num + 1) * sizeof(DGAModeRec))))
- break;
-
- modes = newmodes;
- currentMode = modes + *num;
-
- currentMode->mode = pMode;
- currentMode->flags = DGA_CONCURRENT_ACCESS;
-
- if (pixmap)
- currentMode->flags |= DGA_PIXMAP_AVAILABLE;
-
- if (info->accel) {
- if (info->accel->SetupForSolidFill &&
- info->accel->SubsequentSolidFillRect)
- currentMode->flags |= DGA_FILL_RECT;
- if (info->accel->SetupForScreenToScreenCopy &&
- info->accel->SubsequentScreenToScreenCopy)
- currentMode->flags |= DGA_BLIT_RECT | DGA_BLIT_RECT_TRANS;
- if (currentMode->flags &
- (DGA_PIXMAP_AVAILABLE | DGA_FILL_RECT |
- DGA_BLIT_RECT | DGA_BLIT_RECT_TRANS))
- currentMode->flags &= ~DGA_CONCURRENT_ACCESS;
- }
- if (pMode->Flags & V_DBLSCAN)
- currentMode->flags |= DGA_DOUBLESCAN;
- if (pMode->Flags & V_INTERLACE)
- currentMode->flags |= DGA_INTERLACED;
-
- currentMode->byteOrder = pScrn->imageByteOrder;
- currentMode->depth = depth;
- currentMode->bitsPerPixel = bitsPerPixel;
- currentMode->red_mask = red;
- currentMode->green_mask = green;
- currentMode->blue_mask = blue;
- currentMode->visualClass = visualClass;
- currentMode->viewportWidth = pMode->HDisplay;
- currentMode->viewportHeight = pMode->VDisplay;
- currentMode->xViewportStep = 8;
- currentMode->yViewportStep = 1;
- currentMode->viewportFlags = DGA_FLIP_RETRACE;
- currentMode->offset = 0;
- currentMode->address = (unsigned char*)info->LinearAddr;
- currentMode->bytesPerScanline = pitch * Bpp;
- currentMode->imageWidth = pitch;
- currentMode->imageHeight = (info->FbMapSize
- / currentMode->bytesPerScanline);
- currentMode->pixmapWidth = currentMode->imageWidth;
- currentMode->pixmapHeight = currentMode->imageHeight;
- currentMode->maxViewportX = (currentMode->imageWidth
- - currentMode->viewportWidth);
- /* this might need to get clamped to some maximum */
- currentMode->maxViewportY = (currentMode->imageHeight
- - currentMode->viewportHeight);
- (*num)++;
- }
-
- pMode = pMode->next;
- if (pMode == firstMode)
- break;
- }
-
- if (secondPitch) {
- secondPitch = 0;
- goto SECOND_PASS;
- }
-
- return modes;
-}
-
-Bool
-R128DGAInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- DGAModePtr modes = NULL;
- int num = 0;
-
- /* 8 */
- modes = R128SetupDGAMode (pScrn, modes, &num, 8, 8,
- (pScrn->bitsPerPixel == 8),
- (pScrn->bitsPerPixel != 8) ? 0 : pScrn->displayWidth,
- 0, 0, 0, PseudoColor);
-
- /* 15 */
- modes = R128SetupDGAMode (pScrn, modes, &num, 16, 15,
- (pScrn->bitsPerPixel == 16),
- (pScrn->depth != 15) ? 0 : pScrn->displayWidth,
- 0x7c00, 0x03e0, 0x001f, TrueColor);
-
- modes = R128SetupDGAMode (pScrn, modes, &num, 16, 15,
- (pScrn->bitsPerPixel == 16),
- (pScrn->depth != 15) ? 0 : pScrn->displayWidth,
- 0x7c00, 0x03e0, 0x001f, DirectColor);
-
- /* 16 */
- modes = R128SetupDGAMode (pScrn, modes, &num, 16, 16,
- (pScrn->bitsPerPixel == 16),
- (pScrn->depth != 16) ? 0 : pScrn->displayWidth,
- 0xf800, 0x07e0, 0x001f, TrueColor);
-
- modes = R128SetupDGAMode (pScrn, modes, &num, 16, 16,
- (pScrn->bitsPerPixel == 16),
- (pScrn->depth != 16) ? 0 : pScrn->displayWidth,
- 0xf800, 0x07e0, 0x001f, DirectColor);
-
- /* 24 */
- modes = R128SetupDGAMode (pScrn, modes, &num, 24, 24,
- (pScrn->bitsPerPixel == 24),
- (pScrn->bitsPerPixel != 24) ? 0 : pScrn->displayWidth,
- 0xff0000, 0x00ff00, 0x0000ff, TrueColor);
-
- modes = R128SetupDGAMode (pScrn, modes, &num, 24, 24,
- (pScrn->bitsPerPixel == 24),
- (pScrn->bitsPerPixel != 24) ? 0 : pScrn->displayWidth,
- 0xff0000, 0x00ff00, 0x0000ff, DirectColor);
-
- /* 32 */
- modes = R128SetupDGAMode (pScrn, modes, &num, 32, 24,
- (pScrn->bitsPerPixel == 32),
- (pScrn->bitsPerPixel != 32) ? 0 : pScrn->displayWidth,
- 0xff0000, 0x00ff00, 0x0000ff, TrueColor);
-
- modes = R128SetupDGAMode (pScrn, modes, &num, 32, 24,
- (pScrn->bitsPerPixel == 32),
- (pScrn->bitsPerPixel != 32) ? 0 : pScrn->displayWidth,
- 0xff0000, 0x00ff00, 0x0000ff, DirectColor);
-
- info->numDGAModes = num;
- info->DGAModes = modes;
-
- info->DGAFuncs.OpenFramebuffer = R128_OpenFramebuffer;
- info->DGAFuncs.CloseFramebuffer = NULL;
- info->DGAFuncs.SetMode = R128_SetMode;
- info->DGAFuncs.SetViewport = R128_SetViewport;
- info->DGAFuncs.GetViewport = R128_GetViewport;
-
- info->DGAFuncs.Sync = NULL;
- info->DGAFuncs.FillRect = NULL;
- info->DGAFuncs.BlitRect = NULL;
- info->DGAFuncs.BlitTransRect = NULL;
-
- if (info->accel) {
- info->DGAFuncs.Sync = info->accel->Sync;
- if (info->accel->SetupForSolidFill &&
- info->accel->SubsequentSolidFillRect)
- info->DGAFuncs.FillRect = R128_FillRect;
- if (info->accel->SetupForScreenToScreenCopy &&
- info->accel->SubsequentScreenToScreenCopy) {
- info->DGAFuncs.BlitRect = R128_BlitRect;
- info->DGAFuncs.BlitTransRect = R128_BlitTransRect;
- }
- }
-
- return DGAInit(pScreen, &(info->DGAFuncs), modes, num);
-}
-
-
-static Bool
-R128_SetMode(
- ScrnInfoPtr pScrn,
- DGAModePtr pMode
-){
- static R128FBLayout SavedLayouts[MAXSCREENS];
- int indx = pScrn->pScreen->myNum;
- R128InfoPtr info = R128PTR(pScrn);
-
- if(!pMode) { /* restore the original mode */
- /* put the ScreenParameters back */
- if(info->DGAactive)
- memcpy(&info->CurrentLayout, &SavedLayouts[indx], sizeof(R128FBLayout));
-
- pScrn->currentMode = info->CurrentLayout.mode;
-
- pScrn->SwitchMode(indx, pScrn->currentMode, 0);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- R128CCE_STOP(pScrn, info);
- }
-#endif
- if (info->accelOn)
- R128EngineInit(pScrn);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- R128CCE_START(pScrn, info);
- }
-#endif
- pScrn->AdjustFrame(indx, 0, 0, 0);
- info->DGAactive = FALSE;
- } else {
- if(!info->DGAactive) { /* save the old parameters */
- memcpy(&SavedLayouts[indx], &info->CurrentLayout, sizeof(R128FBLayout));
- info->DGAactive = TRUE;
- }
-
- info->CurrentLayout.bitsPerPixel = pMode->bitsPerPixel;
- info->CurrentLayout.depth = pMode->depth;
- info->CurrentLayout.displayWidth = pMode->bytesPerScanline /
- (pMode->bitsPerPixel >> 3);
- info->CurrentLayout.pixel_bytes = pMode->bitsPerPixel / 8;
- info->CurrentLayout.pixel_code = (pMode->bitsPerPixel != 16
- ? pMode->bitsPerPixel
- : pMode->depth);
- /* R128ModeInit() will set the mode field */
-
- pScrn->SwitchMode(indx, pMode->mode, 0);
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- R128CCE_STOP(pScrn, info);
- }
-#endif
- if (info->accelOn)
- R128EngineInit(pScrn);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- R128CCE_START(pScrn, info);
- }
-#endif
- }
-
- return TRUE;
-}
-
-
-
-static int
-R128_GetViewport(
- ScrnInfoPtr pScrn
-){
- R128InfoPtr info = R128PTR(pScrn);
-
- return info->DGAViewportStatus;
-}
-
-
-static void
-R128_SetViewport(
- ScrnInfoPtr pScrn,
- int x, int y,
- int flags
-){
- R128InfoPtr info = R128PTR(pScrn);
-
- pScrn->AdjustFrame(pScrn->pScreen->myNum, x, y, flags);
- info->DGAViewportStatus = 0; /* FIXME */
-}
-
-
-static void
-R128_FillRect (
- ScrnInfoPtr pScrn,
- int x, int y, int w, int h,
- unsigned long color
-){
- R128InfoPtr info = R128PTR(pScrn);
-
- (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (CARD32)(~0));
- (*info->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h);
-
- if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
- SET_SYNC_FLAG(info->accel);
-}
-
-static void
-R128_BlitRect(
- ScrnInfoPtr pScrn,
- int srcx, int srcy,
- int w, int h,
- int dstx, int dsty
-){
- R128InfoPtr info = R128PTR(pScrn);
- int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1;
- int ydir = (srcy < dsty) ? -1 : 1;
-
- (*info->accel->SetupForScreenToScreenCopy)(
- pScrn, xdir, ydir, GXcopy, (CARD32)(~0), -1);
- (*info->accel->SubsequentScreenToScreenCopy)(
- pScrn, srcx, srcy, dstx, dsty, w, h);
-
- if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
- SET_SYNC_FLAG(info->accel);
-}
-
-
-static void
-R128_BlitTransRect(
- ScrnInfoPtr pScrn,
- int srcx, int srcy,
- int w, int h,
- int dstx, int dsty,
- unsigned long color
-){
- R128InfoPtr info = R128PTR(pScrn);
- int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1;
- int ydir = (srcy < dsty) ? -1 : 1;
-
- info->XAAForceTransBlit = TRUE;
-
- (*info->accel->SetupForScreenToScreenCopy)(
- pScrn, xdir, ydir, GXcopy, (CARD32)(~0), color);
-
- info->XAAForceTransBlit = FALSE;
-
- (*info->accel->SubsequentScreenToScreenCopy)(
- pScrn, srcx, srcy, dstx, dsty, w, h);
-
- if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
- SET_SYNC_FLAG(info->accel);
-}
-
-
-static Bool
-R128_OpenFramebuffer(
- ScrnInfoPtr pScrn,
- char **name,
- unsigned char **mem,
- int *size,
- int *offset,
- int *flags
-){
- R128InfoPtr info = R128PTR(pScrn);
-
- *name = NULL; /* no special device */
- *mem = (unsigned char*)info->LinearAddr;
- *size = info->FbMapSize;
- *offset = 0;
- *flags = /* DGA_NEED_ROOT */ 0; /* don't need root, just /dev/mem access */
-
- return TRUE;
-}
diff --git a/src/r128_dri.c b/src/r128_dri.c
deleted file mode 100644
index 2927718..0000000
--- a/src/r128_dri.c
+++ /dev/null
@@ -1,1499 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include <stdio.h>
-
-/*
- * Authors:
- * Kevin E. Martin <martin at valinux.com>
- * Rickard E. Faith <faith at valinux.com>
- * Daryll Strauss <daryll at valinux.com>
- * Gareth Hughes <gareth at valinux.com>
- *
- */
-
- /* Driver data structures */
-#include "r128.h"
-#include "r128_dri.h"
-#include "r128_common.h"
-#include "r128_reg.h"
-#include "r128_sarea.h"
-#include "r128_version.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-#include "xf86PciInfo.h"
-#include "windowstr.h"
-
-#include "shadowfb.h"
- /* GLX/DRI/DRM definitions */
-#define _XF86DRI_SERVER_
-#include "GL/glxtokens.h"
-#include "sarea.h"
-
-static size_t r128_drm_page_size;
-
-static void R128DRITransitionTo2d(ScreenPtr pScreen);
-static void R128DRITransitionTo3d(ScreenPtr pScreen);
-static void R128DRITransitionMultiToSingle3d(ScreenPtr pScreen);
-static void R128DRITransitionSingleToMulti3d(ScreenPtr pScreen);
-
-static void R128DRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
-
-/* Initialize the visual configs that are supported by the hardware.
- These are combined with the visual configs that the indirect
- rendering core supports, and the intersection is exported to the
- client. */
-static Bool R128InitVisualConfigs(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- int numConfigs = 0;
- __GLXvisualConfig *pConfigs = NULL;
- R128ConfigPrivPtr pR128Configs = NULL;
- R128ConfigPrivPtr *pR128ConfigPtrs = NULL;
- int i, accum, stencil, db;
-
- switch (info->CurrentLayout.pixel_code) {
- case 8: /* 8bpp mode is not support */
- case 15: /* FIXME */
- case 24: /* FIXME */
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] R128DRIScreenInit failed (depth %d not supported). "
- "Disabling DRI.\n", info->CurrentLayout.pixel_code);
- return FALSE;
-
-#define R128_USE_ACCUM 1
-#define R128_USE_STENCIL 1
-#define R128_USE_DB 1
-
- case 16:
- numConfigs = 1;
- if (R128_USE_ACCUM) numConfigs *= 2;
- if (R128_USE_STENCIL) numConfigs *= 2;
- if (R128_USE_DB) numConfigs *= 2;
-
- if (!(pConfigs
- = (__GLXvisualConfig*)xcalloc(sizeof(__GLXvisualConfig),
- numConfigs))) {
- return FALSE;
- }
- if (!(pR128Configs
- = (R128ConfigPrivPtr)xcalloc(sizeof(R128ConfigPrivRec),
- numConfigs))) {
- xfree(pConfigs);
- return FALSE;
- }
- if (!(pR128ConfigPtrs
- = (R128ConfigPrivPtr*)xcalloc(sizeof(R128ConfigPrivPtr),
- numConfigs))) {
- xfree(pConfigs);
- xfree(pR128Configs);
- return FALSE;
- }
-
- i = 0;
- for (db = 0; db <= R128_USE_DB; db++) {
- for (accum = 0; accum <= R128_USE_ACCUM; accum++) {
- for (stencil = 0; stencil <= R128_USE_STENCIL; stencil++) {
- pR128ConfigPtrs[i] = &pR128Configs[i];
-
- pConfigs[i].vid = (VisualID)(-1);
- pConfigs[i].class = -1;
- pConfigs[i].rgba = TRUE;
- pConfigs[i].redSize = 5;
- pConfigs[i].greenSize = 6;
- pConfigs[i].blueSize = 5;
- pConfigs[i].alphaSize = 0;
- pConfigs[i].redMask = 0x0000F800;
- pConfigs[i].greenMask = 0x000007E0;
- pConfigs[i].blueMask = 0x0000001F;
- pConfigs[i].alphaMask = 0x00000000;
- if (accum) { /* Simulated in software */
- pConfigs[i].accumRedSize = 16;
- pConfigs[i].accumGreenSize = 16;
- pConfigs[i].accumBlueSize = 16;
- pConfigs[i].accumAlphaSize = 0;
- } else {
- pConfigs[i].accumRedSize = 0;
- pConfigs[i].accumGreenSize = 0;
- pConfigs[i].accumBlueSize = 0;
- pConfigs[i].accumAlphaSize = 0;
- }
- if (db)
- pConfigs[i].doubleBuffer = TRUE;
- else
- pConfigs[i].doubleBuffer = FALSE;
- pConfigs[i].stereo = FALSE;
- pConfigs[i].bufferSize = 16;
- pConfigs[i].depthSize = 16;
- if (stencil)
- pConfigs[i].stencilSize = 8; /* Simulated in software */
- else
- pConfigs[i].stencilSize = 0;
- pConfigs[i].auxBuffers = 0;
- pConfigs[i].level = 0;
- if (accum || stencil) {
- pConfigs[i].visualRating = GLX_SLOW_CONFIG;
- } else {
- pConfigs[i].visualRating = GLX_NONE;
- }
- pConfigs[i].transparentPixel = GLX_NONE;
- pConfigs[i].transparentRed = 0;
- pConfigs[i].transparentGreen = 0;
- pConfigs[i].transparentBlue = 0;
- pConfigs[i].transparentAlpha = 0;
- pConfigs[i].transparentIndex = 0;
- i++;
- }
- }
- }
- break;
-
- case 32:
- numConfigs = 1;
- if (R128_USE_ACCUM) numConfigs *= 2;
- if (R128_USE_STENCIL) numConfigs *= 2;
- if (R128_USE_DB) numConfigs *= 2;
-
- if (!(pConfigs
- = (__GLXvisualConfig*)xcalloc(sizeof(__GLXvisualConfig),
- numConfigs))) {
- return FALSE;
- }
- if (!(pR128Configs
- = (R128ConfigPrivPtr)xcalloc(sizeof(R128ConfigPrivRec),
- numConfigs))) {
- xfree(pConfigs);
- return FALSE;
- }
- if (!(pR128ConfigPtrs
- = (R128ConfigPrivPtr*)xcalloc(sizeof(R128ConfigPrivPtr),
- numConfigs))) {
- xfree(pConfigs);
- xfree(pR128Configs);
- return FALSE;
- }
-
- i = 0;
- for (db = 0; db <= R128_USE_DB; db++) {
- for (accum = 0; accum <= R128_USE_ACCUM; accum++) {
- for (stencil = 0; stencil <= R128_USE_STENCIL; stencil++) {
- pR128ConfigPtrs[i] = &pR128Configs[i];
-
- pConfigs[i].vid = (VisualID)(-1);
- pConfigs[i].class = -1;
- pConfigs[i].rgba = TRUE;
- pConfigs[i].redSize = 8;
- pConfigs[i].greenSize = 8;
- pConfigs[i].blueSize = 8;
- pConfigs[i].alphaSize = 0;
- pConfigs[i].redMask = 0x00FF0000;
- pConfigs[i].greenMask = 0x0000FF00;
- pConfigs[i].blueMask = 0x000000FF;
- pConfigs[i].alphaMask = 0x00000000;
- if (accum) { /* Simulated in software */
- pConfigs[i].accumRedSize = 16;
- pConfigs[i].accumGreenSize = 16;
- pConfigs[i].accumBlueSize = 16;
- pConfigs[i].accumAlphaSize = 0;
- } else {
- pConfigs[i].accumRedSize = 0;
- pConfigs[i].accumGreenSize = 0;
- pConfigs[i].accumBlueSize = 0;
- pConfigs[i].accumAlphaSize = 0;
- }
- if (db)
- pConfigs[i].doubleBuffer = TRUE;
- else
- pConfigs[i].doubleBuffer = FALSE;
- pConfigs[i].stereo = FALSE;
- pConfigs[i].bufferSize = 24;
- if (stencil) {
- pConfigs[i].depthSize = 24;
- pConfigs[i].stencilSize = 8;
- } else {
- pConfigs[i].depthSize = 24;
- pConfigs[i].stencilSize = 0;
- }
- pConfigs[i].auxBuffers = 0;
- pConfigs[i].level = 0;
- if (accum) {
- pConfigs[i].visualRating = GLX_SLOW_CONFIG;
- } else {
- pConfigs[i].visualRating = GLX_NONE;
- }
- pConfigs[i].transparentPixel = GLX_NONE;
- pConfigs[i].transparentRed = 0;
- pConfigs[i].transparentGreen = 0;
- pConfigs[i].transparentBlue = 0;
- pConfigs[i].transparentAlpha = 0;
- pConfigs[i].transparentIndex = 0;
- i++;
- }
- }
- }
- break;
- }
-
- info->numVisualConfigs = numConfigs;
- info->pVisualConfigs = pConfigs;
- info->pVisualConfigsPriv = pR128Configs;
- GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pR128ConfigPtrs);
- return TRUE;
-}
-
-/* Create the Rage 128-specific context information */
-static Bool R128CreateContext(ScreenPtr pScreen, VisualPtr visual,
- drm_context_t hwContext, void *pVisualConfigPriv,
- DRIContextType contextStore)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
-
- info->drmCtx = hwContext;
- return TRUE;
-}
-
-/* Destroy the Rage 128-specific context information */
-static void R128DestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
- DRIContextType contextStore)
-{
- /* Nothing yet */
-}
-
-/* Called when the X server is woken up to allow the last client's
- context to be saved and the X server's context to be loaded. This is
- not necessary for the Rage 128 since the client detects when it's
- context is not currently loaded and then load's it itself. Since the
- registers to start and stop the CCE are privileged, only the X server
- can start/stop the engine. */
-static void R128EnterServer(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
-
- if (info->accel) info->accel->NeedToSync = TRUE;
-}
-
-/* Called when the X server goes to sleep to allow the X server's
- context to be saved and the last client's context to be loaded. This
- is not necessary for the Rage 128 since the client detects when it's
- context is not currently loaded and then load's it itself. Since the
- registers to start and stop the CCE are privileged, only the X server
- can start/stop the engine. */
-static void R128LeaveServer(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if (!info->directRenderingEnabled) {
- /* Save all hardware scissors */
- info->sc_left = INREG(R128_SC_LEFT);
- info->sc_right = INREG(R128_SC_RIGHT);
- info->sc_top = INREG(R128_SC_TOP);
- info->sc_bottom = INREG(R128_SC_BOTTOM);
- info->aux_sc_cntl = INREG(R128_SC_BOTTOM);
- } else if (info->CCEInUse) {
- R128CCEReleaseIndirect(pScrn);
-
- info->CCEInUse = FALSE;
- }
-}
-
-/* Contexts can be swapped by the X server if necessary. This callback
- is currently only used to perform any functions necessary when
- entering or leaving the X server, and in the future might not be
- necessary. */
-static void R128DRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
- DRIContextType oldContextType, void *oldContext,
- DRIContextType newContextType, void *newContext)
-{
- if ((syncType==DRI_3D_SYNC) && (oldContextType==DRI_2D_CONTEXT) &&
- (newContextType==DRI_2D_CONTEXT)) { /* Entering from Wakeup */
- R128EnterServer(pScreen);
- }
- if ((syncType==DRI_2D_SYNC) && (oldContextType==DRI_NO_CONTEXT) &&
- (newContextType==DRI_2D_CONTEXT)) { /* Exiting from Block Handler */
- R128LeaveServer(pScreen);
- }
-}
-
-/* Initialize the state of the back and depth buffers. */
-static void R128DRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx)
-{
- /* FIXME: This routine needs to have acceleration turned on */
- ScreenPtr pScreen = pWin->drawable.pScreen;
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- BoxPtr pbox, pboxSave;
- int nbox, nboxSave;
- int depth;
-
- /* FIXME: Use accel when CCE 2D code is written
- * EA: What is this code kept for? Radeon doesn't have it and
- * has a comment: "There's no need for the 2d driver to be clearing
- * buffers for the 3d client. It knows how to do that on its own."
- */
- if (info->directRenderingEnabled)
- return;
-
- /* FIXME: This should be based on the __GLXvisualConfig info */
- switch (pScrn->bitsPerPixel) {
- case 8: depth = 0x000000ff; break;
- case 16: depth = 0x0000ffff; break;
- case 24: depth = 0x00ffffff; break;
- case 32: depth = 0xffffffff; break;
- default: depth = 0x00000000; break;
- }
-
- /* FIXME: Copy XAAPaintWindow() and use REGION_TRANSLATE() */
- /* FIXME: Only initialize the back and depth buffers for contexts
- that request them */
-
- pboxSave = pbox = REGION_RECTS(prgn);
- nboxSave = nbox = REGION_NUM_RECTS(prgn);
-
- (*info->accel->SetupForSolidFill)(pScrn, 0, GXcopy, (CARD32)(-1));
- for (; nbox; nbox--, pbox++) {
- (*info->accel->SubsequentSolidFillRect)(pScrn,
- pbox->x1 + info->fbX,
- pbox->y1 + info->fbY,
- pbox->x2 - pbox->x1,
- pbox->y2 - pbox->y1);
- (*info->accel->SubsequentSolidFillRect)(pScrn,
- pbox->x1 + info->backX,
- pbox->y1 + info->backY,
- pbox->x2 - pbox->x1,
- pbox->y2 - pbox->y1);
- }
-
- pbox = pboxSave;
- nbox = nboxSave;
-
- /* FIXME: this needs to consider depth tiling. */
- (*info->accel->SetupForSolidFill)(pScrn, depth, GXcopy, (CARD32)(-1));
- for (; nbox; nbox--, pbox++)
- (*info->accel->SubsequentSolidFillRect)(pScrn,
- pbox->x1 + info->depthX,
- pbox->y1 + info->depthY,
- pbox->x2 - pbox->x1,
- pbox->y2 - pbox->y1);
-
- info->accel->NeedToSync = TRUE;
-}
-
-/* Copy the back and depth buffers when the X server moves a window. */
-static void R128DRIMoveBuffers(WindowPtr pWin, DDXPointRec ptOldOrg,
- RegionPtr prgnSrc, CARD32 indx)
-{
- ScreenPtr pScreen = pWin->drawable.pScreen;
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
-
- /* FIXME: This routine needs to have acceleration turned on */
- /* FIXME: Copy XAACopyWindow() and use REGION_TRANSLATE() */
- /* FIXME: Only initialize the back and depth buffers for contexts
- that request them */
-
- /* FIXME: Use accel when CCE 2D code is written */
- if (info->directRenderingEnabled)
- return;
-}
-
-/* Initialize the AGP state. Request memory for use in AGP space, and
- initialize the Rage 128 registers to point to that memory. */
-static Bool R128DRIAgpInit(R128InfoPtr info, ScreenPtr pScreen)
-{
- unsigned char *R128MMIO = info->MMIO;
- unsigned long mode;
- unsigned int vendor, device;
- int ret;
- unsigned long cntl, chunk;
- int s, l;
- int flags;
- unsigned long agpBase;
-
- if (drmAgpAcquire(info->drmFD) < 0) {
- xf86DrvMsg(pScreen->myNum, X_WARNING, "[agp] AGP not available\n");
- return FALSE;
- }
-
- /* Modify the mode if the default mode is
- not appropriate for this particular
- combination of graphics card and AGP
- chipset. */
-
- mode = drmAgpGetMode(info->drmFD); /* Default mode */
- vendor = drmAgpVendorId(info->drmFD);
- device = drmAgpDeviceId(info->drmFD);
-
- mode &= ~R128_AGP_MODE_MASK;
- switch (info->agpMode) {
- case 4: mode |= R128_AGP_4X_MODE;
- case 2: mode |= R128_AGP_2X_MODE;
- case 1: default: mode |= R128_AGP_1X_MODE;
- }
-
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
- mode, vendor, device,
- PCI_DEV_VENDOR_ID(info->PciInfo),
- PCI_DEV_DEVICE_ID(info->PciInfo));
-
- if (drmAgpEnable(info->drmFD, mode) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
- drmAgpRelease(info->drmFD);
- return FALSE;
- }
-
- info->agpOffset = 0;
-
- if ((ret = drmAgpAlloc(info->drmFD, info->agpSize*1024*1024, 0, NULL,
- &info->agpMemHandle)) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Out of memory (%d)\n", ret);
- drmAgpRelease(info->drmFD);
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] %d kB allocated with handle 0x%08x\n",
- info->agpSize*1024, info->agpMemHandle);
-
- if (drmAgpBind(info->drmFD, info->agpMemHandle, info->agpOffset) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not bind\n");
- drmAgpFree(info->drmFD, info->agpMemHandle);
- drmAgpRelease(info->drmFD);
- return FALSE;
- }
-
- /* Initialize the CCE ring buffer data */
- info->ringStart = info->agpOffset;
- info->ringMapSize = info->ringSize*1024*1024 + r128_drm_page_size;
- info->ringSizeLog2QW = R128MinBits(info->ringSize*1024*1024/8) - 1;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = r128_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- /* Reserve the rest for AGP textures */
- info->agpTexStart = info->bufStart + info->bufMapSize;
- s = (info->agpSize*1024*1024 - info->agpTexStart);
- l = R128MinBits((s-1) / R128_NR_TEX_REGIONS);
- if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY;
- info->agpTexMapSize = (s >> l) << l;
- info->log2AGPTexGran = l;
-
- if (info->CCESecure) flags = DRM_READ_ONLY;
- else flags = 0;
-
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_AGP, flags, &info->ringHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add ring mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring handle = 0x%08x\n", info->ringHandle);
-
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
-
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_AGP, flags, &info->ringReadPtrHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add ring read ptr mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
-
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not map ring read ptr\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
-
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_AGP, 0, &info->bufHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add vertex/indirect buffers mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
-
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not map vertex/indirect buffers\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
-
- if (drmAddMap(info->drmFD, info->agpTexStart, info->agpTexMapSize,
- DRM_AGP, 0, &info->agpTexHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add AGP texture map mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] AGP texture map handle = 0x%08x\n",
- info->agpTexHandle);
-
- if (drmMap(info->drmFD, info->agpTexHandle, info->agpTexMapSize,
- &info->agpTex) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not map AGP texture map\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] AGP Texture map mapped at 0x%08lx\n",
- (unsigned long)info->agpTex);
-
- /* Initialize Rage 128's AGP registers */
- cntl = INREG(R128_AGP_CNTL);
- cntl &= ~R128_AGP_APER_SIZE_MASK;
- switch (info->agpSize) {
- case 256: cntl |= R128_AGP_APER_SIZE_256MB; break;
- case 128: cntl |= R128_AGP_APER_SIZE_128MB; break;
- case 64: cntl |= R128_AGP_APER_SIZE_64MB; break;
- case 32: cntl |= R128_AGP_APER_SIZE_32MB; break;
- case 16: cntl |= R128_AGP_APER_SIZE_16MB; break;
- case 8: cntl |= R128_AGP_APER_SIZE_8MB; break;
- case 4: cntl |= R128_AGP_APER_SIZE_4MB; break;
- default:
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Illegal aperture size %d kB\n",
- info->agpSize*1024);
- return FALSE;
- }
- agpBase = drmAgpBase(info->drmFD);
- OUTREG(R128_AGP_BASE, agpBase);
- OUTREG(R128_AGP_CNTL, cntl);
-
- /* Disable Rage 128's PCIGART registers */
- chunk = INREG(R128_BM_CHUNK_0_VAL);
- chunk &= ~(R128_BM_PTR_FORCE_TO_PCI |
- R128_BM_PM4_RD_FORCE_TO_PCI |
- R128_BM_GLOBAL_FORCE_TO_PCI);
- OUTREG(R128_BM_CHUNK_0_VAL, chunk);
-
- OUTREG(R128_PCI_GART_PAGE, 1); /* Ensure AGP GART is used (for now) */
-
- return TRUE;
-}
-
-static Bool R128DRIPciInit(R128InfoPtr info, ScreenPtr pScreen)
-{
- unsigned char *R128MMIO = info->MMIO;
- CARD32 chunk;
- int ret;
- int flags;
-
- info->agpOffset = 0;
-
- ret = drmScatterGatherAlloc(info->drmFD, info->agpSize*1024*1024,
- &info->pciMemHandle);
- if (ret < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Out of memory (%d)\n", ret);
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] %d kB allocated with handle 0x%08x\n",
- info->agpSize*1024, info->pciMemHandle);
-
- /* Initialize the CCE ring buffer data */
- info->ringStart = info->agpOffset;
- info->ringMapSize = info->ringSize*1024*1024 + r128_drm_page_size;
- info->ringSizeLog2QW = R128MinBits(info->ringSize*1024*1024/8) - 1;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = r128_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
-
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add ring mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring handle = 0x%08x\n", info->ringHandle);
-
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ring);
-
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add ring read ptr mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
-
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not map ring read ptr\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring read ptr contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ringReadPtr);
-
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add vertex/indirect buffers mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
-
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not map vertex/indirect buffers\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Vertex/indirect buffers contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->buf);
-
- switch (info->Chipset) {
- case PCI_CHIP_RAGE128LE:
- case PCI_CHIP_RAGE128RE:
- case PCI_CHIP_RAGE128RK:
- case PCI_CHIP_RAGE128PD:
- case PCI_CHIP_RAGE128PP:
- case PCI_CHIP_RAGE128PR:
- /* This is a PCI card, do nothing */
- break;
-
- case PCI_CHIP_RAGE128LF:
- case PCI_CHIP_RAGE128MF:
- case PCI_CHIP_RAGE128ML:
- case PCI_CHIP_RAGE128RF:
- case PCI_CHIP_RAGE128RG:
- case PCI_CHIP_RAGE128RL:
- case PCI_CHIP_RAGE128SM:
- case PCI_CHIP_RAGE128PF:
- case PCI_CHIP_RAGE128TF:
- case PCI_CHIP_RAGE128TL:
- case PCI_CHIP_RAGE128TR:
- /* FIXME: ATI documentation does not specify if the following chips are
- * AGP or PCI, it just mentions their PCI IDs. I'm assuming they're AGP
- * until I get more correct information. <mharris at redhat.com>
- */
- case PCI_CHIP_RAGE128PA:
- case PCI_CHIP_RAGE128PB:
- case PCI_CHIP_RAGE128PC:
- case PCI_CHIP_RAGE128PE:
- case PCI_CHIP_RAGE128PG:
- case PCI_CHIP_RAGE128PH:
- case PCI_CHIP_RAGE128PI:
- case PCI_CHIP_RAGE128PJ:
- case PCI_CHIP_RAGE128PK:
- case PCI_CHIP_RAGE128PL:
- case PCI_CHIP_RAGE128PM:
- case PCI_CHIP_RAGE128PN:
- case PCI_CHIP_RAGE128PO:
- case PCI_CHIP_RAGE128PQ:
- case PCI_CHIP_RAGE128PS:
- case PCI_CHIP_RAGE128PT:
- case PCI_CHIP_RAGE128PU:
- case PCI_CHIP_RAGE128PV:
- case PCI_CHIP_RAGE128PW:
- case PCI_CHIP_RAGE128PX:
- case PCI_CHIP_RAGE128SE:
- case PCI_CHIP_RAGE128SF:
- case PCI_CHIP_RAGE128SG:
- case PCI_CHIP_RAGE128SH:
- case PCI_CHIP_RAGE128SK:
- case PCI_CHIP_RAGE128SL:
- case PCI_CHIP_RAGE128SN:
- case PCI_CHIP_RAGE128TS:
- case PCI_CHIP_RAGE128TT:
- case PCI_CHIP_RAGE128TU:
- default:
- /* This is really an AGP card, force PCI GART mode */
- chunk = INREG(R128_BM_CHUNK_0_VAL);
- chunk |= (R128_BM_PTR_FORCE_TO_PCI |
- R128_BM_PM4_RD_FORCE_TO_PCI |
- R128_BM_GLOBAL_FORCE_TO_PCI);
- OUTREG(R128_BM_CHUNK_0_VAL, chunk);
- OUTREG(R128_PCI_GART_PAGE, 0); /* Ensure PCI GART is used */
- break;
- }
-
- return TRUE;
-}
-
-/* Add a map for the MMIO registers that will be accessed by any
- DRI-based clients. */
-static Bool R128DRIMapInit(R128InfoPtr info, ScreenPtr pScreen)
-{
- int flags;
-
- if (info->CCESecure) flags = DRM_READ_ONLY;
- else flags = 0;
-
- /* Map registers */
- info->registerSize = R128_MMIOSIZE;
- if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize,
- DRM_REGISTERS, flags, &info->registerHandle) < 0) {
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] register handle = 0x%08x\n", info->registerHandle);
-
- return TRUE;
-}
-
-/* Initialize the kernel data structures. */
-static int R128DRIKernelInit(R128InfoPtr info, ScreenPtr pScreen)
-{
- drmR128Init drmInfo;
-
- memset( &drmInfo, 0, sizeof(drmR128Init) );
-
- drmInfo.func = DRM_R128_INIT_CCE;
- drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
- drmInfo.is_pci = info->IsPCI;
- drmInfo.cce_mode = info->CCEMode;
- drmInfo.cce_secure = info->CCESecure;
- drmInfo.ring_size = info->ringSize*1024*1024;
- drmInfo.usec_timeout = info->CCEusecTimeout;
-
- drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
- drmInfo.depth_bpp = info->CurrentLayout.pixel_code;
-
- drmInfo.front_offset = info->frontOffset;
- drmInfo.front_pitch = info->frontPitch;
-
- drmInfo.back_offset = info->backOffset;
- drmInfo.back_pitch = info->backPitch;
-
- drmInfo.depth_offset = info->depthOffset;
- drmInfo.depth_pitch = info->depthPitch;
- drmInfo.span_offset = info->spanOffset;
-
- drmInfo.fb_offset = info->fbHandle;
- drmInfo.mmio_offset = info->registerHandle;
- drmInfo.ring_offset = info->ringHandle;
- drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
- drmInfo.buffers_offset = info->bufHandle;
- drmInfo.agp_textures_offset = info->agpTexHandle;
-
- if (drmCommandWrite(info->drmFD, DRM_R128_INIT,
- &drmInfo, sizeof(drmR128Init)) < 0)
- return FALSE;
-
- return TRUE;
-}
-
-/* Add a map for the vertex buffers that will be accessed by any
- DRI-based clients. */
-static Bool R128DRIBufInit(R128InfoPtr info, ScreenPtr pScreen)
-{
- /* Initialize vertex buffers */
- if (info->IsPCI) {
- info->bufNumBufs = drmAddBufs(info->drmFD,
- info->bufMapSize / R128_BUFFER_SIZE,
- R128_BUFFER_SIZE,
- DRM_SG_BUFFER,
- info->bufStart);
- } else {
- info->bufNumBufs = drmAddBufs(info->drmFD,
- info->bufMapSize / R128_BUFFER_SIZE,
- R128_BUFFER_SIZE,
- DRM_AGP_BUFFER,
- info->bufStart);
- }
- if (info->bufNumBufs <= 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[drm] Could not create vertex/indirect buffers list\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] Added %d %d byte vertex/indirect buffers\n",
- info->bufNumBufs, R128_BUFFER_SIZE);
-
- if (!(info->buffers = drmMapBufs(info->drmFD))) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[drm] Failed to map vertex/indirect buffers list\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] Mapped %d vertex/indirect buffers\n",
- info->buffers->count);
-
- return TRUE;
-}
-
-static void R128DRIIrqInit(R128InfoPtr info, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-
- if (!info->irq) {
- info->irq = drmGetInterruptFromBusID(
- info->drmFD,
- PCI_CFG_BUS(info->PciInfo),
- PCI_CFG_DEV(info->PciInfo),
- PCI_CFG_FUNC(info->PciInfo));
-
- if((drmCtlInstHandler(info->drmFD, info->irq)) != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[drm] failure adding irq handler, "
- "there is a device already using that irq\n"
- "[drm] falling back to irq-free operation\n");
- info->irq = 0;
- } else {
- unsigned char *R128MMIO = info->MMIO;
- info->gen_int_cntl = INREG( R128_GEN_INT_CNTL );
- }
- }
-
- if (info->irq)
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[drm] dma control initialized, using IRQ %d\n",
- info->irq);
-}
-
-/* Initialize the CCE state, and start the CCE (if used by the X server) */
-static void R128DRICCEInit(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- /* Turn on bus mastering */
- info->BusCntl &= ~R128_BUS_MASTER_DIS;
-
- /* CCEMode is initialized in r128_driver.c */
- switch (info->CCEMode) {
- case R128_PM4_NONPM4: info->CCEFifoSize = 0; break;
- case R128_PM4_192PIO: info->CCEFifoSize = 192; break;
- case R128_PM4_192BM: info->CCEFifoSize = 192; break;
- case R128_PM4_128PIO_64INDBM: info->CCEFifoSize = 128; break;
- case R128_PM4_128BM_64INDBM: info->CCEFifoSize = 128; break;
- case R128_PM4_64PIO_128INDBM: info->CCEFifoSize = 64; break;
- case R128_PM4_64BM_128INDBM: info->CCEFifoSize = 64; break;
- case R128_PM4_64PIO_64VCBM_64INDBM: info->CCEFifoSize = 64; break;
- case R128_PM4_64BM_64VCBM_64INDBM: info->CCEFifoSize = 64; break;
- case R128_PM4_64PIO_64VCPIO_64INDPIO: info->CCEFifoSize = 64; break;
- }
-
- if (info->directRenderingEnabled) {
- /* Make sure the CCE is on for the X server */
- R128CCE_START(pScrn, info);
- } else {
- /* Make sure the CCE is off for the X server */
- R128CCE_STOP(pScrn, info);
- }
-}
-
-/* Initialize the screen-specific data structures for the DRI and the
- Rage 128. This is the main entry point to the device-specific
- initialization code. It calls device-independent DRI functions to
- create the DRI data structures and initialize the DRI state. */
-Bool R128DRIScreenInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- DRIInfoPtr pDRIInfo;
- R128DRIPtr pR128DRI;
- int major, minor, patch;
- drmVersionPtr version;
-
- /* Check that the GLX, DRI, and DRM modules have been loaded by testing
- * for known symbols in each module. */
- if (!xf86LoaderCheckSymbol("GlxSetVisualConfigs")) return FALSE;
- if (!xf86LoaderCheckSymbol("drmAvailable")) return FALSE;
- if (!xf86LoaderCheckSymbol("DRIQueryVersion")) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] R128DRIScreenInit failed (libdri.a too old)\n");
- return FALSE;
- }
-
- /* Check the DRI version */
- DRIQueryVersion(&major, &minor, &patch);
- if (major != DRIINFO_MAJOR_VERSION || minor < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] R128DRIScreenInit failed because of a version mismatch.\n"
- "[dri] libdri version is %d.%d.%d but version %d.%d.x is needed.\n"
- "[dri] Disabling the DRI.\n",
- major, minor, patch,
- DRIINFO_MAJOR_VERSION, 0);
- return FALSE;
- }
-
- switch (info->CurrentLayout.pixel_code) {
- case 8:
- /* These modes are not supported (yet). */
- case 15:
- case 24:
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] R128DRIScreenInit failed (depth %d not supported). "
- "[dri] Disabling DRI.\n", info->CurrentLayout.pixel_code);
- return FALSE;
-
- /* Only 16 and 32 color depths are supports currently. */
- case 16:
- case 32:
- break;
- }
-
- r128_drm_page_size = getpagesize();
-
- /* Create the DRI data structure, and fill it in before calling the
- DRIScreenInit(). */
- if (!(pDRIInfo = DRICreateInfoRec())) return FALSE;
-
- info->pDRIInfo = pDRIInfo;
- pDRIInfo->drmDriverName = R128_DRIVER_NAME;
- pDRIInfo->clientDriverName = R128_DRIVER_NAME;
- if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
- pDRIInfo->busIdString = DRICreatePCIBusID(info->PciInfo);
- } else {
- pDRIInfo->busIdString = xalloc(64);
- sprintf(pDRIInfo->busIdString,
- "PCI:%d:%d:%d",
- PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
- }
- pDRIInfo->ddxDriverMajorVersion = R128_VERSION_MAJOR;
- pDRIInfo->ddxDriverMinorVersion = R128_VERSION_MINOR;
- pDRIInfo->ddxDriverPatchVersion = R128_VERSION_PATCH;
- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr;
- pDRIInfo->frameBufferSize = info->FbMapSize;
- pDRIInfo->frameBufferStride = (pScrn->displayWidth *
- info->CurrentLayout.pixel_bytes);
- pDRIInfo->ddxDrawableTableEntry = R128_MAX_DRAWABLES;
- pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES
- < R128_MAX_DRAWABLES
- ? SAREA_MAX_DRAWABLES
- : R128_MAX_DRAWABLES);
-
-#ifdef NOT_DONE
- /* FIXME: Need to extend DRI protocol to pass this size back to
- * client for SAREA mapping that includes a device private record
- */
- pDRIInfo->SAREASize =
- ((sizeof(XF86DRISAREARec) + 0xfff) & 0x1000); /* round to page */
- /* + shared memory device private rec */
-#else
- /* For now the mapping works by using a fixed size defined
- * in the SAREA header
- */
- if (sizeof(XF86DRISAREARec)+sizeof(R128SAREAPriv)>SAREA_MAX) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] Data does not fit in SAREA. Disabling DRI.\n");
- return FALSE;
- }
- pDRIInfo->SAREASize = SAREA_MAX;
-#endif
-
- if (!(pR128DRI = (R128DRIPtr)xcalloc(sizeof(R128DRIRec),1))) {
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
- return FALSE;
- }
- pDRIInfo->devPrivate = pR128DRI;
- pDRIInfo->devPrivateSize = sizeof(R128DRIRec);
- pDRIInfo->contextSize = sizeof(R128DRIContextRec);
-
- pDRIInfo->CreateContext = R128CreateContext;
- pDRIInfo->DestroyContext = R128DestroyContext;
- pDRIInfo->SwapContext = R128DRISwapContext;
- pDRIInfo->InitBuffers = R128DRIInitBuffers;
- pDRIInfo->MoveBuffers = R128DRIMoveBuffers;
- pDRIInfo->bufferRequests = DRI_ALL_WINDOWS;
- pDRIInfo->TransitionTo2d = R128DRITransitionTo2d;
- pDRIInfo->TransitionTo3d = R128DRITransitionTo3d;
- pDRIInfo->TransitionSingleToMulti3D = R128DRITransitionSingleToMulti3d;
- pDRIInfo->TransitionMultiToSingle3D = R128DRITransitionMultiToSingle3d;
-
- pDRIInfo->createDummyCtx = TRUE;
- pDRIInfo->createDummyCtxPriv = FALSE;
-
- if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] DRIScreenInit failed. Disabling DRI.\n");
- xfree(pDRIInfo->devPrivate);
- pDRIInfo->devPrivate = NULL;
- DRIDestroyInfoRec(pDRIInfo);
- pDRIInfo = NULL;
- return FALSE;
- }
-
- /* Check the DRM lib version.
- drmGetLibVersion was not supported in version 1.0, so check for
- symbol first to avoid possible crash or hang.
- */
- if (xf86LoaderCheckSymbol("drmGetLibVersion")) {
- version = drmGetLibVersion(info->drmFD);
- }
- else {
- /* drmlib version 1.0.0 didn't have the drmGetLibVersion
- entry point. Fake it by allocating a version record
- via drmGetVersion and changing it to version 1.0.0
- */
- version = drmGetVersion(info->drmFD);
- version->version_major = 1;
- version->version_minor = 0;
- version->version_patchlevel = 0;
- }
-
- if (version) {
- if (version->version_major != 1 ||
- version->version_minor < 1) {
- /* incompatible drm library version */
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] R128DRIScreenInit failed because of a version mismatch.\n"
- "[dri] libdrm.a module version is %d.%d.%d but version 1.1.x is needed.\n"
- "[dri] Disabling DRI.\n",
- version->version_major,
- version->version_minor,
- version->version_patchlevel);
- drmFreeVersion(version);
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
- drmFreeVersion(version);
- }
-
- /* Check the r128 DRM version */
- version = drmGetVersion(info->drmFD);
- if (version) {
- if (version->version_major != 2 ||
- version->version_minor < 2) {
- /* incompatible drm version */
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] R128DRIScreenInit failed because of a version mismatch.\n"
- "[dri] r128.o kernel module version is %d.%d.%d but version 2.2 or greater is needed.\n"
- "[dri] Disabling the DRI.\n",
- version->version_major,
- version->version_minor,
- version->version_patchlevel);
- drmFreeVersion(version);
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
- info->drmMinor = version->version_minor;
- drmFreeVersion(version);
- }
-
- /* Initialize AGP */
- if (!info->IsPCI && !R128DRIAgpInit(info, pScreen)) {
- info->IsPCI = TRUE;
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "[agp] AGP failed to initialize -- falling back to PCI mode.\n");
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "[agp] Make sure you have the agpgart kernel module loaded.\n");
- }
-
- /* Initialize PCIGART */
- if (info->IsPCI && !R128DRIPciInit(info, pScreen)) {
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* DRIScreenInit doesn't add all the
- common mappings. Add additional
- mappings here. */
- if (!R128DRIMapInit(info, pScreen)) {
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* DRIScreenInit adds the frame buffer
- map, but we need it as well */
- {
- void *scratch_ptr;
- int scratch_int;
-
- DRIGetDeviceInfo(pScreen, &info->fbHandle,
- &scratch_int, &scratch_int,
- &scratch_int, &scratch_int,
- &scratch_ptr);
- }
-
- /* FIXME: When are these mappings unmapped? */
-
- if (!R128InitVisualConfigs(pScreen)) {
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n");
-
- return TRUE;
-}
-
-/* Finish initializing the device-dependent DRI state, and call
- DRIFinishScreenInit() to complete the device-independent DRI
- initialization. */
-Bool R128DRIFinishScreenInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- R128SAREAPrivPtr pSAREAPriv;
- R128DRIPtr pR128DRI;
-
- info->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
- /* info->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
-
- /* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit
- because *DRIKernelInit requires that the hardware lock is held by
- the X server, and the first time the hardware lock is grabbed is
- in DRIFinishScreenInit. */
- if (!DRIFinishScreenInit(pScreen)) {
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize the kernel data structures */
- if (!R128DRIKernelInit(info, pScreen)) {
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize the vertex buffers list */
- if (!R128DRIBufInit(info, pScreen)) {
- R128DRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize IRQ */
- R128DRIIrqInit(info, pScreen);
-
- /* Initialize and start the CCE if required */
- R128DRICCEInit(pScrn);
-
- pSAREAPriv = (R128SAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
- memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
- pR128DRI = (R128DRIPtr)info->pDRIInfo->devPrivate;
-
- pR128DRI->deviceID = info->Chipset;
- pR128DRI->width = pScrn->virtualX;
- pR128DRI->height = pScrn->virtualY;
- pR128DRI->depth = pScrn->depth;
- pR128DRI->bpp = pScrn->bitsPerPixel;
-
- pR128DRI->IsPCI = info->IsPCI;
- pR128DRI->AGPMode = info->agpMode;
-
- pR128DRI->frontOffset = info->frontOffset;
- pR128DRI->frontPitch = info->frontPitch;
- pR128DRI->backOffset = info->backOffset;
- pR128DRI->backPitch = info->backPitch;
- pR128DRI->depthOffset = info->depthOffset;
- pR128DRI->depthPitch = info->depthPitch;
- pR128DRI->spanOffset = info->spanOffset;
- pR128DRI->textureOffset = info->textureOffset;
- pR128DRI->textureSize = info->textureSize;
- pR128DRI->log2TexGran = info->log2TexGran;
-
- pR128DRI->registerHandle = info->registerHandle;
- pR128DRI->registerSize = info->registerSize;
-
- pR128DRI->agpTexHandle = info->agpTexHandle;
- pR128DRI->agpTexMapSize = info->agpTexMapSize;
- pR128DRI->log2AGPTexGran = info->log2AGPTexGran;
- pR128DRI->agpTexOffset = info->agpTexStart;
- pR128DRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
-
- /* Have shadowfb run only while there is 3d active. */
- if (info->allowPageFlip && info->drmMinor >= 5 ) {
- ShadowFBInit( pScreen, R128DRIRefreshArea );
- } else if (info->allowPageFlip) {
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "[dri] Kernel module version 2.5.0 or newer is required for pageflipping.\n");
- info->allowPageFlip = 0;
- }
-
- return TRUE;
-}
-
-/* The screen is being closed, so clean up any state and free any
- resources used by the DRI. */
-void R128DRICloseScreen(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- drmR128Init drmInfo;
-
- /* Stop the CCE if it is still in use */
- if (info->directRenderingEnabled) {
- R128CCE_STOP(pScrn, info);
- }
-
- if (info->irq) {
- drmCtlUninstHandler(info->drmFD);
- info->irq = 0;
- info->gen_int_cntl = 0;
- }
-
- /* De-allocate vertex buffers */
- if (info->buffers) {
- drmUnmapBufs(info->buffers);
- info->buffers = NULL;
- }
-
- /* De-allocate all kernel resources */
- memset(&drmInfo, 0, sizeof(drmR128Init));
- drmInfo.func = DRM_R128_CLEANUP_CCE;
- drmCommandWrite(info->drmFD, DRM_R128_INIT,
- &drmInfo, sizeof(drmR128Init));
-
- /* De-allocate all AGP resources */
- if (info->agpTex) {
- drmUnmap(info->agpTex, info->agpTexMapSize);
- info->agpTex = NULL;
- }
- if (info->buf) {
- drmUnmap(info->buf, info->bufMapSize);
- info->buf = NULL;
- }
- if (info->ringReadPtr) {
- drmUnmap(info->ringReadPtr, info->ringReadMapSize);
- info->ringReadPtr = NULL;
- }
- if (info->ring) {
- drmUnmap(info->ring, info->ringMapSize);
- info->ring = NULL;
- }
- if (info->agpMemHandle != DRM_AGP_NO_HANDLE) {
- drmAgpUnbind(info->drmFD, info->agpMemHandle);
- drmAgpFree(info->drmFD, info->agpMemHandle);
- info->agpMemHandle = DRM_AGP_NO_HANDLE;
- drmAgpRelease(info->drmFD);
- }
- if (info->pciMemHandle) {
- drmScatterGatherFree(info->drmFD, info->pciMemHandle);
- info->pciMemHandle = 0;
- }
-
- /* De-allocate all DRI resources */
- DRICloseScreen(pScreen);
-
- /* De-allocate all DRI data structures */
- if (info->pDRIInfo) {
- if (info->pDRIInfo->devPrivate) {
- xfree(info->pDRIInfo->devPrivate);
- info->pDRIInfo->devPrivate = NULL;
- }
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
- }
- if (info->pVisualConfigs) {
- xfree(info->pVisualConfigs);
- info->pVisualConfigs = NULL;
- }
- if (info->pVisualConfigsPriv) {
- xfree(info->pVisualConfigsPriv);
- info->pVisualConfigsPriv = NULL;
- }
-}
-
-/* Use callbacks from dri.c to support pageflipping mode for a single
- * 3d context without need for any specific full-screen extension.
- */
-
-/* Use the shadowfb module to maintain a list of dirty rectangles.
- * These are blitted to the back buffer to keep both buffers clean
- * during page-flipping when the 3d application isn't fullscreen.
- *
- * Unlike most use of the shadowfb code, both buffers are in video memory.
- *
- * An alternative to this would be to organize for all on-screen drawing
- * operations to be duplicated for the two buffers. That might be
- * faster, but seems like a lot more work...
- */
-
-
-static void R128DRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int i;
- R128SAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
-
- /* Don't want to do this when no 3d is active and pages are
- * right-way-round
- */
- if (!pSAREAPriv->pfAllowPageFlip && pSAREAPriv->pfCurrentPage == 0)
- return;
-
- (*info->accel->SetupForScreenToScreenCopy)(pScrn,
- 1, 1, GXcopy,
- (CARD32)(-1), -1);
-
- for (i = 0 ; i < num ; i++, pbox++) {
- int xa = max(pbox->x1, 0), xb = min(pbox->x2, pScrn->virtualX-1);
- int ya = max(pbox->y1, 0), yb = min(pbox->y2, pScrn->virtualY-1);
-
- if (xa <= xb && ya <= yb) {
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya,
- xa + info->backX,
- ya + info->backY,
- xb - xa + 1,
- yb - ya + 1);
- }
- }
-}
-
-static void R128EnablePageFlip(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- R128SAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
-
- if (info->allowPageFlip) {
- /* Duplicate the frontbuffer to the backbuffer */
- (*info->accel->SetupForScreenToScreenCopy)(pScrn,
- 1, 1, GXcopy,
- (CARD32)(-1), -1);
-
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn,
- 0,
- 0,
- info->backX,
- info->backY,
- pScrn->virtualX,
- pScrn->virtualY);
-
- pSAREAPriv->pfAllowPageFlip = 1;
- }
-}
-
-static void R128DisablePageFlip(ScreenPtr pScreen)
-{
- /* Tell the clients not to pageflip. How?
- * -- Field in sarea, plus bumping the window counters.
- * -- DRM needs to cope with Front-to-Back swapbuffers.
- */
- R128SAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
-
- pSAREAPriv->pfAllowPageFlip = 0;
-}
-
-static void R128DRITransitionSingleToMulti3d(ScreenPtr pScreen)
-{
- R128DisablePageFlip(pScreen);
-}
-
-static void R128DRITransitionMultiToSingle3d(ScreenPtr pScreen)
-{
- /* Let the remaining 3d app start page flipping again */
- R128EnablePageFlip(pScreen);
-}
-
-static void R128DRITransitionTo3d(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
-
- R128EnablePageFlip(pScreen);
-
- info->have3DWindows = 1;
-
- if (info->cursor_start)
- xf86ForceHWCursor(pScreen, TRUE);
-}
-
-static void R128DRITransitionTo2d(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- R128SAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
-
- /* Try flipping back to the front page if necessary */
- if (pSAREAPriv->pfCurrentPage == 1)
- drmCommandNone(info->drmFD, DRM_R128_FLIP);
-
- /* Shut down shadowing if we've made it back to the front page */
- if (pSAREAPriv->pfCurrentPage == 0) {
- R128DisablePageFlip(pScreen);
- } else {
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "[dri] R128DRITransitionTo2d: "
- "kernel failed to unflip buffers.\n");
- }
-
- info->have3DWindows = 0;
-
- if (info->cursor_start)
- xf86ForceHWCursor(pScreen, FALSE);
-}
diff --git a/src/r128_dri.h b/src/r128_dri.h
deleted file mode 100644
index 3fae3f6..0000000
--- a/src/r128_dri.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at valinux.com>
- * Rickard E. Faith <faith at valinux.com>
- * Gareth Hughes <gareth at valinux.com>
- *
- */
-
-#ifndef _R128_DRI_
-#define _R128_DRI_
-
-#include "xf86drm.h"
-
-/* DRI Driver defaults */
-#define R128_DEFAULT_CCE_PIO_MODE R128_PM4_64PIO_64VCBM_64INDBM
-#define R128_DEFAULT_CCE_BM_MODE R128_PM4_64BM_64VCBM_64INDBM
-#define R128_DEFAULT_AGP_MODE 1
-#define R128_DEFAULT_AGP_SIZE 8 /* MB (must be a power of 2 and > 4MB) */
-#define R128_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
-#define R128_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
-#define R128_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */
-
-#define R128_DEFAULT_CCE_TIMEOUT 10000 /* usecs */
-
-#define R128_AGP_MAX_MODE 4
-
-#define R128_CARD_TYPE_R128 1
-#define R128_CARD_TYPE_R128_PRO 2
-#define R128_CARD_TYPE_R128_MOBILITY 3
-
-#define R128CCE_USE_RING_BUFFER(m) \
-(((m) == R128_PM4_192BM) || \
- ((m) == R128_PM4_128BM_64INDBM) || \
- ((m) == R128_PM4_64BM_128INDBM) || \
- ((m) == R128_PM4_64BM_64VCBM_64INDBM))
-
-typedef struct {
- /* DRI screen private data */
- int deviceID; /* PCI device ID */
- int width; /* Width in pixels of display */
- int height; /* Height in scanlines of display */
- int depth; /* Depth of display (8, 15, 16, 24) */
- int bpp; /* Bit depth of display (8, 16, 24, 32) */
-
- int IsPCI; /* Current card is a PCI card */
- int AGPMode;
-
- int frontOffset; /* Start of front buffer */
- int frontPitch;
- int backOffset; /* Start of shared back buffer */
- int backPitch;
- int depthOffset; /* Start of shared depth buffer */
- int depthPitch;
- int spanOffset; /* Start of scratch spanline */
- int textureOffset;/* Start of texture data in frame buffer */
- int textureSize;
- int log2TexGran;
-
- /* MMIO register data */
- drm_handle_t registerHandle;
- drmSize registerSize;
-
- /* CCE AGP Texture data */
- drm_handle_t agpTexHandle;
- drmSize agpTexMapSize;
- int log2AGPTexGran;
- int agpTexOffset;
- unsigned int sarea_priv_offset;
-} R128DRIRec, *R128DRIPtr;
-
-#endif
diff --git a/src/r128_dripriv.h b/src/r128_dripriv.h
deleted file mode 100644
index 269bac9..0000000
--- a/src/r128_dripriv.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- *
- */
-
-#ifndef _R128_DRIPRIV_H_
-#define _R128_DRIPRIV_H_
-
-#include "GL/glxint.h"
-
-#define R128_MAX_DRAWABLES 256
-
-extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs,
- void **configprivs);
-
-typedef struct {
- /* Nothing here yet */
- int dummy;
-} R128ConfigPrivRec, *R128ConfigPrivPtr;
-
-typedef struct {
- /* Nothing here yet */
- int dummy;
-} R128DRIContextRec, *R128DRIContextPtr;
-
-#endif
diff --git a/src/r128_driver.c b/src/r128_driver.c
deleted file mode 100644
index 0e693e0..0000000
--- a/src/r128_driver.c
+++ /dev/null
@@ -1,4463 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- * Gareth Hughes <gareth at valinux.com>
- *
- * Credits:
- *
- * Thanks to Alan Hourihane <alanh at fairlite.demon..co.uk> and SuSE for
- * providing source code to their 3.3.x Rage 128 driver. Portions of
- * this file are based on the initialization code for that driver.
- *
- * References:
- *
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- * This server does not yet support these XFree86 4.0 features:
- * DDC1 & DDC2
- * shadowfb
- * overlay planes
- *
- * Modified by Marc Aurele La France <tsi at xfree86.org> for ATI driver merge.
- *
- * Dualhead support - Alex Deucher <agd5f at yahoo.com>
- */
-
-#include <string.h>
-#include <stdio.h>
-
- /* Driver data structures */
-#include "r128.h"
-#include "r128_probe.h"
-#include "r128_reg.h"
-#include "r128_version.h"
-
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "r128_dri.h"
-#include "r128_common.h"
-#include "r128_sarea.h"
-#endif
-
-#include "fb.h"
-
- /* colormap initialization */
-#include "micmap.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "xf86PciInfo.h"
-#include "xf86RAC.h"
-#include "xf86Resources.h"
-#include "xf86cmap.h"
-#include "xf86xv.h"
-#include "vbe.h"
-
- /* fbdevhw & vgahw */
-#ifdef WITH_VGAHW
-#include "vgaHW.h"
-#endif
-#include "fbdevhw.h"
-#include "dixstruct.h"
-
- /* DPMS support. */
-#define DPMS_SERVER
-#include <X11/extensions/dpms.h>
-
-#ifndef MAX
-#define MAX(a,b) ((a)>(b)?(a):(b))
-#endif
-
-#define USE_CRT_ONLY 0
-
- /* Forward definitions for driver functions */
-static Bool R128CloseScreen(int scrnIndex, ScreenPtr pScreen);
-static Bool R128SaveScreen(ScreenPtr pScreen, int mode);
-static void R128Save(ScrnInfoPtr pScrn);
-static void R128Restore(ScrnInfoPtr pScrn);
-static Bool R128ModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
-static void R128DisplayPowerManagementSet(ScrnInfoPtr pScrn,
- int PowerManagementMode, int flags);
-static void R128DisplayPowerManagementSetLCD(ScrnInfoPtr pScrn,
- int PowerManagementMode, int flags);
-
-typedef enum {
- OPTION_NOACCEL,
- OPTION_SW_CURSOR,
- OPTION_DAC_6BIT,
- OPTION_DAC_8BIT,
-#ifdef XF86DRI
- OPTION_XV_DMA,
- OPTION_IS_PCI,
- OPTION_CCE_PIO,
- OPTION_NO_SECURITY,
- OPTION_USEC_TIMEOUT,
- OPTION_AGP_MODE,
- OPTION_AGP_SIZE,
- OPTION_RING_SIZE,
- OPTION_BUFFER_SIZE,
- OPTION_PAGE_FLIP,
-#endif
-#if USE_CRT_ONLY
- /* FIXME: Disable CRTOnly until it is tested */
- OPTION_CRT,
-#endif
- OPTION_DISPLAY,
- OPTION_PANEL_WIDTH,
- OPTION_PANEL_HEIGHT,
- OPTION_PROG_FP_REGS,
- OPTION_FBDEV,
- OPTION_VIDEO_KEY,
- OPTION_SHOW_CACHE,
- OPTION_VGA_ACCESS
-} R128Opts;
-
-static const OptionInfoRec R128Options[] = {
- { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE },
-#ifdef XF86DRI
- { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_IS_PCI, "ForcePCIMode", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_CCE_PIO, "CCEPIOMode", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_NO_SECURITY, "CCENoSecurity", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_USEC_TIMEOUT, "CCEusecTimeout", OPTV_INTEGER, {0}, FALSE },
- { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE },
- { OPTION_AGP_SIZE, "AGPSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE },
-#endif
- { OPTION_DISPLAY, "Display", OPTV_STRING, {0}, FALSE },
- { OPTION_PANEL_WIDTH, "PanelWidth", OPTV_INTEGER, {0}, FALSE },
- { OPTION_PANEL_HEIGHT, "PanelHeight", OPTV_INTEGER, {0}, FALSE },
- { OPTION_PROG_FP_REGS, "ProgramFPRegs", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
- { OPTION_SHOW_CACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE },
- { -1, NULL, OPTV_NONE, {0}, FALSE }
-};
-
-const OptionInfoRec *R128OptionsWeak(void) { return R128Options; }
-
-R128RAMRec R128RAM[] = { /* Memory Specifications
- From RAGE 128 Software Development
- Manual (Technical Reference Manual P/N
- SDK-G04000 Rev 0.01), page 3-21. */
- { 4, 4, 3, 3, 1, 3, 1, 16, 12, "128-bit SDR SGRAM 1:1" },
- { 4, 8, 3, 3, 1, 3, 1, 17, 13, "64-bit SDR SGRAM 1:1" },
- { 4, 4, 1, 2, 1, 2, 1, 16, 12, "64-bit SDR SGRAM 2:1" },
- { 4, 4, 3, 3, 2, 3, 1, 16, 12, "64-bit DDR SGRAM" },
-};
-
-int getR128EntityIndex(void)
-{
- int *r128_entity_index = LoaderSymbol("gR128EntityIndex");
- if (!r128_entity_index)
- return -1;
- else
- return *r128_entity_index;
-}
-
-R128EntPtr R128EntPriv(ScrnInfoPtr pScrn)
-{
- DevUnion *pPriv;
- R128InfoPtr info = R128PTR(pScrn);
- pPriv = xf86GetEntityPrivate(info->pEnt->index,
- getR128EntityIndex());
- return pPriv->ptr;
-}
-
-/* Allocate our private R128InfoRec. */
-static Bool R128GetRec(ScrnInfoPtr pScrn)
-{
- if (pScrn->driverPrivate) return TRUE;
-
- pScrn->driverPrivate = xnfcalloc(sizeof(R128InfoRec), 1);
- return TRUE;
-}
-
-/* Free our private R128InfoRec. */
-static void R128FreeRec(ScrnInfoPtr pScrn)
-{
- if (!pScrn || !pScrn->driverPrivate) return;
- xfree(pScrn->driverPrivate);
- pScrn->driverPrivate = NULL;
-}
-
-/* Memory map the MMIO region. Used during pre-init and by R128MapMem,
- below. */
-static Bool R128MapMMIO(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (info->FBDev) {
- info->MMIO = fbdevHWMapMMIO(pScrn);
- } else {
-#ifndef XSERVER_LIBPCIACCESS
- info->MMIO = xf86MapPciMem(pScrn->scrnIndex,
- VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
- info->PciTag,
- info->MMIOAddr,
- R128_MMIOSIZE);
-#else
- int err = pci_device_map_range(info->PciInfo,
- info->MMIOAddr,
- R128_MMIOSIZE,
- PCI_DEV_MAP_FLAG_WRITABLE,
- &info->MMIO);
-
- if (err) {
- xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
- "Unable to map MMIO aperture. %s (%d)\n",
- strerror (err), err);
- return FALSE;
- }
-#endif
- }
-
- if (!info->MMIO) return FALSE;
- return TRUE;
-}
-
-/* Unmap the MMIO region. Used during pre-init and by R128UnmapMem,
- below. */
-static Bool R128UnmapMMIO(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (info->FBDev)
- fbdevHWUnmapMMIO(pScrn);
- else {
-#ifndef XSERVER_LIBPCIACCESS
- xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, R128_MMIOSIZE);
-#else
- pci_device_unmap_range(info->PciInfo, info->MMIO, R128_MMIOSIZE);
-#endif
- }
- info->MMIO = NULL;
- return TRUE;
-}
-
-/* Memory map the frame buffer. Used by R128MapMem, below. */
-static Bool R128MapFB(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (info->FBDev) {
- info->FB = fbdevHWMapVidmem(pScrn);
- } else {
-#ifndef XSERVER_LIBPCIACCESS
- info->FB = xf86MapPciMem(pScrn->scrnIndex,
- VIDMEM_FRAMEBUFFER,
- info->PciTag,
- info->LinearAddr,
- info->FbMapSize);
-#else
- int err = pci_device_map_range(info->PciInfo,
- info->LinearAddr,
- info->FbMapSize,
- PCI_DEV_MAP_FLAG_WRITABLE |
- PCI_DEV_MAP_FLAG_WRITE_COMBINE,
- &info->FB);
-
- if (err) {
- xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
- "Unable to map FB aperture. %s (%d)\n",
- strerror (err), err);
- return FALSE;
- }
-#endif
- }
-
- if (!info->FB) return FALSE;
- return TRUE;
-}
-
-/* Unmap the frame buffer. Used by R128UnmapMem, below. */
-static Bool R128UnmapFB(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (info->FBDev)
- fbdevHWUnmapVidmem(pScrn);
- else
-#ifndef XSERVER_LIBPCIACCESS
- xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize);
-#else
- pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize);
-#endif
- info->FB = NULL;
- return TRUE;
-}
-
-/* Memory map the MMIO region and the frame buffer. */
-static Bool R128MapMem(ScrnInfoPtr pScrn)
-{
- if (!R128MapMMIO(pScrn)) return FALSE;
- if (!R128MapFB(pScrn)) {
- R128UnmapMMIO(pScrn);
- return FALSE;
- }
- return TRUE;
-}
-
-/* Unmap the MMIO region and the frame buffer. */
-static Bool R128UnmapMem(ScrnInfoPtr pScrn)
-{
- if (!R128UnmapMMIO(pScrn) || !R128UnmapFB(pScrn)) return FALSE;
- return TRUE;
-}
-
-/* Read PLL information */
-unsigned R128INPLL(ScrnInfoPtr pScrn, int addr)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG8(R128_CLOCK_CNTL_INDEX, addr & 0x3f);
- return INREG(R128_CLOCK_CNTL_DATA);
-}
-
-#if 0
-/* Read PAL information (only used for debugging). */
-static int R128INPAL(int idx)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG(R128_PALETTE_INDEX, idx << 16);
- return INREG(R128_PALETTE_DATA);
-}
-#endif
-
-/* Wait for vertical sync. */
-void R128WaitForVerticalSync(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i;
-
- OUTREG(R128_GEN_INT_STATUS, R128_VSYNC_INT_AK);
- for (i = 0; i < R128_TIMEOUT; i++) {
- if (INREG(R128_GEN_INT_STATUS) & R128_VSYNC_INT) break;
- }
-}
-
-/* Blank screen. */
-static void R128Blank(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if(!info->IsSecondary)
- {
- switch(info->DisplayType)
- {
- case MT_LCD:
- OUTREGP(R128_LVDS_GEN_CNTL, R128_LVDS_DISPLAY_DIS,
- ~R128_LVDS_DISPLAY_DIS);
- break;
- case MT_CRT:
- OUTREGP(R128_CRTC_EXT_CNTL, R128_CRTC_DISPLAY_DIS, ~R128_CRTC_DISPLAY_DIS);
- break;
- case MT_DFP:
- OUTREGP(R128_FP_GEN_CNTL, R128_FP_BLANK_DIS, ~R128_FP_BLANK_DIS);
- break;
- case MT_NONE:
- default:
- break;
- }
- }
- else
- {
- OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_DISP_DIS, ~R128_CRTC2_DISP_DIS);
- }
-}
-
-/* Unblank screen. */
-static void R128Unblank(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if(!info->IsSecondary)
- {
- switch(info->DisplayType)
- {
- case MT_LCD:
- OUTREGP(R128_LVDS_GEN_CNTL, 0,
- ~R128_LVDS_DISPLAY_DIS);
- break;
- case MT_CRT:
- OUTREGP(R128_CRTC_EXT_CNTL, 0, ~R128_CRTC_DISPLAY_DIS);
- break;
- case MT_DFP:
- OUTREGP(R128_FP_GEN_CNTL, 0, ~R128_FP_BLANK_DIS);
- break;
- case MT_NONE:
- default:
- break;
- }
- }
- else
- {
- switch(info->DisplayType)
- {
- case MT_LCD:
- case MT_DFP:
- case MT_CRT:
- OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~R128_CRTC2_DISP_DIS);
- break;
- case MT_NONE:
- default:
- break;
- }
- }
-}
-
-/* Compute log base 2 of val. */
-int R128MinBits(int val)
-{
- int bits;
-
- if (!val) return 1;
- for (bits = 0; val; val >>= 1, ++bits);
- return bits;
-}
-
-/* Compute n/d with rounding. */
-static int R128Div(int n, int d)
-{
- return (n + (d / 2)) / d;
-}
-
-/* Read the Video BIOS block and the FP registers (if applicable). */
-static Bool R128GetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int i;
- int FPHeader = 0;
-
-#define R128_BIOS8(v) (info->VBIOS[v])
-#define R128_BIOS16(v) (info->VBIOS[v] | \
- (info->VBIOS[(v) + 1] << 8))
-#define R128_BIOS32(v) (info->VBIOS[v] | \
- (info->VBIOS[(v) + 1] << 8) | \
- (info->VBIOS[(v) + 2] << 16) | \
- (info->VBIOS[(v) + 3] << 24))
-
-#ifdef XSERVER_LIBPCIACCESS
- info->VBIOS = xalloc(info->PciInfo->rom_size);
-#else
- info->VBIOS = xalloc(R128_VBIOS_SIZE);
-#endif
-
- if (!info->VBIOS) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Cannot allocate space for hold Video BIOS!\n");
- return FALSE;
- }
-
- if (pInt10) {
- info->BIOSAddr = pInt10->BIOSseg << 4;
- (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr),
- R128_VBIOS_SIZE);
- } else {
-#ifdef XSERVER_LIBPCIACCESS
- if (pci_device_read_rom(info->PciInfo, info->VBIOS)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Failed to read PCI ROM!\n");
- }
-#else
- xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, R128_VBIOS_SIZE);
- if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Video BIOS not detected in PCI space!\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Attempting to read Video BIOS from legacy ISA space!\n");
- info->BIOSAddr = 0x000c0000;
- xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, R128_VBIOS_SIZE, info->VBIOS);
- }
-#endif
- }
- if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) {
- info->BIOSAddr = 0x00000000;
- xfree(info->VBIOS);
- info->VBIOS = NULL;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Video BIOS not found!\n");
- }
-
- if(info->HasCRTC2)
- {
- if(info->IsSecondary)
- {
- /* there may be a way to detect this, for now, just assume
- second head is CRT */
- info->DisplayType = MT_CRT;
-
- if(info->DisplayType > MT_NONE)
- {
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
- pR128Ent->HasSecondary = TRUE;
-
- }
- else return FALSE;
-
- }
- else
- {
- /* really need some sort of detection here */
- if (info->HasPanelRegs) {
- info->DisplayType = MT_LCD;
- } else if (info->isDFP) {
- info->DisplayType = MT_DFP;
- } else
- {
- /*DVI port has no monitor connected, try CRT port.
- If something on CRT port, treat it as primary*/
- if(xf86IsEntityShared(pScrn->entityList[0]))
- {
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
- pR128Ent->BypassSecondary = TRUE;
- }
-
- info->DisplayType = MT_CRT;
-#if 0
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No monitor detected!!!\n");
- return FALSE;
- }
-#endif
- }
- }
- }
- else
- {
- /*Regular Radeon ASIC, only one CRTC, but it could be
- used for DFP with a DVI output, like AIW board*/
- if(info->isDFP) info->DisplayType = MT_DFP;
- else info->DisplayType = MT_CRT;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s Display == Type %d\n",
- (info->IsSecondary ? "Secondary" : "Primary"),
- info->DisplayType);
-
-
- if (info->VBIOS && info->DisplayType == MT_LCD) {
- info->FPBIOSstart = 0;
-
- /* FIXME: There should be direct access to the start of the FP info
- tables, but until we find out where that offset is stored, we
- must search for the ATI signature string: "M3 ". */
- for (i = 4; i < R128_VBIOS_SIZE-8; i++) {
- if (R128_BIOS8(i) == 'M' &&
- R128_BIOS8(i+1) == '3' &&
- R128_BIOS8(i+2) == ' ' &&
- R128_BIOS8(i+3) == ' ' &&
- R128_BIOS8(i+4) == ' ' &&
- R128_BIOS8(i+5) == ' ' &&
- R128_BIOS8(i+6) == ' ' &&
- R128_BIOS8(i+7) == ' ') {
- FPHeader = i-2;
- break;
- }
- }
-
- if (!FPHeader) return TRUE;
-
- /* Assume that only one panel is attached and supported */
- for (i = FPHeader+20; i < FPHeader+84; i += 2) {
- if (R128_BIOS16(i) != 0) {
- info->FPBIOSstart = R128_BIOS16(i);
- break;
- }
- }
- if (!info->FPBIOSstart) return TRUE;
-
- if (!info->PanelXRes)
- info->PanelXRes = R128_BIOS16(info->FPBIOSstart+25);
- if (!info->PanelYRes)
- info->PanelYRes = R128_BIOS16(info->FPBIOSstart+27);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel size: %dx%d\n",
- info->PanelXRes, info->PanelYRes);
-
- info->PanelPwrDly = R128_BIOS8(info->FPBIOSstart+56);
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel ID: ");
- for (i = 1; i <= 24; i++)
- ErrorF("%c", R128_BIOS8(info->FPBIOSstart+i));
- ErrorF("\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel Type: ");
- i = R128_BIOS16(info->FPBIOSstart+29);
- if (i & 1) ErrorF("Color, ");
- else ErrorF("Monochrome, ");
- if (i & 2) ErrorF("Dual(split), ");
- else ErrorF("Single, ");
- switch ((i >> 2) & 0x3f) {
- case 0: ErrorF("STN"); break;
- case 1: ErrorF("TFT"); break;
- case 2: ErrorF("Active STN"); break;
- case 3: ErrorF("EL"); break;
- case 4: ErrorF("Plasma"); break;
- default: ErrorF("UNKNOWN"); break;
- }
- ErrorF("\n");
- if (R128_BIOS8(info->FPBIOSstart+61) & 1) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel Interface: LVDS\n");
- } else {
- /* FIXME: Add Non-LVDS flat pael support */
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Non-LVDS panel interface detected! "
- "This support is untested and may not "
- "function properly\n");
- }
- }
-
- if (!info->PanelXRes || !info->PanelYRes) {
- info->HasPanelRegs = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Can't determine panel dimensions, and none specified.\n"
- "\tDisabling programming of FP registers.\n");
- }
-
- return TRUE;
-}
-
-/* Read PLL parameters from BIOS block. Default to typical values if there
- is no BIOS. */
-static Bool R128GetPLLParameters(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- R128PLLPtr pll = &info->pll;
-
-#if defined(__powerpc__) || defined(__alpha__)
- /* there is no bios under Linux PowerPC but Open Firmware
- does set up the PLL registers properly and we can use
- those to calculate xclk and find the reference divider */
-
- unsigned x_mpll_ref_fb_div;
- unsigned xclk_cntl;
- unsigned Nx, M;
- unsigned PostDivSet[] = {0, 1, 2, 4, 8, 3, 6, 12};
-
- /* Assume REF clock is 2950 (in units of 10khz) */
- /* and that all pllclk must be between 125 Mhz and 250Mhz */
- pll->reference_freq = 2950;
- pll->min_pll_freq = 12500;
- pll->max_pll_freq = 25000;
-
- /* need to memory map the io to use INPLL since it
- has not been done yet at this point in the startup */
- R128MapMMIO(pScrn);
- x_mpll_ref_fb_div = INPLL(pScrn, R128_X_MPLL_REF_FB_DIV);
- xclk_cntl = INPLL(pScrn, R128_XCLK_CNTL) & 0x7;
- pll->reference_div =
- INPLL(pScrn,R128_PPLL_REF_DIV) & R128_PPLL_REF_DIV_MASK;
- /* unmap it again */
- R128UnmapMMIO(pScrn);
-
- Nx = (x_mpll_ref_fb_div & 0x00FF00) >> 8;
- M = (x_mpll_ref_fb_div & 0x0000FF);
-
- pll->xclk = R128Div((2 * Nx * pll->reference_freq),
- (M * PostDivSet[xclk_cntl]));
-
-#else /* !defined(__powerpc__) */
-
- if (!info->VBIOS) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Video BIOS not detected, using default PLL parameters!\n");
- /* These probably aren't going to work for
- the card you are using. Specifically,
- reference freq can be 29.50MHz,
- 28.63MHz, or 14.32MHz. YMMV. */
- pll->reference_freq = 2950;
- pll->reference_div = 65;
- pll->min_pll_freq = 12500;
- pll->max_pll_freq = 25000;
- pll->xclk = 10300;
- } else {
- CARD16 bios_header = R128_BIOS16(0x48);
- CARD16 pll_info_block = R128_BIOS16(bios_header + 0x30);
- R128TRACE(("Header at 0x%04x; PLL Information at 0x%04x\n",
- bios_header, pll_info_block));
-
- pll->reference_freq = R128_BIOS16(pll_info_block + 0x0e);
- pll->reference_div = R128_BIOS16(pll_info_block + 0x10);
- pll->min_pll_freq = R128_BIOS32(pll_info_block + 0x12);
- pll->max_pll_freq = R128_BIOS32(pll_info_block + 0x16);
- pll->xclk = R128_BIOS16(pll_info_block + 0x08);
- }
-#endif /* __powerpc__ */
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n",
- pll->reference_freq,
- pll->reference_div,
- pll->min_pll_freq,
- pll->max_pll_freq,
- pll->xclk);
-
- return TRUE;
-}
-
-/* This is called by R128PreInit to set up the default visual. */
-static Bool R128PreInitVisual(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (!xf86SetDepthBpp(pScrn, 0, 0, 0, (Support24bppFb
- | Support32bppFb
- | SupportConvert32to24
- )))
- return FALSE;
-
- switch (pScrn->depth) {
- case 8:
- case 15:
- case 16:
- case 24:
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Given depth (%d) is not supported by %s driver\n",
- pScrn->depth, R128_DRIVER_NAME);
- return FALSE;
- }
-
- xf86PrintDepthBpp(pScrn);
-
- info->fifo_slots = 0;
- info->pix24bpp = xf86GetBppFromDepth(pScrn, pScrn->depth);
- info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel;
- info->CurrentLayout.depth = pScrn->depth;
- info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8;
- info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16
- ? pScrn->bitsPerPixel
- : pScrn->depth);
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n",
- pScrn->depth,
- info->CurrentLayout.pixel_bytes,
- info->CurrentLayout.pixel_bytes > 1 ? "s" : "",
- info->pix24bpp);
-
-
- if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE;
-
- if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Default visual (%s) is not supported at depth %d\n",
- xf86GetVisualName(pScrn->defaultVisual), pScrn->depth);
- return FALSE;
- }
- return TRUE;
-
-}
-
-/* This is called by R128PreInit to handle all color weight issues. */
-static Bool R128PreInitWeight(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- /* Save flag for 6 bit DAC to use for
- setting CRTC registers. Otherwise use
- an 8 bit DAC, even if xf86SetWeight sets
- pScrn->rgbBits to some value other than
- 8. */
- info->dac6bits = FALSE;
- if (pScrn->depth > 8) {
- rgb defaultWeight = { 0, 0, 0 };
- if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE;
- } else {
- pScrn->rgbBits = 8;
- if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) {
- pScrn->rgbBits = 6;
- info->dac6bits = TRUE;
- }
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d bits per RGB (%d bit DAC)\n",
- pScrn->rgbBits, info->dac6bits ? 6 : 8);
-
- return TRUE;
-
-}
-
-/* This is called by R128PreInit to handle config file overrides for things
- like chipset and memory regions. Also determine memory size and type.
- If memory type ever needs an override, put it in this routine. */
-static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- EntityInfoPtr pEnt = info->pEnt;
- GDevPtr dev = pEnt->device;
- int offset = 0; /* RAM Type */
- MessageType from;
-
- /* Chipset */
- from = X_PROBED;
- if (dev->chipset && *dev->chipset) {
- info->Chipset = xf86StringToToken(R128Chipsets, dev->chipset);
- from = X_CONFIG;
- } else if (dev->chipID >= 0) {
- info->Chipset = dev->chipID;
- from = X_CONFIG;
- } else {
- info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
- }
- pScrn->chipset = (char *)xf86TokenToString(R128Chipsets, info->Chipset);
-
- if (!pScrn->chipset) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "ChipID 0x%04x is not recognized\n", info->Chipset);
- return FALSE;
- }
-
- if (info->Chipset < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Chipset \"%s\" is not recognized\n", pScrn->chipset);
- return FALSE;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Chipset: \"%s\" (ChipID = 0x%04x)\n",
- pScrn->chipset,
- info->Chipset);
-
- /* Framebuffer */
-
- from = X_PROBED;
- info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & 0xfc000000;
- pScrn->memPhysBase = info->LinearAddr;
- if (dev->MemBase) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Linear address override, using 0x%08lx instead of 0x%08lx\n",
- dev->MemBase,
- info->LinearAddr);
- info->LinearAddr = dev->MemBase;
- from = X_CONFIG;
- } else if (!info->LinearAddr) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No valid linear framebuffer address\n");
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Linear framebuffer at 0x%08lx\n", info->LinearAddr);
-
- /* MMIO registers */
- from = X_PROBED;
- info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & 0xffffff00;
- if (dev->IOBase) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "MMIO address override, using 0x%08lx instead of 0x%08lx\n",
- dev->IOBase,
- info->MMIOAddr);
- info->MMIOAddr = dev->IOBase;
- from = X_CONFIG;
- } else if (!info->MMIOAddr) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n");
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, from,
- "MMIO registers at 0x%08lx\n", info->MMIOAddr);
-
-#ifndef XSERVER_LIBPCIACCESS
- /* BIOS */
- from = X_PROBED;
- info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000;
- if (dev->BiosBase) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "BIOS address override, using 0x%08lx instead of 0x%08lx\n",
- dev->BiosBase,
- info->BIOSAddr);
- info->BIOSAddr = dev->BiosBase;
- from = X_CONFIG;
- }
- if (info->BIOSAddr) {
- xf86DrvMsg(pScrn->scrnIndex, from,
- "BIOS at 0x%08lx\n", info->BIOSAddr);
- }
-#endif
-
- /* Flat panel (part 1) */
- if (xf86GetOptValBool(info->Options, OPTION_PROG_FP_REGS,
- &info->HasPanelRegs)) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Turned flat panel register programming %s\n",
- info->HasPanelRegs ? "on" : "off");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "\n\nWARNING: Forcing the driver to use/not use the flat panel registers\nmight damage your flat panel. Use at your *OWN* *RISK*.\n\n");
- } else {
- info->isDFP = FALSE;
- info->isPro2 = FALSE;
- info->HasCRTC2 = FALSE;
- switch (info->Chipset) {
- /* R128 Pro and Pro2 can have DFP, we will deal with it.
- No support for dual-head/xinerama yet.
- M3 can also have DFP, no support for now */
- case PCI_CHIP_RAGE128TF:
- case PCI_CHIP_RAGE128TL:
- case PCI_CHIP_RAGE128TR:
- /* FIXME: RAGE128 TS/TT/TU are assumed to be PRO2 as all 6 chips came
- * out at the same time, so are of the same family likely.
- * This requires confirmation however to be fully correct.
- * Mike A. Harris <mharris at redhat.com>
- */
- case PCI_CHIP_RAGE128TS:
- case PCI_CHIP_RAGE128TT:
- case PCI_CHIP_RAGE128TU: info->isPro2 = TRUE;
- /* FIXME: RAGE128 P[ABCEGHIJKLMNOQSTUVWX] are assumed to have DFP
- * capability, as the comment at the top suggests.
- * This requires confirmation however to be fully correct.
- * Mike A. Harris <mharris at redhat.com>
- */
- case PCI_CHIP_RAGE128PA:
- case PCI_CHIP_RAGE128PB:
- case PCI_CHIP_RAGE128PC:
- case PCI_CHIP_RAGE128PE:
- case PCI_CHIP_RAGE128PG:
- case PCI_CHIP_RAGE128PH:
- case PCI_CHIP_RAGE128PI:
- case PCI_CHIP_RAGE128PJ:
- case PCI_CHIP_RAGE128PK:
- case PCI_CHIP_RAGE128PL:
- case PCI_CHIP_RAGE128PM:
- case PCI_CHIP_RAGE128PN:
- case PCI_CHIP_RAGE128PO:
- case PCI_CHIP_RAGE128PQ:
- case PCI_CHIP_RAGE128PS:
- case PCI_CHIP_RAGE128PT:
- case PCI_CHIP_RAGE128PU:
- case PCI_CHIP_RAGE128PV:
- case PCI_CHIP_RAGE128PW:
- case PCI_CHIP_RAGE128PX:
-
- case PCI_CHIP_RAGE128PD:
- case PCI_CHIP_RAGE128PF:
- case PCI_CHIP_RAGE128PP:
- case PCI_CHIP_RAGE128PR: info->isDFP = TRUE; break;
-
- case PCI_CHIP_RAGE128LE:
- case PCI_CHIP_RAGE128LF:
- case PCI_CHIP_RAGE128MF:
- case PCI_CHIP_RAGE128ML:
- info->HasPanelRegs = TRUE;
- /* which chips support dualhead? */
- info->HasCRTC2 = TRUE;
- break;
- case PCI_CHIP_RAGE128RE:
- case PCI_CHIP_RAGE128RF:
- case PCI_CHIP_RAGE128RG:
- case PCI_CHIP_RAGE128RK:
- case PCI_CHIP_RAGE128RL:
- case PCI_CHIP_RAGE128SM:
- /* FIXME: RAGE128 S[EFGHKLN] are assumed to be like the SM above as
- * all of them are listed as "Rage 128 4x" in ATI docs.
- * This requires confirmation however to be fully correct.
- * Mike A. Harris <mharris at redhat.com>
- */
- case PCI_CHIP_RAGE128SE:
- case PCI_CHIP_RAGE128SF:
- case PCI_CHIP_RAGE128SG:
- case PCI_CHIP_RAGE128SH:
- case PCI_CHIP_RAGE128SK:
- case PCI_CHIP_RAGE128SL:
- case PCI_CHIP_RAGE128SN:
- default: info->HasPanelRegs = FALSE; break;
- }
- }
-
- /* Read registers used to determine options */
- from = X_PROBED;
- R128MapMMIO(pScrn);
- R128MMIO = info->MMIO;
-
- if (info->FBDev)
- pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024;
- else
- pScrn->videoRam = INREG(R128_CONFIG_MEMSIZE) / 1024;
-
- info->MemCntl = INREG(R128_MEM_CNTL);
- info->BusCntl = INREG(R128_BUS_CNTL);
-
- /* On non-flat panel systems, the default is to display to the CRT,
- and on flat panel systems, the default is to display to the flat
- panel unless the user explicity chooses otherwise using the "Display"
- config file setting. BIOS_5_SCRATCH holds the display device on flat
- panel systems only. */
- if (info->HasPanelRegs) {
- char *Display = xf86GetOptValString(info->Options, OPTION_DISPLAY);
-
- if (info->FBDev)
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Option \"Display\" ignored "
- "(framebuffer device determines display type)\n");
- else if (info->IsPrimary || info->IsSecondary)
- info->BIOSDisplay = R128_DUALHEAD;
- else if (!Display || !xf86NameCmp(Display, "FP"))
- info->BIOSDisplay = R128_BIOS_DISPLAY_FP;
- else if (!xf86NameCmp(Display, "BIOS"))
- info->BIOSDisplay = INREG8(R128_BIOS_5_SCRATCH);
- else if (!xf86NameCmp(Display, "Mirror"))
- info->BIOSDisplay = R128_BIOS_DISPLAY_FP_CRT;
- else if (!xf86NameCmp(Display, "CRT"))
- info->BIOSDisplay = R128_BIOS_DISPLAY_CRT;
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Unsupported type \"%s\" specified for Option \"Display\".\n"
- "\tSupported types are: "
- "\"BIOS\", \"Mirror\", \"CRT\" and \"FP\"\n", Display);
- return FALSE;
- }
- } else {
- info->BIOSDisplay = R128_BIOS_DISPLAY_CRT;
- }
-
- R128MMIO = NULL;
- R128UnmapMMIO(pScrn);
-
- /* RAM */
- switch (info->MemCntl & 0x3) {
- case 0: /* SDR SGRAM 1:1 */
- switch (info->Chipset) {
- case PCI_CHIP_RAGE128TF:
- case PCI_CHIP_RAGE128TL:
- case PCI_CHIP_RAGE128TR:
- case PCI_CHIP_RAGE128LE:
- case PCI_CHIP_RAGE128LF:
- case PCI_CHIP_RAGE128MF:
- case PCI_CHIP_RAGE128ML:
- case PCI_CHIP_RAGE128RE:
- case PCI_CHIP_RAGE128RF:
- case PCI_CHIP_RAGE128RG: offset = 0; break; /* 128-bit SDR SGRAM 1:1 */
- case PCI_CHIP_RAGE128RK:
- case PCI_CHIP_RAGE128RL:
- case PCI_CHIP_RAGE128SM:
- default: offset = 1; break; /* 64-bit SDR SGRAM 1:1 */
- }
- break;
- case 1: offset = 2; break; /* 64-bit SDR SGRAM 2:1 */
- case 2: offset = 3; break; /* 64-bit DDR SGRAM */
- default: offset = 1; break; /* 64-bit SDR SGRAM 1:1 */
- }
- info->ram = &R128RAM[offset];
-
- if (dev->videoRam) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Video RAM override, using %d kB instead of %d kB\n",
- dev->videoRam,
- pScrn->videoRam);
- from = X_CONFIG;
- pScrn->videoRam = dev->videoRam;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from,
- "VideoRAM: %d kByte (%s)\n", pScrn->videoRam, info->ram->name);
-
- if (info->IsPrimary) {
- pScrn->videoRam /= 2;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %dk of videoram for primary head\n",
- pScrn->videoRam);
- }
-
- if (info->IsSecondary) {
- pScrn->videoRam /= 2;
- info->LinearAddr += pScrn->videoRam * 1024;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %dk of videoram for secondary head\n",
- pScrn->videoRam);
- }
-
- pScrn->videoRam &= ~1023;
- info->FbMapSize = pScrn->videoRam * 1024;
-
-
- /* Flat panel (part 2) */
- switch (info->BIOSDisplay) {
- case R128_DUALHEAD:
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Dual display\n");
- break;
- case R128_BIOS_DISPLAY_FP:
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Using flat panel for display\n");
- break;
- case R128_BIOS_DISPLAY_CRT:
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Using external CRT for display\n");
- break;
- case R128_BIOS_DISPLAY_FP_CRT:
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Using both flat panel and external CRT "
- "for display\n");
- break;
- }
-
- if (info->HasPanelRegs) {
- /* Panel width/height overrides */
- info->PanelXRes = 0;
- info->PanelYRes = 0;
- if (xf86GetOptValInteger(info->Options,
- OPTION_PANEL_WIDTH, &(info->PanelXRes))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Flat panel width: %d\n", info->PanelXRes);
- }
- if (xf86GetOptValInteger(info->Options,
- OPTION_PANEL_HEIGHT, &(info->PanelYRes))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Flat panel height: %d\n", info->PanelYRes);
- }
- }
-
-#ifdef XF86DRI
- /* DMA for Xv */
- info->DMAForXv = xf86ReturnOptValBool(info->Options, OPTION_XV_DMA, FALSE);
- if (info->DMAForXv) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Will try to use DMA for Xv image transfers\n");
- }
-
- /* AGP/PCI */
- if (xf86ReturnOptValBool(info->Options, OPTION_IS_PCI, FALSE)) {
- info->IsPCI = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI-only mode\n");
- } else {
- switch (info->Chipset) {
- case PCI_CHIP_RAGE128LE:
- case PCI_CHIP_RAGE128RE:
- case PCI_CHIP_RAGE128RK:
- case PCI_CHIP_RAGE128PD:
- case PCI_CHIP_RAGE128PR:
- case PCI_CHIP_RAGE128PP: info->IsPCI = TRUE; break;
- case PCI_CHIP_RAGE128LF:
- case PCI_CHIP_RAGE128MF:
- case PCI_CHIP_RAGE128ML:
- case PCI_CHIP_RAGE128PF:
- case PCI_CHIP_RAGE128RF:
- case PCI_CHIP_RAGE128RG:
- case PCI_CHIP_RAGE128RL:
- case PCI_CHIP_RAGE128SM:
- case PCI_CHIP_RAGE128TF:
- case PCI_CHIP_RAGE128TL:
- case PCI_CHIP_RAGE128TR:
- /* FIXME: Rage 128 S[EFGHKLN], T[STU], P[ABCEGHIJKLMNOQSTUVWX] are
- * believed to be AGP, but need confirmation. <mharris at redhat.com>
- */
- case PCI_CHIP_RAGE128PA:
- case PCI_CHIP_RAGE128PB:
- case PCI_CHIP_RAGE128PC:
- case PCI_CHIP_RAGE128PE:
- case PCI_CHIP_RAGE128PG:
- case PCI_CHIP_RAGE128PH:
- case PCI_CHIP_RAGE128PI:
- case PCI_CHIP_RAGE128PJ:
- case PCI_CHIP_RAGE128PK:
- case PCI_CHIP_RAGE128PL:
- case PCI_CHIP_RAGE128PM:
- case PCI_CHIP_RAGE128PN:
- case PCI_CHIP_RAGE128PO:
- case PCI_CHIP_RAGE128PQ:
- case PCI_CHIP_RAGE128PS:
- case PCI_CHIP_RAGE128PT:
- case PCI_CHIP_RAGE128PU:
- case PCI_CHIP_RAGE128PV:
- case PCI_CHIP_RAGE128PW:
- case PCI_CHIP_RAGE128PX:
- case PCI_CHIP_RAGE128TS:
- case PCI_CHIP_RAGE128TT:
- case PCI_CHIP_RAGE128TU:
- case PCI_CHIP_RAGE128SE:
- case PCI_CHIP_RAGE128SF:
- case PCI_CHIP_RAGE128SG:
- case PCI_CHIP_RAGE128SH:
- case PCI_CHIP_RAGE128SK:
- case PCI_CHIP_RAGE128SL:
- case PCI_CHIP_RAGE128SN:
- default: info->IsPCI = FALSE; break;
- }
- }
-#endif
-
- return TRUE;
-}
-
-static Bool R128PreInitDDC(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
-{
-#if !defined(__powerpc__) && !defined(__alpha__) && !defined(__sparc__)
- R128InfoPtr info = R128PTR(pScrn);
- vbeInfoPtr pVbe;
-#endif
-
- if (!xf86LoadSubModule(pScrn, "ddc")) return FALSE;
-
-#if defined(__powerpc__) || defined(__alpha__) || defined(__sparc__)
- /* Int10 is broken on PPC and some Alphas */
- return TRUE;
-#else
- if (xf86LoadSubModule(pScrn, "vbe")) {
- pVbe = VBEInit(pInt10,info->pEnt->index);
- if (!pVbe) return FALSE;
- xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(pVbe,NULL)));
- vbeFree(pVbe);
- return TRUE;
- } else
- return FALSE;
-#endif
-}
-
-/* This is called by R128PreInit to initialize gamma correction. */
-static Bool R128PreInitGamma(ScrnInfoPtr pScrn)
-{
- Gamma zeros = { 0.0, 0.0, 0.0 };
-
- if (!xf86SetGamma(pScrn, zeros)) return FALSE;
- return TRUE;
-}
-
-static void
-R128I2CGetBits(I2CBusPtr b, int *Clock, int *data)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
- unsigned long val;
- unsigned char *R128MMIO = info->MMIO;
-
- /* Get the result. */
- val = INREG(info->DDCReg);
- *Clock = (val & R128_GPIO_MONID_Y_3) != 0;
- *data = (val & R128_GPIO_MONID_Y_0) != 0;
-
-}
-
-static void
-R128I2CPutBits(I2CBusPtr b, int Clock, int data)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
- unsigned long val;
- unsigned char *R128MMIO = info->MMIO;
-
- val = INREG(info->DDCReg)
- & ~(CARD32)(R128_GPIO_MONID_EN_0 | R128_GPIO_MONID_EN_3);
- val |= (Clock ? 0:R128_GPIO_MONID_EN_3);
- val |= (data ? 0:R128_GPIO_MONID_EN_0);
- OUTREG(info->DDCReg, val);
-}
-
-
-static Bool
-R128I2cInit(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- if ( !xf86LoadSubModule(pScrn, "i2c") ) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Failed to load i2c module\n");
- return FALSE;
- }
-
- info->pI2CBus = xf86CreateI2CBusRec();
- if(!info->pI2CBus) return FALSE;
-
- info->pI2CBus->BusName = "DDC";
- info->pI2CBus->scrnIndex = pScrn->scrnIndex;
- info->DDCReg = R128_GPIO_MONID;
- info->pI2CBus->I2CPutBits = R128I2CPutBits;
- info->pI2CBus->I2CGetBits = R128I2CGetBits;
- info->pI2CBus->AcknTimeout = 5;
-
- if (!xf86I2CBusInit(info->pI2CBus)) {
- return FALSE;
- }
- return TRUE;
-}
-
-/* return TRUE is a DFP is indeed connected to a DVI port */
-static Bool R128GetDFPInfo(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- int i;
- xf86MonPtr MonInfo = NULL;
- xf86MonPtr ddc;
- unsigned char *R128MMIO = info->MMIO;
-
- if(!R128I2cInit(pScrn)){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "I2C initialization failed!\n");
- }
-
- OUTREG(info->DDCReg, (INREG(info->DDCReg)
- | R128_GPIO_MONID_MASK_0 | R128_GPIO_MONID_MASK_3));
-
- OUTREG(info->DDCReg, INREG(info->DDCReg)
- & ~(CARD32)(R128_GPIO_MONID_A_0 | R128_GPIO_MONID_A_3));
-
- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus);
- if(!MonInfo) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No DFP detected\n");
- return FALSE;
- }
- xf86SetDDCproperties(pScrn, MonInfo);
- ddc = pScrn->monitor->DDC;
-
- for(i=0; i<4; i++)
- {
- if((ddc->det_mon[i].type == 0) &&
- (ddc->det_mon[i].section.d_timings.h_active > 0) &&
- (ddc->det_mon[i].section.d_timings.v_active > 0))
- {
- info->PanelXRes =
- ddc->det_mon[i].section.d_timings.h_active;
- info->PanelYRes =
- ddc->det_mon[i].section.d_timings.v_active;
-
- info->HOverPlus =
- ddc->det_mon[i].section.d_timings.h_sync_off;
- info->HSyncWidth =
- ddc->det_mon[i].section.d_timings.h_sync_width;
- info->HBlank =
- ddc->det_mon[i].section.d_timings.h_blanking;
- info->VOverPlus =
- ddc->det_mon[i].section.d_timings.v_sync_off;
- info->VSyncWidth =
- ddc->det_mon[i].section.d_timings.v_sync_width;
- info->VBlank =
- ddc->det_mon[i].section.d_timings.v_blanking;
- }
- }
- return TRUE;
-}
-
-
-static void R128SetSyncRangeFromEdid(ScrnInfoPtr pScrn, int flag)
-{
- int i;
- xf86MonPtr ddc = pScrn->monitor->DDC;
- if(flag) /*HSync*/
- {
- for(i=0; i<4; i++)
- {
- if(ddc->det_mon[i].type == DS_RANGES)
- {
- pScrn->monitor->nHsync = 1;
- pScrn->monitor->hsync[0].lo =
- ddc->det_mon[i].section.ranges.min_h;
- pScrn->monitor->hsync[0].hi =
- ddc->det_mon[i].section.ranges.max_h;
- return;
- }
- }
- /*if no sync ranges detected in detailed timing table,
- let's try to derive them from supported VESA modes
- Are we doing too much here!!!?
- **/
- i = 0;
- if(ddc->timings1.t1 & 0x02) /*800x600 at 56*/
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 35.2;
- i++;
- }
- if(ddc->timings1.t1 & 0x04) /*640x480 at 75*/
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 37.5;
- i++;
- }
- if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t1 & 0x01))
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 37.9;
- i++;
- }
- if(ddc->timings1.t2 & 0x40)
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 46.9;
- i++;
- }
- if((ddc->timings1.t2 & 0x80) || (ddc->timings1.t2 & 0x08))
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 48.1;
- i++;
- }
- if(ddc->timings1.t2 & 0x04)
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 56.5;
- i++;
- }
- if(ddc->timings1.t2 & 0x02)
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 60.0;
- i++;
- }
- if(ddc->timings1.t2 & 0x01)
- {
- pScrn->monitor->hsync[i].lo =
- pScrn->monitor->hsync[i].hi = 64.0;
- i++;
- }
- pScrn->monitor->nHsync = i;
- }
- else /*Vrefresh*/
- {
- for(i=0; i<4; i++)
- {
- if(ddc->det_mon[i].type == DS_RANGES)
- {
- pScrn->monitor->nVrefresh = 1;
- pScrn->monitor->vrefresh[0].lo =
- ddc->det_mon[i].section.ranges.min_v;
- pScrn->monitor->vrefresh[0].hi =
- ddc->det_mon[i].section.ranges.max_v;
- return;
- }
- }
- i = 0;
- if(ddc->timings1.t1 & 0x02) /*800x600 at 56*/
- {
- pScrn->monitor->vrefresh[i].lo =
- pScrn->monitor->vrefresh[i].hi = 56;
- i++;
- }
- if((ddc->timings1.t1 & 0x01) || (ddc->timings1.t2 & 0x08))
- {
- pScrn->monitor->vrefresh[i].lo =
- pScrn->monitor->vrefresh[i].hi = 60;
- i++;
- }
- if(ddc->timings1.t2 & 0x04)
- {
- pScrn->monitor->vrefresh[i].lo =
- pScrn->monitor->vrefresh[i].hi = 70;
- i++;
- }
- if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t2 & 0x80))
- {
- pScrn->monitor->vrefresh[i].lo =
- pScrn->monitor->vrefresh[i].hi = 72;
- i++;
- }
- if((ddc->timings1.t1 & 0x04) || (ddc->timings1.t2 & 0x40)
- || (ddc->timings1.t2 & 0x02) || (ddc->timings1.t2 & 0x01))
- {
- pScrn->monitor->vrefresh[i].lo =
- pScrn->monitor->vrefresh[i].hi = 75;
- i++;
- }
- pScrn->monitor->nVrefresh = i;
- }
-}
-
-/***********
- xfree's xf86ValidateModes routine deosn't work well with DFPs
- here is our own validation routine. All modes between
- 640<=XRes<=MaxRes and 480<=YRes<=MaxYRes will be permitted.
- NOTE: RageProII doesn't support rmx, can only work with the
- standard modes the monitor can support (scale).
-************/
-
-static int R128ValidateFPModes(ScrnInfoPtr pScrn)
-{
- int i, j, count=0, width, height;
- R128InfoPtr info = R128PTR(pScrn);
- DisplayModePtr last = NULL, new = NULL, first = NULL;
- xf86MonPtr ddc;
-
- /* Free any allocated modes during configuration. We don't need them*/
- while (pScrn->modes)
- {
- xf86DeleteMode(&pScrn->modes, pScrn->modes);
- }
- while (pScrn->modePool)
- {
- xf86DeleteMode(&pScrn->modePool, pScrn->modePool);
- }
-
- pScrn->virtualX = pScrn->display->virtualX;
- pScrn->virtualY = pScrn->display->virtualY;
-
- /* If no mode specified in config, we use native resolution*/
- if(!pScrn->display->modes[0])
- {
- pScrn->display->modes[0] = xnfalloc(16);
- sprintf(pScrn->display->modes[0], "%dx%d",
- info->PanelXRes, info->PanelYRes);
- }
-
- for(i=0; pScrn->display->modes[i] != NULL; i++)
- {
- if (sscanf(pScrn->display->modes[i], "%dx%d", &width, &height) == 2)
- {
-
- if(width < 640 || width > info->PanelXRes ||
- height < 480 || height > info->PanelYRes)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Mode %s is out of range.\n"
- "Valid mode should be between 640x480-%dx%d\n",
- pScrn->display->modes[i], info->PanelXRes, info->PanelYRes);
- continue;
- }
-
- new = xnfcalloc(1, sizeof(DisplayModeRec));
- new->prev = last;
- new->name = xnfalloc(strlen(pScrn->display->modes[i]) + 1);
- strcpy(new->name, pScrn->display->modes[i]);
- new->HDisplay = new->CrtcHDisplay = width;
- new->VDisplay = new->CrtcVDisplay = height;
-
- ddc = pScrn->monitor->DDC;
- for(j=0; j<DET_TIMINGS; j++)
- {
- /*We use native mode clock only*/
- if(ddc->det_mon[j].type == 0){
- new->Clock = ddc->det_mon[j].section.d_timings.clock / 1000;
- break;
- }
- }
-
- if(new->prev) new->prev->next = new;
- last = new;
- if(!first) first = new;
- pScrn->display->virtualX =
- pScrn->virtualX = MAX(pScrn->virtualX, width);
- pScrn->display->virtualY =
- pScrn->virtualY = MAX(pScrn->virtualY, height);
- count++;
- }
- else
- {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Mode name %s is invalid\n", pScrn->display->modes[i]);
- continue;
- }
- }
-
- if(last)
- {
- last->next = first;
- first->prev = last;
- pScrn->modes = first;
-
- /*FIXME: May need to validate line pitch here*/
- {
- int dummy = 0;
- switch(pScrn->depth / 8)
- {
- case 1:
- dummy = 128 - pScrn->virtualX % 128;
- break;
- case 2:
- dummy = 32 - pScrn->virtualX % 32;
- break;
- case 3:
- case 4:
- dummy = 16 - pScrn->virtualX % 16;
- }
- pScrn->displayWidth = pScrn->virtualX + dummy;
- }
-
- }
-
- return count;
-}
-
-
-/* This is called by R128PreInit to validate modes and compute parameters
- for all of the valid modes. */
-static Bool R128PreInitModes(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- ClockRangePtr clockRanges;
- int modesFound;
-
- if(info->isDFP) {
- R128MapMem(pScrn);
- info->BIOSDisplay = R128_BIOS_DISPLAY_FP;
- /* validate if DFP really connected. */
- if(!R128GetDFPInfo(pScrn)) {
- info->isDFP = FALSE;
- info->BIOSDisplay = R128_BIOS_DISPLAY_CRT;
- } else if(!info->isPro2) {
- /* RageProII doesn't support rmx, we can't use native-mode
- stretching for other non-native modes. It will rely on
- whatever VESA modes monitor can support. */
- modesFound = R128ValidateFPModes(pScrn);
- if(modesFound < 1) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No valid mode found for this DFP/LCD\n");
- R128UnmapMem(pScrn);
- return FALSE;
-
- }
- }
- R128UnmapMem(pScrn);
- }
-
- if(!info->isDFP || info->isPro2) {
- /* Get mode information */
- pScrn->progClock = TRUE;
- clockRanges = xnfcalloc(sizeof(*clockRanges), 1);
- clockRanges->next = NULL;
- clockRanges->minClock = info->pll.min_pll_freq;
- clockRanges->maxClock = info->pll.max_pll_freq * 10;
- clockRanges->clockIndex = -1;
- if (info->HasPanelRegs || info->isDFP) {
- clockRanges->interlaceAllowed = FALSE;
- clockRanges->doubleScanAllowed = FALSE;
- } else {
- clockRanges->interlaceAllowed = TRUE;
- clockRanges->doubleScanAllowed = TRUE;
- }
-
- if(pScrn->monitor->DDC) {
- /*if we still don't know sync range yet, let's try EDID.
- Note that, since we can have dual heads, the Xconfigurator
- may not be able to probe both monitors correctly through
- vbe probe function (R128ProbeDDC). Here we provide an
- additional way to auto-detect sync ranges if they haven't
- been added to XF86Config manually.
- **/
- if(pScrn->monitor->nHsync <= 0)
- R128SetSyncRangeFromEdid(pScrn, 1);
- if(pScrn->monitor->nVrefresh <= 0)
- R128SetSyncRangeFromEdid(pScrn, 0);
- }
-
- modesFound = xf86ValidateModes(pScrn,
- pScrn->monitor->Modes,
- pScrn->display->modes,
- clockRanges,
- NULL, /* linePitches */
- 8 * 64, /* minPitch */
- 8 * 1024, /* maxPitch */
-/*
- * ATI docs say pitchInc must be 8 * 64, but this doesn't permit a pitch of
- * 800 bytes, which is known to work on the Rage128 LF on clamshell iBooks
- */
- 8 * 32, /* pitchInc */
- 128, /* minHeight */
- 2048, /* maxHeight */
- pScrn->display->virtualX,
- pScrn->display->virtualY,
- info->FbMapSize,
- LOOKUP_BEST_REFRESH);
-
- if (modesFound < 1 && info->FBDev) {
- fbdevHWUseBuildinMode(pScrn);
- pScrn->displayWidth = fbdevHWGetLineLength(pScrn)/(pScrn->bitsPerPixel/8);
- modesFound = 1;
- }
-
- if (modesFound == -1) return FALSE;
- xf86PruneDriverModes(pScrn);
- if (!modesFound || !pScrn->modes) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n");
- return FALSE;
- }
- xf86SetCrtcForModes(pScrn, 0);
- }
- /* Set DPI */
- pScrn->currentMode = pScrn->modes;
- xf86PrintModes(pScrn);
-
- xf86SetDpi(pScrn, 0, 0);
-
- /* Get ScreenInit function */
- if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
-
- info->CurrentLayout.displayWidth = pScrn->displayWidth;
- info->CurrentLayout.mode = pScrn->currentMode;
-
- return TRUE;
-}
-
-/* This is called by R128PreInit to initialize the hardware cursor. */
-static Bool R128PreInitCursor(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
- if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
- }
- return TRUE;
-}
-
-/* This is called by R128PreInit to initialize hardware acceleration. */
-static Bool R128PreInitAccel(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- if (!xf86LoadSubModule(pScrn, "xaa")) return FALSE;
- }
- return TRUE;
-}
-
-static Bool R128PreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
-{
- R128InfoPtr info = R128PTR(pScrn);
-#if 1 && !defined(__alpha__)
- /* int10 is broken on some Alphas */
- if (xf86LoadSubModule(pScrn, "int10")) {
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n");
- *ppInt10 = xf86InitInt10(info->pEnt->index);
- }
-#endif
- return TRUE;
-}
-
-#ifdef XF86DRI
-static Bool R128PreInitDRI(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (xf86ReturnOptValBool(info->Options, OPTION_CCE_PIO, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CCE into PIO mode\n");
- info->CCEMode = R128_DEFAULT_CCE_PIO_MODE;
- } else {
- info->CCEMode = R128_DEFAULT_CCE_BM_MODE;
- }
-
- if (xf86ReturnOptValBool(info->Options, OPTION_NO_SECURITY, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "WARNING!!! CCE Security checks disabled!!! **********\n");
- info->CCESecure = FALSE;
- } else {
- info->CCESecure = TRUE;
- }
-
- info->agpMode = R128_DEFAULT_AGP_MODE;
- info->agpSize = R128_DEFAULT_AGP_SIZE;
- info->ringSize = R128_DEFAULT_RING_SIZE;
- info->bufSize = R128_DEFAULT_BUFFER_SIZE;
- info->agpTexSize = R128_DEFAULT_AGP_TEX_SIZE;
-
- info->CCEusecTimeout = R128_DEFAULT_CCE_TIMEOUT;
-
- if (!info->IsPCI) {
- if (xf86GetOptValInteger(info->Options,
- OPTION_AGP_MODE, &(info->agpMode))) {
- if (info->agpMode < 1 || info->agpMode > R128_AGP_MAX_MODE) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal AGP Mode: %d\n", info->agpMode);
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Using AGP %dx mode\n", info->agpMode);
- }
-
- if (xf86GetOptValInteger(info->Options,
- OPTION_AGP_SIZE, (int *)&(info->agpSize))) {
- switch (info->agpSize) {
- case 4:
- case 8:
- case 16:
- case 32:
- case 64:
- case 128:
- case 256:
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal AGP size: %d MB\n", info->agpSize);
- return FALSE;
- }
- }
-
- if (xf86GetOptValInteger(info->Options,
- OPTION_RING_SIZE, &(info->ringSize))) {
- if (info->ringSize < 1 || info->ringSize >= (int)info->agpSize) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal ring buffer size: %d MB\n",
- info->ringSize);
- return FALSE;
- }
- }
-
- if (xf86GetOptValInteger(info->Options,
- OPTION_BUFFER_SIZE, &(info->bufSize))) {
- if (info->bufSize < 1 || info->bufSize >= (int)info->agpSize) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
- return FALSE;
- }
- if (info->bufSize > 2) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Clamping vertex/indirect buffers size to 2 MB\n");
- info->bufSize = 2;
- }
- }
-
- if (info->ringSize + info->bufSize + info->agpTexSize >
- (int)info->agpSize) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Buffers are too big for requested AGP space\n");
- return FALSE;
- }
-
- info->agpTexSize = info->agpSize - (info->ringSize + info->bufSize);
- }
-
- if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT,
- &(info->CCEusecTimeout))) {
- /* This option checked by the R128 DRM kernel module */
- }
-
- if (!xf86LoadSubModule(pScrn, "shadowfb")) {
- info->allowPageFlip = 0;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't load shadowfb module:\n");
- } else {
- info->allowPageFlip = xf86ReturnOptValBool(info->Options,
- OPTION_PAGE_FLIP,
- FALSE);
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Page flipping %sabled\n",
- info->allowPageFlip ? "en" : "dis");
-
- return TRUE;
-}
-#endif
-
-static void
-R128ProbeDDC(ScrnInfoPtr pScrn, int indx)
-{
- vbeInfoPtr pVbe;
- if (xf86LoadSubModule(pScrn, "vbe")) {
- pVbe = VBEInit(NULL,indx);
- ConfiguredMonitor = vbeDoEDID(pVbe, NULL);
- vbeFree(pVbe);
- }
-}
-
-/* R128PreInit is called once at server startup. */
-Bool R128PreInit(ScrnInfoPtr pScrn, int flags)
-{
- R128InfoPtr info;
- xf86Int10InfoPtr pInt10 = NULL;
-
- R128TRACE(("R128PreInit\n"));
-
- if (pScrn->numEntities != 1) return FALSE;
-
- if (!R128GetRec(pScrn)) return FALSE;
-
- info = R128PTR(pScrn);
-
- info->IsSecondary = FALSE;
- info->IsPrimary = FALSE;
- info->SwitchingMode = FALSE;
-
- info->pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
- if (info->pEnt->location.type != BUS_PCI) goto fail;
-
- if(xf86IsEntityShared(pScrn->entityList[0]))
- {
- if(xf86IsPrimInitDone(pScrn->entityList[0]))
- {
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- info->IsSecondary = TRUE;
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
- if(pR128Ent->BypassSecondary) return FALSE;
- pR128Ent->pSecondaryScrn = pScrn;
- }
- else
- {
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- info->IsPrimary = TRUE;
- xf86SetPrimInitDone(pScrn->entityList[0]);
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
- pR128Ent->pPrimaryScrn = pScrn;
- pR128Ent->IsDRIEnabled = FALSE;
- pR128Ent->BypassSecondary = FALSE;
- pR128Ent->HasSecondary = FALSE;
- pR128Ent->RestorePrimary = FALSE;
- pR128Ent->IsSecondaryRestored = FALSE;
- }
- }
-
- if (flags & PROBE_DETECT) {
- R128ProbeDDC(pScrn, info->pEnt->index);
- return TRUE;
- }
-
- info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
- info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "PCI bus %d card %d func %d\n",
- PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
-
- if (xf86RegisterResources(info->pEnt->index, 0, ResNone)) goto fail;
- if (xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr)) goto fail;
-
- pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR;
- pScrn->monitor = pScrn->confScreen->monitor;
-
- if (!R128PreInitVisual(pScrn)) goto fail;
-
- /* We can't do this until we have a
- pScrn->display. */
- xf86CollectOptions(pScrn, NULL);
- if (!(info->Options = xalloc(sizeof(R128Options)))) goto fail;
- memcpy(info->Options, R128Options, sizeof(R128Options));
- xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
-
- /* By default, don't do VGA IOs on ppc */
-#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW)
- info->VGAAccess = FALSE;
-#else
- info->VGAAccess = TRUE;
-#endif
-
-#ifdef WITH_VGAHW
- xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess);
- if (info->VGAAccess) {
- if (!xf86LoadSubModule(pScrn, "vgahw"))
- info->VGAAccess = FALSE;
- else {
- if (!vgaHWGetHWRec(pScrn))
- info->VGAAccess = FALSE;
- }
- if (!info->VGAAccess)
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed,"
- " trying to run without it\n");
- } else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
- " VGA module load skipped\n");
- if (info->VGAAccess)
- vgaHWGetIOBase(VGAHWPTR(pScrn));
-#else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAHW support not compiled, VGA "
- "module load skipped\n");
-#endif
-
-
-
- if (!R128PreInitWeight(pScrn)) goto fail;
-
- if(xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, &(info->videoKey))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n",
- info->videoKey);
- } else {
- info->videoKey = 0x1E;
- }
-
- if (xf86ReturnOptValBool(info->Options, OPTION_SHOW_CACHE, FALSE)) {
- info->showCache = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShowCache enabled\n");
- }
-
-#ifdef __powerpc__
- if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, TRUE))
-#else
- if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, FALSE))
-#endif
- {
- info->FBDev = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Using framebuffer device\n");
- }
-
- if (info->FBDev) {
- /* check for linux framebuffer device */
- if (!xf86LoadSubModule(pScrn, "fbdevhw")) return FALSE;
- if (!fbdevHWInit(pScrn, info->PciInfo, NULL)) return FALSE;
- pScrn->SwitchMode = fbdevHWSwitchModeWeak();
- pScrn->AdjustFrame = fbdevHWAdjustFrameWeak();
- pScrn->ValidMode = fbdevHWValidModeWeak();
- }
-
- if (!info->FBDev)
- if (!R128PreInitInt10(pScrn, &pInt10)) goto fail;
-
- if (!R128PreInitConfig(pScrn)) goto fail;
-
- if (!R128GetBIOSParameters(pScrn, pInt10)) goto fail;
-
- if (!R128GetPLLParameters(pScrn)) goto fail;
-
- /* Don't fail on this one */
- R128PreInitDDC(pScrn, pInt10);
-
- if (!R128PreInitGamma(pScrn)) goto fail;
-
- if (!R128PreInitModes(pScrn)) goto fail;
-
- if (!R128PreInitCursor(pScrn)) goto fail;
-
- if (!R128PreInitAccel(pScrn)) goto fail;
-
-#ifdef XF86DRI
- if (!R128PreInitDRI(pScrn)) goto fail;
-#endif
-
- /* Free the video bios (if applicable) */
- if (info->VBIOS) {
- xfree(info->VBIOS);
- info->VBIOS = NULL;
- }
-
- /* Free int10 info */
- if (pInt10)
- xf86FreeInt10(pInt10);
-
- xf86DrvMsg(pScrn->scrnIndex, X_NOTICE,
- "For information on using the multimedia capabilities\n\tof this"
- " adapter, please see http://gatos.sf.net.\n");
-
- return TRUE;
-
- fail:
- /* Pre-init failed. */
-
- /* Free the video bios (if applicable) */
- if (info->VBIOS) {
- xfree(info->VBIOS);
- info->VBIOS = NULL;
- }
-
- /* Free int10 info */
- if (pInt10)
- xf86FreeInt10(pInt10);
-
-#ifdef WITH_VGAHW
- if (info->VGAAccess)
- vgaHWFreeHWRec(pScrn);
-#endif
- R128FreeRec(pScrn);
- return FALSE;
-}
-
-/* Load a palette. */
-static void R128LoadPalette(ScrnInfoPtr pScrn, int numColors,
- int *indices, LOCO *colors, VisualPtr pVisual)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i, j;
- int idx;
- unsigned char r, g, b;
-
- /* If the second monitor is connected, we also
- need to deal with the secondary palette*/
- if (info->IsSecondary) j = 1;
- else j = 0;
-
- PAL_SELECT(j);
-
-
- /* Select palette 0 (main CRTC) if using FP-enabled chip */
- /*if (info->HasPanelRegs || info->isDFP) PAL_SELECT(0);*/
-
- if (info->CurrentLayout.depth == 15) {
- /* 15bpp mode. This sends 32 values. */
- for (i = 0; i < numColors; i++) {
- idx = indices[i];
- r = colors[idx].red;
- g = colors[idx].green;
- b = colors[idx].blue;
- OUTPAL(idx * 8, r, g, b);
- }
- }
- else if (info->CurrentLayout.depth == 16) {
- /* 16bpp mode. This sends 64 values. */
- /* There are twice as many green values as
- there are values for red and blue. So,
- we take each red and blue pair, and
- combine it with each of the two green
- values. */
- for (i = 0; i < numColors; i++) {
- idx = indices[i];
- r = colors[idx / 2].red;
- g = colors[idx].green;
- b = colors[idx / 2].blue;
- OUTPAL(idx * 4, r, g, b);
- }
- }
- else {
- /* 8bpp mode. This sends 256 values. */
- for (i = 0; i < numColors; i++) {
- idx = indices[i];
- r = colors[idx].red;
- b = colors[idx].blue;
- g = colors[idx].green;
- OUTPAL(idx, r, g, b);
- }
- }
-}
-
-static void
-R128BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
-{
- ScreenPtr pScreen = screenInfo.screens[i];
- ScrnInfoPtr pScrn = xf86Screens[i];
- R128InfoPtr info = R128PTR(pScrn);
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled)
- FLUSH_RING();
-#endif
-
- pScreen->BlockHandler = info->BlockHandler;
- (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
- pScreen->BlockHandler = R128BlockHandler;
-
- if(info->VideoTimerCallback) {
- (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
- }
-}
-
-/* Called at the start of each server generation. */
-Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen,
- int argc, char **argv)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- BoxRec MemBox;
- int y2;
-
- R128TRACE(("R128ScreenInit %x %d\n", pScrn->memPhysBase, pScrn->fbOffset));
-
-#ifdef XF86DRI
- /* Turn off the CCE for now. */
- info->CCEInUse = FALSE;
- info->indirectBuffer = NULL;
-#endif
-
- if (!R128MapMem(pScrn)) return FALSE;
- pScrn->fbOffset = 0;
- if(info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
-#ifdef XF86DRI
- info->fbX = 0;
- info->fbY = 0;
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
-#endif
-
- info->PaletteSavedOnVT = FALSE;
-
- R128Save(pScrn);
- if (info->FBDev) {
- if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE;
- } else {
- if (!R128ModeInit(pScrn, pScrn->currentMode)) return FALSE;
- }
-
- R128SaveScreen(pScreen, SCREEN_SAVER_ON);
- pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
-
- /* Visual setup */
- miClearVisualTypes();
- if (!miSetVisualTypes(pScrn->depth,
- miGetDefaultVisualMask(pScrn->depth),
- pScrn->rgbBits,
- pScrn->defaultVisual)) return FALSE;
- miSetPixmapDepths ();
-
-#ifdef XF86DRI
- /* Setup DRI after visuals have been
- established, but before fbScreenInit is
- called. fbScreenInit will eventually
- call the driver's InitGLXVisuals call
- back. */
- {
- /* FIXME: When we move to dynamic allocation of back and depth
- buffers, we will want to revisit the following check for 3
- times the virtual size of the screen below. */
- int width_bytes = (pScrn->displayWidth *
- info->CurrentLayout.pixel_bytes);
- int maxy = info->FbMapSize / width_bytes;
-
- if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- xf86DrvMsg(scrnIndex, X_WARNING,
- "Acceleration disabled, not initializing the DRI\n");
- info->directRenderingEnabled = FALSE;
- } else if (maxy <= pScrn->virtualY * 3) {
- xf86DrvMsg(scrnIndex, X_WARNING,
- "Static buffer allocation failed -- "
- "need at least %d kB video memory\n",
- (pScrn->displayWidth * pScrn->virtualY *
- info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
- info->directRenderingEnabled = FALSE;
- } else {
- if(info->IsSecondary)
- info->directRenderingEnabled = FALSE;
- else
- {
- /* Xinerama has sync problem with DRI, disable it for now */
- if(xf86IsEntityShared(pScrn->entityList[0]))
- {
- info->directRenderingEnabled = FALSE;
- xf86DrvMsg(scrnIndex, X_WARNING,
- "Direct Rendering Disabled -- "
- "Dual-head configuration is not working with DRI "
- "at present.\nPlease use only one Device/Screen "
- "section in your XFConfig file.\n");
- }
- else
- info->directRenderingEnabled =
- R128DRIScreenInit(pScreen);
- if(xf86IsEntityShared(pScrn->entityList[0]))
- {
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
- pR128Ent->IsDRIEnabled = info->directRenderingEnabled;
- }
- }
- }
- }
-#endif
-
- if (!fbScreenInit (pScreen, info->FB,
- pScrn->virtualX, pScrn->virtualY,
- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
- pScrn->bitsPerPixel))
- return FALSE;
-
- xf86SetBlackWhitePixels(pScreen);
-
- if (pScrn->bitsPerPixel > 8) {
- VisualPtr visual;
-
- visual = pScreen->visuals + pScreen->numVisuals;
- while (--visual >= pScreen->visuals) {
- if ((visual->class | DynamicClass) == DirectColor) {
- visual->offsetRed = pScrn->offset.red;
- visual->offsetGreen = pScrn->offset.green;
- visual->offsetBlue = pScrn->offset.blue;
- visual->redMask = pScrn->mask.red;
- visual->greenMask = pScrn->mask.green;
- visual->blueMask = pScrn->mask.blue;
- }
- }
- }
-
- /* must be after RGB order fixed */
- fbPictureInit (pScreen, 0, 0);
-
- /* Memory manager setup */
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- FBAreaPtr fbarea;
- int width_bytes = (pScrn->displayWidth *
- info->CurrentLayout.pixel_bytes);
- int cpp = info->CurrentLayout.pixel_bytes;
- int bufferSize = pScrn->virtualY * width_bytes;
- int l, total;
- int scanlines;
-
- switch (info->CCEMode) {
- case R128_DEFAULT_CCE_PIO_MODE:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CCE in PIO mode\n");
- break;
- case R128_DEFAULT_CCE_BM_MODE:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CCE in BM mode\n");
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CCE in UNKNOWN mode\n");
- break;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB AGP aperture\n", info->agpSize);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for the ring buffer\n", info->ringSize);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for vertex/indirect buffers\n", info->bufSize);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for AGP textures\n", info->agpTexSize);
-
- /* Try for front, back, depth, and two framebuffers worth of
- * pixmap cache. Should be enough for a fullscreen background
- * image plus some leftovers.
- */
- info->textureSize = info->FbMapSize - 5 * bufferSize;
-
- /* If that gives us less than half the available memory, let's
- * be greedy and grab some more. Sorry, I care more about 3D
- * performance than playing nicely, and you'll get around a full
- * framebuffer's worth of pixmap cache anyway.
- */
- if (info->textureSize < (int)info->FbMapSize / 2) {
- info->textureSize = info->FbMapSize - 4 * bufferSize;
- }
-
- if (info->textureSize > 0) {
- l = R128MinBits((info->textureSize-1) / R128_NR_TEX_REGIONS);
- if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY;
-
- /* Round the texture size up to the nearest whole number of
- * texture regions. Again, be greedy about this, don't
- * round down.
- */
- info->log2TexGran = l;
- info->textureSize = (info->textureSize >> l) << l;
- } else {
- info->textureSize = 0;
- }
-
- /* Set a minimum usable local texture heap size. This will fit
- * two 256x256x32bpp textures.
- */
- if (info->textureSize < 512 * 1024) {
- info->textureOffset = 0;
- info->textureSize = 0;
- }
-
- total = info->FbMapSize - info->textureSize;
- scanlines = total / width_bytes;
- if (scanlines > 8191) scanlines = 8191;
-
- /* Recalculate the texture offset and size to accomodate any
- * rounding to a whole number of scanlines.
- */
- info->textureOffset = scanlines * width_bytes;
-
- MemBox.x1 = 0;
- MemBox.y1 = 0;
- MemBox.x2 = pScrn->displayWidth;
- MemBox.y2 = scanlines;
-
- if (!xf86InitFBManager(pScreen, &MemBox)) {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Memory manager initialization to (%d,%d) (%d,%d) failed\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- return FALSE;
- } else {
- int width, height;
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Memory manager initialized to (%d,%d) (%d,%d)\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- if ((fbarea = xf86AllocateOffscreenArea(pScreen,
- pScrn->displayWidth,
- 2, 0, NULL, NULL, NULL))) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved area from (%d,%d) to (%d,%d)\n",
- fbarea->box.x1, fbarea->box.y1,
- fbarea->box.x2, fbarea->box.y2);
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n");
- }
- if (xf86QueryLargestOffscreenArea(pScreen, &width,
- &height, 0, 0, 0)) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Largest offscreen area available: %d x %d\n",
- width, height);
- }
- }
-
- /* Allocate the shared back buffer */
- if ((fbarea = xf86AllocateOffscreenArea(pScreen,
- pScrn->virtualX,
- pScrn->virtualY,
- 32, NULL, NULL, NULL))) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved back buffer from (%d,%d) to (%d,%d)\n",
- fbarea->box.x1, fbarea->box.y1,
- fbarea->box.x2, fbarea->box.y2);
-
- info->backX = fbarea->box.x1;
- info->backY = fbarea->box.y1;
- info->backOffset = (fbarea->box.y1 * width_bytes +
- fbarea->box.x1 * cpp);
- info->backPitch = pScrn->displayWidth;
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve back buffer\n");
- info->backX = -1;
- info->backY = -1;
- info->backOffset = -1;
- info->backPitch = -1;
- }
-
- /* Allocate the shared depth buffer */
- if ((fbarea = xf86AllocateOffscreenArea(pScreen,
- pScrn->virtualX,
- pScrn->virtualY + 1,
- 32, NULL, NULL, NULL))) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved depth buffer from (%d,%d) to (%d,%d)\n",
- fbarea->box.x1, fbarea->box.y1,
- fbarea->box.x2, fbarea->box.y2);
-
- info->depthX = fbarea->box.x1;
- info->depthY = fbarea->box.y1;
- info->depthOffset = (fbarea->box.y1 * width_bytes +
- fbarea->box.x1 * cpp);
- info->depthPitch = pScrn->displayWidth;
- info->spanOffset = ((fbarea->box.y2 - 1) * width_bytes +
- fbarea->box.x1 * cpp);
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved depth span from (%d,%d) offset 0x%x\n",
- fbarea->box.x1, fbarea->box.y2 - 1, info->spanOffset);
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve depth buffer\n");
- info->depthX = -1;
- info->depthY = -1;
- info->depthOffset = -1;
- info->depthPitch = -1;
- info->spanOffset = -1;
- }
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved %d kb for textures at offset 0x%x\n",
- info->textureSize/1024, info->textureOffset);
- }
- else
-#endif
- {
- MemBox.x1 = 0;
- MemBox.y1 = 0;
- MemBox.x2 = pScrn->displayWidth;
- y2 = (info->FbMapSize
- / (pScrn->displayWidth *
- info->CurrentLayout.pixel_bytes));
- /* The acceleration engine uses 14 bit
- signed coordinates, so we can't have any
- drawable caches beyond this region. */
- if (y2 > 8191) y2 = 8191;
- MemBox.y2 = y2;
-
- if (!xf86InitFBManager(pScreen, &MemBox)) {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Memory manager initialization to (%d,%d) (%d,%d) failed\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- return FALSE;
- } else {
- int width, height;
- FBAreaPtr fbarea;
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Memory manager initialized to (%d,%d) (%d,%d)\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- if ((fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
- 2, 0, NULL, NULL, NULL))) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved area from (%d,%d) to (%d,%d)\n",
- fbarea->box.x1, fbarea->box.y1,
- fbarea->box.x2, fbarea->box.y2);
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n");
- }
- if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
- 0, 0, 0)) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Largest offscreen area available: %d x %d\n",
- width, height);
- }
- }
- }
-
- /* Acceleration setup */
- if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- if (R128AccelInit(pScreen)) {
- xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
- info->accelOn = TRUE;
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Acceleration initialization failed\n");
- xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
- info->accelOn = FALSE;
- }
- } else {
- xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
- info->accelOn = FALSE;
- }
-
- /* DGA setup */
- R128DGAInit(pScreen);
-
- /* Backing store setup */
- miInitializeBackingStore(pScreen);
- xf86SetBackingStore(pScreen);
-
- /* Set Silken Mouse */
- xf86SetSilkenMouse(pScreen);
-
- /* Cursor setup */
- miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
-
- /* Hardware cursor setup */
- if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
- if (R128CursorInit(pScreen)) {
- int width, height;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor (scanline %ld)\n",
- info->cursor_start / pScrn->displayWidth);
- if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
- 0, 0, 0)) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Largest offscreen area available: %d x %d\n",
- width, height);
- }
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Hardware cursor initialization failed\n");
- xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
- }
- } else {
- info->cursor_start = 0;
- xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
- }
-
- /* Colormap setup */
- if (!miCreateDefColormap(pScreen)) return FALSE;
- if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8,
- (info->FBDev ? fbdevHWLoadPaletteWeak() :
- R128LoadPalette), NULL,
- CMAP_PALETTED_TRUECOLOR
- | CMAP_RELOAD_ON_MODE_SWITCH
-#if 0 /* This option messes up text mode! (eich at suse.de) */
- | CMAP_LOAD_EVEN_IF_OFFSCREEN
-#endif
- )) return FALSE;
-
- /* DPMS setup - FIXME: also for mirror mode in non-fbdev case? - Michel */
- if (info->FBDev)
- xf86DPMSInit(pScreen, fbdevHWDPMSSetWeak(), 0);
-
- else {
- if (info->DisplayType == MT_LCD)
- xf86DPMSInit(pScreen, R128DisplayPowerManagementSetLCD, 0);
- else
- xf86DPMSInit(pScreen, R128DisplayPowerManagementSet, 0);
- }
-
- if (!info->IsSecondary)
- R128InitVideo(pScreen);
-
- /* Provide SaveScreen */
- pScreen->SaveScreen = R128SaveScreen;
-
- /* Wrap CloseScreen */
- info->CloseScreen = pScreen->CloseScreen;
- pScreen->CloseScreen = R128CloseScreen;
-
- /* Note unused options */
- if (serverGeneration == 1)
- xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
-
-#ifdef XF86DRI
- /* DRI finalization */
- if (info->directRenderingEnabled) {
- /* Now that mi, fb, drm and others have
- done their thing, complete the DRI
- setup. */
- info->directRenderingEnabled = R128DRIFinishScreenInit(pScreen);
- }
- if (info->directRenderingEnabled) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct rendering disabled\n");
- }
-#endif
-
- info->BlockHandler = pScreen->BlockHandler;
- pScreen->BlockHandler = R128BlockHandler;
-
- return TRUE;
-}
-
-/* Write common registers (initialized to 0). */
-static void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl | R128_FP_BLANK_DIS);
-
- OUTREG(R128_OVR_CLR, restore->ovr_clr);
- OUTREG(R128_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
- OUTREG(R128_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
- OUTREG(R128_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
- OUTREG(R128_MPP_TB_CONFIG, restore->mpp_tb_config );
- OUTREG(R128_MPP_GP_CONFIG, restore->mpp_gp_config );
- OUTREG(R128_SUBPIC_CNTL, restore->subpic_cntl);
- OUTREG(R128_VIPH_CONTROL, restore->viph_control);
- OUTREG(R128_I2C_CNTL_1, restore->i2c_cntl_1);
- OUTREG(R128_GEN_INT_CNTL, restore->gen_int_cntl);
- OUTREG(R128_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
- OUTREG(R128_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
- OUTREG(R128_BUS_CNTL, restore->bus_cntl);
- OUTREG(R128_CONFIG_CNTL, restore->config_cntl);
-}
-
-/* Write CRTC registers. */
-static void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
-
- OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
- R128_CRTC_VSYNC_DIS | R128_CRTC_HSYNC_DIS | R128_CRTC_DISPLAY_DIS);
-
- OUTREGP(R128_DAC_CNTL, restore->dac_cntl,
- R128_DAC_RANGE_CNTL | R128_DAC_BLANKING);
-
- OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
- OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
- OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
- OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
- OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
- OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
- OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
-}
-
-/* Write CRTC2 registers. */
-static void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn,
- R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREGP(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl,
- R128_CRTC2_DISP_DIS);
-
- OUTREG(R128_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
- OUTREG(R128_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
- OUTREG(R128_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
- OUTREG(R128_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
- OUTREG(R128_CRTC2_OFFSET, restore->crtc2_offset);
- OUTREG(R128_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
- OUTREG(R128_CRTC2_PITCH, restore->crtc2_pitch);
-}
-
-/* Write flat panel registers */
-static void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- CARD32 tmp;
-
- if (info->BIOSDisplay != R128_DUALHEAD)
- OUTREG(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
- OUTREG(R128_FP_HORZ_STRETCH, restore->fp_horz_stretch);
- OUTREG(R128_FP_VERT_STRETCH, restore->fp_vert_stretch);
- OUTREG(R128_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
- OUTREG(R128_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
- OUTREG(R128_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
- OUTREG(R128_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
- OUTREG(R128_TMDS_CRC, restore->tmds_crc);
- OUTREG(R128_FP_PANEL_CNTL, restore->fp_panel_cntl);
- OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl & ~(CARD32)R128_FP_BLANK_DIS);
-
- if(info->isDFP) return;
-
- tmp = INREG(R128_LVDS_GEN_CNTL);
- if ((tmp & (R128_LVDS_ON | R128_LVDS_BLON)) ==
- (restore->lvds_gen_cntl & (R128_LVDS_ON | R128_LVDS_BLON))) {
- OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
- } else {
- if (restore->lvds_gen_cntl & (R128_LVDS_ON | R128_LVDS_BLON)) {
- OUTREG(R128_LVDS_GEN_CNTL,
- restore->lvds_gen_cntl & (CARD32)~R128_LVDS_BLON);
- usleep(R128PTR(pScrn)->PanelPwrDly * 1000);
- OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
- } else {
- OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl | R128_LVDS_BLON);
- usleep(R128PTR(pScrn)->PanelPwrDly * 1000);
- OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
- }
- }
-}
-
-static void R128PLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
-{
- while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
-}
-
-static void R128PLLWriteUpdate(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
-
- OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W,
- ~R128_PPLL_ATOMIC_UPDATE_W);
-
-}
-
-static void R128PLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn)
-{
- while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
-}
-
-static void R128PLL2WriteUpdate(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
-
- OUTPLLP(pScrn, R128_P2PLL_REF_DIV,
- R128_P2PLL_ATOMIC_UPDATE_W,
- ~(R128_P2PLL_ATOMIC_UPDATE_W));
-}
-
-/* Write PLL registers. */
-static void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
-
- OUTPLLP(pScrn, R128_VCLK_ECP_CNTL,
- R128_VCLK_SRC_SEL_CPUCLK,
- ~(R128_VCLK_SRC_SEL_MASK));
-
- OUTPLLP(pScrn,
- R128_PPLL_CNTL,
- R128_PPLL_RESET
- | R128_PPLL_ATOMIC_UPDATE_EN
- | R128_PPLL_VGA_ATOMIC_UPDATE_EN,
- ~(R128_PPLL_RESET
- | R128_PPLL_ATOMIC_UPDATE_EN
- | R128_PPLL_VGA_ATOMIC_UPDATE_EN));
-
- OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, ~(R128_PLL_DIV_SEL));
-
-/* R128PLLWaitForReadUpdateComplete(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_REF_DIV,
- restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK);
-/* R128PLLWriteUpdate(pScrn);
-
- R128PLLWaitForReadUpdateComplete(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_DIV_3,
- restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK);
-/* R128PLLWriteUpdate(pScrn);*/
- OUTPLLP(pScrn, R128_PPLL_DIV_3,
- restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK);
-
- R128PLLWriteUpdate(pScrn);
- R128PLLWaitForReadUpdateComplete(pScrn);
-
- OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl);
-/* R128PLLWriteUpdate(pScrn);*/
-
- OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~(R128_PPLL_RESET
- | R128_PPLL_SLEEP
- | R128_PPLL_ATOMIC_UPDATE_EN
- | R128_PPLL_VGA_ATOMIC_UPDATE_EN));
-
- R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- restore->ppll_ref_div,
- restore->ppll_div_3,
- restore->htotal_cntl,
- INPLL(pScrn, R128_PPLL_CNTL)));
- R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
- restore->ppll_ref_div & R128_PPLL_REF_DIV_MASK,
- restore->ppll_div_3 & R128_PPLL_FB3_DIV_MASK,
- (restore->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16));
-
- usleep(5000); /* let the clock lock */
-
- OUTPLLP(pScrn, R128_VCLK_ECP_CNTL,
- R128_VCLK_SRC_SEL_PPLLCLK,
- ~(R128_VCLK_SRC_SEL_MASK));
-
-}
-
-/* Write PLL2 registers. */
-static void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
- R128_V2CLK_SRC_SEL_CPUCLK,
- ~R128_V2CLK_SRC_SEL_MASK);
-
- OUTPLLP(pScrn,
- R128_P2PLL_CNTL,
- R128_P2PLL_RESET
- | R128_P2PLL_ATOMIC_UPDATE_EN
- | R128_P2PLL_VGA_ATOMIC_UPDATE_EN,
- ~(R128_P2PLL_RESET
- | R128_P2PLL_ATOMIC_UPDATE_EN
- | R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
-
-#if 1
- OUTREGP(R128_CLOCK_CNTL_INDEX, 0, R128_PLL2_DIV_SEL_MASK);
-#endif
-
- /*R128PLL2WaitForReadUpdateComplete(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_REF_DIV, restore->p2pll_ref_div, ~R128_P2PLL_REF_DIV_MASK);
-
-/* R128PLL2WriteUpdate(pScrn);
- R128PLL2WaitForReadUpdateComplete(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_DIV_0,
- restore->p2pll_div_0, ~R128_P2PLL_FB0_DIV_MASK);
-
-/* R128PLL2WriteUpdate(pScrn);
- R128PLL2WaitForReadUpdateComplete(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_DIV_0,
- restore->p2pll_div_0, ~R128_P2PLL_POST0_DIV_MASK);
-
- R128PLL2WriteUpdate(pScrn);
- R128PLL2WaitForReadUpdateComplete(pScrn);
-
- OUTPLL(R128_HTOTAL2_CNTL, restore->htotal_cntl2);
-
-/* R128PLL2WriteUpdate(pScrn);*/
-
- OUTPLLP(pScrn, R128_P2PLL_CNTL, 0, ~(R128_P2PLL_RESET
- | R128_P2PLL_SLEEP
- | R128_P2PLL_ATOMIC_UPDATE_EN
- | R128_P2PLL_VGA_ATOMIC_UPDATE_EN));
-
- R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- restore->p2pll_ref_div,
- restore->p2pll_div_0,
- restore->htotal_cntl2,
- INPLL(pScrn, RADEON_P2PLL_CNTL)));
- R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n",
- restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- restore->p2pll_div_0 & RADEON_P2PLL_FB3_DIV_MASK,
- (restore->p2pll_div_0 & RADEON_P2PLL_POST3_DIV_MASK) >>16));
-
- usleep(5000); /* Let the clock to lock */
-
- OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL,
- R128_V2CLK_SRC_SEL_P2PLLCLK,
- ~R128_V2CLK_SRC_SEL_MASK);
-
-}
-
-/* Write DDA registers. */
-static void R128RestoreDDARegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG(R128_DDA_CONFIG, restore->dda_config);
- OUTREG(R128_DDA_ON_OFF, restore->dda_on_off);
-}
-
-/* Write DDA registers. */
-static void R128RestoreDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- OUTREG(R128_DDA2_CONFIG, restore->dda2_config);
- OUTREG(R128_DDA2_ON_OFF, restore->dda2_on_off);
-}
-
-/* Write palette data. */
-static void R128RestorePalette(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i;
-
- if (!restore->palette_valid) return;
-
- PAL_SELECT(1);
- OUTPAL_START(0);
- for (i = 0; i < 256; i++) {
- R128WaitForFifo(pScrn, 32); /* delay */
- OUTPAL_NEXT_CARD32(restore->palette2[i]);
- }
-
- PAL_SELECT(0);
- OUTPAL_START(0);
- for (i = 0; i < 256; i++) {
- R128WaitForFifo(pScrn, 32); /* delay */
- OUTPAL_NEXT_CARD32(restore->palette[i]);
- }
-
-}
-
-/* Write out state to define a new video mode. */
-static void R128RestoreMode(ScrnInfoPtr pScrn, R128SavePtr restore)
-{
- R128InfoPtr info = R128PTR(pScrn);
- DevUnion* pPriv;
- R128EntPtr pR128Ent;
- static R128SaveRec restore0;
-
- R128TRACE(("R128RestoreMode(%p)\n", restore));
- if(!info->HasCRTC2)
- {
- R128RestoreCommonRegisters(pScrn, restore);
- R128RestoreDDARegisters(pScrn, restore);
- R128RestoreCrtcRegisters(pScrn, restore);
- if((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD))
- {
- R128RestoreFPRegisters(pScrn, restore);
- }
- R128RestorePLLRegisters(pScrn, restore);
- return;
- }
-
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getR128EntityIndex());
- pR128Ent = pPriv->ptr;
-
-
- /*****
- When changing mode with Dual-head card (VE/M6), care must
- be taken for the special order in setting registers. CRTC2 has
- to be set before changing CRTC_EXT register.
- In the dual-head setup, X server calls this routine twice with
- primary and secondary pScrn pointers respectively. The calls
- can come with different order. Regardless the order of X server issuing
- the calls, we have to ensure we set registers in the right order!!!
- Otherwise we may get a blank screen.
- *****/
-
- if(info->IsSecondary)
- {
- if (!pR128Ent->RestorePrimary && !info->SwitchingMode)
- R128RestoreCommonRegisters(pScrn, restore);
- R128RestoreDDA2Registers(pScrn, restore);
- R128RestoreCrtc2Registers(pScrn, restore);
- R128RestorePLL2Registers(pScrn, restore);
-
- if(info->SwitchingMode) return;
-
- pR128Ent->IsSecondaryRestored = TRUE;
-
- if(pR128Ent->RestorePrimary)
- {
- R128InfoPtr info0 = R128PTR(pR128Ent->pPrimaryScrn);
- pR128Ent->RestorePrimary = FALSE;
-
- R128RestoreCrtcRegisters(pScrn, &restore0);
- if((info0->DisplayType == MT_DFP) ||
- (info0->DisplayType == MT_LCD))
- {
- R128RestoreFPRegisters(pScrn, &restore0);
- }
-
- R128RestorePLLRegisters(pScrn, &restore0);
- pR128Ent->IsSecondaryRestored = FALSE;
-
- }
- }
- else
- {
- if (!pR128Ent->IsSecondaryRestored)
- R128RestoreCommonRegisters(pScrn, restore);
- R128RestoreDDARegisters(pScrn, restore);
- if(!pR128Ent->HasSecondary || pR128Ent->IsSecondaryRestored
- || info->SwitchingMode)
- {
- pR128Ent->IsSecondaryRestored = FALSE;
- R128RestoreCrtcRegisters(pScrn, restore);
- if((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD))
- {
- R128RestoreFPRegisters(pScrn, restore);
- }
- R128RestorePLLRegisters(pScrn, restore);
- }
- else
- {
- memcpy(&restore0, restore, sizeof(restore0));
- pR128Ent->RestorePrimary = TRUE;
- }
- }
-
- R128RestorePalette(pScrn, restore);
-}
-
-/* Read common registers. */
-static void R128SaveCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- save->ovr_clr = INREG(R128_OVR_CLR);
- save->ovr_wid_left_right = INREG(R128_OVR_WID_LEFT_RIGHT);
- save->ovr_wid_top_bottom = INREG(R128_OVR_WID_TOP_BOTTOM);
- save->ov0_scale_cntl = INREG(R128_OV0_SCALE_CNTL);
- save->mpp_tb_config = INREG(R128_MPP_TB_CONFIG);
- save->mpp_gp_config = INREG(R128_MPP_GP_CONFIG);
- save->subpic_cntl = INREG(R128_SUBPIC_CNTL);
- save->viph_control = INREG(R128_VIPH_CONTROL);
- save->i2c_cntl_1 = INREG(R128_I2C_CNTL_1);
- save->gen_int_cntl = INREG(R128_GEN_INT_CNTL);
- save->cap0_trig_cntl = INREG(R128_CAP0_TRIG_CNTL);
- save->cap1_trig_cntl = INREG(R128_CAP1_TRIG_CNTL);
- save->bus_cntl = INREG(R128_BUS_CNTL);
- save->config_cntl = INREG(R128_CONFIG_CNTL);
-}
-
-/* Read CRTC registers. */
-static void R128SaveCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- save->crtc_gen_cntl = INREG(R128_CRTC_GEN_CNTL);
- save->crtc_ext_cntl = INREG(R128_CRTC_EXT_CNTL);
- save->dac_cntl = INREG(R128_DAC_CNTL);
- save->crtc_h_total_disp = INREG(R128_CRTC_H_TOTAL_DISP);
- save->crtc_h_sync_strt_wid = INREG(R128_CRTC_H_SYNC_STRT_WID);
- save->crtc_v_total_disp = INREG(R128_CRTC_V_TOTAL_DISP);
- save->crtc_v_sync_strt_wid = INREG(R128_CRTC_V_SYNC_STRT_WID);
- save->crtc_offset = INREG(R128_CRTC_OFFSET);
- save->crtc_offset_cntl = INREG(R128_CRTC_OFFSET_CNTL);
- save->crtc_pitch = INREG(R128_CRTC_PITCH);
-}
-
-/* Read flat panel registers */
-static void R128SaveFPRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- if (info->BIOSDisplay != R128_DUALHEAD)
- save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL);
- save->fp_crtc_h_total_disp = INREG(R128_FP_CRTC_H_TOTAL_DISP);
- save->fp_crtc_v_total_disp = INREG(R128_FP_CRTC_V_TOTAL_DISP);
- save->fp_gen_cntl = INREG(R128_FP_GEN_CNTL);
- save->fp_h_sync_strt_wid = INREG(R128_FP_H_SYNC_STRT_WID);
- save->fp_horz_stretch = INREG(R128_FP_HORZ_STRETCH);
- save->fp_panel_cntl = INREG(R128_FP_PANEL_CNTL);
- save->fp_v_sync_strt_wid = INREG(R128_FP_V_SYNC_STRT_WID);
- save->fp_vert_stretch = INREG(R128_FP_VERT_STRETCH);
- save->lvds_gen_cntl = INREG(R128_LVDS_GEN_CNTL);
- save->tmds_crc = INREG(R128_TMDS_CRC);
- save->tmds_transmitter_cntl = INREG(R128_TMDS_TRANSMITTER_CNTL);
-}
-
-/* Read CRTC2 registers. */
-static void R128SaveCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL);
- save->crtc2_h_total_disp = INREG(R128_CRTC2_H_TOTAL_DISP);
- save->crtc2_h_sync_strt_wid = INREG(R128_CRTC2_H_SYNC_STRT_WID);
- save->crtc2_v_total_disp = INREG(R128_CRTC2_V_TOTAL_DISP);
- save->crtc2_v_sync_strt_wid = INREG(R128_CRTC2_V_SYNC_STRT_WID);
- save->crtc2_offset = INREG(R128_CRTC2_OFFSET);
- save->crtc2_offset_cntl = INREG(R128_CRTC2_OFFSET_CNTL);
- save->crtc2_pitch = INREG(R128_CRTC2_PITCH);
-}
-
-/* Read PLL registers. */
-static void R128SavePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- save->ppll_ref_div = INPLL(pScrn, R128_PPLL_REF_DIV);
- save->ppll_div_3 = INPLL(pScrn, R128_PPLL_DIV_3);
- save->htotal_cntl = INPLL(pScrn, R128_HTOTAL_CNTL);
-
- R128TRACE(("Read: 0x%08x 0x%08x 0x%08x\n",
- save->ppll_ref_div,
- save->ppll_div_3,
- save->htotal_cntl));
- R128TRACE(("Read: rd=%d, fd=%d, pd=%d\n",
- save->ppll_ref_div & R128_PPLL_REF_DIV_MASK,
- save->ppll_div_3 & R128_PPLL_FB3_DIV_MASK,
- (save->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16));
-}
-
-/* Read PLL2 registers. */
-static void R128SavePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- save->p2pll_ref_div = INPLL(pScrn, R128_P2PLL_REF_DIV);
- save->p2pll_div_0 = INPLL(pScrn, R128_P2PLL_DIV_0);
- save->htotal_cntl2 = INPLL(pScrn, R128_HTOTAL2_CNTL);
-
- R128TRACE(("Read: 0x%08x 0x%08x 0x%08x\n",
- save->p2pll_ref_div,
- save->p2pll_div_0,
- save->htotal_cntl2));
- R128TRACE(("Read: rd=%d, fd=%d, pd=%d\n",
- save->p2pll_ref_div & R128_P2PLL_REF_DIV_MASK,
- save->p2pll_div_0 & R128_P2PLL_FB0_DIV_MASK,
- (save->p2pll_div_0 & R128_P2PLL_POST0_DIV_MASK) >> 16));
-}
-
-/* Read DDA registers. */
-static void R128SaveDDARegisters(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- save->dda_config = INREG(R128_DDA_CONFIG);
- save->dda_on_off = INREG(R128_DDA_ON_OFF);
-}
-
-/* Read DDA2 registers. */
-static void R128SaveDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
-
- save->dda2_config = INREG(R128_DDA2_CONFIG);
- save->dda2_on_off = INREG(R128_DDA2_ON_OFF);
-}
-
-/* Read palette data. */
-static void R128SavePalette(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int i;
-
- PAL_SELECT(1);
- INPAL_START(0);
- for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT();
- PAL_SELECT(0);
- INPAL_START(0);
- for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT();
- save->palette_valid = TRUE;
-}
-
-/* Save state that defines current video mode. */
-static void R128SaveMode(ScrnInfoPtr pScrn, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- R128TRACE(("R128SaveMode(%p)\n", save));
-
- if(info->IsSecondary)
- {
- R128SaveCrtc2Registers(pScrn, save);
- R128SavePLL2Registers(pScrn, save);
- R128SaveDDA2Registers(pScrn, save);
- }
- else
- {
- R128SaveCommonRegisters(pScrn, save);
- R128SaveCrtcRegisters(pScrn, save);
- if((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD))
- {
- R128SaveFPRegisters(pScrn, save);
- }
- R128SavePLLRegisters(pScrn, save);
- R128SaveDDARegisters(pScrn, save);
- R128SavePalette(pScrn, save);
- }
-
- R128TRACE(("R128SaveMode returns %p\n", save));
-}
-
-/* Save everything needed to restore the original VC state. */
-static void R128Save(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128SavePtr save = &info->SavedReg;
-
- R128TRACE(("R128Save\n"));
- if (info->FBDev) {
- fbdevHWSave(pScrn);
- return;
- }
-
- if (!info->IsSecondary) {
-#ifdef WITH_VGAHW
- if (info->VGAAccess) {
- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- vgaHWUnlock(hwp);
-# if defined(__powerpc__)
- /* temporary hack to prevent crashing on PowerMacs when trying to
- * read VGA fonts and colormap, will find a better solution
- * in the future. TODO: Check if there's actually some VGA stuff
- * setup in the card at all !!
- */
- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
-# else
- /* Save mode * & fonts & cmap */
- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS);
-# endif
- vgaHWLock(hwp);
- }
-#endif
-
- save->dp_datatype = INREG(R128_DP_DATATYPE);
- save->gen_reset_cntl = INREG(R128_GEN_RESET_CNTL);
- save->clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX);
- save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG);
- save->amcgpio_mask = INREG(R128_AMCGPIO_MASK);
- }
-
- R128SaveMode(pScrn, save);
-
-}
-
-/* Restore the original (text) mode. */
-static void R128Restore(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128SavePtr restore = &info->SavedReg;
-
- R128TRACE(("R128Restore\n"));
- if (info->FBDev) {
- fbdevHWRestore(pScrn);
- return;
- }
-
- R128Blank(pScrn);
-
- if (!info->IsSecondary) {
- OUTREG(R128_AMCGPIO_MASK, restore->amcgpio_mask);
- OUTREG(R128_AMCGPIO_EN_REG, restore->amcgpio_en_reg);
- OUTREG(R128_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
- OUTREG(R128_GEN_RESET_CNTL, restore->gen_reset_cntl);
- OUTREG(R128_DP_DATATYPE, restore->dp_datatype);
- }
-
- R128RestoreMode(pScrn, restore);
-#ifdef WITH_VGAHW
- if (info->VGAAccess) {
- vgaHWPtr hwp = VGAHWPTR(pScrn);
- if (!info->IsSecondary) {
- vgaHWUnlock(hwp);
-# if defined(__powerpc__)
- /* Temporary hack to prevent crashing on PowerMacs when trying to
- * write VGA fonts, will find a better solution in the future
- */
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
-# else
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-# endif
- vgaHWLock(hwp);
- } else {
- R128EntPtr pR128Ent = R128EntPriv(pScrn);
- ScrnInfoPtr pScrn0 = pR128Ent->pPrimaryScrn;
- R128InfoPtr info0 = R128PTR(pScrn0);
- vgaHWPtr hwp0;
-
- if (info0->VGAAccess) {
- hwp0 = VGAHWPTR(pScrn0);
- vgaHWUnlock(hwp0);
-#if defined(__powerpc__)
- vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE);
-#else
- vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-#endif
- vgaHWLock(hwp0);
- }
- }
- }
-#endif
-
- R128WaitForVerticalSync(pScrn);
- R128Unblank(pScrn);
-}
-
-/* Define common registers for requested video mode. */
-static void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info)
-{
- save->ovr_clr = 0;
- save->ovr_wid_left_right = 0;
- save->ovr_wid_top_bottom = 0;
- save->ov0_scale_cntl = 0;
- save->mpp_tb_config = 0;
- save->mpp_gp_config = 0;
- save->subpic_cntl = 0;
- save->viph_control = 0;
- save->i2c_cntl_1 = 0;
-#ifdef XF86DRI
- save->gen_int_cntl = info->gen_int_cntl;
-#else
- save->gen_int_cntl = 0;
-#endif
- save->cap0_trig_cntl = 0;
- save->cap1_trig_cntl = 0;
- save->bus_cntl = info->BusCntl;
- /*
- * If bursts are enabled, turn on discards and aborts
- */
- if (save->bus_cntl & (R128_BUS_WRT_BURST|R128_BUS_READ_BURST))
- save->bus_cntl |= R128_BUS_RD_DISCARD_EN | R128_BUS_RD_ABORT_EN;
-}
-
-/* Define CRTC registers for requested video mode. */
-static Bool R128InitCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr save,
- DisplayModePtr mode, R128InfoPtr info)
-{
- int format;
- int hsync_start;
- int hsync_wid;
- int hsync_fudge;
- int vsync_wid;
- int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
- int hsync_fudge_fp[] = { 0x12, 0x11, 0x09, 0x09, 0x05, 0x05 };
-// int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 };
-
- switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; break;
- case 8: format = 2; break;
- case 15: format = 3; break; /* 555 */
- case 16: format = 4; break; /* 565 */
- case 24: format = 5; break; /* RGB */
- case 32: format = 6; break; /* xRGB */
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Unsupported pixel depth (%d)\n",
- info->CurrentLayout.bitsPerPixel);
- return FALSE;
- }
-
- if ((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD))
- hsync_fudge = hsync_fudge_fp[format-1];
- else
- hsync_fudge = hsync_fudge_default[format-1];
-
- save->crtc_gen_cntl = (R128_CRTC_EXT_DISP_EN
- | R128_CRTC_EN
- | (format << 8)
- | ((mode->Flags & V_DBLSCAN)
- ? R128_CRTC_DBL_SCAN_EN
- : 0)
- | ((mode->Flags & V_INTERLACE)
- ? R128_CRTC_INTERLACE_EN
- : 0)
- | ((mode->Flags & V_CSYNC)
- ? R128_CRTC_CSYNC_EN
- : 0));
-
- if((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD))
- {
- save->crtc_ext_cntl = R128_VGA_ATI_LINEAR |
- R128_XCRT_CNT_EN;
- save->crtc_gen_cntl &= ~(R128_CRTC_DBL_SCAN_EN |
- R128_CRTC_INTERLACE_EN);
- }
- else
- save->crtc_ext_cntl = R128_VGA_ATI_LINEAR |
- R128_XCRT_CNT_EN |
- R128_CRTC_CRT_ON;
-
- save->dac_cntl = (R128_DAC_MASK_ALL
- | R128_DAC_VGA_ADR_EN
- | (info->dac6bits ? 0 : R128_DAC_8BIT_EN));
-
-
- if(info->isDFP && !info->isPro2)
- {
- if(info->PanelXRes < mode->CrtcHDisplay)
- mode->HDisplay = mode->CrtcHDisplay = info->PanelXRes;
- if(info->PanelYRes < mode->CrtcVDisplay)
- mode->VDisplay = mode->CrtcVDisplay = info->PanelYRes;
- mode->CrtcHTotal = mode->CrtcHDisplay + info->HBlank;
- mode->CrtcHSyncStart = mode->CrtcHDisplay + info->HOverPlus;
- mode->CrtcHSyncEnd = mode->CrtcHSyncStart + info->HSyncWidth;
- mode->CrtcVTotal = mode->CrtcVDisplay + info->VBlank;
- mode->CrtcVSyncStart = mode->CrtcVDisplay + info->VOverPlus;
- mode->CrtcVSyncEnd = mode->CrtcVSyncStart + info->VSyncWidth;
- }
-
- save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff)
- | (((mode->CrtcHDisplay / 8) - 1) << 16));
-
- hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
- if (!hsync_wid) hsync_wid = 1;
- if (hsync_wid > 0x3f) hsync_wid = 0x3f;
-
- hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge;
-
- save->crtc_h_sync_strt_wid = ((hsync_start & 0xfff)
- | (hsync_wid << 16)
- | ((mode->Flags & V_NHSYNC)
- ? R128_CRTC_H_SYNC_POL
- : 0));
-
-#if 1
- /* This works for double scan mode. */
- save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay - 1) << 16));
-#else
- /* This is what cce/nbmode.c example code
- does -- is this correct? */
- save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay
- * ((mode->Flags & V_DBLSCAN) ? 2 : 1) - 1)
- << 16));
-#endif
-
- vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
- if (!vsync_wid) vsync_wid = 1;
- if (vsync_wid > 0x1f) vsync_wid = 0x1f;
-
- save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
- | (vsync_wid << 16)
- | ((mode->Flags & V_NVSYNC)
- ? R128_CRTC_V_SYNC_POL
- : 0));
- save->crtc_offset = 0;
- save->crtc_offset_cntl = 0;
- save->crtc_pitch = info->CurrentLayout.displayWidth / 8;
-
- R128TRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n",
- save->crtc_pitch, pScrn->virtualX, info->CurrentLayout.displayWidth));
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* Change the endianness of the aperture */
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: save->config_cntl |= APER_0_BIG_ENDIAN_16BPP_SWAP; break;
- case 32: save->config_cntl |= APER_0_BIG_ENDIAN_32BPP_SWAP; break;
- default: break;
- }
-#endif
-
- return TRUE;
-}
-
-/* Define CRTC2 registers for requested video mode. */
-static Bool R128InitCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr save,
- DisplayModePtr mode, R128InfoPtr info)
-{
- int format;
- int hsync_start;
- int hsync_wid;
- int hsync_fudge;
- int vsync_wid;
- int bytpp;
- int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
-
- switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; bytpp = 0; break;
- case 8: format = 2; bytpp = 1; break;
- case 15: format = 3; bytpp = 2; break; /* 555 */
- case 16: format = 4; bytpp = 2; break; /* 565 */
- case 24: format = 5; bytpp = 3; break; /* RGB */
- case 32: format = 6; bytpp = 4; break; /* xRGB */
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel);
- return FALSE;
- }
- R128TRACE(("Format = %d (%d bytes per pixel)\n", format, bytpp));
-
- hsync_fudge = hsync_fudge_default[format-1];
-
- save->crtc2_gen_cntl = (R128_CRTC2_EN
- | (format << 8)
- | ((mode->Flags & V_DBLSCAN)
- ? R128_CRTC2_DBL_SCAN_EN
- : 0));
-/*
- save->crtc2_gen_cntl &= ~R128_CRTC_EXT_DISP_EN;
- save->crtc2_gen_cntl |= (1 << 21);
-*/
- save->crtc2_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff)
- | (((mode->CrtcHDisplay / 8) - 1) << 16));
-
- hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
- if (!hsync_wid) hsync_wid = 1;
- if (hsync_wid > 0x3f) hsync_wid = 0x3f;
-
- hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge;
-
- save->crtc2_h_sync_strt_wid = ((hsync_start & 0xfff)
- | (hsync_wid << 16)
- | ((mode->Flags & V_NHSYNC)
- ? R128_CRTC2_H_SYNC_POL
- : 0));
-
-#if 1
- /* This works for double scan mode. */
- save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay - 1) << 16));
-#else
- /* This is what cce/nbmode.c example code
- does -- is this correct? */
- save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay
- * ((mode->Flags & V_DBLSCAN) ? 2 : 1) - 1)
- << 16));
-#endif
-
- vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
- if (!vsync_wid) vsync_wid = 1;
- if (vsync_wid > 0x1f) vsync_wid = 0x1f;
-
- save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
- | (vsync_wid << 16)
- | ((mode->Flags & V_NVSYNC)
- ? R128_CRTC2_V_SYNC_POL
- : 0));
-
- save->crtc2_offset = 0;
- save->crtc2_offset_cntl = 0;
-
- save->crtc2_pitch = info->CurrentLayout.displayWidth / 8;
-
- R128TRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n",
- save->crtc2_pitch, pScrn->virtualX,
- info->CurrentLayout.displayWidth));
- return TRUE;
-}
-
-/* Define CRTC registers for requested video mode. */
-static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save,
- DisplayModePtr mode, R128InfoPtr info)
-{
- int xres = mode->CrtcHDisplay;
- int yres = mode->CrtcVDisplay;
- float Hratio, Vratio;
-
- if (info->BIOSDisplay == R128_BIOS_DISPLAY_CRT) {
- save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
- save->crtc2_gen_cntl = 0;
- save->fp_gen_cntl = orig->fp_gen_cntl;
- save->fp_gen_cntl &= ~(R128_FP_FPON |
- R128_FP_CRTC_USE_SHADOW_VEND |
- R128_FP_CRTC_HORZ_DIV2_EN |
- R128_FP_CRTC_HOR_CRT_DIV2_DIS |
- R128_FP_USE_SHADOW_EN);
- save->fp_gen_cntl |= (R128_FP_SEL_CRTC2 |
- R128_FP_CRTC_DONT_SHADOW_VPAR);
- save->fp_panel_cntl = orig->fp_panel_cntl & (CARD32)~R128_FP_DIGON;
- save->lvds_gen_cntl = orig->lvds_gen_cntl &
- (CARD32)~(R128_LVDS_ON | R128_LVDS_BLON);
- return;
- }
-
- if (xres > info->PanelXRes) xres = info->PanelXRes;
- if (yres > info->PanelYRes) yres = info->PanelYRes;
-
- Hratio = (float)xres/(float)info->PanelXRes;
- Vratio = (float)yres/(float)info->PanelYRes;
-
- save->fp_horz_stretch =
- (((((int)(Hratio * R128_HORZ_STRETCH_RATIO_MAX + 0.5))
- & R128_HORZ_STRETCH_RATIO_MASK) << R128_HORZ_STRETCH_RATIO_SHIFT) |
- (orig->fp_horz_stretch & (R128_HORZ_PANEL_SIZE |
- R128_HORZ_FP_LOOP_STRETCH |
- R128_HORZ_STRETCH_RESERVED)));
- save->fp_horz_stretch &= ~R128_HORZ_AUTO_RATIO_FIX_EN;
- save->fp_horz_stretch &= ~R128_AUTO_HORZ_RATIO;
- if (xres == info->PanelXRes)
- save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE);
- else
- save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE);
-
- save->fp_vert_stretch =
- (((((int)(Vratio * R128_VERT_STRETCH_RATIO_MAX + 0.5))
- & R128_VERT_STRETCH_RATIO_MASK) << R128_VERT_STRETCH_RATIO_SHIFT) |
- (orig->fp_vert_stretch & (R128_VERT_PANEL_SIZE |
- R128_VERT_STRETCH_RESERVED)));
- save->fp_vert_stretch &= ~R128_VERT_AUTO_RATIO_EN;
- if (yres == info->PanelYRes)
- save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND);
- else
- save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND);
-
- save->fp_gen_cntl = (orig->fp_gen_cntl &
- (CARD32)~(R128_FP_SEL_CRTC2 |
- R128_FP_CRTC_USE_SHADOW_VEND |
- R128_FP_CRTC_HORZ_DIV2_EN |
- R128_FP_CRTC_HOR_CRT_DIV2_DIS |
- R128_FP_USE_SHADOW_EN));
-
- save->fp_panel_cntl = orig->fp_panel_cntl;
- save->lvds_gen_cntl = orig->lvds_gen_cntl;
- save->tmds_crc = orig->tmds_crc;
-
- /* Disable CRT output by disabling CRT output and setting the CRT
- DAC to use CRTC2, which we set to 0's. In the future, we will
- want to use the dual CRTC capabilities of the R128 to allow both
- the flat panel and external CRT to either simultaneously display
- the same image or display two different images. */
-
-
- if(!info->isDFP){
- if (info->BIOSDisplay == R128_BIOS_DISPLAY_FP_CRT) {
- save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
- } else if (info->BIOSDisplay == R128_DUALHEAD) {
- save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
- save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
- save->dac_cntl |= R128_DAC_PALETTE2_SNOOP_EN;
- } else {
- save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON;
- save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
- save->crtc2_gen_cntl = 0;
- }
- }
-
- /* WARNING: Be careful about turning on the flat panel */
- if(info->isDFP){
- save->fp_gen_cntl = orig->fp_gen_cntl;
-
- save->fp_gen_cntl &= ~(R128_FP_CRTC_USE_SHADOW_VEND |
- R128_FP_CRTC_USE_SHADOW_ROWCUR |
- R128_FP_CRTC_HORZ_DIV2_EN |
- R128_FP_CRTC_HOR_CRT_DIV2_DIS |
- R128_FP_CRT_SYNC_SEL |
- R128_FP_USE_SHADOW_EN);
-
- save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON);
- save->fp_gen_cntl |= (R128_FP_FPON | R128_FP_TDMS_EN |
- R128_FP_CRTC_DONT_SHADOW_VPAR | R128_FP_CRTC_DONT_SHADOW_HEND);
- save->tmds_transmitter_cntl = (orig->tmds_transmitter_cntl
- & ~(CARD32)R128_TMDS_PLLRST) | R128_TMDS_PLLEN;
- }
- else
- save->lvds_gen_cntl |= (R128_LVDS_ON | R128_LVDS_BLON);
-
- save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
- save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
- save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
- save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
-}
-
-/* Define PLL registers for requested video mode. */
-static void R128InitPLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save,
- R128PLLPtr pll, double dot_clock)
-{
- unsigned long freq = dot_clock * 100;
- struct {
- int divider;
- int bitvalue;
- } *post_div,
- post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- Reference Manual (Technical Reference
- Manual P/N RRG-G04100-C Rev. 0.04), page
- 3-17 (PLL_DIV_[3:0]). */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
-
- { 3, 4 }, /* VCLK_SRC/3 */
- /* bitvalue = 5 is reserved */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- save->pll_output_freq = post_div->divider * freq;
- if (save->pll_output_freq >= pll->min_pll_freq
- && save->pll_output_freq <= pll->max_pll_freq) break;
- }
-
- save->dot_clock_freq = freq;
- save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
- pll->reference_freq);
- save->post_div = post_div->divider;
-
- R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
- save->dot_clock_freq,
- save->pll_output_freq,
- save->feedback_div,
- save->post_div));
-
- save->ppll_ref_div = pll->reference_div;
- save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
- save->htotal_cntl = 0;
-
-}
-
-/* Define PLL2 registers for requested video mode. */
-static void R128InitPLL2Registers(R128SavePtr save, R128PLLPtr pll,
- double dot_clock)
-{
- unsigned long freq = dot_clock * 100;
- struct {
- int divider;
- int bitvalue;
- } *post_div,
- post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- Reference Manual (Technical Reference
- Manual P/N RRG-G04100-C Rev. 0.04), page
- 3-17 (PLL_DIV_[3:0]). */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
-
- { 3, 4 }, /* VCLK_SRC/3 */
- /* bitvalue = 5 is reserved */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- save->pll_output_freq_2 = post_div->divider * freq;
- if (save->pll_output_freq_2 >= pll->min_pll_freq
- && save->pll_output_freq_2 <= pll->max_pll_freq) break;
- }
-
- save->dot_clock_freq_2 = freq;
- save->feedback_div_2 = R128Div(pll->reference_div
- * save->pll_output_freq_2,
- pll->reference_freq);
- save->post_div_2 = post_div->divider;
-
- R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n",
- save->dot_clock_freq_2,
- save->pll_output_freq_2,
- save->feedback_div_2,
- save->post_div_2));
-
- save->p2pll_ref_div = pll->reference_div;
- save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
- save->htotal_cntl2 = 0;
-}
-
-/* Define DDA registers for requested video mode. */
-static Bool R128InitDDARegisters(ScrnInfoPtr pScrn, R128SavePtr save,
- R128PLLPtr pll, R128InfoPtr info,
- DisplayModePtr mode)
-{
- int DisplayFifoWidth = 128;
- int DisplayFifoDepth = 32;
- int XclkFreq;
- int VclkFreq;
- int XclksPerTransfer;
- int XclksPerTransferPrecise;
- int UseablePrecision;
- int Roff;
- int Ron;
-
- XclkFreq = pll->xclk;
-
- VclkFreq = R128Div(pll->reference_freq * save->feedback_div,
- pll->reference_div * save->post_div);
-
- if(info->isDFP && !info->isPro2){
- if(info->PanelXRes != mode->CrtcHDisplay)
- VclkFreq = (VclkFreq * mode->CrtcHDisplay)/info->PanelXRes;
- }
-
- XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
-
- XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
- << (11 - UseablePrecision),
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
-
- Ron = (4 * info->ram->MB
- + 3 * MAX(info->ram->Trcd - 2, 0)
- + 2 * info->ram->Trp
- + info->ram->Twr
- + info->ram->CL
- + info->ram->Tr2w
- + XclksPerTransfer) << (11 - UseablePrecision);
-
- if (Ron + info->ram->Rloop >= Roff) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n",
- Ron, info->ram->Rloop, Roff);
- return FALSE;
- }
-
- save->dda_config = (XclksPerTransferPrecise
- | (UseablePrecision << 16)
- | (info->ram->Rloop << 20));
-
- save->dda_on_off = (Ron << 16) | Roff;
-
- R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n",
- XclkFreq,
- VclkFreq,
- XclksPerTransfer,
- XclksPerTransferPrecise,
- UseablePrecision));
- R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n",
- Roff, Ron, info->ram->Rloop));
-
- return TRUE;
-}
-
-/* Define DDA2 registers for requested video mode. */
-static Bool R128InitDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr save,
- R128PLLPtr pll, R128InfoPtr info,
- DisplayModePtr mode)
-{
- int DisplayFifoWidth = 128;
- int DisplayFifoDepth = 32;
- int XclkFreq;
- int VclkFreq;
- int XclksPerTransfer;
- int XclksPerTransferPrecise;
- int UseablePrecision;
- int Roff;
- int Ron;
-
- XclkFreq = pll->xclk;
-
- VclkFreq = R128Div(pll->reference_freq * save->feedback_div_2,
- pll->reference_div * save->post_div_2);
-
- if(info->isDFP && !info->isPro2){
- if(info->PanelXRes != mode->CrtcHDisplay)
- VclkFreq = (VclkFreq * mode->CrtcHDisplay)/info->PanelXRes;
- }
-
- XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth,
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- UseablePrecision = R128MinBits(XclksPerTransfer) + 1;
-
- XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth)
- << (11 - UseablePrecision),
- VclkFreq * (info->CurrentLayout.pixel_bytes * 8));
-
- Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4);
-
- Ron = (4 * info->ram->MB
- + 3 * MAX(info->ram->Trcd - 2, 0)
- + 2 * info->ram->Trp
- + info->ram->Twr
- + info->ram->CL
- + info->ram->Tr2w
- + XclksPerTransfer) << (11 - UseablePrecision);
-
-
- if (Ron + info->ram->Rloop >= Roff) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n",
- Ron, info->ram->Rloop, Roff);
- return FALSE;
- }
-
- save->dda2_config = (XclksPerTransferPrecise
- | (UseablePrecision << 16)
- | (info->ram->Rloop << 20));
-
- /*save->dda2_on_off = (Ron << 16) | Roff;*/
- /* shift most be 18 otherwise there's corruption on crtc2 */
- save->dda2_on_off = (Ron << 18) | Roff;
-
- R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n",
- XclkFreq,
- VclkFreq,
- XclksPerTransfer,
- XclksPerTransferPrecise,
- UseablePrecision));
- R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n",
- Roff, Ron, info->ram->Rloop));
-
- return TRUE;
-}
-
-#if 0
-/* Define initial palette for requested video mode. This doesn't do
- anything for XFree86 4.0. */
-static void R128InitPalette(R128SavePtr save)
-{
- save->palette_valid = FALSE;
-}
-#endif
-
-/* Define registers for a requested video mode. */
-static Bool R128Init(ScrnInfoPtr pScrn, DisplayModePtr mode, R128SavePtr save)
-{
- R128InfoPtr info = R128PTR(pScrn);
- double dot_clock = mode->Clock/1000.0;
-
-#if R128_DEBUG
- ErrorF("%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)",
- mode->name,
- dot_clock,
-
- mode->HDisplay,
- mode->HSyncStart,
- mode->HSyncEnd,
- mode->HTotal,
-
- mode->VDisplay,
- mode->VSyncStart,
- mode->VSyncEnd,
- mode->VTotal,
- pScrn->depth,
- pScrn->bitsPerPixel);
- if (mode->Flags & V_DBLSCAN) ErrorF(" D");
- if (mode->Flags & V_CSYNC) ErrorF(" C");
- if (mode->Flags & V_INTERLACE) ErrorF(" I");
- if (mode->Flags & V_PHSYNC) ErrorF(" +H");
- if (mode->Flags & V_NHSYNC) ErrorF(" -H");
- if (mode->Flags & V_PVSYNC) ErrorF(" +V");
- if (mode->Flags & V_NVSYNC) ErrorF(" -V");
- ErrorF("\n");
- ErrorF("%-12.12s %7.2f %4d %4d %4d %4d %4d %4d %4d %4d (%d,%d)",
- mode->name,
- dot_clock,
-
- mode->CrtcHDisplay,
- mode->CrtcHSyncStart,
- mode->CrtcHSyncEnd,
- mode->CrtcHTotal,
-
- mode->CrtcVDisplay,
- mode->CrtcVSyncStart,
- mode->CrtcVSyncEnd,
- mode->CrtcVTotal,
- pScrn->depth,
- pScrn->bitsPerPixel);
- if (mode->Flags & V_DBLSCAN) ErrorF(" D");
- if (mode->Flags & V_CSYNC) ErrorF(" C");
- if (mode->Flags & V_INTERLACE) ErrorF(" I");
- if (mode->Flags & V_PHSYNC) ErrorF(" +H");
- if (mode->Flags & V_NHSYNC) ErrorF(" -H");
- if (mode->Flags & V_PVSYNC) ErrorF(" +V");
- if (mode->Flags & V_NVSYNC) ErrorF(" -V");
- ErrorF("\n");
-#endif
-
- info->Flags = mode->Flags;
-
- if(info->IsSecondary)
- {
- if (!R128InitCrtc2Registers(pScrn, save,
- pScrn->currentMode,info))
- return FALSE;
- R128InitPLL2Registers(save, &info->pll, dot_clock);
- if (!R128InitDDA2Registers(pScrn, save, &info->pll, info, mode))
- return FALSE;
- }
- else
- {
- R128InitCommonRegisters(save, info);
- if(!R128InitCrtcRegisters(pScrn, save, mode, info))
- return FALSE;
- if(dot_clock)
- {
- R128InitPLLRegisters(pScrn, save, &info->pll, dot_clock);
- if (!R128InitDDARegisters(pScrn, save, &info->pll, info, mode))
- return FALSE;
- }
- else
- {
- save->ppll_ref_div = info->SavedReg.ppll_ref_div;
- save->ppll_div_3 = info->SavedReg.ppll_div_3;
- save->htotal_cntl = info->SavedReg.htotal_cntl;
- save->dda_config = info->SavedReg.dda_config;
- save->dda_on_off = info->SavedReg.dda_on_off;
- }
- /* not used for now */
- /*if (!info->PaletteSavedOnVT) RADEONInitPalette(save);*/
- }
-
- if (((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD)))
- {
- R128InitFPRegisters(&info->SavedReg, save, mode, info);
- }
-
- R128TRACE(("R128Init returns %p\n", save));
- return TRUE;
-}
-
-/* Initialize a new mode. */
-static Bool R128ModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
-{
- R128InfoPtr info = R128PTR(pScrn);
-
- if (!R128Init(pScrn, mode, &info->ModeReg)) return FALSE;
- /* FIXME? DRILock/DRIUnlock here? */
- pScrn->vtSema = TRUE;
- R128Blank(pScrn);
- R128RestoreMode(pScrn, &info->ModeReg);
- R128Unblank(pScrn);
-
- info->CurrentLayout.mode = mode;
-
- return TRUE;
-}
-
-static Bool R128SaveScreen(ScreenPtr pScreen, int mode)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- Bool unblank;
-
- unblank = xf86IsUnblank(mode);
- if (unblank)
- SetTimeSinceLastInputEvent();
-
- if ((pScrn != NULL) && pScrn->vtSema) {
- if (unblank)
- R128Unblank(pScrn);
- else
- R128Blank(pScrn);
- }
- return TRUE;
-}
-
-/*
- * SwitchMode() doesn't work right on crtc2 on some laptops.
- * The workaround is to switch the mode, then switch to another VT, then
- * switch back. --AGD
- */
-Bool R128SwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
- Bool ret;
-
- info->SwitchingMode = TRUE;
- ret = R128ModeInit(xf86Screens[scrnIndex], mode);
- info->SwitchingMode = FALSE;
- return ret;
-}
-
-/* Used to disallow modes that are not supported by the hardware. */
-ModeStatus R128ValidMode(int scrnIndex, DisplayModePtr mode,
- Bool verbose, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
-
- if (info->BIOSDisplay == R128_BIOS_DISPLAY_CRT)
- return MODE_OK;
-
- if(info->isDFP) {
- if(info->PanelXRes < mode->CrtcHDisplay ||
- info->PanelYRes < mode->CrtcVDisplay)
- return MODE_NOMODE;
- else
- return MODE_OK;
- }
-
- if (info->DisplayType == MT_LCD) {
- if (mode->Flags & V_INTERLACE) return MODE_NO_INTERLACE;
- if (mode->Flags & V_DBLSCAN) return MODE_NO_DBLESCAN;
- }
-
- if (info->DisplayType == MT_LCD &&
- info->VBIOS) {
- int i;
- for (i = info->FPBIOSstart+64; R128_BIOS16(i) != 0; i += 2) {
- int j = R128_BIOS16(i);
-
- if (mode->CrtcHDisplay == R128_BIOS16(j) &&
- mode->CrtcVDisplay == R128_BIOS16(j+2)) {
- if ((flags & MODECHECK_FINAL) == MODECHECK_FINAL) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Modifying mode according to VBIOS: %ix%i [pclk %.1f MHz] for FP to: ",
- mode->CrtcHDisplay,mode->CrtcVDisplay,
- (float)mode->Clock/1000);
-
- /* Assume we are using expanded mode */
- if (R128_BIOS16(j+5)) j = R128_BIOS16(j+5);
- else j += 9;
-
- mode->Clock = (CARD32)R128_BIOS16(j) * 10;
-
- mode->HDisplay = mode->CrtcHDisplay =
- ((R128_BIOS16(j+10) & 0x01ff)+1)*8;
- mode->HSyncStart = mode->CrtcHSyncStart =
- ((R128_BIOS16(j+12) & 0x01ff)+1)*8;
- mode->HSyncEnd = mode->CrtcHSyncEnd =
- mode->CrtcHSyncStart + (R128_BIOS8(j+14) & 0x1f);
- mode->HTotal = mode->CrtcHTotal =
- ((R128_BIOS16(j+8) & 0x01ff)+1)*8;
-
- mode->VDisplay = mode->CrtcVDisplay =
- (R128_BIOS16(j+17) & 0x07ff)+1;
- mode->VSyncStart = mode->CrtcVSyncStart =
- (R128_BIOS16(j+19) & 0x07ff)+1;
- mode->VSyncEnd = mode->CrtcVSyncEnd =
- mode->CrtcVSyncStart + ((R128_BIOS16(j+19) >> 11) & 0x1f);
- mode->VTotal = mode->CrtcVTotal =
- (R128_BIOS16(j+15) & 0x07ff)+1;
- xf86ErrorF("%ix%i [pclk %.1f MHz]\n",
- mode->CrtcHDisplay,mode->CrtcVDisplay,
- (float)mode->Clock/1000);
- }
- return MODE_OK;
- }
- }
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 5,
- "Mode rejected for FP %ix%i [pclk: %.1f] "
- "(not listed in VBIOS)\n",
- mode->CrtcHDisplay, mode->CrtcVDisplay,
- (float)mode->Clock / 1000);
- return MODE_NOMODE;
- }
-
- return MODE_OK;
-}
-
-/* Adjust viewport into virtual desktop such that (0,0) in viewport space
- is (x,y) in virtual space. */
-void R128AdjustFrame(int scrnIndex, int x, int y, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int Base;
-
- if(info->showCache && y && pScrn->vtSema)
- y += pScrn->virtualY - 1;
-
- Base = y * info->CurrentLayout.displayWidth + x;
-
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: Base *= 2; break;
- case 24: Base *= 3; break;
- case 32: Base *= 4; break;
- }
-
- Base &= ~7; /* 3 lower bits are always 0 */
-
- if (info->CurrentLayout.pixel_code == 24)
- Base += 8 * (Base % 3); /* Must be multiple of 8 and 3 */
-
- if(info->IsSecondary)
- {
- Base += pScrn->fbOffset;
- OUTREG(R128_CRTC2_OFFSET, Base);
- }
- else
- OUTREG(R128_CRTC_OFFSET, Base);
-
-}
-
-/* Called when VT switching back to the X server. Reinitialize the video
- mode. */
-Bool R128EnterVT(int scrnIndex, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
-
- R128TRACE(("R128EnterVT\n"));
- if (info->FBDev) {
- if (!fbdevHWEnterVT(scrnIndex,flags)) return FALSE;
- } else
- if (!R128ModeInit(pScrn, pScrn->currentMode)) return FALSE;
- if (info->accelOn)
- R128EngineInit(pScrn);
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- if (info->irq) {
- /* Need to make sure interrupts are enabled */
- unsigned char *R128MMIO = info->MMIO;
- OUTREG(R128_GEN_INT_CNTL, info->gen_int_cntl);
- }
- R128CCE_START(pScrn, info);
- DRIUnlock(pScrn->pScreen);
- }
-#endif
-
- info->PaletteSavedOnVT = FALSE;
- pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
-
- return TRUE;
-}
-
-/* Called when VT switching away from the X server. Restore the original
- text mode. */
-void R128LeaveVT(int scrnIndex, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
- R128SavePtr save = &info->ModeReg;
-
- R128TRACE(("R128LeaveVT\n"));
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- DRILock(pScrn->pScreen, 0);
- R128CCE_STOP(pScrn, info);
- }
-#endif
- R128SavePalette(pScrn, save);
- info->PaletteSavedOnVT = TRUE;
- if (info->FBDev)
- fbdevHWLeaveVT(scrnIndex,flags);
- else
- R128Restore(pScrn);
-}
-
-
-/* Called at the end of each server generation. Restore the original text
- mode, unmap video memory, and unwrap and call the saved CloseScreen
- function. */
-static Bool R128CloseScreen(int scrnIndex, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
-
- R128TRACE(("R128CloseScreen\n"));
-
-#ifdef XF86DRI
- /* Disable direct rendering */
- if (info->directRenderingEnabled) {
- R128DRICloseScreen(pScreen);
- info->directRenderingEnabled = FALSE;
- }
-#endif
-
- if (pScrn->vtSema) {
- R128Restore(pScrn);
- R128UnmapMem(pScrn);
- }
-
- if (info->accel) XAADestroyInfoRec(info->accel);
- info->accel = NULL;
-
- if (info->scratch_save) xfree(info->scratch_save);
- info->scratch_save = NULL;
-
- if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
- info->cursor = NULL;
-
- if (info->DGAModes) xfree(info->DGAModes);
- info->DGAModes = NULL;
-
- if (info->adaptor) {
- xfree(info->adaptor->pPortPrivates[0].ptr);
- xf86XVFreeVideoAdaptorRec(info->adaptor);
- info->adaptor = NULL;
- }
-
- pScrn->vtSema = FALSE;
-
- pScreen->BlockHandler = info->BlockHandler;
- pScreen->CloseScreen = info->CloseScreen;
- return (*pScreen->CloseScreen)(scrnIndex, pScreen);
-}
-
-void R128FreeScreen(int scrnIndex, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- R128InfoPtr info = R128PTR(pScrn);
-
- R128TRACE(("R128FreeScreen\n"));
-#ifdef WITH_VGAHW
- if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
- vgaHWFreeHWRec(pScrn);
-#endif
- R128FreeRec(pScrn);
-}
-
-/* Sets VESA Display Power Management Signaling (DPMS) Mode. */
-static void R128DisplayPowerManagementSet(ScrnInfoPtr pScrn,
- int PowerManagementMode, int flags)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int mask = (R128_CRTC_DISPLAY_DIS
- | R128_CRTC_HSYNC_DIS
- | R128_CRTC_VSYNC_DIS);
- int mask2 = R128_CRTC2_DISP_DIS;
-
- switch (PowerManagementMode) {
- case DPMSModeOn:
- /* Screen: On; HSync: On, VSync: On */
- if (info->IsSecondary)
- OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~mask2);
- else
- OUTREGP(R128_CRTC_EXT_CNTL, 0, ~mask);
- break;
- case DPMSModeStandby:
- /* Screen: Off; HSync: Off, VSync: On */
- if (info->IsSecondary)
- OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_DISP_DIS, ~mask2);
- else
- OUTREGP(R128_CRTC_EXT_CNTL,
- R128_CRTC_DISPLAY_DIS | R128_CRTC_HSYNC_DIS, ~mask);
- break;
- case DPMSModeSuspend:
- /* Screen: Off; HSync: On, VSync: Off */
- if (info->IsSecondary)
- OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_DISP_DIS, ~mask2);
- else
- OUTREGP(R128_CRTC_EXT_CNTL,
- R128_CRTC_DISPLAY_DIS | R128_CRTC_VSYNC_DIS, ~mask);
- break;
- case DPMSModeOff:
- /* Screen: Off; HSync: Off, VSync: Off */
- if (info->IsSecondary)
- OUTREGP(R128_CRTC2_GEN_CNTL, mask2, ~mask2);
- else
- OUTREGP(R128_CRTC_EXT_CNTL, mask, ~mask);
- break;
- }
- if(info->isDFP) {
- switch (PowerManagementMode) {
- case DPMSModeOn:
- OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) | (R128_FP_FPON | R128_FP_TDMS_EN));
- break;
- case DPMSModeStandby:
- case DPMSModeSuspend:
- case DPMSModeOff:
- OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) & ~(R128_FP_FPON | R128_FP_TDMS_EN));
- break;
- }
- }
-}
-
-static int r128_set_backlight_enable(ScrnInfoPtr pScrn, int on);
-
-static void R128DisplayPowerManagementSetLCD(ScrnInfoPtr pScrn,
- int PowerManagementMode, int flags)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int mask = R128_LVDS_DISPLAY_DIS;
-
- switch (PowerManagementMode) {
- case DPMSModeOn:
- /* Screen: On; HSync: On, VSync: On */
- OUTREGP(R128_LVDS_GEN_CNTL, 0, ~mask);
- r128_set_backlight_enable(pScrn, 1);
- break;
- case DPMSModeStandby:
- /* Fall through */
- case DPMSModeSuspend:
- /* Fall through */
- break;
- case DPMSModeOff:
- /* Screen: Off; HSync: Off, VSync: Off */
- OUTREGP(R128_LVDS_GEN_CNTL, mask, ~mask);
- r128_set_backlight_enable(pScrn, 0);
- break;
- }
-}
-
-static int r128_set_backlight_enable(ScrnInfoPtr pScrn, int on)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- unsigned int lvds_gen_cntl = INREG(R128_LVDS_GEN_CNTL);
-
- lvds_gen_cntl |= (/*R128_LVDS_BL_MOD_EN |*/ R128_LVDS_BLON);
- if (on) {
- lvds_gen_cntl |= R128_LVDS_DIGON;
- if (!(lvds_gen_cntl & R128_LVDS_ON)) {
- lvds_gen_cntl &= ~R128_LVDS_BLON;
- OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl);
- (void)INREG(R128_LVDS_GEN_CNTL);
- usleep(10000);
- lvds_gen_cntl |= R128_LVDS_BLON;
- OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl);
- }
-#if 0
- lvds_gen_cntl &= ~R128_LVDS_BL_MOD_LEVEL_MASK;
- lvds_gen_cntl |= (0xFF /* backlight_conv[level] */ <<
- R128_LVDS_BL_MOD_LEVEL_SHIFT);
-#endif
- lvds_gen_cntl |= (R128_LVDS_ON | R128_LVDS_EN);
- lvds_gen_cntl &= ~R128_LVDS_DISPLAY_DIS;
- } else {
-#if 0
- lvds_gen_cntl &= ~R128_LVDS_BL_MOD_LEVEL_MASK;
- lvds_gen_cntl |= (0xFF /* backlight_conv[0] */ <<
- R128_LVDS_BL_MOD_LEVEL_SHIFT);
-#endif
- lvds_gen_cntl |= R128_LVDS_DISPLAY_DIS;
- OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl);
- usleep(10);
- lvds_gen_cntl &= ~(R128_LVDS_ON | R128_LVDS_EN | R128_LVDS_BLON
- | R128_LVDS_DIGON);
- }
-
- OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl);
-
- return 0;
-}
diff --git a/src/r128_misc.c b/src/r128_misc.c
deleted file mode 100644
index 2dc6040..0000000
--- a/src/r128_misc.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "r128_probe.h"
-#include "r128_version.h"
-
-#include "xf86.h"
-
-/* Module loader interface for subsidiary driver module */
-
-static XF86ModuleVersionInfo R128VersionRec =
-{
- R128_DRIVER_NAME,
- MODULEVENDORSTRING,
- MODINFOSTRING1,
- MODINFOSTRING2,
- XORG_VERSION_CURRENT,
- R128_VERSION_MAJOR, R128_VERSION_MINOR, R128_VERSION_PATCH,
- ABI_CLASS_VIDEODRV,
- ABI_VIDEODRV_VERSION,
- MOD_CLASS_VIDEODRV,
- {0, 0, 0, 0}
-};
-
-/*
- * R128Setup --
- *
- * This function is called every time the module is loaded.
- */
-static pointer
-R128Setup
-(
- pointer Module,
- pointer Options,
- int *ErrorMajor,
- int *ErrorMinor
-)
-{
- static Bool Inited = FALSE;
-
- if (!Inited)
- {
- Inited = TRUE;
- xf86AddDriver(&R128, Module, HaveDriverFuncs);
- }
-
- return (pointer)TRUE;
-}
-
-/* The following record must be called r128ModuleData */
-_X_EXPORT XF86ModuleData r128ModuleData =
-{
- &R128VersionRec,
- R128Setup,
- NULL
-};
diff --git a/src/r128_probe.c b/src/r128_probe.c
deleted file mode 100644
index b1f427a..0000000
--- a/src/r128_probe.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- */
-
-#include "r128_probe.h"
-#include "r128_version.h"
-#include "atipcirename.h"
-
-#include "xf86.h"
-#include "xf86PciInfo.h"
-#include "xf86Resources.h"
-
-#ifndef XSERVER_LIBPCIACCESS
-static Bool R128Probe(DriverPtr drv, int flags);
-#endif
-
-SymTabRec R128Chipsets[] = {
- { PCI_CHIP_RAGE128LE, "ATI Rage 128 Mobility M3 LE (PCI)" },
- { PCI_CHIP_RAGE128LF, "ATI Rage 128 Mobility M3 LF (AGP)" },
- { PCI_CHIP_RAGE128MF, "ATI Rage 128 Mobility M4 MF (AGP)" },
- { PCI_CHIP_RAGE128ML, "ATI Rage 128 Mobility M4 ML (AGP)" },
- { PCI_CHIP_RAGE128PA, "ATI Rage 128 Pro GL PA (PCI/AGP)" },
- { PCI_CHIP_RAGE128PB, "ATI Rage 128 Pro GL PB (PCI/AGP)" },
- { PCI_CHIP_RAGE128PC, "ATI Rage 128 Pro GL PC (PCI/AGP)" },
- { PCI_CHIP_RAGE128PD, "ATI Rage 128 Pro GL PD (PCI)" },
- { PCI_CHIP_RAGE128PE, "ATI Rage 128 Pro GL PE (PCI/AGP)" },
- { PCI_CHIP_RAGE128PF, "ATI Rage 128 Pro GL PF (AGP)" },
- { PCI_CHIP_RAGE128PG, "ATI Rage 128 Pro VR PG (PCI/AGP)" },
- { PCI_CHIP_RAGE128PH, "ATI Rage 128 Pro VR PH (PCI/AGP)" },
- { PCI_CHIP_RAGE128PI, "ATI Rage 128 Pro VR PI (PCI/AGP)" },
- { PCI_CHIP_RAGE128PJ, "ATI Rage 128 Pro VR PJ (PCI/AGP)" },
- { PCI_CHIP_RAGE128PK, "ATI Rage 128 Pro VR PK (PCI/AGP)" },
- { PCI_CHIP_RAGE128PL, "ATI Rage 128 Pro VR PL (PCI/AGP)" },
- { PCI_CHIP_RAGE128PM, "ATI Rage 128 Pro VR PM (PCI/AGP)" },
- { PCI_CHIP_RAGE128PN, "ATI Rage 128 Pro VR PN (PCI/AGP)" },
- { PCI_CHIP_RAGE128PO, "ATI Rage 128 Pro VR PO (PCI/AGP)" },
- { PCI_CHIP_RAGE128PP, "ATI Rage 128 Pro VR PP (PCI)" },
- { PCI_CHIP_RAGE128PQ, "ATI Rage 128 Pro VR PQ (PCI/AGP)" },
- { PCI_CHIP_RAGE128PR, "ATI Rage 128 Pro VR PR (PCI)" },
- { PCI_CHIP_RAGE128PS, "ATI Rage 128 Pro VR PS (PCI/AGP)" },
- { PCI_CHIP_RAGE128PT, "ATI Rage 128 Pro VR PT (PCI/AGP)" },
- { PCI_CHIP_RAGE128PU, "ATI Rage 128 Pro VR PU (PCI/AGP)" },
- { PCI_CHIP_RAGE128PV, "ATI Rage 128 Pro VR PV (PCI/AGP)" },
- { PCI_CHIP_RAGE128PW, "ATI Rage 128 Pro VR PW (PCI/AGP)" },
- { PCI_CHIP_RAGE128PX, "ATI Rage 128 Pro VR PX (PCI/AGP)" },
- { PCI_CHIP_RAGE128RE, "ATI Rage 128 GL RE (PCI)" },
- { PCI_CHIP_RAGE128RF, "ATI Rage 128 GL RF (AGP)" },
- { PCI_CHIP_RAGE128RG, "ATI Rage 128 RG (AGP)" },
- { PCI_CHIP_RAGE128RK, "ATI Rage 128 VR RK (PCI)" },
- { PCI_CHIP_RAGE128RL, "ATI Rage 128 VR RL (AGP)" },
- { PCI_CHIP_RAGE128SE, "ATI Rage 128 4X SE (PCI/AGP)" },
- { PCI_CHIP_RAGE128SF, "ATI Rage 128 4X SF (PCI/AGP)" },
- { PCI_CHIP_RAGE128SG, "ATI Rage 128 4X SG (PCI/AGP)" },
- { PCI_CHIP_RAGE128SH, "ATI Rage 128 4X SH (PCI/AGP)" },
- { PCI_CHIP_RAGE128SK, "ATI Rage 128 4X SK (PCI/AGP)" },
- { PCI_CHIP_RAGE128SL, "ATI Rage 128 4X SL (PCI/AGP)" },
- { PCI_CHIP_RAGE128SM, "ATI Rage 128 4X SM (AGP)" },
- { PCI_CHIP_RAGE128SN, "ATI Rage 128 4X SN (PCI/AGP)" },
- { PCI_CHIP_RAGE128TF, "ATI Rage 128 Pro ULTRA TF (AGP)" },
- { PCI_CHIP_RAGE128TL, "ATI Rage 128 Pro ULTRA TL (AGP)" },
- { PCI_CHIP_RAGE128TR, "ATI Rage 128 Pro ULTRA TR (AGP)" },
- { PCI_CHIP_RAGE128TS, "ATI Rage 128 Pro ULTRA TS (AGP?)" },
- { PCI_CHIP_RAGE128TT, "ATI Rage 128 Pro ULTRA TT (AGP?)" },
- { PCI_CHIP_RAGE128TU, "ATI Rage 128 Pro ULTRA TU (AGP?)" },
- { -1, NULL }
-};
-
-static PciChipsets R128PciChipsets[] = {
- { PCI_CHIP_RAGE128LE, PCI_CHIP_RAGE128LE, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128LF, PCI_CHIP_RAGE128LF, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128MF, PCI_CHIP_RAGE128MF, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128ML, PCI_CHIP_RAGE128ML, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PA, PCI_CHIP_RAGE128PA, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PB, PCI_CHIP_RAGE128PB, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PC, PCI_CHIP_RAGE128PC, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PD, PCI_CHIP_RAGE128PD, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PE, PCI_CHIP_RAGE128PE, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PF, PCI_CHIP_RAGE128PF, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PG, PCI_CHIP_RAGE128PG, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PH, PCI_CHIP_RAGE128PH, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PI, PCI_CHIP_RAGE128PI, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PJ, PCI_CHIP_RAGE128PJ, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PK, PCI_CHIP_RAGE128PK, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PL, PCI_CHIP_RAGE128PL, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PM, PCI_CHIP_RAGE128PM, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PN, PCI_CHIP_RAGE128PN, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PO, PCI_CHIP_RAGE128PO, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PP, PCI_CHIP_RAGE128PP, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PQ, PCI_CHIP_RAGE128PQ, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PR, PCI_CHIP_RAGE128PR, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PS, PCI_CHIP_RAGE128PS, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PT, PCI_CHIP_RAGE128PT, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PU, PCI_CHIP_RAGE128PU, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PV, PCI_CHIP_RAGE128PV, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PW, PCI_CHIP_RAGE128PW, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128PX, PCI_CHIP_RAGE128PX, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128RE, PCI_CHIP_RAGE128RE, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128RF, PCI_CHIP_RAGE128RF, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128RG, PCI_CHIP_RAGE128RG, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128RK, PCI_CHIP_RAGE128RK, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128RL, PCI_CHIP_RAGE128RL, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SE, PCI_CHIP_RAGE128SE, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SF, PCI_CHIP_RAGE128SF, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SG, PCI_CHIP_RAGE128SG, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SH, PCI_CHIP_RAGE128SH, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SK, PCI_CHIP_RAGE128SK, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SL, PCI_CHIP_RAGE128SL, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SM, PCI_CHIP_RAGE128SM, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128SN, PCI_CHIP_RAGE128SN, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128TF, PCI_CHIP_RAGE128TF, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128TL, PCI_CHIP_RAGE128TL, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128TR, PCI_CHIP_RAGE128TR, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128TS, PCI_CHIP_RAGE128TS, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128TT, PCI_CHIP_RAGE128TT, RES_SHARED_VGA },
- { PCI_CHIP_RAGE128TU, PCI_CHIP_RAGE128TU, RES_SHARED_VGA },
- { -1, -1, RES_UNDEFINED }
-};
-
-#ifdef XSERVER_LIBPCIACCESS
-
-static const struct pci_id_match r128_device_match[] = {
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128LE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128LF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128MF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128ML, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PA, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PB, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PC, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PD, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PG, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PI, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PJ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PL, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PM, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PN, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PO, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PP, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PQ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PR, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PS, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PT, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PU, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PV, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PW, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128PX, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128RE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128RF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128RG, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128RK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128RL, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SG, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SL, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SM, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128SN, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128TF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128TL, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128TR, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128TS, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128TT, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RAGE128TU, 0 ),
- { 0, 0, 0 }
-};
-
-#endif /* XSERVER_LIBPCIACCESS */
-
-int gR128EntityIndex = -1;
-
-/* Return the options for supported chipset 'n'; NULL otherwise */
-static const OptionInfoRec *
-R128AvailableOptions(int chipid, int busid)
-{
- return R128OptionsWeak();
-}
-
-/* Return the string name for supported chipset 'n'; NULL otherwise. */
-static void
-R128Identify(int flags)
-{
- xf86PrintChipsets(R128_NAME,
- "Driver for ATI Rage 128 chipsets",
- R128Chipsets);
-}
-
-static Bool
-r128_get_scrninfo(int entity_num)
-{
- ScrnInfoPtr pScrn = NULL;
- EntityInfoPtr pEnt;
-
- pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, R128PciChipsets,
- NULL,
- NULL, NULL, NULL, NULL);
-
- if (!pScrn)
- return FALSE;
-
- pScrn->driverVersion = R128_VERSION_CURRENT;
- pScrn->driverName = R128_DRIVER_NAME;
- pScrn->name = R128_NAME;
-#ifdef XSERVER_LIBPCIACCESS
- pScrn->Probe = NULL;
-#else
- pScrn->Probe = R128Probe;
-#endif
- pScrn->PreInit = R128PreInit;
- pScrn->ScreenInit = R128ScreenInit;
- pScrn->SwitchMode = R128SwitchMode;
- pScrn->AdjustFrame = R128AdjustFrame;
- pScrn->EnterVT = R128EnterVT;
- pScrn->LeaveVT = R128LeaveVT;
- pScrn->FreeScreen = R128FreeScreen;
- pScrn->ValidMode = R128ValidMode;
-
- pEnt = xf86GetEntityInfo(entity_num);
-
- /* mobility cards support Dual-Head, mark the entity as sharable*/
- if (pEnt->chipset == PCI_CHIP_RAGE128LE ||
- pEnt->chipset == PCI_CHIP_RAGE128LF ||
- pEnt->chipset == PCI_CHIP_RAGE128MF ||
- pEnt->chipset == PCI_CHIP_RAGE128ML)
- {
- static int instance = 0;
- DevUnion* pPriv;
-
- xf86SetEntitySharable(entity_num);
-
- xf86SetEntityInstanceForScreen(pScrn,
- pScrn->entityList[0],
- instance);
-
- if (gR128EntityIndex < 0)
- {
- gR128EntityIndex = xf86AllocateEntityPrivateIndex();
-
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- gR128EntityIndex);
-
- if (!pPriv->ptr)
- {
- R128EntPtr pR128Ent;
- pPriv->ptr = xnfcalloc(sizeof(R128EntRec), 1);
- pR128Ent = pPriv->ptr;
- pR128Ent->IsDRIEnabled = FALSE;
- pR128Ent->BypassSecondary = FALSE;
- pR128Ent->HasSecondary = FALSE;
- pR128Ent->IsSecondaryRestored = FALSE;
- }
- }
- instance++;
- }
-
- xfree(pEnt);
-
- return TRUE;
-}
-
-#ifndef XSERVER_LIBPCIACCESS
-
-/* Return TRUE if chipset is present; FALSE otherwise. */
-static Bool
-R128Probe(DriverPtr drv, int flags)
-{
- int numUsed;
- int numDevSections;
- int *usedChips;
- GDevPtr *devSections;
- Bool foundScreen = FALSE;
- int i;
-
- if (!xf86GetPciVideoInfo()) return FALSE;
-
- numDevSections = xf86MatchDevice(R128_NAME, &devSections);
-
- if (!numDevSections) return FALSE;
-
- numUsed = xf86MatchPciInstances(R128_NAME,
- PCI_VENDOR_ATI,
- R128Chipsets,
- R128PciChipsets,
- devSections,
- numDevSections,
- drv,
- &usedChips);
-
- if (numUsed<=0) return FALSE;
-
- if (flags & PROBE_DETECT)
- foundScreen = TRUE;
- else for (i = 0; i < numUsed; i++) {
- if (r128_get_scrninfo(usedChips[i]))
- foundScreen = TRUE;
- }
-
- xfree(usedChips);
- xfree(devSections);
-
- return foundScreen;
-}
-
-#else /* XSERVER_LIBPCIACCESS */
-
-static Bool
-r128_pci_probe(
- DriverPtr pDriver,
- int entity_num,
- struct pci_device *device,
- intptr_t match_data
-)
-{
- return r128_get_scrninfo(entity_num);
-}
-
-#endif /* XSERVER_LIBPCIACCESS */
-
-_X_EXPORT DriverRec R128 =
-{
- R128_VERSION_CURRENT,
- R128_DRIVER_NAME,
- R128Identify,
-#ifdef XSERVER_LIBPCIACCESS
- NULL,
-#else
- R128Probe,
-#endif
- R128AvailableOptions,
- NULL,
- 0,
- NULL,
-#ifdef XSERVER_LIBPCIACCESS
- r128_device_match,
- r128_pci_probe
-#endif
-};
diff --git a/src/r128_probe.h b/src/r128_probe.h
deleted file mode 100644
index 59c9a00..0000000
--- a/src/r128_probe.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at valinux.com>
- *
- * Modified by Marc Aurele La France <tsi at xfree86.org> for ATI driver merge.
- */
-
-#ifndef _R128_PROBE_H_
-#define _R128_PROBE_H_ 1
-
-#include "xf86str.h"
-
-extern DriverRec R128;
-
-typedef struct
-{
- Bool IsDRIEnabled;
-
- Bool HasSecondary;
- Bool BypassSecondary;
- /*These two registers are used to make sure the CRTC2 is
- retored before CRTC_EXT, otherwise it could lead to blank screen.*/
- Bool IsSecondaryRestored;
- Bool RestorePrimary;
-
- ScrnInfoPtr pSecondaryScrn;
- ScrnInfoPtr pPrimaryScrn;
-} R128EntRec, *R128EntPtr;
-
-/* r128_probe.c */
-extern SymTabRec R128Chipsets[];
-
-/* r128_driver.c */
-extern Bool R128PreInit(ScrnInfoPtr, int);
-extern Bool R128ScreenInit(int, ScreenPtr, int, char **);
-extern Bool R128SwitchMode(int, DisplayModePtr, int);
-extern void R128AdjustFrame(int, int, int, int);
-extern Bool R128EnterVT(int, int);
-extern void R128LeaveVT(int, int);
-extern void R128FreeScreen(int, int);
-extern ModeStatus R128ValidMode(int, DisplayModePtr, Bool, int);
-
-extern const OptionInfoRec * R128OptionsWeak(void);
-
-#endif /* _R128_PROBE_H_ */
diff --git a/src/r128_reg.h b/src/r128_reg.h
deleted file mode 100644
index dac22e6..0000000
--- a/src/r128_reg.h
+++ /dev/null
@@ -1,1533 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Rickard E. Faith <faith at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- * Gareth Hughes <gareth at valinux.com>
- *
- * References:
- *
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
-
-#ifndef _R128_REG_H_
-#define _R128_REG_H_
-
-#include "compiler.h"
-
- /* Memory mapped register access macros */
-#define INREG8(addr) MMIO_IN8(R128MMIO, addr)
-#define INREG16(addr) MMIO_IN16(R128MMIO, addr)
-#define INREG(addr) MMIO_IN32(R128MMIO, addr)
-#define OUTREG8(addr, val) MMIO_OUT8(R128MMIO, addr, val)
-#define OUTREG16(addr, val) MMIO_OUT16(R128MMIO, addr, val)
-#define OUTREG(addr, val) MMIO_OUT32(R128MMIO, addr, val)
-
-#define ADDRREG(addr) ((volatile CARD32 *)(pointer)(R128MMIO + (addr)))
-
-
-#define OUTREGP(addr, val, mask) \
- do { \
- CARD32 tmp = INREG(addr); \
- tmp &= (mask); \
- tmp |= ((val) & ~(mask)); \
- OUTREG(addr, tmp); \
- } while (0)
-
-#define INPLL(pScrn, addr) R128INPLL(pScrn, addr)
-
-#define OUTPLL(addr, val) \
- do { \
- OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x3f) | R128_PLL_WR_EN); \
- OUTREG(R128_CLOCK_CNTL_DATA, val); \
- } while (0)
-
-#define OUTPLLP(pScrn, addr, val, mask) \
- do { \
- CARD32 tmp = INPLL(pScrn, addr); \
- tmp &= (mask); \
- tmp |= ((val) & ~(mask)); \
- OUTPLL(addr, tmp); \
- } while (0)
-
-#define OUTPAL_START(idx) \
- do { \
- OUTREG8(R128_PALETTE_INDEX, (idx)); \
- } while (0)
-
-#define OUTPAL_NEXT(r, g, b) \
- do { \
- OUTREG(R128_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
- } while (0)
-
-#define OUTPAL_NEXT_CARD32(v) \
- do { \
- OUTREG(R128_PALETTE_DATA, (v & 0x00ffffff)); \
- } while (0)
-
-#define OUTPAL(idx, r, g, b) \
- do { \
- OUTPAL_START((idx)); \
- OUTPAL_NEXT((r), (g), (b)); \
- } while (0)
-
-#define INPAL_START(idx) \
- do { \
- OUTREG(R128_PALETTE_INDEX, (idx) << 16); \
- } while (0)
-
-#define INPAL_NEXT() INREG(R128_PALETTE_DATA)
-
-#define PAL_SELECT(idx) \
- do { \
- CARD32 tmp = INREG(R128_DAC_CNTL); \
- if (idx) { \
- OUTREG(R128_DAC_CNTL, tmp | R128_DAC_PALETTE_ACC_CTL); \
- } else { \
- OUTREG(R128_DAC_CNTL, tmp & \
- (CARD32)~R128_DAC_PALETTE_ACC_CTL); \
- } \
- } while (0)
-
-#define R128_ADAPTER_ID 0x0f2c /* PCI */
-#define R128_AGP_APER_OFFSET 0x0178
-#define R128_AGP_BASE 0x0170
-#define R128_AGP_CNTL 0x0174
-# define R128_AGP_APER_SIZE_256MB (0x00 << 0)
-# define R128_AGP_APER_SIZE_128MB (0x20 << 0)
-# define R128_AGP_APER_SIZE_64MB (0x30 << 0)
-# define R128_AGP_APER_SIZE_32MB (0x38 << 0)
-# define R128_AGP_APER_SIZE_16MB (0x3c << 0)
-# define R128_AGP_APER_SIZE_8MB (0x3e << 0)
-# define R128_AGP_APER_SIZE_4MB (0x3f << 0)
-# define R128_AGP_APER_SIZE_MASK (0x3f << 0)
-#define R128_AGP_CNTL_B 0x0b44
-#define R128_AGP_COMMAND 0x0f58 /* PCI */
-#define R128_AGP_PLL_CNTL 0x0010 /* PLL */
-#define R128_AGP_STATUS 0x0f54 /* PCI */
-# define R128_AGP_1X_MODE 0x01
-# define R128_AGP_2X_MODE 0x02
-# define R128_AGP_4X_MODE 0x04
-# define R128_AGP_MODE_MASK 0x07
-#define R128_AMCGPIO_A_REG 0x01a0
-#define R128_AMCGPIO_EN_REG 0x01a8
-#define R128_AMCGPIO_MASK 0x0194
-#define R128_AMCGPIO_Y_REG 0x01a4
-#define R128_ATTRDR 0x03c1 /* VGA */
-#define R128_ATTRDW 0x03c0 /* VGA */
-#define R128_ATTRX 0x03c0 /* VGA */
-#define R128_AUX_SC_CNTL 0x1660
-# define R128_AUX1_SC_EN (1 << 0)
-# define R128_AUX1_SC_MODE_OR (0 << 1)
-# define R128_AUX1_SC_MODE_NAND (1 << 1)
-# define R128_AUX2_SC_EN (1 << 2)
-# define R128_AUX2_SC_MODE_OR (0 << 3)
-# define R128_AUX2_SC_MODE_NAND (1 << 3)
-# define R128_AUX3_SC_EN (1 << 4)
-# define R128_AUX3_SC_MODE_OR (0 << 5)
-# define R128_AUX3_SC_MODE_NAND (1 << 5)
-#define R128_AUX1_SC_BOTTOM 0x1670
-#define R128_AUX1_SC_LEFT 0x1664
-#define R128_AUX1_SC_RIGHT 0x1668
-#define R128_AUX1_SC_TOP 0x166c
-#define R128_AUX2_SC_BOTTOM 0x1680
-#define R128_AUX2_SC_LEFT 0x1674
-#define R128_AUX2_SC_RIGHT 0x1678
-#define R128_AUX2_SC_TOP 0x167c
-#define R128_AUX3_SC_BOTTOM 0x1690
-#define R128_AUX3_SC_LEFT 0x1684
-#define R128_AUX3_SC_RIGHT 0x1688
-#define R128_AUX3_SC_TOP 0x168c
-#define R128_AUX_WINDOW_HORZ_CNTL 0x02d8
-#define R128_AUX_WINDOW_VERT_CNTL 0x02dc
-
-#define R128_BASE_CODE 0x0f0b
-#define R128_BIOS_0_SCRATCH 0x0010
-#define R128_BIOS_1_SCRATCH 0x0014
-#define R128_BIOS_2_SCRATCH 0x0018
-#define R128_BIOS_3_SCRATCH 0x001c
-#define R128_BIOS_4_SCRATCH 0x0020
-#define R128_BIOS_5_SCRATCH 0x0024
-# define R128_BIOS_DISPLAY_FP (1 << 0)
-# define R128_BIOS_DISPLAY_CRT (2 << 0)
-# define R128_BIOS_DISPLAY_FP_CRT (3 << 0)
-/* R128_DUALHEAD is just a flag for the driver;
- it doesn't actually correspond to any bits */
-# define R128_DUALHEAD 4
-#define R128_BIOS_6_SCRATCH 0x0028
-#define R128_BIOS_7_SCRATCH 0x002c
-#define R128_BIOS_ROM 0x0f30 /* PCI */
-#define R128_BIST 0x0f0f /* PCI */
-#define R128_BM_CHUNK_0_VAL 0x0a18
-# define R128_BM_PTR_FORCE_TO_PCI (1 << 21)
-# define R128_BM_PM4_RD_FORCE_TO_PCI (1 << 22)
-# define R128_BM_GLOBAL_FORCE_TO_PCI (1 << 23)
-#define R128_BRUSH_DATA0 0x1480
-#define R128_BRUSH_DATA1 0x1484
-#define R128_BRUSH_DATA10 0x14a8
-#define R128_BRUSH_DATA11 0x14ac
-#define R128_BRUSH_DATA12 0x14b0
-#define R128_BRUSH_DATA13 0x14b4
-#define R128_BRUSH_DATA14 0x14b8
-#define R128_BRUSH_DATA15 0x14bc
-#define R128_BRUSH_DATA16 0x14c0
-#define R128_BRUSH_DATA17 0x14c4
-#define R128_BRUSH_DATA18 0x14c8
-#define R128_BRUSH_DATA19 0x14cc
-#define R128_BRUSH_DATA2 0x1488
-#define R128_BRUSH_DATA20 0x14d0
-#define R128_BRUSH_DATA21 0x14d4
-#define R128_BRUSH_DATA22 0x14d8
-#define R128_BRUSH_DATA23 0x14dc
-#define R128_BRUSH_DATA24 0x14e0
-#define R128_BRUSH_DATA25 0x14e4
-#define R128_BRUSH_DATA26 0x14e8
-#define R128_BRUSH_DATA27 0x14ec
-#define R128_BRUSH_DATA28 0x14f0
-#define R128_BRUSH_DATA29 0x14f4
-#define R128_BRUSH_DATA3 0x148c
-#define R128_BRUSH_DATA30 0x14f8
-#define R128_BRUSH_DATA31 0x14fc
-#define R128_BRUSH_DATA32 0x1500
-#define R128_BRUSH_DATA33 0x1504
-#define R128_BRUSH_DATA34 0x1508
-#define R128_BRUSH_DATA35 0x150c
-#define R128_BRUSH_DATA36 0x1510
-#define R128_BRUSH_DATA37 0x1514
-#define R128_BRUSH_DATA38 0x1518
-#define R128_BRUSH_DATA39 0x151c
-#define R128_BRUSH_DATA4 0x1490
-#define R128_BRUSH_DATA40 0x1520
-#define R128_BRUSH_DATA41 0x1524
-#define R128_BRUSH_DATA42 0x1528
-#define R128_BRUSH_DATA43 0x152c
-#define R128_BRUSH_DATA44 0x1530
-#define R128_BRUSH_DATA45 0x1534
-#define R128_BRUSH_DATA46 0x1538
-#define R128_BRUSH_DATA47 0x153c
-#define R128_BRUSH_DATA48 0x1540
-#define R128_BRUSH_DATA49 0x1544
-#define R128_BRUSH_DATA5 0x1494
-#define R128_BRUSH_DATA50 0x1548
-#define R128_BRUSH_DATA51 0x154c
-#define R128_BRUSH_DATA52 0x1550
-#define R128_BRUSH_DATA53 0x1554
-#define R128_BRUSH_DATA54 0x1558
-#define R128_BRUSH_DATA55 0x155c
-#define R128_BRUSH_DATA56 0x1560
-#define R128_BRUSH_DATA57 0x1564
-#define R128_BRUSH_DATA58 0x1568
-#define R128_BRUSH_DATA59 0x156c
-#define R128_BRUSH_DATA6 0x1498
-#define R128_BRUSH_DATA60 0x1570
-#define R128_BRUSH_DATA61 0x1574
-#define R128_BRUSH_DATA62 0x1578
-#define R128_BRUSH_DATA63 0x157c
-#define R128_BRUSH_DATA7 0x149c
-#define R128_BRUSH_DATA8 0x14a0
-#define R128_BRUSH_DATA9 0x14a4
-#define R128_BRUSH_SCALE 0x1470
-#define R128_BRUSH_Y_X 0x1474
-#define R128_BUS_CNTL 0x0030
-# define R128_BUS_MASTER_DIS (1 << 6)
-# define R128_BUS_RD_DISCARD_EN (1 << 24)
-# define R128_BUS_RD_ABORT_EN (1 << 25)
-# define R128_BUS_MSTR_DISCONNECT_EN (1 << 28)
-# define R128_BUS_WRT_BURST (1 << 29)
-# define R128_BUS_READ_BURST (1 << 30)
-#define R128_BUS_CNTL1 0x0034
-# define R128_BUS_WAIT_ON_LOCK_EN (1 << 4)
-
-#define R128_CACHE_CNTL 0x1724
-#define R128_CACHE_LINE 0x0f0c /* PCI */
-#define R128_CAP0_TRIG_CNTL 0x0950 /* ? */
-#define R128_CAP1_TRIG_CNTL 0x09c0 /* ? */
-#define R128_CAPABILITIES_ID 0x0f50 /* PCI */
-#define R128_CAPABILITIES_PTR 0x0f34 /* PCI */
-#define R128_CLK_PIN_CNTL 0x0001 /* PLL */
-#define R128_CLOCK_CNTL_DATA 0x000c
-#define R128_CLOCK_CNTL_INDEX 0x0008
-# define R128_PLL_WR_EN (1 << 7)
-# define R128_PLL_DIV_SEL (3 << 8)
-# define R128_PLL2_DIV_SEL_MASK ~(3 << 8)
-#define R128_CLR_CMP_CLR_3D 0x1a24
-#define R128_CLR_CMP_CLR_DST 0x15c8
-#define R128_CLR_CMP_CLR_SRC 0x15c4
-#define R128_CLR_CMP_CNTL 0x15c0
-# define R128_SRC_CMP_EQ_COLOR (4 << 0)
-# define R128_SRC_CMP_NEQ_COLOR (5 << 0)
-# define R128_CLR_CMP_SRC_SOURCE (1 << 24)
-#define R128_CLR_CMP_MASK 0x15cc
-# define R128_CLR_CMP_MSK 0xffffffff
-#define R128_CLR_CMP_MASK_3D 0x1A28
-#define R128_COMMAND 0x0f04 /* PCI */
-#define R128_COMPOSITE_SHADOW_ID 0x1a0c
-#define R128_CONFIG_APER_0_BASE 0x0100
-#define R128_CONFIG_APER_1_BASE 0x0104
-#define R128_CONFIG_APER_SIZE 0x0108
-#define R128_CONFIG_BONDS 0x00e8
-#define R128_CONFIG_CNTL 0x00e0
-# define APER_0_BIG_ENDIAN_16BPP_SWAP (1 << 0)
-# define APER_0_BIG_ENDIAN_32BPP_SWAP (2 << 0)
-#define R128_CONFIG_MEMSIZE 0x00f8
-#define R128_CONFIG_MEMSIZE_EMBEDDED 0x0114
-#define R128_CONFIG_REG_1_BASE 0x010c
-#define R128_CONFIG_REG_APER_SIZE 0x0110
-#define R128_CONFIG_XSTRAP 0x00e4
-#define R128_CONSTANT_COLOR_C 0x1d34
-# define R128_CONSTANT_COLOR_MASK 0x00ffffff
-# define R128_CONSTANT_COLOR_ONE 0x00ffffff
-# define R128_CONSTANT_COLOR_ZERO 0x00000000
-#define R128_CRC_CMDFIFO_ADDR 0x0740
-#define R128_CRC_CMDFIFO_DOUT 0x0744
-#define R128_CRTC_CRNT_FRAME 0x0214
-#define R128_CRTC_DEBUG 0x021c
-#define R128_CRTC_EXT_CNTL 0x0054
-# define R128_CRTC_VGA_XOVERSCAN (1 << 0)
-# define R128_VGA_ATI_LINEAR (1 << 3)
-# define R128_XCRT_CNT_EN (1 << 6)
-# define R128_CRTC_HSYNC_DIS (1 << 8)
-# define R128_CRTC_VSYNC_DIS (1 << 9)
-# define R128_CRTC_DISPLAY_DIS (1 << 10)
-# define R128_CRTC_CRT_ON (1 << 15)
-# define R128_FP_OUT_EN (1 << 22)
-# define R128_FP_ACTIVE (1 << 23)
-#define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
-# define R128_CRTC_HSYNC_DIS_BYTE (1 << 0)
-# define R128_CRTC_VSYNC_DIS_BYTE (1 << 1)
-# define R128_CRTC_DISPLAY_DIS_BYTE (1 << 2)
-#define R128_CRTC_GEN_CNTL 0x0050
-# define R128_CRTC_DBL_SCAN_EN (1 << 0)
-# define R128_CRTC_INTERLACE_EN (1 << 1)
-# define R128_CRTC_CSYNC_EN (1 << 4)
-# define R128_CRTC_CUR_EN (1 << 16)
-# define R128_CRTC_CUR_MODE_MASK (7 << 17)
-# define R128_CRTC_ICON_EN (1 << 20)
-# define R128_CRTC_EXT_DISP_EN (1 << 24)
-# define R128_CRTC_EN (1 << 25)
-# define R128_CRTC_DISP_REQ_EN_B (1 << 26)
-#define R128_CRTC_GUI_TRIG_VLINE 0x0218
-#define R128_CRTC_H_SYNC_STRT_WID 0x0204
-# define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
-# define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3)
-# define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
-# define R128_CRTC_H_SYNC_WID (0x3f << 16)
-# define R128_CRTC_H_SYNC_WID_SHIFT 16
-# define R128_CRTC_H_SYNC_POL (1 << 23)
-#define R128_CRTC_H_TOTAL_DISP 0x0200
-# define R128_CRTC_H_TOTAL (0x01ff << 0)
-# define R128_CRTC_H_TOTAL_SHIFT 0
-# define R128_CRTC_H_DISP (0x00ff << 16)
-# define R128_CRTC_H_DISP_SHIFT 16
-#define R128_CRTC_OFFSET 0x0224
-#define R128_CRTC_OFFSET_CNTL 0x0228
-#define R128_CRTC_PITCH 0x022c
-#define R128_CRTC_STATUS 0x005c
-# define R128_CRTC_VBLANK_SAVE (1 << 1)
-#define R128_CRTC_V_SYNC_STRT_WID 0x020c
-# define R128_CRTC_V_SYNC_STRT (0x7ff << 0)
-# define R128_CRTC_V_SYNC_STRT_SHIFT 0
-# define R128_CRTC_V_SYNC_WID (0x1f << 16)
-# define R128_CRTC_V_SYNC_WID_SHIFT 16
-# define R128_CRTC_V_SYNC_POL (1 << 23)
-#define R128_CRTC_V_TOTAL_DISP 0x0208
-# define R128_CRTC_V_TOTAL (0x07ff << 0)
-# define R128_CRTC_V_TOTAL_SHIFT 0
-# define R128_CRTC_V_DISP (0x07ff << 16)
-# define R128_CRTC_V_DISP_SHIFT 16
-#define R128_CRTC_VLINE_CRNT_VLINE 0x0210
-# define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
-#define R128_CRTC2_CRNT_FRAME 0x0314
-#define R128_CRTC2_DEBUG 0x031c
-#define R128_CRTC2_GEN_CNTL 0x03f8
-# define R128_CRTC2_DBL_SCAN_EN (1 << 0)
-# define R128_CRTC2_CUR_EN (1 << 16)
-# define R128_CRTC2_ICON_EN (1 << 20)
-# define R128_CRTC2_DISP_DIS (1 << 23)
-# define R128_CRTC2_EN (1 << 25)
-# define R128_CRTC2_DISP_REQ_EN_B (1 << 26)
-#define R128_CRTC2_GUI_TRIG_VLINE 0x0318
-#define R128_CRTC2_H_SYNC_STRT_WID 0x0304
-# define R128_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
-# define R128_CRTC2_H_SYNC_STRT_CHAR (0x1ff << 3)
-# define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
-# define R128_CRTC2_H_SYNC_WID (0x3f << 16)
-# define R128_CRTC2_H_SYNC_WID_SHIFT 16
-# define R128_CRTC2_H_SYNC_POL (1 << 23)
-#define R128_CRTC2_H_TOTAL_DISP 0x0300
-# define R128_CRTC2_H_TOTAL (0x01ff << 0)
-# define R128_CRTC2_H_TOTAL_SHIFT 0
-# define R128_CRTC2_H_DISP (0x00ff << 16)
-# define R128_CRTC2_H_DISP_SHIFT 16
-#define R128_CRTC2_OFFSET 0x0324
-#define R128_CRTC2_OFFSET_CNTL 0x0328
-# define R128_CRTC2_TILE_EN (1 << 15)
-#define R128_CRTC2_PITCH 0x032c
-#define R128_CRTC2_STATUS 0x03fc
-#define R128_CRTC2_V_SYNC_STRT_WID 0x030c
-# define R128_CRTC2_V_SYNC_STRT (0x7ff << 0)
-# define R128_CRTC2_V_SYNC_STRT_SHIFT 0
-# define R128_CRTC2_V_SYNC_WID (0x1f << 16)
-# define R128_CRTC2_V_SYNC_WID_SHIFT 16
-# define R128_CRTC2_V_SYNC_POL (1 << 23)
-#define R128_CRTC2_V_TOTAL_DISP 0x0308
-# define R128_CRTC2_V_TOTAL (0x07ff << 0)
-# define R128_CRTC2_V_TOTAL_SHIFT 0
-# define R128_CRTC2_V_DISP (0x07ff << 16)
-# define R128_CRTC2_V_DISP_SHIFT 16
-#define R128_CRTC2_VLINE_CRNT_VLINE 0x0310
-#define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
-#define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
-#define R128_CUR_CLR0 0x026c
-#define R128_CUR_CLR1 0x0270
-#define R128_CUR_HORZ_VERT_OFF 0x0268
-#define R128_CUR_HORZ_VERT_POSN 0x0264
-#define R128_CUR_OFFSET 0x0260
-# define R128_CUR_LOCK (1 << 31)
-#define R128_CUR2_CLR0 0x036c
-#define R128_CUR2_CLR1 0x0370
-#define R128_CUR2_HORZ_VERT_OFF 0x0368
-#define R128_CUR2_HORZ_VERT_POSN 0x0364
-#define R128_CUR2_OFFSET 0x0360
-# define R128_CUR2_LOCK (1 << 31)
-
-#define R128_DAC_CNTL 0x0058
-# define R128_DAC_RANGE_CNTL (3 << 0)
-# define R128_DAC_BLANKING (1 << 2)
-# define R128_DAC_CRT_SEL_CRTC2 (1 << 4)
-# define R128_DAC_PALETTE_ACC_CTL (1 << 5)
-# define R128_DAC_PALETTE2_SNOOP_EN (1 << 6)
-# define R128_DAC_8BIT_EN (1 << 8)
-# define R128_DAC_VGA_ADR_EN (1 << 13)
-# define R128_DAC_MASK_ALL (0xff << 24)
-#define R128_DAC_CRC_SIG 0x02cc
-#define R128_DAC_DATA 0x03c9 /* VGA */
-#define R128_DAC_MASK 0x03c6 /* VGA */
-#define R128_DAC_R_INDEX 0x03c7 /* VGA */
-#define R128_DAC_W_INDEX 0x03c8 /* VGA */
-#define R128_DDA_CONFIG 0x02e0
-#define R128_DDA_ON_OFF 0x02e4
-#define R128_DDA2_CONFIG 0x03e0
-#define R128_DDA2_ON_OFF 0x03e4
-#define R128_DEFAULT_OFFSET 0x16e0
-#define R128_DEFAULT_PITCH 0x16e4
-#define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
-# define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
-# define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
-#define R128_DEFAULT2_OFFSET 0x16f8
-#define R128_DEFAULT2_PITCH 0x16fc
-#define R128_DEFAULT2_SC_BOTTOM_RIGHT 0x16dc
-#define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820
-#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824
-#define R128_DEVICE_ID 0x0f02 /* PCI */
-#define R128_DP_BRUSH_BKGD_CLR 0x1478
-#define R128_DP_BRUSH_FRGD_CLR 0x147c
-#define R128_DP_CNTL 0x16c0
-# define R128_DST_X_LEFT_TO_RIGHT (1 << 0)
-# define R128_DST_Y_TOP_TO_BOTTOM (1 << 1)
-#define R128_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
-# define R128_DST_Y_MAJOR (1 << 2)
-# define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
-# define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
-#define R128_DP_DATATYPE 0x16c4
-# define R128_HOST_BIG_ENDIAN_EN (1 << 29)
-#define R128_DP_GUI_MASTER_CNTL 0x146c
-# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
-# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
-# define R128_GMC_SRC_CLIPPING (1 << 2)
-# define R128_GMC_DST_CLIPPING (1 << 3)
-# define R128_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
-# define R128_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
-# define R128_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
-# define R128_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
-# define R128_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
-# define R128_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
-# define R128_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
-# define R128_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
-# define R128_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
-# define R128_GMC_BRUSH_8x8_COLOR (10 << 4)
-# define R128_GMC_BRUSH_1X8_COLOR (12 << 4)
-# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
-# define R128_GMC_BRUSH_NONE (15 << 4)
-# define R128_GMC_DST_8BPP_CI (2 << 8)
-# define R128_GMC_DST_15BPP (3 << 8)
-# define R128_GMC_DST_16BPP (4 << 8)
-# define R128_GMC_DST_24BPP (5 << 8)
-# define R128_GMC_DST_32BPP (6 << 8)
-# define R128_GMC_DST_8BPP_RGB (7 << 8)
-# define R128_GMC_DST_Y8 (8 << 8)
-# define R128_GMC_DST_RGB8 (9 << 8)
-# define R128_GMC_DST_VYUY (11 << 8)
-# define R128_GMC_DST_YVYU (12 << 8)
-# define R128_GMC_DST_AYUV444 (14 << 8)
-# define R128_GMC_DST_ARGB4444 (15 << 8)
-# define R128_GMC_DST_DATATYPE_MASK (0x0f << 8)
-# define R128_GMC_DST_DATATYPE_SHIFT 8
-# define R128_GMC_SRC_DATATYPE_MASK (3 << 12)
-# define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
-# define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
-# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
-# define R128_GMC_BYTE_PIX_ORDER (1 << 14)
-# define R128_GMC_BYTE_MSB_TO_LSB (0 << 14)
-# define R128_GMC_BYTE_LSB_TO_MSB (1 << 14)
-# define R128_GMC_CONVERSION_TEMP (1 << 15)
-# define R128_GMC_CONVERSION_TEMP_6500 (0 << 15)
-# define R128_GMC_CONVERSION_TEMP_9300 (1 << 15)
-# define R128_GMC_ROP3_MASK (0xff << 16)
-# define R128_DP_SRC_SOURCE_MASK (7 << 24)
-# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
-# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
-# define R128_GMC_3D_FCN_EN (1 << 27)
-# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
-# define R128_GMC_AUX_CLIP_DIS (1 << 29)
-# define R128_GMC_WR_MSK_DIS (1 << 30)
-# define R128_GMC_LD_BRUSH_Y_X (1 << 31)
-# define R128_ROP3_ZERO 0x00000000
-# define R128_ROP3_DSa 0x00880000
-# define R128_ROP3_SDna 0x00440000
-# define R128_ROP3_S 0x00cc0000
-# define R128_ROP3_DSna 0x00220000
-# define R128_ROP3_D 0x00aa0000
-# define R128_ROP3_DSx 0x00660000
-# define R128_ROP3_DSo 0x00ee0000
-# define R128_ROP3_DSon 0x00110000
-# define R128_ROP3_DSxn 0x00990000
-# define R128_ROP3_Dn 0x00550000
-# define R128_ROP3_SDno 0x00dd0000
-# define R128_ROP3_Sn 0x00330000
-# define R128_ROP3_DSno 0x00bb0000
-# define R128_ROP3_DSan 0x00770000
-# define R128_ROP3_ONE 0x00ff0000
-# define R128_ROP3_DPa 0x00a00000
-# define R128_ROP3_PDna 0x00500000
-# define R128_ROP3_P 0x00f00000
-# define R128_ROP3_DPna 0x000a0000
-# define R128_ROP3_D 0x00aa0000
-# define R128_ROP3_DPx 0x005a0000
-# define R128_ROP3_DPo 0x00fa0000
-# define R128_ROP3_DPon 0x00050000
-# define R128_ROP3_PDxn 0x00a50000
-# define R128_ROP3_PDno 0x00f50000
-# define R128_ROP3_Pn 0x000f0000
-# define R128_ROP3_DPno 0x00af0000
-# define R128_ROP3_DPan 0x005f0000
-
-
-#define R128_DP_GUI_MASTER_CNTL_C 0x1c84
-#define R128_DP_MIX 0x16c8
-#define R128_DP_SRC_BKGD_CLR 0x15dc
-#define R128_DP_SRC_FRGD_CLR 0x15d8
-#define R128_DP_WRITE_MASK 0x16cc
-#define R128_DST_BRES_DEC 0x1630
-#define R128_DST_BRES_ERR 0x1628
-#define R128_DST_BRES_INC 0x162c
-#define R128_DST_BRES_LNTH 0x1634
-#define R128_DST_BRES_LNTH_SUB 0x1638
-#define R128_DST_HEIGHT 0x1410
-#define R128_DST_HEIGHT_WIDTH 0x143c
-#define R128_DST_HEIGHT_WIDTH_8 0x158c
-#define R128_DST_HEIGHT_WIDTH_BW 0x15b4
-#define R128_DST_HEIGHT_Y 0x15a0
-#define R128_DST_OFFSET 0x1404
-#define R128_DST_PITCH 0x1408
-#define R128_DST_PITCH_OFFSET 0x142c
-#define R128_DST_PITCH_OFFSET_C 0x1c80
-# define R128_PITCH_SHIFT 21
-# define R128_DST_TILE (1 << 31)
-#define R128_DST_WIDTH 0x140c
-#define R128_DST_WIDTH_HEIGHT 0x1598
-#define R128_DST_WIDTH_X 0x1588
-#define R128_DST_WIDTH_X_INCY 0x159c
-#define R128_DST_X 0x141c
-#define R128_DST_X_SUB 0x15a4
-#define R128_DST_X_Y 0x1594
-#define R128_DST_Y 0x1420
-#define R128_DST_Y_SUB 0x15a8
-#define R128_DST_Y_X 0x1438
-
-#define R128_EXT_MEM_CNTL 0x0144
-
-#define R128_FCP_CNTL 0x0012 /* PLL */
-#define R128_FLUSH_1 0x1704
-#define R128_FLUSH_2 0x1708
-#define R128_FLUSH_3 0x170c
-#define R128_FLUSH_4 0x1710
-#define R128_FLUSH_5 0x1714
-#define R128_FLUSH_6 0x1718
-#define R128_FLUSH_7 0x171c
-#define R128_FOG_3D_TABLE_START 0x1810
-#define R128_FOG_3D_TABLE_END 0x1814
-#define R128_FOG_3D_TABLE_DENSITY 0x181c
-#define R128_FOG_TABLE_INDEX 0x1a14
-#define R128_FOG_TABLE_DATA 0x1a18
-#define R128_FP_CRTC_H_TOTAL_DISP 0x0250
-#define R128_FP_CRTC_V_TOTAL_DISP 0x0254
-#define R128_FP_GEN_CNTL 0x0284
-# define R128_FP_FPON (1 << 0)
-# define R128_FP_BLANK_DIS (1 << 1)
-# define R128_FP_TDMS_EN (1 << 2)
-# define R128_FP_DETECT_SENSE (1 << 8)
-# define R128_FP_SEL_CRTC2 (1 << 13)
-# define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
-# define R128_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
-# define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18)
-# define R128_FP_CRTC_USE_SHADOW_ROWCUR (1 << 19)
-# define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20)
-# define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21)
-# define R128_FP_CRT_SYNC_SEL (1 << 23)
-# define R128_FP_USE_SHADOW_EN (1 << 24)
-#define R128_FP_H_SYNC_STRT_WID 0x02c4
-#define R128_FP_HORZ_STRETCH 0x028c
-# define R128_HORZ_STRETCH_RATIO_MASK 0xffff
-# define R128_HORZ_STRETCH_RATIO_SHIFT 0
-# define R128_HORZ_STRETCH_RATIO_MAX 4096
-# define R128_HORZ_PANEL_SIZE (0xff << 16)
-# define R128_HORZ_PANEL_SHIFT 16
-# define R128_AUTO_HORZ_RATIO (0 << 24)
-# define R128_HORZ_STRETCH_PIXREP (0 << 25)
-# define R128_HORZ_STRETCH_BLEND (1 << 25)
-# define R128_HORZ_STRETCH_ENABLE (1 << 26)
-# define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27)
-# define R128_HORZ_STRETCH_RESERVED (1 << 30)
-# define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31)
-
-#define R128_FP_PANEL_CNTL 0x0288
-# define R128_FP_DIGON (1 << 0)
-# define R128_FP_BLON (1 << 1)
-#define R128_FP_V_SYNC_STRT_WID 0x02c8
-#define R128_FP_VERT_STRETCH 0x0290
-# define R128_VERT_PANEL_SIZE (0x7ff << 0)
-# define R128_VERT_PANEL_SHIFT 0
-# define R128_VERT_STRETCH_RATIO_MASK 0x3ff
-# define R128_VERT_STRETCH_RATIO_SHIFT 11
-# define R128_VERT_STRETCH_RATIO_MAX 1024
-# define R128_VERT_STRETCH_ENABLE (1 << 24)
-# define R128_VERT_STRETCH_LINEREP (0 << 25)
-# define R128_VERT_STRETCH_BLEND (1 << 25)
-# define R128_VERT_AUTO_RATIO_EN (1 << 26)
-# define R128_VERT_STRETCH_RESERVED 0xf8e00000
-
-#define R128_GEN_INT_CNTL 0x0040
-#define R128_GEN_INT_STATUS 0x0044
-# define R128_VSYNC_INT_AK (1 << 2)
-# define R128_VSYNC_INT (1 << 2)
-#define R128_GEN_RESET_CNTL 0x00f0
-# define R128_SOFT_RESET_GUI (1 << 0)
-# define R128_SOFT_RESET_VCLK (1 << 8)
-# define R128_SOFT_RESET_PCLK (1 << 9)
-# define R128_SOFT_RESET_DISPENG_XCLK (1 << 11)
-# define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12)
-#define R128_GENENB 0x03c3 /* VGA */
-#define R128_GENFC_RD 0x03ca /* VGA */
-#define R128_GENFC_WT 0x03da /* VGA, 0x03ba */
-#define R128_GENMO_RD 0x03cc /* VGA */
-#define R128_GENMO_WT 0x03c2 /* VGA */
-#define R128_GENS0 0x03c2 /* VGA */
-#define R128_GENS1 0x03da /* VGA, 0x03ba */
-#define R128_GPIO_MONID 0x0068
-# define R128_GPIO_MONID_A_0 (1 << 0)
-# define R128_GPIO_MONID_A_1 (1 << 1)
-# define R128_GPIO_MONID_A_2 (1 << 2)
-# define R128_GPIO_MONID_A_3 (1 << 3)
-# define R128_GPIO_MONID_Y_0 (1 << 8)
-# define R128_GPIO_MONID_Y_1 (1 << 9)
-# define R128_GPIO_MONID_Y_2 (1 << 10)
-# define R128_GPIO_MONID_Y_3 (1 << 11)
-# define R128_GPIO_MONID_EN_0 (1 << 16)
-# define R128_GPIO_MONID_EN_1 (1 << 17)
-# define R128_GPIO_MONID_EN_2 (1 << 18)
-# define R128_GPIO_MONID_EN_3 (1 << 19)
-# define R128_GPIO_MONID_MASK_0 (1 << 24)
-# define R128_GPIO_MONID_MASK_1 (1 << 25)
-# define R128_GPIO_MONID_MASK_2 (1 << 26)
-# define R128_GPIO_MONID_MASK_3 (1 << 27)
-#define R128_GPIO_MONIDB 0x006c
-#define R128_GRPH8_DATA 0x03cf /* VGA */
-#define R128_GRPH8_IDX 0x03ce /* VGA */
-#define R128_GUI_DEBUG0 0x16a0
-#define R128_GUI_DEBUG1 0x16a4
-#define R128_GUI_DEBUG2 0x16a8
-#define R128_GUI_DEBUG3 0x16ac
-#define R128_GUI_DEBUG4 0x16b0
-#define R128_GUI_DEBUG5 0x16b4
-#define R128_GUI_DEBUG6 0x16b8
-#define R128_GUI_PROBE 0x16bc
-#define R128_GUI_SCRATCH_REG0 0x15e0
-#define R128_GUI_SCRATCH_REG1 0x15e4
-#define R128_GUI_SCRATCH_REG2 0x15e8
-#define R128_GUI_SCRATCH_REG3 0x15ec
-#define R128_GUI_SCRATCH_REG4 0x15f0
-#define R128_GUI_SCRATCH_REG5 0x15f4
-#define R128_GUI_STAT 0x1740
-# define R128_GUI_FIFOCNT_MASK 0x0fff
-# define R128_GUI_ACTIVE (1 << 31)
-
-#define R128_HEADER 0x0f0e /* PCI */
-#define R128_HOST_DATA0 0x17c0
-#define R128_HOST_DATA1 0x17c4
-#define R128_HOST_DATA2 0x17c8
-#define R128_HOST_DATA3 0x17cc
-#define R128_HOST_DATA4 0x17d0
-#define R128_HOST_DATA5 0x17d4
-#define R128_HOST_DATA6 0x17d8
-#define R128_HOST_DATA7 0x17dc
-#define R128_HOST_DATA_LAST 0x17e0
-#define R128_HOST_PATH_CNTL 0x0130
-#define R128_HTOTAL_CNTL 0x0009 /* PLL */
-#define R128_HTOTAL2_CNTL 0x002e /* PLL */
-#define R128_HW_DEBUG 0x0128
-#define R128_HW_DEBUG2 0x011c
-
-#define R128_I2C_CNTL_1 0x0094 /* ? */
-#define R128_INTERRUPT_LINE 0x0f3c /* PCI */
-#define R128_INTERRUPT_PIN 0x0f3d /* PCI */
-#define R128_IO_BASE 0x0f14 /* PCI */
-
-#define R128_LATENCY 0x0f0d /* PCI */
-#define R128_LEAD_BRES_DEC 0x1608
-#define R128_LEAD_BRES_ERR 0x1600
-#define R128_LEAD_BRES_INC 0x1604
-#define R128_LEAD_BRES_LNTH 0x161c
-#define R128_LEAD_BRES_LNTH_SUB 0x1624
-#define R128_LVDS_GEN_CNTL 0x02d0
-# define R128_LVDS_ON (1 << 0)
-# define R128_LVDS_DISPLAY_DIS (1 << 1)
-# define R128_LVDS_EN (1 << 7)
-# define R128_LVDS_DIGON (1 << 18)
-# define R128_LVDS_BLON (1 << 19)
-# define R128_LVDS_SEL_CRTC2 (1 << 23)
-# define R128_HSYNC_DELAY_SHIFT 28
-# define R128_HSYNC_DELAY_MASK (0xf << 28)
-
-#define R128_MAX_LATENCY 0x0f3f /* PCI */
-#define R128_MCLK_CNTL 0x000f /* PLL */
-# define R128_FORCE_GCP (1 << 16)
-# define R128_FORCE_PIPE3D_CP (1 << 17)
-# define R128_FORCE_RCP (1 << 18)
-#define R128_MDGPIO_A_REG 0x01ac
-#define R128_MDGPIO_EN_REG 0x01b0
-#define R128_MDGPIO_MASK 0x0198
-#define R128_MDGPIO_Y_REG 0x01b4
-#define R128_MEM_ADDR_CONFIG 0x0148
-#define R128_MEM_BASE 0x0f10 /* PCI */
-#define R128_MEM_CNTL 0x0140
-#define R128_MEM_INIT_LAT_TIMER 0x0154
-#define R128_MEM_INTF_CNTL 0x014c
-#define R128_MEM_SDRAM_MODE_REG 0x0158
-#define R128_MEM_STR_CNTL 0x0150
-#define R128_MEM_VGA_RP_SEL 0x003c
-#define R128_MEM_VGA_WP_SEL 0x0038
-#define R128_MIN_GRANT 0x0f3e /* PCI */
-#define R128_MM_DATA 0x0004
-#define R128_MM_INDEX 0x0000
-#define R128_MPLL_CNTL 0x000e /* PLL */
-#define R128_MPP_TB_CONFIG 0x01c0 /* ? */
-#define R128_MPP_GP_CONFIG 0x01c8 /* ? */
-
-#define R128_N_VIF_COUNT 0x0248
-
-#define R128_OVR_CLR 0x0230
-#define R128_OVR_WID_LEFT_RIGHT 0x0234
-#define R128_OVR_WID_TOP_BOTTOM 0x0238
-
-/* first overlay unit (there is only one) */
-
-#define R128_OV0_Y_X_START 0x0400
-#define R128_OV0_Y_X_END 0x0404
-#define R128_OV0_EXCLUSIVE_HORZ 0x0408
-# define R128_EXCL_HORZ_START_MASK 0x000000ff
-# define R128_EXCL_HORZ_END_MASK 0x0000ff00
-# define R128_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
-# define R128_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
-#define R128_OV0_EXCLUSIVE_VERT 0x040C
-# define R128_EXCL_VERT_START_MASK 0x000003ff
-# define R128_EXCL_VERT_END_MASK 0x03ff0000
-#define R128_OV0_REG_LOAD_CNTL 0x0410
-# define R128_REG_LD_CTL_LOCK 0x00000001L
-# define R128_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
-# define R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
-# define R128_REG_LD_CTL_LOCK_READBACK 0x00000008L
-#define R128_OV0_SCALE_CNTL 0x0420
-# define R128_SCALER_PIX_EXPAND 0x00000001L
-# define R128_SCALER_Y2R_TEMP 0x00000002L
-# define R128_SCALER_HORZ_PICK_NEAREST 0x00000003L
-# define R128_SCALER_VERT_PICK_NEAREST 0x00000004L
-# define R128_SCALER_SIGNED_UV 0x00000010L
-# define R128_SCALER_GAMMA_SEL_MASK 0x00000060L
-# define R128_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
-# define R128_SCALER_GAMMA_SEL_G22 0x00000020L
-# define R128_SCALER_GAMMA_SEL_G18 0x00000040L
-# define R128_SCALER_GAMMA_SEL_G14 0x00000060L
-# define R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
-# define R128_SCALER_SURFAC_FORMAT 0x00000f00L
-# define R128_SCALER_SOURCE_15BPP 0x00000300L
-# define R128_SCALER_SOURCE_16BPP 0x00000400L
-# define R128_SCALER_SOURCE_32BPP 0x00000600L
-# define R128_SCALER_SOURCE_YUV9 0x00000900L
-# define R128_SCALER_SOURCE_YUV12 0x00000A00L
-# define R128_SCALER_SOURCE_VYUY422 0x00000B00L
-# define R128_SCALER_SOURCE_YVYU422 0x00000C00L
-# define R128_SCALER_SMART_SWITCH 0x00008000L
-# define R128_SCALER_BURST_PER_PLANE 0x00ff0000L
-# define R128_SCALER_DOUBLE_BUFFER 0x01000000L
-# define R128_SCALER_DIS_LIMIT 0x08000000L
-# define R128_SCALER_PRG_LOAD_START 0x10000000L
-# define R128_SCALER_INT_EMU 0x20000000L
-# define R128_SCALER_ENABLE 0x40000000L
-# define R128_SCALER_SOFT_RESET 0x80000000L
-#define R128_OV0_V_INC 0x0424
-#define R128_OV0_P1_V_ACCUM_INIT 0x0428
-# define R128_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
-# define R128_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
-#define R128_OV0_P23_V_ACCUM_INIT 0x042C
-#define R128_OV0_P1_BLANK_LINES_AT_TOP 0x0430
-# define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
-# define R128_P1_ACTIVE_LINES_M1 0x0fff0000L
-#define R128_OV0_P23_BLANK_LINES_AT_TOP 0x0434
-# define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
-# define R128_P23_ACTIVE_LINES_M1 0x07ff0000L
-#define R128_OV0_VID_BUF0_BASE_ADRS 0x0440
-# define R128_VIF_BUF0_PITCH_SEL 0x00000001L
-# define R128_VIF_BUF0_TILE_ADRS 0x00000002L
-# define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
-# define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
-#define R128_OV0_VID_BUF1_BASE_ADRS 0x0444
-# define R128_VIF_BUF1_PITCH_SEL 0x00000001L
-# define R128_VIF_BUF1_TILE_ADRS 0x00000002L
-# define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
-# define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
-#define R128_OV0_VID_BUF2_BASE_ADRS 0x0448
-# define R128_VIF_BUF2_PITCH_SEL 0x00000001L
-# define R128_VIF_BUF2_TILE_ADRS 0x00000002L
-# define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
-# define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
-#define R128_OV0_VID_BUF3_BASE_ADRS 0x044C
-#define R128_OV0_VID_BUF4_BASE_ADRS 0x0450
-#define R128_OV0_VID_BUF5_BASE_ADRS 0x0454
-#define R128_OV0_VID_BUF_PITCH0_VALUE 0x0460
-#define R128_OV0_VID_BUF_PITCH1_VALUE 0x0464
-#define R128_OV0_AUTO_FLIP_CNTL 0x0470
-#define R128_OV0_DEINTERLACE_PATTERN 0x0474
-#define R128_OV0_H_INC 0x0480
-#define R128_OV0_STEP_BY 0x0484
-#define R128_OV0_P1_H_ACCUM_INIT 0x0488
-#define R128_OV0_P23_H_ACCUM_INIT 0x048C
-#define R128_OV0_P1_X_START_END 0x0494
-#define R128_OV0_P2_X_START_END 0x0498
-#define R128_OV0_P3_X_START_END 0x049C
-#define R128_OV0_FILTER_CNTL 0x04A0
-#define R128_OV0_FOUR_TAP_COEF_0 0x04B0
-#define R128_OV0_FOUR_TAP_COEF_1 0x04B4
-#define R128_OV0_FOUR_TAP_COEF_2 0x04B8
-#define R128_OV0_FOUR_TAP_COEF_3 0x04BC
-#define R128_OV0_FOUR_TAP_COEF_4 0x04C0
-#define R128_OV0_COLOUR_CNTL 0x04E0
-#define R128_OV0_VIDEO_KEY_CLR 0x04E4
-#define R128_OV0_VIDEO_KEY_MSK 0x04E8
-#define R128_OV0_GRAPHICS_KEY_CLR 0x04EC
-#define R128_OV0_GRAPHICS_KEY_MSK 0x04F0
-#define R128_OV0_KEY_CNTL 0x04F4
-# define R128_VIDEO_KEY_FN_MASK 0x00000007L
-# define R128_VIDEO_KEY_FN_FALSE 0x00000000L
-# define R128_VIDEO_KEY_FN_TRUE 0x00000001L
-# define R128_VIDEO_KEY_FN_EQ 0x00000004L
-# define R128_VIDEO_KEY_FN_NE 0x00000005L
-# define R128_GRAPHIC_KEY_FN_MASK 0x00000070L
-# define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L
-# define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L
-# define R128_GRAPHIC_KEY_FN_EQ 0x00000040L
-# define R128_GRAPHIC_KEY_FN_NE 0x00000050L
-# define R128_CMP_MIX_MASK 0x00000100L
-# define R128_CMP_MIX_OR 0x00000000L
-# define R128_CMP_MIX_AND 0x00000100L
-#define R128_OV0_TEST 0x04F8
-
-
-#define R128_PALETTE_DATA 0x00b4
-#define R128_PALETTE_INDEX 0x00b0
-#define R128_PC_DEBUG_MODE 0x1760
-#define R128_PC_GUI_CTLSTAT 0x1748
-#define R128_PC_GUI_MODE 0x1744
-# define R128_PC_IGNORE_UNIFY (1 << 5)
-#define R128_PC_MISC_CNTL 0x0188
-#define R128_PC_NGUI_CTLSTAT 0x0184
-# define R128_PC_FLUSH_GUI (3 << 0)
-# define R128_PC_RI_GUI (1 << 2)
-# define R128_PC_FLUSH_ALL 0x00ff
-# define R128_PC_BUSY (1 << 31)
-#define R128_PC_NGUI_MODE 0x0180
-#define R128_PCI_GART_PAGE 0x017c
-#define R128_PLANE_3D_MASK_C 0x1d44
-#define R128_PLL_TEST_CNTL 0x0013 /* PLL */
-#define R128_PMI_CAP_ID 0x0f5c /* PCI */
-#define R128_PMI_DATA 0x0f63 /* PCI */
-#define R128_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
-#define R128_PMI_PMC_REG 0x0f5e /* PCI */
-#define R128_PMI_PMCSR_REG 0x0f60 /* PCI */
-#define R128_PMI_REGISTER 0x0f5c /* PCI */
-#define R128_PPLL_CNTL 0x0002 /* PLL */
-# define R128_PPLL_RESET (1 << 0)
-# define R128_PPLL_SLEEP (1 << 1)
-# define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16)
-# define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-#define R128_PPLL_DIV_0 0x0004 /* PLL */
-#define R128_PPLL_DIV_1 0x0005 /* PLL */
-#define R128_PPLL_DIV_2 0x0006 /* PLL */
-#define R128_PPLL_DIV_3 0x0007 /* PLL */
-# define R128_PPLL_FB3_DIV_MASK 0x07ff
-# define R128_PPLL_POST3_DIV_MASK 0x00070000
-#define R128_PPLL_REF_DIV 0x0003 /* PLL */
-# define R128_PPLL_REF_DIV_MASK 0x03ff
-# define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#define R128_P2PLL_CNTL 0x002a /* P2PLL */
-# define R128_P2PLL_RESET (1 << 0)
-# define R128_P2PLL_SLEEP (1 << 1)
-# define R128_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
-# define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define R128_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define R128_P2PLL_DIV_0 0x002c
-# define R128_P2PLL_FB0_DIV_MASK 0x07ff
-# define R128_P2PLL_POST0_DIV_MASK 0x00070000
-#define R128_P2PLL_REF_DIV 0x002B /* PLL */
-# define R128_P2PLL_REF_DIV_MASK 0x03ff
-# define R128_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define R128_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
-#define R128_REG_BASE 0x0f18 /* PCI */
-#define R128_REGPROG_INF 0x0f09 /* PCI */
-#define R128_REVISION_ID 0x0f08 /* PCI */
-
-#define R128_SC_BOTTOM 0x164c
-#define R128_SC_BOTTOM_RIGHT 0x16f0
-#define R128_SC_BOTTOM_RIGHT_C 0x1c8c
-#define R128_SC_LEFT 0x1640
-#define R128_SC_RIGHT 0x1644
-#define R128_SC_TOP 0x1648
-#define R128_SC_TOP_LEFT 0x16ec
-#define R128_SC_TOP_LEFT_C 0x1c88
-#define R128_SEQ8_DATA 0x03c5 /* VGA */
-#define R128_SEQ8_IDX 0x03c4 /* VGA */
-#define R128_SNAPSHOT_F_COUNT 0x0244
-#define R128_SNAPSHOT_VH_COUNTS 0x0240
-#define R128_SNAPSHOT_VIF_COUNT 0x024c
-#define R128_SRC_OFFSET 0x15ac
-#define R128_SRC_PITCH 0x15b0
-#define R128_SRC_PITCH_OFFSET 0x1428
-#define R128_SRC_SC_BOTTOM 0x165c
-#define R128_SRC_SC_BOTTOM_RIGHT 0x16f4
-#define R128_SRC_SC_RIGHT 0x1654
-#define R128_SRC_X 0x1414
-#define R128_SRC_X_Y 0x1590
-#define R128_SRC_Y 0x1418
-#define R128_SRC_Y_X 0x1434
-#define R128_STATUS 0x0f06 /* PCI */
-#define R128_SUBPIC_CNTL 0x0540 /* ? */
-#define R128_SUB_CLASS 0x0f0a /* PCI */
-#define R128_SURFACE_DELAY 0x0b00
-#define R128_SURFACE0_INFO 0x0b0c
-#define R128_SURFACE0_LOWER_BOUND 0x0b04
-#define R128_SURFACE0_UPPER_BOUND 0x0b08
-#define R128_SURFACE1_INFO 0x0b1c
-#define R128_SURFACE1_LOWER_BOUND 0x0b14
-#define R128_SURFACE1_UPPER_BOUND 0x0b18
-#define R128_SURFACE2_INFO 0x0b2c
-#define R128_SURFACE2_LOWER_BOUND 0x0b24
-#define R128_SURFACE2_UPPER_BOUND 0x0b28
-#define R128_SURFACE3_INFO 0x0b3c
-#define R128_SURFACE3_LOWER_BOUND 0x0b34
-#define R128_SURFACE3_UPPER_BOUND 0x0b38
-#define R128_SW_SEMAPHORE 0x013c
-
-#define R128_TEST_DEBUG_CNTL 0x0120
-#define R128_TEST_DEBUG_MUX 0x0124
-#define R128_TEST_DEBUG_OUT 0x012c
-#define R128_TMDS_CRC 0x02a0
-#define R128_TMDS_TRANSMITTER_CNTL 0x02a4
-# define R128_TMDS_PLLEN (1 << 0)
-# define R128_TMDS_PLLRST (1 << 1)
-#define R128_TRAIL_BRES_DEC 0x1614
-#define R128_TRAIL_BRES_ERR 0x160c
-#define R128_TRAIL_BRES_INC 0x1610
-#define R128_TRAIL_X 0x1618
-#define R128_TRAIL_X_SUB 0x1620
-
-#define R128_VCLK_ECP_CNTL 0x0008 /* PLL */
-# define R128_VCLK_SRC_SEL_MASK 0x03
-# define R128_VCLK_SRC_SEL_CPUCLK 0x00
-# define R128_VCLK_SRC_SEL_PPLLCLK 0x03
-# define R128_ECP_DIV_MASK (3 << 8)
-#define R128_V2CLK_VCLKTV_CNTL 0x002d /* PLL */
-# define R128_V2CLK_SRC_SEL_MASK 0x03
-# define R128_V2CLK_SRC_SEL_CPUCLK 0x00
-# define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03
-#define R128_VENDOR_ID 0x0f00 /* PCI */
-#define R128_VGA_DDA_CONFIG 0x02e8
-#define R128_VGA_DDA_ON_OFF 0x02ec
-#define R128_VID_BUFFER_CONTROL 0x0900
-#define R128_VIDEOMUX_CNTL 0x0190
-#define R128_VIPH_CONTROL 0x01D0 /* ? */
-
-#define R128_WAIT_UNTIL 0x1720
-
-#define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */
-#define R128_XCLK_CNTL 0x000d /* PLL */
-#define R128_XDLL_CNTL 0x000c /* PLL */
-#define R128_XPLL_CNTL 0x000b /* PLL */
-
- /* Registers for CCE and Microcode Engine */
-#define R128_PM4_MICROCODE_ADDR 0x07d4
-#define R128_PM4_MICROCODE_RADDR 0x07d8
-#define R128_PM4_MICROCODE_DATAH 0x07dc
-#define R128_PM4_MICROCODE_DATAL 0x07e0
-
-#define R128_PM4_BUFFER_OFFSET 0x0700
-#define R128_PM4_BUFFER_CNTL 0x0704
-# define R128_PM4_NONPM4 (0 << 28)
-# define R128_PM4_192PIO (1 << 28)
-# define R128_PM4_192BM (2 << 28)
-# define R128_PM4_128PIO_64INDBM (3 << 28)
-# define R128_PM4_128BM_64INDBM (4 << 28)
-# define R128_PM4_64PIO_128INDBM (5 << 28)
-# define R128_PM4_64BM_128INDBM (6 << 28)
-# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
-# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
-# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
-#define R128_PM4_BUFFER_WM_CNTL 0x0708
-# define R128_WMA_SHIFT 0
-# define R128_WMB_SHIFT 8
-# define R128_WMC_SHIFT 16
-# define R128_WB_WM_SHIFT 24
-#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
-#define R128_PM4_BUFFER_DL_RPTR 0x0710
-#define R128_PM4_BUFFER_DL_WPTR 0x0714
-# define R128_PM4_BUFFER_DL_DONE (1 << 31)
-#define R128_PM4_BUFFER_DL_WPTR_DELAY 0x0718
-# define R128_PRE_WRITE_TIMER_SHIFT 0
-# define R128_PRE_WRITE_LIMIT_SHIFT 23
-#define R128_PM4_VC_FPU_SETUP 0x071c
-# define R128_FRONT_DIR_CW (0 << 0)
-# define R128_FRONT_DIR_CCW (1 << 0)
-# define R128_FRONT_DIR_MASK (1 << 0)
-# define R128_BACKFACE_CULL (0 << 1)
-# define R128_BACKFACE_POINTS (1 << 1)
-# define R128_BACKFACE_LINES (2 << 1)
-# define R128_BACKFACE_SOLID (3 << 1)
-# define R128_BACKFACE_MASK (3 << 1)
-# define R128_FRONTFACE_CULL (0 << 3)
-# define R128_FRONTFACE_POINTS (1 << 3)
-# define R128_FRONTFACE_LINES (2 << 3)
-# define R128_FRONTFACE_SOLID (3 << 3)
-# define R128_FRONTFACE_MASK (3 << 3)
-# define R128_FPU_COLOR_SOLID (0 << 5)
-# define R128_FPU_COLOR_FLAT (1 << 5)
-# define R128_FPU_COLOR_GOURAUD (2 << 5)
-# define R128_FPU_COLOR_GOURAUD2 (3 << 5)
-# define R128_FPU_COLOR_MASK (3 << 5)
-# define R128_FPU_SUB_PIX_2BITS (0 << 7)
-# define R128_FPU_SUB_PIX_4BITS (1 << 7)
-# define R128_FPU_MODE_2D (0 << 8)
-# define R128_FPU_MODE_3D (1 << 8)
-# define R128_TRAP_BITS_DISABLE (1 << 9)
-# define R128_EDGE_ANTIALIAS (1 << 10)
-# define R128_SUPERSAMPLE (1 << 11)
-# define R128_XFACTOR_2 (0 << 12)
-# define R128_XFACTOR_4 (1 << 12)
-# define R128_YFACTOR_2 (0 << 13)
-# define R128_YFACTOR_4 (1 << 13)
-# define R128_FLAT_SHADE_VERTEX_D3D (0 << 14)
-# define R128_FLAT_SHADE_VERTEX_OGL (1 << 14)
-# define R128_FPU_ROUND_TRUNCATE (0 << 15)
-# define R128_FPU_ROUND_NEAREST (1 << 15)
-# define R128_WM_SEL_8DW (0 << 16)
-# define R128_WM_SEL_16DW (1 << 16)
-# define R128_WM_SEL_32DW (2 << 16)
-#define R128_PM4_VC_DEBUG_CONFIG 0x07a4
-#define R128_PM4_VC_STAT 0x07a8
-#define R128_PM4_VC_TIMESTAMP0 0x07b0
-#define R128_PM4_VC_TIMESTAMP1 0x07b4
-#define R128_PM4_STAT 0x07b8
-# define R128_PM4_FIFOCNT_MASK 0x0fff
-# define R128_PM4_BUSY (1 << 16)
-# define R128_PM4_GUI_ACTIVE (1 << 31)
-#define R128_PM4_BUFFER_ADDR 0x07f0
-#define R128_PM4_MICRO_CNTL 0x07fc
-# define R128_PM4_MICRO_FREERUN (1 << 30)
-#define R128_PM4_FIFO_DATA_EVEN 0x1000
-#define R128_PM4_FIFO_DATA_ODD 0x1004
-
-#define R128_SCALE_3D_CNTL 0x1a00
-# define R128_SCALE_DITHER_ERR_DIFF (0 << 1)
-# define R128_SCALE_DITHER_TABLE (1 << 1)
-# define R128_TEX_CACHE_SIZE_FULL (0 << 2)
-# define R128_TEX_CACHE_SIZE_HALF (1 << 2)
-# define R128_DITHER_INIT_CURR (0 << 3)
-# define R128_DITHER_INIT_RESET (1 << 3)
-# define R128_ROUND_24BIT (1 << 4)
-# define R128_TEX_CACHE_DISABLE (1 << 5)
-# define R128_SCALE_3D_NOOP (0 << 6)
-# define R128_SCALE_3D_SCALE (1 << 6)
-# define R128_SCALE_3D_TEXMAP_SHADE (2 << 6)
-# define R128_SCALE_PIX_BLEND (0 << 8)
-# define R128_SCALE_PIX_REPLICATE (1 << 8)
-# define R128_TEX_CACHE_SPLIT (1 << 9)
-# define R128_APPLE_YUV_MODE (1 << 10)
-# define R128_TEX_CACHE_PALLETE_MODE (1 << 11)
-# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12)
-# define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12)
-# define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12)
-# define R128_ALPHA_COMB_SUB_SRC_DST_NCLAMP (3 << 12)
-# define R128_ALPHA_COMB_FCN_MASK (3 << 12)
-# define R128_FOG_VERTEX (0 << 14)
-# define R128_FOG_TABLE (1 << 14)
-# define R128_SIGNED_DST_CLAMP (1 << 15)
-
-# define R128_ALPHA_BLEND_ZERO (0 )
-# define R128_ALPHA_BLEND_ONE (1 )
-# define R128_ALPHA_BLEND_SRCCOLOR (2 )
-# define R128_ALPHA_BLEND_INVSRCCOLOR (3 )
-# define R128_ALPHA_BLEND_SRCALPHA (4 )
-# define R128_ALPHA_BLEND_INVSRCALPHA (5 )
-# define R128_ALPHA_BLEND_DSTALPHA (6 )
-# define R128_ALPHA_BLEND_INVDSTALPHA (7 )
-# define R128_ALPHA_BLEND_DSTCOLOR (8 )
-# define R128_ALPHA_BLEND_INVDSTCOLOR (9 )
-# define R128_ALPHA_BLEND_SAT (10) /* aka SRCALPHASAT */
-# define R128_ALPHA_BLEND_BLEND (11) /* aka BOTHSRCALPHA */
-# define R128_ALPHA_BLEND_INVBLEND (12) /* aka BOTHINVSRCALPHA */
-# define R128_ALPHA_BLEND_MASK (15)
-
-# define R128_ALPHA_BLEND_SRC_SHIFT (16)
-# define R128_ALPHA_BLEND_DST_SHIFT (20)
-
-# define R128_ALPHA_TEST_NEVER (0 << 24)
-# define R128_ALPHA_TEST_LESS (1 << 24)
-# define R128_ALPHA_TEST_LESSEQUAL (2 << 24)
-# define R128_ALPHA_TEST_EQUAL (3 << 24)
-# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24)
-# define R128_ALPHA_TEST_GREATER (5 << 24)
-# define R128_ALPHA_TEST_NEQUAL (6 << 24)
-# define R128_ALPHA_TEST_ALWAYS (7 << 24)
-# define R128_ALPHA_TEST_MASK (7 << 24)
-# define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28)
-# define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28)
-# define R128_COMPOSITE_SHADOW (1 << 29)
-# define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30)
-# define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31)
-# define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31)
-#define R128_SCALE_3D_DATATYPE 0x1a20
-
-#define R128_SETUP_CNTL 0x1bc4
-# define R128_DONT_START_TRIANGLE (1 << 0)
-# define R128_Z_BIAS (0 << 1)
-# define R128_DONT_START_ANY_ON (1 << 2)
-# define R128_COLOR_SOLID_COLOR (0 << 3)
-# define R128_COLOR_FLAT_VERT_1 (1 << 3)
-# define R128_COLOR_FLAT_VERT_2 (2 << 3)
-# define R128_COLOR_FLAT_VERT_3 (3 << 3)
-# define R128_COLOR_GOURAUD (4 << 3)
-# define R128_PRIM_TYPE_TRI (0 << 7)
-# define R128_PRIM_TYPE_LINE (1 << 7)
-# define R128_PRIM_TYPE_POINT (2 << 7)
-# define R128_PRIM_TYPE_POLY_EDGE (3 << 7)
-# define R128_TEXTURE_ST_MULT_W (0 << 9)
-# define R128_TEXTURE_ST_DIRECT (1 << 9)
-# define R128_STARTING_VERTEX_1 (1 << 14)
-# define R128_STARTING_VERTEX_2 (2 << 14)
-# define R128_STARTING_VERTEX_3 (3 << 14)
-# define R128_ENDING_VERTEX_1 (1 << 16)
-# define R128_ENDING_VERTEX_2 (2 << 16)
-# define R128_ENDING_VERTEX_3 (3 << 16)
-# define R128_SU_POLY_LINE_LAST (0 << 18)
-# define R128_SU_POLY_LINE_NOT_LAST (1 << 18)
-# define R128_SUB_PIX_2BITS (0 << 19)
-# define R128_SUB_PIX_4BITS (1 << 19)
-# define R128_SET_UP_CONTINUE (1 << 31)
-
-#define R128_WINDOW_XY_OFFSET 0x1bcc
-# define R128_WINDOW_Y_SHIFT 4
-# define R128_WINDOW_X_SHIFT 20
-
-#define R128_Z_OFFSET_C 0x1c90
-#define R128_Z_PITCH_C 0x1c94
-# define R128_Z_TILE (1 << 16)
-#define R128_Z_STEN_CNTL_C 0x1c98
-# define R128_Z_PIX_WIDTH_16 (0 << 1)
-# define R128_Z_PIX_WIDTH_24 (1 << 1)
-# define R128_Z_PIX_WIDTH_32 (2 << 1)
-# define R128_Z_PIX_WIDTH_MASK (3 << 1)
-# define R128_Z_TEST_NEVER (0 << 4)
-# define R128_Z_TEST_LESS (1 << 4)
-# define R128_Z_TEST_LESSEQUAL (2 << 4)
-# define R128_Z_TEST_EQUAL (3 << 4)
-# define R128_Z_TEST_GREATEREQUAL (4 << 4)
-# define R128_Z_TEST_GREATER (5 << 4)
-# define R128_Z_TEST_NEQUAL (6 << 4)
-# define R128_Z_TEST_ALWAYS (7 << 4)
-# define R128_Z_TEST_MASK (7 << 4)
-# define R128_STENCIL_TEST_NEVER (0 << 12)
-# define R128_STENCIL_TEST_LESS (1 << 12)
-# define R128_STENCIL_TEST_LESSEQUAL (2 << 12)
-# define R128_STENCIL_TEST_EQUAL (3 << 12)
-# define R128_STENCIL_TEST_GREATEREQUAL (4 << 12)
-# define R128_STENCIL_TEST_GREATER (5 << 12)
-# define R128_STENCIL_TEST_NEQUAL (6 << 12)
-# define R128_STENCIL_TEST_ALWAYS (7 << 12)
-# define R128_STENCIL_S_FAIL_KEEP (0 << 16)
-# define R128_STENCIL_S_FAIL_ZERO (1 << 16)
-# define R128_STENCIL_S_FAIL_REPLACE (2 << 16)
-# define R128_STENCIL_S_FAIL_INC (3 << 16)
-# define R128_STENCIL_S_FAIL_DEC (4 << 16)
-# define R128_STENCIL_S_FAIL_INV (5 << 16)
-# define R128_STENCIL_ZPASS_KEEP (0 << 20)
-# define R128_STENCIL_ZPASS_ZERO (1 << 20)
-# define R128_STENCIL_ZPASS_REPLACE (2 << 20)
-# define R128_STENCIL_ZPASS_INC (3 << 20)
-# define R128_STENCIL_ZPASS_DEC (4 << 20)
-# define R128_STENCIL_ZPASS_INV (5 << 20)
-# define R128_STENCIL_ZFAIL_KEEP (0 << 24)
-# define R128_STENCIL_ZFAIL_ZERO (1 << 24)
-# define R128_STENCIL_ZFAIL_REPLACE (2 << 24)
-# define R128_STENCIL_ZFAIL_INC (3 << 24)
-# define R128_STENCIL_ZFAIL_DEC (4 << 24)
-# define R128_STENCIL_ZFAIL_INV (5 << 24)
-#define R128_TEX_CNTL_C 0x1c9c
-# define R128_Z_ENABLE (1 << 0)
-# define R128_Z_WRITE_ENABLE (1 << 1)
-# define R128_STENCIL_ENABLE (1 << 3)
-# define R128_SHADE_ENABLE (0 << 4)
-# define R128_TEXMAP_ENABLE (1 << 4)
-# define R128_SEC_TEXMAP_ENABLE (1 << 5)
-# define R128_FOG_ENABLE (1 << 7)
-# define R128_DITHER_ENABLE (1 << 8)
-# define R128_ALPHA_ENABLE (1 << 9)
-# define R128_ALPHA_TEST_ENABLE (1 << 10)
-# define R128_SPEC_LIGHT_ENABLE (1 << 11)
-# define R128_TEX_CHROMA_KEY_ENABLE (1 << 12)
-# define R128_ALPHA_IN_TEX_COMPLETE_A (0 << 13)
-# define R128_ALPHA_IN_TEX_LSB_A (1 << 13)
-# define R128_LIGHT_DIS (0 << 14)
-# define R128_LIGHT_COPY (1 << 14)
-# define R128_LIGHT_MODULATE (2 << 14)
-# define R128_LIGHT_ADD (3 << 14)
-# define R128_LIGHT_BLEND_CONSTANT (4 << 14)
-# define R128_LIGHT_BLEND_TEXTURE (5 << 14)
-# define R128_LIGHT_BLEND_VERTEX (6 << 14)
-# define R128_LIGHT_BLEND_CONST_COLOR (7 << 14)
-# define R128_ALPHA_LIGHT_DIS (0 << 18)
-# define R128_ALPHA_LIGHT_COPY (1 << 18)
-# define R128_ALPHA_LIGHT_MODULATE (2 << 18)
-# define R128_ALPHA_LIGHT_ADD (3 << 18)
-# define R128_ANTI_ALIAS (1 << 21)
-# define R128_TEX_CACHE_FLUSH (1 << 23)
-# define R128_LOD_BIAS_SHIFT 24
-# define R128_LOD_BIAS_MASK (0xff << 24)
-#define R128_MISC_3D_STATE_CNTL_REG 0x1ca0
-# define R128_REF_ALPHA_MASK 0xff
-# define R128_MISC_SCALE_3D_NOOP (0 << 8)
-# define R128_MISC_SCALE_3D_SCALE (1 << 8)
-# define R128_MISC_SCALE_3D_TEXMAP_SHADE (2 << 8)
-# define R128_MISC_SCALE_PIX_BLEND (0 << 10)
-# define R128_MISC_SCALE_PIX_REPLICATE (1 << 10)
-/* Bits [14:12] are the same as R128_SCALE_3D_CNTL */
-/* Bit [15] is unknown */
-/* Bits [26:16] are the same as R128_SCALE_3D_CNTL */
-/* Bits [31:27] are unknown */
-
-#define R128_TEXTURE_CLR_CMP_CLR_C 0x1ca4
-#define R128_TEXTURE_CLR_CMP_MSK_C 0x1ca8
-#define R128_FOG_COLOR_C 0x1cac
-# define R128_FOG_BLUE_SHIFT 0
-# define R128_FOG_GREEN_SHIFT 8
-# define R128_FOG_RED_SHIFT 16
-#define R128_PRIM_TEX_CNTL_C 0x1cb0
-# define R128_MIN_BLEND_NEAREST (0 << 1)
-# define R128_MIN_BLEND_LINEAR (1 << 1)
-# define R128_MIN_BLEND_MIPNEAREST (2 << 1)
-# define R128_MIN_BLEND_MIPLINEAR (3 << 1)
-# define R128_MIN_BLEND_LINEARMIPNEAREST (4 << 1)
-# define R128_MIN_BLEND_LINEARMIPLINEAR (5 << 1)
-# define R128_MIN_BLEND_MASK (7 << 1)
-# define R128_MAG_BLEND_NEAREST (0 << 4)
-# define R128_MAG_BLEND_LINEAR (1 << 4)
-# define R128_MAG_BLEND_MASK (7 << 4)
-# define R128_MIP_MAP_DISABLE (1 << 7)
-# define R128_TEX_CLAMP_S_WRAP (0 << 8)
-# define R128_TEX_CLAMP_S_MIRROR (1 << 8)
-# define R128_TEX_CLAMP_S_CLAMP (2 << 8)
-# define R128_TEX_CLAMP_S_BORDER_COLOR (3 << 8)
-# define R128_TEX_CLAMP_S_MASK (3 << 8)
-# define R128_TEX_WRAP_S (1 << 10)
-# define R128_TEX_CLAMP_T_WRAP (0 << 11)
-# define R128_TEX_CLAMP_T_MIRROR (1 << 11)
-# define R128_TEX_CLAMP_T_CLAMP (2 << 11)
-# define R128_TEX_CLAMP_T_BORDER_COLOR (3 << 11)
-# define R128_TEX_CLAMP_T_MASK (3 << 11)
-# define R128_TEX_WRAP_T (1 << 13)
-# define R128_TEX_PERSPECTIVE_DISABLE (1 << 14)
-# define R128_DATATYPE_VQ (0 << 16)
-# define R128_DATATYPE_CI4 (1 << 16)
-# define R128_DATATYPE_CI8 (2 << 16)
-# define R128_DATATYPE_ARGB1555 (3 << 16)
-# define R128_DATATYPE_RGB565 (4 << 16)
-# define R128_DATATYPE_RGB888 (5 << 16)
-# define R128_DATATYPE_ARGB8888 (6 << 16)
-# define R128_DATATYPE_RGB332 (7 << 16)
-# define R128_DATATYPE_Y8 (8 << 16)
-# define R128_DATATYPE_RGB8 (9 << 16)
-# define R128_DATATYPE_CI16 (10 << 16)
-# define R128_DATATYPE_YVYU422 (11 << 16)
-# define R128_DATATYPE_VYUY422 (12 << 16)
-# define R128_DATATYPE_AYUV444 (14 << 16)
-# define R128_DATATYPE_ARGB4444 (15 << 16)
-# define R128_PALLETE_EITHER (0 << 20)
-# define R128_PALLETE_1 (1 << 20)
-# define R128_PALLETE_2 (2 << 20)
-# define R128_PSEUDOCOLOR_DT_RGB565 (0 << 24)
-# define R128_PSEUDOCOLOR_DT_ARGB1555 (1 << 24)
-# define R128_PSEUDOCOLOR_DT_ARGB4444 (2 << 24)
-#define R128_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4
-# define R128_COMB_DIS (0 << 0)
-# define R128_COMB_COPY (1 << 0)
-# define R128_COMB_COPY_INP (2 << 0)
-# define R128_COMB_MODULATE (3 << 0)
-# define R128_COMB_MODULATE2X (4 << 0)
-# define R128_COMB_MODULATE4X (5 << 0)
-# define R128_COMB_ADD (6 << 0)
-# define R128_COMB_ADD_SIGNED (7 << 0)
-# define R128_COMB_BLEND_VERTEX (8 << 0)
-# define R128_COMB_BLEND_TEXTURE (9 << 0)
-# define R128_COMB_BLEND_CONST (10 << 0)
-# define R128_COMB_BLEND_PREMULT (11 << 0)
-# define R128_COMB_BLEND_PREV (12 << 0)
-# define R128_COMB_BLEND_PREMULT_INV (13 << 0)
-# define R128_COMB_ADD_SIGNED2X (14 << 0)
-# define R128_COMB_BLEND_CONST_COLOR (15 << 0)
-# define R128_COMB_MASK (15 << 0)
-# define R128_COLOR_FACTOR_CONST_COLOR (0 << 4)
-# define R128_COLOR_FACTOR_NCONST_COLOR (1 << 4)
-# define R128_COLOR_FACTOR_TEX (4 << 4)
-# define R128_COLOR_FACTOR_NTEX (5 << 4)
-# define R128_COLOR_FACTOR_ALPHA (6 << 4)
-# define R128_COLOR_FACTOR_NALPHA (7 << 4)
-# define R128_COLOR_FACTOR_PREV_COLOR (8 << 4)
-# define R128_COLOR_FACTOR_MASK (15 << 4)
-# define R128_COMB_FCN_MSB (1 << 8)
-# define R128_INPUT_FACTOR_CONST_COLOR (2 << 10)
-# define R128_INPUT_FACTOR_CONST_ALPHA (3 << 10)
-# define R128_INPUT_FACTOR_INT_COLOR (4 << 10)
-# define R128_INPUT_FACTOR_INT_ALPHA (5 << 10)
-# define R128_INPUT_FACTOR_MASK (15 << 10)
-# define R128_COMB_ALPHA_DIS (0 << 14)
-# define R128_COMB_ALPHA_COPY (1 << 14)
-# define R128_COMB_ALPHA_COPY_INP (2 << 14)
-# define R128_COMB_ALPHA_MODULATE (3 << 14)
-# define R128_COMB_ALPHA_MODULATE2X (4 << 14)
-# define R128_COMB_ALPHA_MODULATE4X (5 << 14)
-# define R128_COMB_ALPHA_ADD (6 << 14)
-# define R128_COMB_ALPHA_ADD_SIGNED (7 << 14)
-# define R128_COMB_ALPHA_ADD_SIGNED2X (14 << 14)
-# define R128_COMB_ALPHA_MASK (15 << 14)
-# define R128_ALPHA_FACTOR_TEX_ALPHA (6 << 18)
-# define R128_ALPHA_FACTOR_NTEX_ALPHA (7 << 18)
-# define R128_ALPHA_FACTOR_MASK (15 << 18)
-# define R128_INP_FACTOR_A_CONST_ALPHA (1 << 25)
-# define R128_INP_FACTOR_A_INT_ALPHA (2 << 25)
-# define R128_INP_FACTOR_A_MASK (7 << 25)
-#define R128_TEX_SIZE_PITCH_C 0x1cb8
-# define R128_TEX_PITCH_SHIFT 0
-# define R128_TEX_SIZE_SHIFT 4
-# define R128_TEX_HEIGHT_SHIFT 8
-# define R128_TEX_MIN_SIZE_SHIFT 12
-# define R128_SEC_TEX_PITCH_SHIFT 16
-# define R128_SEC_TEX_SIZE_SHIFT 20
-# define R128_SEC_TEX_HEIGHT_SHIFT 24
-# define R128_SEC_TEX_MIN_SIZE_SHIFT 28
-# define R128_TEX_PITCH_MASK (0x0f << 0)
-# define R128_TEX_SIZE_MASK (0x0f << 4)
-# define R128_TEX_HEIGHT_MASK (0x0f << 8)
-# define R128_TEX_MIN_SIZE_MASK (0x0f << 12)
-# define R128_SEC_TEX_PITCH_MASK (0x0f << 16)
-# define R128_SEC_TEX_SIZE_MASK (0x0f << 20)
-# define R128_SEC_TEX_HEIGHT_MASK (0x0f << 24)
-# define R128_SEC_TEX_MIN_SIZE_MASK (0x0f << 28)
-# define R128_TEX_SIZE_PITCH_SHIFT 0
-# define R128_SEC_TEX_SIZE_PITCH_SHIFT 16
-# define R128_TEX_SIZE_PITCH_MASK (0xffff << 0)
-# define R128_SEC_TEX_SIZE_PITCH_MASK (0xffff << 16)
-#define R128_PRIM_TEX_0_OFFSET_C 0x1cbc
-#define R128_PRIM_TEX_1_OFFSET_C 0x1cc0
-#define R128_PRIM_TEX_2_OFFSET_C 0x1cc4
-#define R128_PRIM_TEX_3_OFFSET_C 0x1cc8
-#define R128_PRIM_TEX_4_OFFSET_C 0x1ccc
-#define R128_PRIM_TEX_5_OFFSET_C 0x1cd0
-#define R128_PRIM_TEX_6_OFFSET_C 0x1cd4
-#define R128_PRIM_TEX_7_OFFSET_C 0x1cd8
-#define R128_PRIM_TEX_8_OFFSET_C 0x1cdc
-#define R128_PRIM_TEX_9_OFFSET_C 0x1ce0
-#define R128_PRIM_TEX_10_OFFSET_C 0x1ce4
-# define R128_TEX_NO_TILE (0 << 30)
-# define R128_TEX_TILED_BY_HOST (1 << 30)
-# define R128_TEX_TILED_BY_STORAGE (2 << 30)
-# define R128_TEX_TILED_BY_STORAGE2 (3 << 30)
-
-#define R128_SEC_TEX_CNTL_C 0x1d00
-# define R128_SEC_SELECT_PRIM_ST (0 << 0)
-# define R128_SEC_SELECT_SEC_ST (1 << 0)
-#define R128_SEC_TEX_COMBINE_CNTL_C 0x1d04
-# define R128_INPUT_FACTOR_PREV_COLOR (8 << 10)
-# define R128_INPUT_FACTOR_PREV_ALPHA (9 << 10)
-# define R128_INP_FACTOR_A_PREV_ALPHA (4 << 25)
-#define R128_SEC_TEX_0_OFFSET_C 0x1d08
-#define R128_SEC_TEX_1_OFFSET_C 0x1d0c
-#define R128_SEC_TEX_2_OFFSET_C 0x1d10
-#define R128_SEC_TEX_3_OFFSET_C 0x1d14
-#define R128_SEC_TEX_4_OFFSET_C 0x1d18
-#define R128_SEC_TEX_5_OFFSET_C 0x1d1c
-#define R128_SEC_TEX_6_OFFSET_C 0x1d20
-#define R128_SEC_TEX_7_OFFSET_C 0x1d24
-#define R128_SEC_TEX_8_OFFSET_C 0x1d28
-#define R128_SEC_TEX_9_OFFSET_C 0x1d2c
-#define R128_SEC_TEX_10_OFFSET_C 0x1d30
-#define R128_CONSTANT_COLOR_C 0x1d34
-# define R128_CONSTANT_BLUE_SHIFT 0
-# define R128_CONSTANT_GREEN_SHIFT 8
-# define R128_CONSTANT_RED_SHIFT 16
-# define R128_CONSTANT_ALPHA_SHIFT 24
-#define R128_PRIM_TEXTURE_BORDER_COLOR_C 0x1d38
-# define R128_PRIM_TEX_BORDER_BLUE_SHIFT 0
-# define R128_PRIM_TEX_BORDER_GREEN_SHIFT 8
-# define R128_PRIM_TEX_BORDER_RED_SHIFT 16
-# define R128_PRIM_TEX_BORDER_ALPHA_SHIFT 24
-#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
-# define R128_SEC_TEX_BORDER_BLUE_SHIFT 0
-# define R128_SEC_TEX_BORDER_GREEN_SHIFT 8
-# define R128_SEC_TEX_BORDER_RED_SHIFT 16
-# define R128_SEC_TEX_BORDER_ALPHA_SHIFT 24
-#define R128_STEN_REF_MASK_C 0x1d40
-# define R128_STEN_REFERENCE_SHIFT 0
-# define R128_STEN_MASK_SHIFT 16
-# define R128_STEN_WRITE_MASK_SHIFT 24
-#define R128_PLANE_3D_MASK_C 0x1d44
-#define R128_TEX_CACHE_STAT_COUNT 0x1974
-
-
- /* Constants */
-#define R128_AGP_TEX_OFFSET 0x02000000
-
-#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
-
- /* CCE packet types */
-#define R128_CCE_PACKET0 0x00000000
-#define R128_CCE_PACKET0_ONE_REG_WR 0x00008000
-#define R128_CCE_PACKET1 0x40000000
-#define R128_CCE_PACKET2 0x80000000
-#define R128_CCE_PACKET3 0xC0000000
-#define R128_CCE_PACKET3_NOP 0xC0001000
-#define R128_CCE_PACKET3_PAINT 0xC0001100
-#define R128_CCE_PACKET3_BITBLT 0xC0001200
-#define R128_CCE_PACKET3_SMALLTEXT 0xC0001300
-#define R128_CCE_PACKET3_HOSTDATA_BLT 0xC0001400
-#define R128_CCE_PACKET3_POLYLINE 0xC0001500
-#define R128_CCE_PACKET3_SCALING 0xC0001600
-#define R128_CCE_PACKET3_TRANS_SCALING 0xC0001700
-#define R128_CCE_PACKET3_POLYSCANLINES 0xC0001800
-#define R128_CCE_PACKET3_NEXT_CHAR 0xC0001900
-#define R128_CCE_PACKET3_PAINT_MULTI 0xC0001A00
-#define R128_CCE_PACKET3_BITBLT_MULTI 0xC0001B00
-#define R128_CCE_PACKET3_PLY_NEXTSCAN 0xC0001D00
-#define R128_CCE_PACKET3_SET_SCISSORS 0xC0001E00
-#define R128_CCE_PACKET3_SET_MODE24BPP 0xC0001F00
-#define R128_CCE_PACKET3_CNTL_PAINT 0xC0009100
-#define R128_CCE_PACKET3_CNTL_BITBLT 0xC0009200
-#define R128_CCE_PACKET3_CNTL_SMALLTEXT 0xC0009300
-#define R128_CCE_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
-#define R128_CCE_PACKET3_CNTL_POLYLINE 0xC0009500
-#define R128_CCE_PACKET3_CNTL_SCALING 0xC0009600
-#define R128_CCE_PACKET3_CNTL_TRANS_SCALING 0xC0009700
-#define R128_CCE_PACKET3_CNTL_POLYSCANLINES 0xC0009800
-#define R128_CCE_PACKET3_CNTL_NEXT_CHAR 0xC0009900
-#define R128_CCE_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
-#define R128_CCE_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
-#define R128_CCE_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
-#define R128_CCE_PACKET3_3D_SAVE_CONTEXT 0xC0002000
-#define R128_CCE_PACKET3_3D_PLAY_CONTEXT 0xC0002100
-#define R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
-#define R128_CCE_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500
-#define R128_CCE_PACKET3_LOAD_PALETTE 0xC0002C00
-#define R128_CCE_PACKET3_PURGE 0xC0002D00
-#define R128_CCE_PACKET3_NEXT_VERTEX_BUNDLE 0xC0002E00
-# define R128_CCE_PACKET_MASK 0xC0000000
-# define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
-# define R128_CCE_PACKET_MAX_DWORDS (1 << 12)
-# define R128_CCE_PACKET0_REG_MASK 0x000007ff
-# define R128_CCE_PACKET1_REG0_MASK 0x000007ff
-# define R128_CCE_PACKET1_REG1_MASK 0x003ff800
-
-#define R128_CCE_VC_FRMT_RHW 0x00000001
-#define R128_CCE_VC_FRMT_DIFFUSE_BGR 0x00000002
-#define R128_CCE_VC_FRMT_DIFFUSE_A 0x00000004
-#define R128_CCE_VC_FRMT_DIFFUSE_ARGB 0x00000008
-#define R128_CCE_VC_FRMT_SPEC_BGR 0x00000010
-#define R128_CCE_VC_FRMT_SPEC_F 0x00000020
-#define R128_CCE_VC_FRMT_SPEC_FRGB 0x00000040
-#define R128_CCE_VC_FRMT_S_T 0x00000080
-#define R128_CCE_VC_FRMT_S2_T2 0x00000100
-#define R128_CCE_VC_FRMT_RHW2 0x00000200
-
-#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
-#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
-#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
-#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
-#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
-#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
-#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
-#define R128_CCE_VC_CNTL_NUM_SHIFT 16
-
-/* hmm copyed blindly (no specs) from radeon.h ... */
-#define R128_RE_TOP_LEFT 0x26c0
-# define R128_RE_LEFT_SHIFT 0
-# define R128_RE_TOP_SHIFT 16
-#define R128_RE_WIDTH_HEIGHT 0x1c44
-# define R128_RE_WIDTH_SHIFT 0
-# define R128_RE_HEIGHT_SHIFT 16
-
-#endif
diff --git a/src/r128_sarea.h b/src/r128_sarea.h
deleted file mode 100644
index 70f9122..0000000
--- a/src/r128_sarea.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- * Precision Insight, Inc., Cedar Park, Texas, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at valinux.com>
- * Gareth Hughes <gareth at valinux.com>
- *
- */
-
-#ifndef _R128_SAREA_H_
-#define _R128_SAREA_H_
-
-#include <X11/Xmd.h>
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the kernel file (r128_drm.h)
- */
-#ifndef __R128_SAREA_DEFINES__
-#define __R128_SAREA_DEFINES__
-
-/* What needs to be changed for the current vertex buffer?
- */
-#define R128_UPLOAD_CONTEXT 0x001
-#define R128_UPLOAD_SETUP 0x002
-#define R128_UPLOAD_TEX0 0x004
-#define R128_UPLOAD_TEX1 0x008
-#define R128_UPLOAD_TEX0IMAGES 0x010
-#define R128_UPLOAD_TEX1IMAGES 0x020
-#define R128_UPLOAD_CORE 0x040
-#define R128_UPLOAD_MASKS 0x080
-#define R128_UPLOAD_WINDOW 0x100
-#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
-#define R128_REQUIRE_QUIESCENCE 0x400
-#define R128_UPLOAD_ALL 0x7ff
-
-#define R128_FRONT 0x1
-#define R128_BACK 0x2
-#define R128_DEPTH 0x4
-
-/* Primitive types
- */
-#define R128_POINTS 0x1
-#define R128_LINES 0x2
-#define R128_LINE_STRIP 0x3
-#define R128_TRIANGLES 0x4
-#define R128_TRIANGLE_FAN 0x5
-#define R128_TRIANGLE_STRIP 0x6
-
-/* Vertex/indirect buffer size
- */
-#define R128_BUFFER_SIZE 16384
-
-/* Byte offsets for indirect buffer data
- */
-#define R128_INDEX_PRIM_OFFSET 20
-#define R128_HOSTDATA_BLIT_OFFSET 32
-
-/* Keep these small for testing
- */
-#define R128_NR_SAREA_CLIPRECTS 12
-
-/* There are 2 heaps (local/AGP). Each region within a heap is a
- * minimum of 64k, and there are at most 64 of them per heap.
- */
-#define R128_CARD_HEAP 0
-#define R128_AGP_HEAP 1
-#define R128_NR_TEX_HEAPS 2
-#define R128_NR_TEX_REGIONS 64
-#define R128_LOG_TEX_GRANULARITY 16
-
-#define R128_NR_CONTEXT_REGS 12
-
-#define R128_MAX_TEXTURE_LEVELS 11
-#define R128_MAX_TEXTURE_UNITS 2
-
-#endif /* __R128_SAREA_DEFINES__ */
-
-typedef struct {
- /* Context state - can be written in one large chunk */
- unsigned int dst_pitch_offset_c;
- unsigned int dp_gui_master_cntl_c;
- unsigned int sc_top_left_c;
- unsigned int sc_bottom_right_c;
- unsigned int z_offset_c;
- unsigned int z_pitch_c;
- unsigned int z_sten_cntl_c;
- unsigned int tex_cntl_c;
- unsigned int misc_3d_state_cntl_reg;
- unsigned int texture_clr_cmp_clr_c;
- unsigned int texture_clr_cmp_msk_c;
- unsigned int fog_color_c;
-
- /* Texture state */
- unsigned int tex_size_pitch_c;
- unsigned int constant_color_c;
-
- /* Setup state */
- unsigned int pm4_vc_fpu_setup;
- unsigned int setup_cntl;
-
- /* Mask state */
- unsigned int dp_write_mask;
- unsigned int sten_ref_mask_c;
- unsigned int plane_3d_mask_c;
-
- /* Window state */
- unsigned int window_xy_offset;
-
- /* Core state */
- unsigned int scale_3d_cntl;
-} r128_context_regs_t;
-
-/* Setup registers for each texture unit
- */
-typedef struct {
- unsigned int tex_cntl;
- unsigned int tex_combine_cntl;
- unsigned int tex_size_pitch;
- unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
- unsigned int tex_border_color;
-} r128_texture_regs_t;
-
-typedef struct {
- /* The channel for communication of state information to the kernel
- * on firing a vertex buffer.
- */
- r128_context_regs_t ContextState;
- r128_texture_regs_t TexState[R128_MAX_TEXTURE_UNITS];
- unsigned int dirty;
- unsigned int vertsize;
- unsigned int vc_format;
-
- /* The current cliprects, or a subset thereof.
- */
- drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
- unsigned int nbox;
-
- /* Counters for throttling of rendering clients.
- */
- unsigned int last_frame;
- unsigned int last_dispatch;
-
- /* Maintain an LRU of contiguous regions of texture space. If you
- * think you own a region of texture memory, and it has an age
- * different to the one you set, then you are mistaken and it has
- * been stolen by another client. If global texAge hasn't changed,
- * there is no need to walk the list.
- *
- * These regions can be used as a proxy for the fine-grained texture
- * information of other clients - by maintaining them in the same
- * lru which is used to age their own textures, clients have an
- * approximate lru for the whole of global texture space, and can
- * make informed decisions as to which areas to kick out. There is
- * no need to choose whether to kick out your own texture or someone
- * else's - simply eject them all in LRU order.
- */
- /* Last elt is sentinal */
- drmTextureRegion texList[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
- /* last time texture was uploaded */
- unsigned int texAge[R128_NR_TEX_HEAPS];
-
- int ctxOwner; /* last context to upload state */
- int pfAllowPageFlip; /* set by the 2d driver, read by the client */
- int pfCurrentPage; /* set by kernel, read by others */
-} R128SAREAPriv, *R128SAREAPrivPtr;
-
-#endif
diff --git a/src/r128_version.h b/src/r128_version.h
deleted file mode 100644
index 3e02a90..0000000
--- a/src/r128_version.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _R128_VERSION_H_
-#define _R128_VERSION_H_ 1
-
-#undef R128_NAME
-#undef R128_DRIVER_NAME
-#undef R128_VERSION_MAJOR
-#undef R128_VERSION_MINOR
-#undef R128_VERSION_PATCH
-#undef R128_VERSION_CURRENT
-#undef R128_VERSION_EVALUATE
-#undef R128_VERSION_STRINGIFY
-#undef R128_VERSION_NAME
-
-#define R128_NAME "R128"
-#define R128_DRIVER_NAME "r128"
-
-#define R128_VERSION_MAJOR 4
-#define R128_VERSION_MINOR 1
-#define R128_VERSION_PATCH 0
-
-#ifndef R128_VERSION_EXTRA
-#define R128_VERSION_EXTRA ""
-#endif
-
-#define R128_VERSION_CURRENT \
- ((R128_VERSION_MAJOR << 20) | \
- (R128_VERSION_MINOR << 10) | \
- (R128_VERSION_PATCH))
-
-#define R128_VERSION_EVALUATE(__x) #__x
-#define R128_VERSION_STRINGIFY(_x) R128_VERSION_EVALUATE(_x)
-#define R128_VERSION_NAME \
- R128_VERSION_STRINGIFY(R128_VERSION_MAJOR) "." \
- R128_VERSION_STRINGIFY(R128_VERSION_MINOR) "." \
- R128_VERSION_STRINGIFY(R128_VERSION_MINOR) R128_VERSION_EXTRA
-
-#endif /* _R128_VERSION_H_ */
diff --git a/src/r128_video.c b/src/r128_video.c
deleted file mode 100644
index 8e83323..0000000
--- a/src/r128_video.c
+++ /dev/null
@@ -1,1028 +0,0 @@
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
-#include "r128.h"
-#include "r128_reg.h"
-
-#ifdef XF86DRI
-#include "r128_common.h"
-#include "r128_sarea.h"
-#endif
-
-#include "xf86.h"
-#include "dixstruct.h"
-
-#include <X11/extensions/Xv.h>
-#include "fourcc.h"
-
-#define OFF_DELAY 250 /* milliseconds */
-#define FREE_DELAY 15000
-
-#define OFF_TIMER 0x01
-#define FREE_TIMER 0x02
-#define CLIENT_VIDEO_ON 0x04
-
-#define TIMER_MASK (OFF_TIMER | FREE_TIMER)
-
-static XF86VideoAdaptorPtr R128SetupImageVideo(ScreenPtr);
-static int R128SetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer);
-static int R128GetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer);
-static void R128StopVideo(ScrnInfoPtr, pointer, Bool);
-static void R128QueryBestSize(ScrnInfoPtr, Bool, short, short, short, short,
- unsigned int *, unsigned int *, pointer);
-static int R128PutImage(ScrnInfoPtr, short, short, short, short, short,
- short, short, short, int, unsigned char*, short,
- short, Bool, RegionPtr, pointer, DrawablePtr);
-static int R128QueryImageAttributes(ScrnInfoPtr, int, unsigned short *,
- unsigned short *, int *, int *);
-
-
-static void R128ResetVideo(ScrnInfoPtr);
-
-static void R128VideoTimerCallback(ScrnInfoPtr pScrn, Time now);
-
-
-#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
-
-static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer;
-
-
-typedef struct {
- int brightness;
- int saturation;
- Bool doubleBuffer;
- unsigned char currentBuffer;
- FBLinearPtr linear;
- RegionRec clip;
- CARD32 colorKey;
- CARD32 videoStatus;
- Time offTime;
- Time freeTime;
- int ecp_div;
-} R128PortPrivRec, *R128PortPrivPtr;
-
-static void R128ECP(ScrnInfoPtr pScrn, R128PortPrivPtr pPriv)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- int dot_clock = info->ModeReg.dot_clock_freq;
-
- if (dot_clock < 12500) pPriv->ecp_div = 0;
- else if (dot_clock < 25000) pPriv->ecp_div = 1;
- else pPriv->ecp_div = 2;
-
- OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, pPriv->ecp_div<<8, ~R128_ECP_DIV_MASK);
-}
-
-void R128InitVideo(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL;
- XF86VideoAdaptorPtr newAdaptor = NULL;
- int num_adaptors;
-
- newAdaptor = R128SetupImageVideo(pScreen);
-
- num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors);
-
- if(newAdaptor) {
- if(!num_adaptors) {
- num_adaptors = 1;
- adaptors = &newAdaptor;
- } else {
- newAdaptors = /* need to free this someplace */
- xalloc((num_adaptors + 1) * sizeof(XF86VideoAdaptorPtr*));
- if(newAdaptors) {
- memcpy(newAdaptors, adaptors, num_adaptors *
- sizeof(XF86VideoAdaptorPtr));
- newAdaptors[num_adaptors] = newAdaptor;
- adaptors = newAdaptors;
- num_adaptors++;
- }
- }
- }
-
- if(num_adaptors)
- xf86XVScreenInit(pScreen, adaptors, num_adaptors);
-
- if(newAdaptors)
- xfree(newAdaptors);
-}
-
-#define MAXWIDTH 2048
-#define MAXHEIGHT 2048
-
-/* client libraries expect an encoding */
-static XF86VideoEncodingRec DummyEncoding =
-{
- 0,
- "XV_IMAGE",
- MAXWIDTH, MAXHEIGHT,
- {1, 1}
-};
-
-#define NUM_FORMATS 12
-
-static XF86VideoFormatRec Formats[NUM_FORMATS] =
-{
- {8, TrueColor}, {8, DirectColor}, {8, PseudoColor},
- {8, GrayScale}, {8, StaticGray}, {8, StaticColor},
- {15, TrueColor}, {16, TrueColor}, {24, TrueColor},
- {15, DirectColor}, {16, DirectColor}, {24, DirectColor}
-};
-
-
-#define NUM_ATTRIBUTES 4
-
-static XF86AttributeRec Attributes[NUM_ATTRIBUTES] =
-{
- {XvSettable | XvGettable, 0, (1 << 24) - 1, "XV_COLORKEY"},
- {XvSettable | XvGettable, -64, 63, "XV_BRIGHTNESS"},
- {XvSettable | XvGettable, 0, 31, "XV_SATURATION"},
- {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}
-};
-
-#define NUM_IMAGES 4
-
-static XF86ImageRec Images[NUM_IMAGES] =
-{
- XVIMAGE_YUY2,
- XVIMAGE_UYVY,
- XVIMAGE_YV12,
- XVIMAGE_I420
-};
-
-static void
-R128ResetVideo(ScrnInfoPtr pScrn)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128PortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
-
-
- OUTREG(R128_OV0_SCALE_CNTL, 0x80000000);
- OUTREG(R128_OV0_EXCLUSIVE_HORZ, 0);
- OUTREG(R128_OV0_AUTO_FLIP_CNTL, 0); /* maybe */
- OUTREG(R128_OV0_FILTER_CNTL, 0x0000000f);
- OUTREG(R128_OV0_COLOUR_CNTL, (pPriv->brightness & 0x7f) |
- (pPriv->saturation << 8) |
- (pPriv->saturation << 16));
- OUTREG(R128_OV0_GRAPHICS_KEY_MSK, (1 << pScrn->depth) - 1);
- OUTREG(R128_OV0_GRAPHICS_KEY_CLR, pPriv->colorKey);
- OUTREG(R128_OV0_KEY_CNTL, R128_GRAPHIC_KEY_FN_NE);
- OUTREG(R128_OV0_TEST, 0);
-}
-
-
-static XF86VideoAdaptorPtr
-R128AllocAdaptor(ScrnInfoPtr pScrn)
-{
- XF86VideoAdaptorPtr adapt;
- R128InfoPtr info = R128PTR(pScrn);
- R128PortPrivPtr pPriv;
-
- if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn)))
- return NULL;
-
- if(!(pPriv = xcalloc(1, sizeof(R128PortPrivRec) + sizeof(DevUnion))))
- {
- xfree(adapt);
- return NULL;
- }
-
- adapt->pPortPrivates = (DevUnion*)(&pPriv[1]);
- adapt->pPortPrivates[0].ptr = (pointer)pPriv;
-
- xvBrightness = MAKE_ATOM("XV_BRIGHTNESS");
- xvSaturation = MAKE_ATOM("XV_SATURATION");
- xvColorKey = MAKE_ATOM("XV_COLORKEY");
- xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER");
-
- pPriv->colorKey = info->videoKey;
- pPriv->doubleBuffer = TRUE;
- pPriv->videoStatus = 0;
- pPriv->brightness = 0;
- pPriv->saturation = 16;
- pPriv->currentBuffer = 0;
- R128ECP(pScrn, pPriv);
-
- return adapt;
-}
-
-static XF86VideoAdaptorPtr
-R128SetupImageVideo(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- R128InfoPtr info = R128PTR(pScrn);
- R128PortPrivPtr pPriv;
- XF86VideoAdaptorPtr adapt;
-
- if(!(adapt = R128AllocAdaptor(pScrn)))
- return NULL;
-
- adapt->type = XvWindowMask | XvInputMask | XvImageMask;
- adapt->flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT;
- adapt->name = "ATI Rage128 Video Overlay";
- adapt->nEncodings = 1;
- adapt->pEncodings = &DummyEncoding;
- adapt->nFormats = NUM_FORMATS;
- adapt->pFormats = Formats;
- adapt->nPorts = 1;
- adapt->nAttributes = NUM_ATTRIBUTES;
- adapt->pAttributes = Attributes;
- adapt->nImages = NUM_IMAGES;
- adapt->pImages = Images;
- adapt->PutVideo = NULL;
- adapt->PutStill = NULL;
- adapt->GetVideo = NULL;
- adapt->GetStill = NULL;
- adapt->StopVideo = R128StopVideo;
- adapt->SetPortAttribute = R128SetPortAttribute;
- adapt->GetPortAttribute = R128GetPortAttribute;
- adapt->QueryBestSize = R128QueryBestSize;
- adapt->PutImage = R128PutImage;
- adapt->QueryImageAttributes = R128QueryImageAttributes;
-
- info->adaptor = adapt;
-
- pPriv = (R128PortPrivPtr)(adapt->pPortPrivates[0].ptr);
- REGION_NULL(pScreen, &(pPriv->clip));
-
- R128ResetVideo(pScrn);
-
- return adapt;
-}
-
-static void
-R128StopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
-{
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128PortPrivPtr pPriv = (R128PortPrivPtr)data;
-
- REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
-
- if(cleanup) {
- if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
- OUTREG(R128_OV0_SCALE_CNTL, 0);
- }
- if(pPriv->linear) {
- xf86FreeOffscreenLinear(pPriv->linear);
- pPriv->linear = NULL;
- }
- pPriv->videoStatus = 0;
- } else {
- if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
- pPriv->videoStatus |= OFF_TIMER;
- pPriv->offTime = currentTime.milliseconds + OFF_DELAY;
- }
- }
-}
-
-static int
-R128SetPortAttribute(
- ScrnInfoPtr pScrn,
- Atom attribute,
- INT32 value,
- pointer data
-){
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128PortPrivPtr pPriv = (R128PortPrivPtr)data;
-
- if(attribute == xvBrightness) {
- if((value < -64) || (value > 63))
- return BadValue;
- pPriv->brightness = value;
-
- OUTREG(R128_OV0_COLOUR_CNTL, (pPriv->brightness & 0x7f) |
- (pPriv->saturation << 8) |
- (pPriv->saturation << 16));
- } else
- if(attribute == xvSaturation) {
- if((value < 0) || (value > 31))
- return BadValue;
- pPriv->saturation = value;
-
- OUTREG(R128_OV0_COLOUR_CNTL, (pPriv->brightness & 0x7f) |
- (pPriv->saturation << 8) |
- (pPriv->saturation << 16));
- } else
- if(attribute == xvDoubleBuffer) {
- if((value < 0) || (value > 1))
- return BadValue;
- pPriv->doubleBuffer = value;
- } else
- if(attribute == xvColorKey) {
- pPriv->colorKey = value;
- OUTREG(R128_OV0_GRAPHICS_KEY_CLR, pPriv->colorKey);
-
- REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
- } else return BadMatch;
-
- return Success;
-}
-
-static int
-R128GetPortAttribute(
- ScrnInfoPtr pScrn,
- Atom attribute,
- INT32 *value,
- pointer data
-){
- R128PortPrivPtr pPriv = (R128PortPrivPtr)data;
-
- if(attribute == xvBrightness) {
- *value = pPriv->brightness;
- } else
- if(attribute == xvSaturation) {
- *value = pPriv->saturation;
- } else
- if(attribute == xvDoubleBuffer) {
- *value = pPriv->doubleBuffer ? 1 : 0;
- } else
- if(attribute == xvColorKey) {
- *value = pPriv->colorKey;
- } else return BadMatch;
-
- return Success;
-}
-
-
-static void
-R128QueryBestSize(
- ScrnInfoPtr pScrn,
- Bool motion,
- short vid_w, short vid_h,
- short drw_w, short drw_h,
- unsigned int *p_w, unsigned int *p_h,
- pointer data
-){
- if(vid_w > (drw_w << 4))
- drw_w = vid_w >> 4;
- if(vid_h > (drw_h << 4))
- drw_h = vid_h >> 4;
-
- *p_w = drw_w;
- *p_h = drw_h;
-}
-
-
-/*
- *
- * R128DMA - abuse the texture blit ioctl to transfer rectangular blocks
- *
- * The block is split into 'passes' pieces of 'hpass' lines which fit entirely
- * into an indirect buffer
- *
- */
-
-static Bool
-R128DMA(
- R128InfoPtr info,
- unsigned char *src,
- unsigned char *dst,
- int srcPitch,
- int dstPitch,
- int h,
- int w
-){
-
-#ifdef XF86DRI
-
-#define BUFSIZE (R128_BUFFER_SIZE - R128_HOSTDATA_BLIT_OFFSET)
-#define MAXPASSES (MAXHEIGHT/(BUFSIZE/(MAXWIDTH*2))+1)
-
- unsigned char *fb = (CARD8*)info->FB;
- unsigned char *buf;
- int err=-1, i, idx, offset, hpass, passes, srcpassbytes, dstpassbytes;
- int sizes[MAXPASSES], list[MAXPASSES];
- drmDMAReq req;
- drmR128Blit blit;
-
- /* Verify conditions and bail out as early as possible */
- if (!info->directRenderingEnabled || !info->DMAForXv)
- return FALSE;
-
- if ((hpass = min(h,(BUFSIZE/w))) == 0)
- return FALSE;
-
- if ((passes = (h+hpass-1)/hpass) > MAXPASSES)
- return FALSE;
-
- /* Request indirect buffers */
- srcpassbytes = w*hpass;
-
- req.context = info->drmCtx;
- req.send_count = 0;
- req.send_list = NULL;
- req.send_sizes = NULL;
- req.flags = DRM_DMA_LARGER_OK;
- req.request_count = passes;
- req.request_size = srcpassbytes + R128_HOSTDATA_BLIT_OFFSET;
- req.request_list = &list[0];
- req.request_sizes = &sizes[0];
- req.granted_count = 0;
-
- if (drmDMA(info->drmFD, &req))
- return FALSE;
-
- if (req.granted_count < passes) {
- drmFreeBufs(info->drmFD, req.granted_count, req.request_list);
- return FALSE;
- }
-
- /* Copy parts of the block into buffers and fire them */
- dstpassbytes = hpass*dstPitch;
- dstPitch /= 8;
-
- for (i=0, offset=dst-fb; i<passes; i++, offset+=dstpassbytes) {
- if (i == (passes-1) && (h % hpass) != 0) {
- hpass = h % hpass;
- srcpassbytes = w*hpass;
- }
-
- idx = req.request_list[i];
- buf = (unsigned char *) info->buffers->list[idx].address + R128_HOSTDATA_BLIT_OFFSET;
-
- if (srcPitch == w) {
- memcpy(buf, src, srcpassbytes);
- src += srcpassbytes;
- } else {
- int count = hpass;
- while(count--) {
- memcpy(buf, src, w);
- src += srcPitch;
- buf += w;
- }
- }
-
- blit.idx = idx;
- blit.offset = offset;
- blit.pitch = dstPitch;
- blit.format = (R128_DATATYPE_CI8 >> 16);
- blit.x = (offset % 32);
- blit.y = 0;
- blit.width = w;
- blit.height = hpass;
-
- if ((err = drmCommandWrite(info->drmFD, DRM_R128_BLIT,
- &blit, sizeof(drmR128Blit))) < 0)
- break;
- }
-
- drmFreeBufs(info->drmFD, req.granted_count, req.request_list);
-
- return (err==0) ? TRUE : FALSE;
-
-#else
-
- /* This is to avoid cluttering the rest of the code with '#ifdef XF86DRI' */
- return FALSE;
-
-#endif /* XF86DRI */
-
-}
-
-
-static void
-R128CopyData422(
- R128InfoPtr info,
- unsigned char *src,
- unsigned char *dst,
- int srcPitch,
- int dstPitch,
- int h,
- int w
-){
- w <<= 1;
-
- /* Attempt data transfer with DMA and fall back to memcpy */
-
- if (!R128DMA(info, src, dst, srcPitch, dstPitch, h, w)) {
- while(h--) {
- memcpy(dst, src, w);
- src += srcPitch;
- dst += dstPitch;
- }
- }
-}
-
-static void
-R128CopyData420(
- R128InfoPtr info,
- unsigned char *src1,
- unsigned char *src2,
- unsigned char *src3,
- unsigned char *dst1,
- unsigned char *dst2,
- unsigned char *dst3,
- int srcPitch,
- int srcPitch2,
- int dstPitch,
- int h,
- int w
-){
- int count;
-
- /* Attempt data transfer with DMA and fall back to memcpy */
-
- if (!R128DMA(info, src1, dst1, srcPitch, dstPitch, h, w)) {
- count = h;
- while(count--) {
- memcpy(dst1, src1, w);
- src1 += srcPitch;
- dst1 += dstPitch;
- }
- }
-
- w >>= 1;
- h >>= 1;
- dstPitch >>= 1;
-
- if (!R128DMA(info, src2, dst2, srcPitch2, dstPitch, h, w)) {
- count = h;
- while(count--) {
- memcpy(dst2, src2, w);
- src2 += srcPitch2;
- dst2 += dstPitch;
- }
- }
-
- if (!R128DMA(info, src3, dst3, srcPitch2, dstPitch, h, w)) {
- count = h;
- while(count--) {
- memcpy(dst3, src3, w);
- src3 += srcPitch2;
- dst3 += dstPitch;
- }
- }
-}
-
-
-static FBLinearPtr
-R128AllocateMemory(
- ScrnInfoPtr pScrn,
- FBLinearPtr linear,
- int size
-){
- ScreenPtr pScreen;
- FBLinearPtr new_linear;
-
- if(linear) {
- if(linear->size >= size)
- return linear;
-
- if(xf86ResizeOffscreenLinear(linear, size))
- return linear;
-
- xf86FreeOffscreenLinear(linear);
- }
-
- pScreen = screenInfo.screens[pScrn->scrnIndex];
-
- new_linear = xf86AllocateOffscreenLinear(pScreen, size, 8,
- NULL, NULL, NULL);
-
- if(!new_linear) {
- int max_size;
-
- xf86QueryLargestOffscreenLinear(pScreen, &max_size, 8,
- PRIORITY_EXTREME);
-
- if(max_size < size)
- return NULL;
-
- xf86PurgeUnlockedOffscreenAreas(pScreen);
- new_linear = xf86AllocateOffscreenLinear(pScreen, size, 8,
- NULL, NULL, NULL);
- }
-
- return new_linear;
-}
-
-static void
-R128DisplayVideo422(
- ScrnInfoPtr pScrn,
- int id,
- int offset,
- short width, short height,
- int pitch,
- int left, int right, int top,
- BoxPtr dstBox,
- short src_w, short src_h,
- short drw_w, short drw_h
-){
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128PortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
- int v_inc, h_inc, step_by, tmp;
- int p1_h_accum_init, p23_h_accum_init;
- int p1_v_accum_init;
-
- R128ECP(pScrn, pPriv);
-
- v_inc = (src_h << 20) / drw_h;
- h_inc = (src_w << (12 + pPriv->ecp_div)) / drw_w;
- step_by = 1;
-
- while(h_inc >= (2 << 12)) {
- step_by++;
- h_inc >>= 1;
- }
-
- /* keep everything in 16.16 */
-
- offset += ((left >> 16) & ~7) << 1;
-
- tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
- p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
- ((tmp << 12) & 0xf0000000);
-
- tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
- p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
- ((tmp << 12) & 0x70000000);
-
- tmp = (top & 0x0000ffff) + 0x00018000;
- p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
-
- left = (left >> 16) & 7;
-
- OUTREG(R128_OV0_REG_LOAD_CNTL, 1);
- while(!(INREG(R128_OV0_REG_LOAD_CNTL) & (1 << 3)));
-
- OUTREG(R128_OV0_H_INC, h_inc | ((h_inc >> 1) << 16));
- OUTREG(R128_OV0_STEP_BY, step_by | (step_by << 8));
- OUTREG(R128_OV0_Y_X_START, dstBox->x1 | (dstBox->y1 << 16));
- OUTREG(R128_OV0_Y_X_END, dstBox->x2 | (dstBox->y2 << 16));
- OUTREG(R128_OV0_V_INC, v_inc);
- OUTREG(R128_OV0_P1_BLANK_LINES_AT_TOP, 0x00000fff | ((src_h - 1) << 16));
- OUTREG(R128_OV0_VID_BUF_PITCH0_VALUE, pitch);
- OUTREG(R128_OV0_P1_X_START_END, (width - 1) | (left << 16));
- left >>= 1; width >>= 1;
- OUTREG(R128_OV0_P2_X_START_END, (width - 1) | (left << 16));
- OUTREG(R128_OV0_P3_X_START_END, (width - 1) | (left << 16));
- OUTREG(R128_OV0_VID_BUF0_BASE_ADRS, offset & 0xfffffff0);
- OUTREG(R128_OV0_P1_V_ACCUM_INIT, p1_v_accum_init);
- OUTREG(R128_OV0_P23_V_ACCUM_INIT, 0);
- OUTREG(R128_OV0_P1_H_ACCUM_INIT, p1_h_accum_init);
- OUTREG(R128_OV0_P23_H_ACCUM_INIT, p23_h_accum_init);
-
- if(id == FOURCC_UYVY)
- OUTREG(R128_OV0_SCALE_CNTL, 0x41FF8C03);
- else
- OUTREG(R128_OV0_SCALE_CNTL, 0x41FF8B03);
-
- OUTREG(R128_OV0_REG_LOAD_CNTL, 0);
-}
-
-static void
-R128DisplayVideo420(
- ScrnInfoPtr pScrn,
- short width, short height,
- int pitch,
- int offset1, int offset2, int offset3,
- int left, int right, int top,
- BoxPtr dstBox,
- short src_w, short src_h,
- short drw_w, short drw_h
-){
- R128InfoPtr info = R128PTR(pScrn);
- unsigned char *R128MMIO = info->MMIO;
- R128PortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
- int v_inc, h_inc, step_by, tmp, leftUV;
- int p1_h_accum_init, p23_h_accum_init;
- int p1_v_accum_init, p23_v_accum_init;
-
- v_inc = (src_h << 20) / drw_h;
- h_inc = (src_w << (12 + pPriv->ecp_div)) / drw_w;
- step_by = 1;
-
- while(h_inc >= (2 << 12)) {
- step_by++;
- h_inc >>= 1;
- }
-
- /* keep everything in 16.16 */
-
- offset1 += (left >> 16) & ~15;
- offset2 += (left >> 17) & ~15;
- offset3 += (left >> 17) & ~15;
-
- tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
- p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
- ((tmp << 12) & 0xf0000000);
-
- tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
- p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
- ((tmp << 12) & 0x70000000);
-
- tmp = (top & 0x0000ffff) + 0x00018000;
- p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
-
- tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
- p23_v_accum_init = ((tmp << 4) & 0x01ff8000) | 0x00000001;
-
- leftUV = (left >> 17) & 15;
- left = (left >> 16) & 15;
-
- OUTREG(R128_OV0_REG_LOAD_CNTL, 1);
- while(!(INREG(R128_OV0_REG_LOAD_CNTL) & (1 << 3)));
-
- OUTREG(R128_OV0_H_INC, h_inc | ((h_inc >> 1) << 16));
- OUTREG(R128_OV0_STEP_BY, step_by | (step_by << 8));
- OUTREG(R128_OV0_Y_X_START, dstBox->x1 | (dstBox->y1 << 16));
- OUTREG(R128_OV0_Y_X_END, dstBox->x2 | (dstBox->y2 << 16));
- OUTREG(R128_OV0_V_INC, v_inc);
- OUTREG(R128_OV0_P1_BLANK_LINES_AT_TOP, 0x00000fff | ((src_h - 1) << 16));
- src_h = (src_h + 1) >> 1;
- OUTREG(R128_OV0_P23_BLANK_LINES_AT_TOP, 0x000007ff | ((src_h - 1) << 16));
- OUTREG(R128_OV0_VID_BUF_PITCH0_VALUE, pitch);
- OUTREG(R128_OV0_VID_BUF_PITCH1_VALUE, pitch >> 1);
- OUTREG(R128_OV0_P1_X_START_END, (width - 1) | (left << 16));
- width >>= 1;
- OUTREG(R128_OV0_P2_X_START_END, (width - 1) | (leftUV << 16));
- OUTREG(R128_OV0_P3_X_START_END, (width - 1) | (leftUV << 16));
- OUTREG(R128_OV0_VID_BUF0_BASE_ADRS, offset1 & 0xfffffff0);
- OUTREG(R128_OV0_VID_BUF1_BASE_ADRS, (offset2 & 0xfffffff0) | 0x00000001);
- OUTREG(R128_OV0_VID_BUF2_BASE_ADRS, (offset3 & 0xfffffff0) | 0x00000001);
- OUTREG(R128_OV0_P1_V_ACCUM_INIT, p1_v_accum_init);
- OUTREG(R128_OV0_P23_V_ACCUM_INIT, p23_v_accum_init);
- OUTREG(R128_OV0_P1_H_ACCUM_INIT, p1_h_accum_init);
- OUTREG(R128_OV0_P23_H_ACCUM_INIT, p23_h_accum_init);
- OUTREG(R128_OV0_SCALE_CNTL, 0x41FF8A03);
-
- OUTREG(R128_OV0_REG_LOAD_CNTL, 0);
-}
-
-
-
-static int
-R128PutImage(
- ScrnInfoPtr pScrn,
- short src_x, short src_y,
- short drw_x, short drw_y,
- short src_w, short src_h,
- short drw_w, short drw_h,
- int id, unsigned char* buf,
- short width, short height,
- Bool Sync,
- RegionPtr clipBoxes, pointer data,
- DrawablePtr pDraw
-){
- R128InfoPtr info = R128PTR(pScrn);
- R128PortPrivPtr pPriv = (R128PortPrivPtr)data;
- unsigned char *fb = (CARD8*)info->FB;
- INT32 xa, xb, ya, yb;
- int new_size, offset, s1offset, s2offset, s3offset;
- int srcPitch, srcPitch2, dstPitch;
- int d1line, d2line, d3line, d1offset, d2offset, d3offset;
- int top, left, npixels, nlines, bpp;
- BoxRec dstBox;
- CARD32 tmp;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char *R128MMIO = info->MMIO;
- CARD32 config_cntl = INREG(R128_CONFIG_CNTL);
-
- /* We need to disable byte swapping, or the data gets mangled */
- OUTREG(R128_CONFIG_CNTL, config_cntl &
- ~(APER_0_BIG_ENDIAN_16BPP_SWAP | APER_0_BIG_ENDIAN_32BPP_SWAP));
-#endif
-
- /*
- * s1offset, s2offset, s3offset - byte offsets to the Y, U and V planes
- * of the source.
- *
- * d1offset, d2offset, d3offset - byte offsets to the Y, U and V planes
- * of the destination.
- *
- * offset - byte offset within the framebuffer to where the destination
- * is stored.
- *
- * d1line, d2line, d3line - byte offsets within the destination to the
- * first displayed scanline in each plane.
- *
- */
-
- if(src_w > (drw_w << 4))
- drw_w = src_w >> 4;
- if(src_h > (drw_h << 4))
- drw_h = src_h >> 4;
-
- /* Clip */
- xa = src_x;
- xb = src_x + src_w;
- ya = src_y;
- yb = src_y + src_h;
-
- dstBox.x1 = drw_x;
- dstBox.x2 = drw_x + drw_w;
- dstBox.y1 = drw_y;
- dstBox.y2 = drw_y + drw_h;
-
- if(!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
- return Success;
-
- dstBox.x1 -= pScrn->frameX0;
- dstBox.x2 -= pScrn->frameX0;
- dstBox.y1 -= pScrn->frameY0;
- dstBox.y2 -= pScrn->frameY0;
-
- bpp = pScrn->bitsPerPixel >> 3;
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- srcPitch = (width + 3) & ~3;
- srcPitch2 = ((width >> 1) + 3) & ~3;
- dstPitch = (width + 31) & ~31; /* of luma */
- new_size = ((dstPitch * (height + (height >> 1))) + bpp - 1) / bpp;
- s1offset = 0;
- s2offset = srcPitch * height;
- s3offset = (srcPitch2 * (height >> 1)) + s2offset;
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- srcPitch = width << 1;
- srcPitch2 = 0;
- dstPitch = ((width << 1) + 15) & ~15;
- new_size = ((dstPitch * height) + bpp - 1) / bpp;
- s1offset = 0;
- s2offset = 0;
- s3offset = 0;
- break;
- }
-
- if(!(pPriv->linear = R128AllocateMemory(pScrn, pPriv->linear,
- pPriv->doubleBuffer ? (new_size << 1) : new_size)))
- {
- return BadAlloc;
- }
-
- pPriv->currentBuffer ^= 1;
-
- /* copy data */
- top = ya >> 16;
- left = (xa >> 16) & ~1;
- npixels = ((((xb + 0xffff) >> 16) + 1) & ~1) - left;
-
- offset = pPriv->linear->offset * bpp;
- if(pPriv->doubleBuffer)
- offset += pPriv->currentBuffer * new_size * bpp;
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- d1line = top * dstPitch;
- d2line = (height * dstPitch) + ((top >> 1) * (dstPitch >> 1));
- d3line = d2line + ((height >> 1) * (dstPitch >> 1));
-
- top &= ~1;
-
- d1offset = (top * dstPitch) + left + offset;
- d2offset = d2line + (left >> 1) + offset;
- d3offset = d3line + (left >> 1) + offset;
-
- s1offset += (top * srcPitch) + left;
- tmp = ((top >> 1) * srcPitch2) + (left >> 1);
- s2offset += tmp;
- s3offset += tmp;
- if(id == FOURCC_YV12) {
- tmp = s2offset;
- s2offset = s3offset;
- s3offset = tmp;
- }
-
- nlines = ((((yb + 0xffff) >> 16) + 1) & ~1) - top;
- R128CopyData420(info, buf + s1offset, buf + s2offset, buf + s3offset,
- fb + d1offset, fb + d2offset, fb + d3offset,
- srcPitch, srcPitch2, dstPitch, nlines, npixels);
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- left <<= 1;
- d1line = top * dstPitch;
- d2line = 0;
- d3line = 0;
- d1offset = d1line + left + offset;
- d2offset = 0;
- d3offset = 0;
- s1offset += (top * srcPitch) + left;
- nlines = ((yb + 0xffff) >> 16) - top;
- R128CopyData422(info, buf + s1offset, fb + d1offset,
- srcPitch, dstPitch, nlines, npixels);
- break;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* restore byte swapping */
- OUTREG(R128_CONFIG_CNTL, config_cntl);
-#endif
-
- /* update cliplist */
- if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
- REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes);
- /* draw these */
- xf86XVFillKeyHelper(pScrn->pScreen, pPriv->colorKey, clipBoxes);
- }
-
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- R128DisplayVideo420(pScrn, width, height, dstPitch,
- offset + d1line, offset + d2line, offset + d3line,
- xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h);
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- R128DisplayVideo422(pScrn, id, offset + d1line, width, height, dstPitch,
- xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h);
- break;
- }
-
- pPriv->videoStatus = CLIENT_VIDEO_ON;
-
- info->VideoTimerCallback = R128VideoTimerCallback;
-
- return Success;
-}
-
-
-static int
-R128QueryImageAttributes(
- ScrnInfoPtr pScrn,
- int id,
- unsigned short *w, unsigned short *h,
- int *pitches, int *offsets
-){
- int size, tmp;
-
- if(*w > MAXWIDTH) *w = MAXWIDTH;
- if(*h > MAXHEIGHT) *h = MAXHEIGHT;
-
- *w = (*w + 1) & ~1;
- if(offsets) offsets[0] = 0;
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- *h = (*h + 1) & ~1;
- size = (*w + 3) & ~3;
- if(pitches) pitches[0] = size;
- size *= *h;
- if(offsets) offsets[1] = size;
- tmp = ((*w >> 1) + 3) & ~3;
- if(pitches) pitches[1] = pitches[2] = tmp;
- tmp *= (*h >> 1);
- size += tmp;
- if(offsets) offsets[2] = size;
- size += tmp;
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- size = *w << 1;
- if(pitches) pitches[0] = size;
- size *= *h;
- break;
- }
-
- return size;
-}
-
-static void
-R128VideoTimerCallback(ScrnInfoPtr pScrn, Time now)
-{
- R128InfoPtr info = R128PTR(pScrn);
- R128PortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
-
- if(pPriv->videoStatus & TIMER_MASK) {
- if(pPriv->videoStatus & OFF_TIMER) {
- if(pPriv->offTime < now) {
- unsigned char *R128MMIO = info->MMIO;
- OUTREG(R128_OV0_SCALE_CNTL, 0);
- pPriv->videoStatus = FREE_TIMER;
- pPriv->freeTime = now + FREE_DELAY;
- }
- } else { /* FREE_TIMER */
- if(pPriv->freeTime < now) {
- if(pPriv->linear) {
- xf86FreeOffscreenLinear(pPriv->linear);
- pPriv->linear = NULL;
- }
- pPriv->videoStatus = 0;
- info->VideoTimerCallback = NULL;
- }
- }
- } else /* shouldn't get here */
- info->VideoTimerCallback = NULL;
-}
commit 4d3a3befcfcfff3825ad4de166de2090aa1c9976
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:48:44 2008 +0200
drop r128 (build system)
diff --git a/Makefile.am b/Makefile.am
index ea2e4a3..56f5cb2 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -24,13 +24,9 @@ SUBDIRS = src man
if BUILD_LINUXDOC
README.ati: README.ati.sgml
$(MAKE_TEXT) README.ati.sgml && mv README.ati.txt README.ati
-
-README.r128: README.r128.sgml
- $(MAKE_TEXT) README.r128.sgml && mv README.r128.txt README.r128
-
endif
-EXTRA_DIST = README.ati README.r128 README.ati.sgml README.r128.sgml ChangeLog
+EXTRA_DIST = README.ati README.ati.sgml ChangeLog
CLEANFILES = ChangeLog
.PHONY: ChangeLog
diff --git a/man/Makefile.am b/man/Makefile.am
index 422794f..9beca27 100644
--- a/man/Makefile.am
+++ b/man/Makefile.am
@@ -27,11 +27,11 @@
drivermandir = $(DRIVER_MAN_DIR)
-driverman_PRE = r128.man
+driverman_PRE =
driverman_DATA = $(driverman_PRE:man=@DRIVER_MAN_SUFFIX@)
-EXTRA_DIST = r128.man
+EXTRA_DIST =
CLEANFILES = $(driverman_DATA)
diff --git a/src/Makefile.am b/src/Makefile.am
index 4341302..4bc1006 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -28,7 +28,6 @@
if DRI
ATIMISC_DRI_SRCS = atidri.c
-R128_DRI_SRCS = r128_dri.c
endif
if ATIMISC_CPIO
@@ -58,13 +57,6 @@ mach64_drv_la_SOURCES = \
atiload.c atimisc.c atimach64probe.c $(ATIMISC_CPIO_SOURCES) \
$(ATIMISC_DGA_SOURCES) $(ATIMISC_DRI_SRCS) $(ATIMISC_EXA_SOURCES)
-r128_drv_la_LTLIBRARIES = r128_drv.la
-r128_drv_la_LDFLAGS = -module -avoid-version
-r128_drv_ladir = @moduledir@/drivers
-r128_drv_la_SOURCES = \
- r128_accel.c r128_cursor.c r128_dga.c r128_driver.c \
- r128_video.c r128_misc.c r128_probe.c $(R128_DRI_SRCS)
-
EXTRA_DIST = \
atimach64render.c \
\
@@ -115,12 +107,4 @@ EXTRA_DIST = \
mach64_common.h \
mach64_dri.h \
mach64_sarea.h \
- r128_common.h \
- r128_dri.h \
- r128_dripriv.h \
- r128.h \
- r128_probe.h \
- r128_reg.h \
- r128_sarea.h \
- r128_version.h \
atipcirename.h
commit df574b7b486be6b00520c6a87dc3f606b4c5395c
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:48:26 2008 +0200
drop ati wrapper
diff --git a/man/Makefile.am b/man/Makefile.am
index c5347d0..422794f 100644
--- a/man/Makefile.am
+++ b/man/Makefile.am
@@ -27,11 +27,11 @@
drivermandir = $(DRIVER_MAN_DIR)
-driverman_PRE = @DRIVER_NAME at .man r128.man
+driverman_PRE = r128.man
driverman_DATA = $(driverman_PRE:man=@DRIVER_MAN_SUFFIX@)
-EXTRA_DIST = @DRIVER_NAME at .man r128.man
+EXTRA_DIST = r128.man
CLEANFILES = $(driverman_DATA)
diff --git a/man/ati.man b/man/ati.man
deleted file mode 100644
index d8d84eb..0000000
--- a/man/ati.man
+++ /dev/null
@@ -1,34 +0,0 @@
-.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.man,v 1.2 2001/01/27 18:20:46 dawes Exp $
-.\" shorthand for double quote that works everywhere.
-.ds q \N'34'
-.TH ATI __drivermansuffix__ __vendorversion__
-.SH NAME
-ati \- ATI video driver
-.SH SYNOPSIS
-.nf
-.B "Section \*qDevice\*q"
-.BI " Identifier \*q" devname \*q
-.B " Driver \*qati\*q"
-\ \ ...
-.B EndSection
-.fi
-.SH DESCRIPTION
-.B ati
-is an __xservername__ wrapper driver for ATI video cards. It autodetects
-whether your hardware has a Radeon, Rage 128, or Mach64 or earlier class of
-chipset, and loads the radeon(__drivermansuffix__),
-r128(__drivermansuffix__), or mach64 driver as
-appropriate.
-.SH SUPPORTED HARDWARE
-The
-.B ati
-driver supports Radeon, Rage 128, and Mach64 and earlier chipsets by loading
-those drivers. See those manpages for specific cards supported.
-.SH CONFIGURATION DETAILS
-Please refer to __xconfigfile__(__filemansuffix__) for general configuration
-details, and the specific card driver for driver configuration details.
-driver.
-.SH "SEE ALSO"
-__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__), r128(__drivermansuffix__), radeon(__drivermansuffix__)
-.SH AUTHORS
-See the individual driver pages for authors.
diff --git a/src/Makefile.am b/src/Makefile.am
index e48bc68..4341302 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -45,12 +45,6 @@ endif
AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@
-ati_drv_la_LTLIBRARIES = ati_drv.la
-ati_drv_la_LDFLAGS = -module -avoid-version
-ati_drv_ladir = @moduledir@/drivers
-ati_drv_la_SOURCES = \
- ati.c atimodule.c
-
mach64_drv_la_LTLIBRARIES = mach64_drv.la
mach64_drv_la_LDFLAGS = -module -avoid-version
mach64_drv_ladir = @moduledir@/drivers
@@ -112,7 +106,6 @@ EXTRA_DIST = \
atituner.h \
atiutil.h \
ativalid.h \
- ativersion.h \
ativga.h \
ativgaio.h \
atividmem.h \
diff --git a/src/ati.c b/src/ati.c
deleted file mode 100644
index b3f07ca..0000000
--- a/src/ati.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*************************************************************************/
-
-/*
- * Author: Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * This is the ATI driver for XFree86.
- *
- * John Donne once said "No man is an island", and I am most certainly not an
- * exception. Contributions, intentional or not, to this and previous versions
- * of this driver by the following are hereby acknowledged:
- *
- * Thomas Roell, Per Lindqvist, Doug Evans, Rik Faith, Arthur Tateishi,
- * Alain Hebert, Ton van Rosmalen, David Chambers, William Shubert,
- * ATI Technologies Incorporated, Robert Wolff, David Dawes, Mark Weaver,
- * Hans Nasten, Kevin Martin, Frederic Rienthaler, Marc Bolduc, Reuben Sumner,
- * Benjamin T. Yang, James Fast Kane, Randall Hopper, W. Marcus Miller,
- * Henrik Harmsen, Christian Lupien, Precision Insight Incorporated,
- * Mark Vojkovich, Huw D M Davies, Andrew C Aitchison, Ani Joshi,
- * Kostas Gewrgiou, Jakub Jelinek, David S. Miller, A E Lawrence,
- * Linus Torvalds, William Blew, Ignacio Garcia Etxebarria, Patrick Chase,
- * Vladimir Dergachev, Egbert Eich, Mike A. Harris
- *
- * ... and, many, many others from around the world.
- *
- * In addition, this work would not have been possible without the active
- * support, both moral and otherwise, of the staff and management of Computing
- * and Network Services at the University of Alberta, in Edmonton, Alberta,
- * Canada.
- *
- * The driver is intended to support all ATI adapters since their VGA Wonder
- * V3, including OEM counterparts.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#ifdef XSERVER_LIBPCIACCESS
-#include <pciaccess.h>
-#endif
-#include "atipcirename.h"
-
-#include "ati.h"
-#include "ativersion.h"
-
-/* names duplicated from version headers */
-#define MACH64_DRIVER_NAME "mach64"
-#define R128_DRIVER_NAME "r128"
-#define RADEON_DRIVER_NAME "radeon"
-
-enum
-{
- ATI_CHIP_FAMILY_NONE = 0,
- ATI_CHIP_FAMILY_Mach64,
- ATI_CHIP_FAMILY_Rage128,
- ATI_CHIP_FAMILY_Radeon
-};
-
-static int ATIChipID(const CARD16);
-
-#ifdef XSERVER_LIBPCIACCESS
-
-/* domain defines (stolen from xserver) */
-#if (defined(__alpha__) || defined(__ia64__)) && defined (linux)
-# define PCI_DOM_MASK 0x01fful
-#else
-# define PCI_DOM_MASK 0x0ffu
-#endif
-
-#define PCI_DOM_FROM_BUS(bus) (((bus) >> 8) & (PCI_DOM_MASK))
-#define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu)
-
-static struct pci_device*
-ati_device_get_from_busid(int bus, int dev, int func)
-{
- return pci_device_find_by_slot(PCI_DOM_FROM_BUS(bus),
- PCI_BUS_NO_DOMAIN(bus),
- dev,
- func);
-}
-
-static struct pci_device*
-ati_device_get_primary()
-{
- struct pci_device *device = NULL;
- struct pci_device_iterator *device_iter;
-
- device_iter = pci_slot_match_iterator_create(NULL);
-
- while ((device = pci_device_next(device_iter)) != NULL) {
- if (xf86IsPrimaryPci(device))
- break;
- }
-
- pci_iterator_destroy(device_iter);
-
- return device;
-}
-
-#else /* XSERVER_LIBPCIACCESS */
-
-static pciVideoPtr
-ati_device_get_from_busid(int bus, int dev, int func)
-{
- pciVideoPtr pVideo = NULL;
- pciVideoPtr *xf86PciVideoInfo;
-
- xf86PciVideoInfo = xf86GetPciVideoInfo();
-
- if (xf86PciVideoInfo == NULL)
- return NULL;
-
- while ((pVideo = *xf86PciVideoInfo++) != NULL)
- {
- if ((pVideo->bus == bus) && (pVideo->device == dev) &&
- (pVideo->func == func))
- break;
- }
-
- return pVideo;
-}
-
-static pciVideoPtr
-ati_device_get_primary()
-{
- pciVideoPtr pVideo = NULL;
- pciVideoPtr *xf86PciVideoInfo;
-
- xf86PciVideoInfo = xf86GetPciVideoInfo();
-
- if (xf86PciVideoInfo == NULL)
- return NULL;
-
- while ((pVideo = *xf86PciVideoInfo++) != NULL)
- {
- if (xf86IsPrimaryPci(pVideo))
- break;
- }
-
- return pVideo;
-}
-
-#endif /* XSERVER_LIBPCIACCESS */
-
-void
-ati_gdev_subdriver(pointer options)
-{
- int nATIGDev, nMach64GDev, nR128GDev, nRadeonGDev;
- GDevPtr *ATIGDevs;
- Bool load_mach64 = FALSE, load_r128 = FALSE, load_radeon = FALSE;
- int i;
-
- /* let the subdrivers configure for themselves */
- if (xf86ServerIsOnlyDetecting())
- return;
-
- /* get Device sections with Driver "ati" */
- nATIGDev = xf86MatchDevice(ATI_DRIVER_NAME, &ATIGDevs);
- nMach64GDev = xf86MatchDevice(MACH64_DRIVER_NAME, NULL);
- nR128GDev = xf86MatchDevice(R128_DRIVER_NAME, NULL);
- nRadeonGDev = xf86MatchDevice(RADEON_DRIVER_NAME, NULL);
-
- for (i = 0; i < nATIGDev; i++) {
- GDevPtr ati_gdev = ATIGDevs[i];
- pciVideoPtr device = NULL;
- int chip_family;
-
- /* get pci device for the Device section */
- if (ati_gdev->busID) {
- int bus, dev, func;
-
- if (!xf86ParsePciBusString(ati_gdev->busID, &bus, &dev, &func))
- continue;
-
- device = ati_device_get_from_busid(bus, dev, func);
- }
- else {
- device = ati_device_get_primary();
- }
-
- if (!device)
- continue;
-
- /* check for non-ati devices and prehistoric mach32 */
- if ((PCI_DEV_VENDOR_ID(device) != PCI_VENDOR_ATI) ||
- (PCI_DEV_DEVICE_ID(device) == PCI_CHIP_MACH32))
- continue;
-
- /* replace Driver line in the Device section */
- chip_family = ATIChipID(PCI_DEV_DEVICE_ID(device));
-
- if (chip_family == ATI_CHIP_FAMILY_Mach64) {
- ati_gdev->driver = MACH64_DRIVER_NAME;
- load_mach64 = TRUE;
- }
-
- if (chip_family == ATI_CHIP_FAMILY_Rage128) {
- ati_gdev->driver = R128_DRIVER_NAME;
- load_r128 = TRUE;
- }
-
- if (chip_family == ATI_CHIP_FAMILY_Radeon) {
- ati_gdev->driver = RADEON_DRIVER_NAME;
- load_radeon = TRUE;
- }
- }
-
- xfree(ATIGDevs);
-
- /* load subdrivers as primary modules and only if they do not get loaded
- * from other device sections
- */
-
- if (load_mach64 && (nMach64GDev == 0))
- xf86LoadOneModule(MACH64_DRIVER_NAME, options);
-
- if (load_r128 && (nR128GDev == 0))
- xf86LoadOneModule(R128_DRIVER_NAME, options);
-
- if (load_radeon && (nRadeonGDev == 0))
- xf86LoadOneModule(RADEON_DRIVER_NAME, options);
-}
-
-/*
- * ATIChipID --
- *
- * This returns the ATI_CHIP_FAMILY_* value associated with a particular ChipID.
- */
-static int
-ATIChipID(const CARD16 ChipID)
-{
- switch (ChipID)
- {
- case PCI_CHIP_MACH64GX:
- case PCI_CHIP_MACH64CX:
- case PCI_CHIP_MACH64CT:
- case PCI_CHIP_MACH64ET:
- case PCI_CHIP_MACH64VT:
- case PCI_CHIP_MACH64GT:
- case PCI_CHIP_MACH64VU:
- case PCI_CHIP_MACH64GU:
- case PCI_CHIP_MACH64LG:
- case PCI_CHIP_MACH64VV:
- case PCI_CHIP_MACH64GV:
- case PCI_CHIP_MACH64GW:
- case PCI_CHIP_MACH64GY:
- case PCI_CHIP_MACH64GZ:
- case PCI_CHIP_MACH64GB:
- case PCI_CHIP_MACH64GD:
- case PCI_CHIP_MACH64GI:
- case PCI_CHIP_MACH64GP:
- case PCI_CHIP_MACH64GQ:
- case PCI_CHIP_MACH64LB:
- case PCI_CHIP_MACH64LD:
- case PCI_CHIP_MACH64LI:
- case PCI_CHIP_MACH64LP:
- case PCI_CHIP_MACH64LQ:
- case PCI_CHIP_MACH64GL:
- case PCI_CHIP_MACH64GM:
- case PCI_CHIP_MACH64GN:
- case PCI_CHIP_MACH64GO:
- case PCI_CHIP_MACH64GR:
- case PCI_CHIP_MACH64GS:
- case PCI_CHIP_MACH64LM:
- case PCI_CHIP_MACH64LN:
- case PCI_CHIP_MACH64LR:
- case PCI_CHIP_MACH64LS:
- return ATI_CHIP_FAMILY_Mach64;
-
- case PCI_CHIP_RAGE128RE:
- case PCI_CHIP_RAGE128RF:
- case PCI_CHIP_RAGE128RG:
- case PCI_CHIP_RAGE128SK:
- case PCI_CHIP_RAGE128SL:
- case PCI_CHIP_RAGE128SM:
- case PCI_CHIP_RAGE128SN:
- case PCI_CHIP_RAGE128RK:
- case PCI_CHIP_RAGE128RL:
- case PCI_CHIP_RAGE128SE:
- case PCI_CHIP_RAGE128SF:
- case PCI_CHIP_RAGE128SG:
- case PCI_CHIP_RAGE128SH:
- case PCI_CHIP_RAGE128PA:
- case PCI_CHIP_RAGE128PB:
- case PCI_CHIP_RAGE128PC:
- case PCI_CHIP_RAGE128PD:
- case PCI_CHIP_RAGE128PE:
- case PCI_CHIP_RAGE128PF:
- case PCI_CHIP_RAGE128PG:
- case PCI_CHIP_RAGE128PH:
- case PCI_CHIP_RAGE128PI:
- case PCI_CHIP_RAGE128PJ:
- case PCI_CHIP_RAGE128PK:
- case PCI_CHIP_RAGE128PL:
- case PCI_CHIP_RAGE128PM:
- case PCI_CHIP_RAGE128PN:
- case PCI_CHIP_RAGE128PO:
- case PCI_CHIP_RAGE128PP:
- case PCI_CHIP_RAGE128PQ:
- case PCI_CHIP_RAGE128PR:
- case PCI_CHIP_RAGE128PS:
- case PCI_CHIP_RAGE128PT:
- case PCI_CHIP_RAGE128PU:
- case PCI_CHIP_RAGE128PV:
- case PCI_CHIP_RAGE128PW:
- case PCI_CHIP_RAGE128PX:
- case PCI_CHIP_RAGE128TF:
- case PCI_CHIP_RAGE128TL:
- case PCI_CHIP_RAGE128TR:
- case PCI_CHIP_RAGE128TS:
- case PCI_CHIP_RAGE128TT:
- case PCI_CHIP_RAGE128TU:
- case PCI_CHIP_RAGE128LE:
- case PCI_CHIP_RAGE128LF:
-#if 0
- case PCI_CHIP_RAGE128LK:
- case PCI_CHIP_RAGE128LL:
-#endif
- case PCI_CHIP_RAGE128MF:
- case PCI_CHIP_RAGE128ML:
- return ATI_CHIP_FAMILY_Rage128;
-
- default:
- return ATI_CHIP_FAMILY_Radeon;
- }
-}
diff --git a/src/atimodule.c b/src/atimodule.c
deleted file mode 100644
index c249333..0000000
--- a/src/atimodule.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "ati.h"
-#include "ativersion.h"
-
-extern void ati_gdev_subdriver(pointer options);
-
-/* Module loader interface */
-
-static XF86ModuleVersionInfo ATIVersionRec =
-{
- ATI_DRIVER_NAME,
- MODULEVENDORSTRING,
- MODINFOSTRING1,
- MODINFOSTRING2,
- XORG_VERSION_CURRENT,
- ATI_VERSION_MAJOR, ATI_VERSION_MINOR, ATI_VERSION_PATCH,
- ABI_CLASS_VIDEODRV,
- ABI_VIDEODRV_VERSION,
- MOD_CLASS_VIDEODRV,
- {0, 0, 0, 0}
-};
-
-/*
- * ATISetup --
- *
- * This function is called every time the module is loaded.
- */
-static pointer
-ATISetup
-(
- pointer Module,
- pointer Options,
- int *ErrorMajor,
- int *ErrorMinor
-)
-{
- static Bool Inited = FALSE;
-
- if (!Inited)
- {
- Inited = TRUE;
- ati_gdev_subdriver(Options);
- }
-
- return (pointer)1;
-}
-
-/* The following record must be called atiModuleData */
-_X_EXPORT XF86ModuleData atiModuleData =
-{
- &ATIVersionRec,
- ATISetup,
- NULL
-};
diff --git a/src/ativersion.h b/src/ativersion.h
deleted file mode 100644
index 578b3c4..0000000
--- a/src/ativersion.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef ___ATIVERSION_H___
-#define ___ATIVERSION_H___ 1
-
-#undef ATI_NAME
-#undef ATI_DRIVER_NAME
-#undef ATI_VERSION_CURRENT
-#undef ATI_VERSION_EVALUATE
-#undef ATI_VERSION_STRINGIFY
-#undef ATI_VERSION_NAME
-
-#define ATI_NAME "ATI"
-#define ATI_DRIVER_NAME "ati"
-
-#ifndef ATI_VERSION_EXTRA
-#define ATI_VERSION_EXTRA ""
-#endif
-
-#define ATI_VERSION_MAJOR PACKAGE_VERSION_MAJOR
-#define ATI_VERSION_MINOR PACKAGE_VERSION_MINOR
-#define ATI_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
-
-#define ATI_VERSION_CURRENT \
- ((ATI_VERSION_MAJOR << 20) | (ATI_VERSION_MINOR << 10) | ATI_VERSION_PATCH)
-
-#define ATI_VERSION_EVALUATE(__x) #__x
-#define ATI_VERSION_STRINGIFY(_x) ATI_VERSION_EVALUATE(_x)
-#define ATI_VERSION_NAME \
- ATI_VERSION_STRINGIFY(ATI_VERSION_MAJOR) "." \
- ATI_VERSION_STRINGIFY(ATI_VERSION_MINOR) "." \
- ATI_VERSION_STRINGIFY(ATI_VERSION_PATCH) ATI_VERSION_EXTRA
-
-#endif /* ___ATIVERSION_H___ */
commit 4d5cc3678ac8d1e8ed18d72d26154494bf1e75e5
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:48:10 2008 +0200
drop AtomBios and pcidb
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
deleted file mode 100644
index 1e48f81..0000000
--- a/src/AtomBios/CD_Operations.c
+++ /dev/null
@@ -1,954 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/**
-
-Module Name:
-
- CD_Operations.c
-
-Abstract:
-
- Functions Implementing Command Operations and other common functions
-
-Revision History:
-
- NEG:27.09.2002 Initiated.
---*/
-#define __SW_4
-
-#include "Decoder.h"
-#include "atombios.h"
-
-
-
-VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData);
-UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable);
-
-
-WRITE_IO_FUNCTION WritePCIFunctions[8] = {
- WritePCIReg32,
- WritePCIReg16, WritePCIReg16, WritePCIReg16,
- WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8
-};
-WRITE_IO_FUNCTION WriteIOFunctions[8] = {
- WriteSysIOReg32,
- WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16,
- WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8
-};
-READ_IO_FUNCTION ReadPCIFunctions[8] = {
- (READ_IO_FUNCTION)ReadPCIReg32,
- (READ_IO_FUNCTION)ReadPCIReg16,
- (READ_IO_FUNCTION)ReadPCIReg16,
- (READ_IO_FUNCTION)ReadPCIReg16,
- (READ_IO_FUNCTION)ReadPCIReg8,
- (READ_IO_FUNCTION)ReadPCIReg8,
- (READ_IO_FUNCTION)ReadPCIReg8,
- (READ_IO_FUNCTION)ReadPCIReg8
-};
-READ_IO_FUNCTION ReadIOFunctions[8] = {
- (READ_IO_FUNCTION)ReadSysIOReg32,
- (READ_IO_FUNCTION)ReadSysIOReg16,
- (READ_IO_FUNCTION)ReadSysIOReg16,
- (READ_IO_FUNCTION)ReadSysIOReg16,
- (READ_IO_FUNCTION)ReadSysIOReg8,
- (READ_IO_FUNCTION)ReadSysIOReg8,
- (READ_IO_FUNCTION)ReadSysIOReg8,
- (READ_IO_FUNCTION)ReadSysIOReg8
-};
-READ_IO_FUNCTION GetParametersDirectArray[8]={
- GetParametersDirect32,
- GetParametersDirect16,GetParametersDirect16,GetParametersDirect16,
- GetParametersDirect8,GetParametersDirect8,GetParametersDirect8,
- GetParametersDirect8
-};
-
-COMMANDS_DECODER PutDataFunctions[6] = {
- PutDataRegister,
- PutDataPS,
- PutDataWS,
- PutDataFB,
- PutDataPLL,
- PutDataMC
-};
-CD_GET_PARAMETERS GetDestination[6] = {
- GetParametersRegister,
- GetParametersPS,
- GetParametersWS,
- GetParametersFB,
- GetParametersPLL,
- GetParametersMC
-};
-
-COMMANDS_DECODER SkipDestination[6] = {
- SkipParameters16,
- SkipParameters8,
- SkipParameters8,
- SkipParameters8,
- SkipParameters8,
- SkipParameters8
-};
-
-CD_GET_PARAMETERS GetSource[8] = {
- GetParametersRegister,
- GetParametersPS,
- GetParametersWS,
- GetParametersFB,
- GetParametersIndirect,
- GetParametersDirect,
- GetParametersPLL,
- GetParametersMC
-};
-
-UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF};
-UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24};
-UINT8 DestinationAlignmentShift[4] = {0,8,16,24};
-
-#define INDIRECTIO_ID 1
-#define INDIRECTIO_END_OF_ID 9
-
-VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp);
-VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-
-INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={
- {IndirectIOCommand,1},
- {IndirectIOCommand,2},
- {ReadIndReg32,3},
- {WriteIndReg32,3},
- {IndirectIOCommand_CLEAR,3},
- {IndirectIOCommand_SET,3},
- {IndirectIOCommand_MOVE_INDEX,4},
- {IndirectIOCommand_MOVE_ATTR,4},
- {IndirectIOCommand_MOVE_DATA,4},
- {IndirectIOCommand,3}
-};
-
-
-VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
-}
-
-
-VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
- pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) &
- (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
-}
-
-VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
- pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2])
- & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
-}
-
-VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]);
- pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2])
- & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]);
-}
-
-
-VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]);
-}
-
-VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]);
-}
-
-
-UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- // if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID;
-// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable;
- while (*pParserTempData->IndirectIOTablePointer)
- {
- if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) &&
- (pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData))
- {
- pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
- while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID)
- {
- IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
- pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
- }
- pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1);
- pParserTempData->IndirectIOTablePointer++;
- return pParserTempData->IndirectData;
- } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
- }
- return 0;
-}
-
-
-
-VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination;
- pParserTempData->Index+=pParserTempData->CurrentRegBlock;
- switch(pParserTempData->Multipurpose.CurrentPort){
- case ATI_RegsPort:
- if (pParserTempData->CurrentPortID == INDIRECT_IO_MM)
- {
- if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2;
- WriteReg32( pParserTempData);
- } else
- {
- pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE;
- IndirectInputOutput(pParserTempData);
- }
- break;
- case PCI_Port:
- WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
- break;
- case SystemIO_Port:
- WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
- break;
- }
-}
-
-VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- pParserTempData->DestData32;
-}
-
-VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C)
- *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32;
- else
- switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)
- {
- case WS_REMINDER_C:
- pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32;
- break;
- case WS_QUOTIENT_C:
- pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32;
- break;
- case WS_DATAPTR_C:
-#ifndef UEFI_BUILD
- pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32;
-#else
- pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32;
-#endif
- break;
- case WS_SHIFT_C:
- pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32;
- break;
- case WS_FB_WINDOW_C:
- pParserTempData->CurrentFB_Window=pParserTempData->DestData32;
- break;
- case WS_ATTRIBUTES_C:
- pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32;
- break;
- }
-
-}
-
-VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
- //Make an Index from address first, then add to the Index
- pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2);
- WriteFrameBuffer32(pParserTempData);
-}
-
-VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
- WritePLL32( pParserTempData );
-}
-
-VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination;
- WriteMC32( pParserTempData );
-}
-
-
-VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
-}
-
-VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
-}
-
-
-UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
- pParserTempData->Index+=pParserTempData->CurrentRegBlock;
- switch(pParserTempData->Multipurpose.CurrentPort)
- {
- case PCI_Port:
- return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
- case SystemIO_Port:
- return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
- case ATI_RegsPort:
- default:
- if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData );
- else
- {
- pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ;
- return IndirectInputOutput(pParserTempData);
- }
- }
-}
-
-UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index);
-}
-
-UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- if (pParserTempData->Index < WS_QUOTIENT_C)
- return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index);
- else
- switch (pParserTempData->Index)
- {
- case WS_REMINDER_C:
- return pParserTempData->MultiplicationOrDivision.Division.Reminder32;
- case WS_QUOTIENT_C:
- return pParserTempData->MultiplicationOrDivision.Division.Quotient32;
- case WS_DATAPTR_C:
- return (UINT32)pParserTempData->CurrentDataBlock;
- case WS_OR_MASK_C:
- return ((UINT32)1) << pParserTempData->Shift2MaskConverter;
- case WS_AND_MASK_C:
- return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter);
- case WS_FB_WINDOW_C:
- return pParserTempData->CurrentFB_Window;
- case WS_ATTRIBUTES_C:
- return pParserTempData->AttributesData;
- }
- return 0;
-
-}
-
-UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2);
- return ReadFrameBuffer32(pParserTempData);
-}
-
-UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- return ReadPLL32( pParserTempData );
-}
-
-UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- return ReadMC32( pParserTempData );
-}
-
-
-UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
- return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock);
-}
-
-UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->CD_Mask.SrcAlignment=alignmentByte0;
- pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- return pParserTempData->Index;
-}
-
-UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
- return pParserTempData->Index;
-}
-
-UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->CD_Mask.SrcAlignment=alignmentDword;
- pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP;
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT32);
- return pParserTempData->Index;
-}
-
-
-UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData);
-}
-
-
-VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
-}
-
-VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
- pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
-}
-
-VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
- {
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- } else
- {
- SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- }
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
-
- if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
- {
- pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 |= pParserTempData->SourceData32;
- } else
- {
- pParserTempData->DestData32=pParserTempData->SourceData32;
- }
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
-
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetParametersDirect(pParserTempData);
- pParserTempData->Index=GetParametersDirect(pParserTempData);
- pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
- pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
- pParserTempData->DestData32 &= pParserTempData->SourceData32;
- pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
- pParserTempData->DestData32 |= pParserTempData->Index;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
- pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
- pParserTempData->DestData32 &= pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 |= pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 ^= pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 <<= pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 >>= pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-
-VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 += pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonSourceDataTransformation(pParserTempData);
- pParserTempData->DestData32 -= pParserTempData->SourceData32;
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonOperationDataTransformation(pParserTempData);
- pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32;
-}
-
-VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
-
- CommonOperationDataTransformation(pParserTempData);
- pParserTempData->MultiplicationOrDivision.Division.Quotient32=
- pParserTempData->DestData32 / pParserTempData->SourceData32;
- pParserTempData->MultiplicationOrDivision.Division.Reminder32=
- pParserTempData->DestData32 % pParserTempData->SourceData32;
-}
-
-
-VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
-
- CommonOperationDataTransformation(pParserTempData);
-
- // Here we just set flags based on evaluation
- if (pParserTempData->DestData32==pParserTempData->SourceData32)
- pParserTempData->CompareFlags = Equal;
- else
- pParserTempData->CompareFlags =
- (UINT8)((pParserTempData->DestData32<pParserTempData->SourceData32) ? Below : Above);
-
-}
-
-VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]);
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-
-}
-
-VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetParametersDirect8(pParserTempData);
-
- // save original value of the destination
- pParserTempData->Index = pParserTempData->DestData32 & ~mask;
- pParserTempData->DestData32 &= mask;
-
- if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE)
- pParserTempData->DestData32 <<= pParserTempData->SourceData32; else
- pParserTempData->DestData32 >>= pParserTempData->SourceData32;
-
- // Clear any bits shifted out of masked area...
- pParserTempData->DestData32 &= mask;
- // ... and restore the area outside of masked with original values
- pParserTempData->DestData32 |= pParserTempData->Index;
-
- // write data back
- PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData);
-}
-
-VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- CommonOperationDataTransformation(pParserTempData);
- pParserTempData->CompareFlags =
- (UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal);
-
-}
-
-VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->CurrentFB_Window=pParserTempData->SourceData32;
-}
-
-VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
- pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
- pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
- pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
- {
- if (*pParserTempData->pWorkingTableData->IP == 'c')
- {
- pParserTempData->pWorkingTableData->IP++;
- pParserTempData->DestData32=GetParametersDirect(pParserTempData);
- pParserTempData->Index=GetParametersDirect16(pParserTempData);
- if (pParserTempData->SourceData32 == pParserTempData->DestData32)
- {
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index);
- return;
- }
- }
- }
- pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
-}
-
-
-VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- UINT8 value;
- UINT16* pMasterDataTable;
- value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
- if (value == 0) pParserTempData->CurrentDataBlock=0; else
- {
- if (value == DB_CURRENT_COMMAND_TABLE)
- {
- pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image);
- } else
- {
- pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData);
- pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value];
- }
- }
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
-}
-
-VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort;
- pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination;
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
-}
-
-VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination;
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
-}
-
-
-//Atavism!!! Review!!!
-VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
- pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination;
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY);
-
-}
-
-VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
- pParserTempData->SourceData32 =
- ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
- DelayMilliseconds(pParserTempData);
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
-}
-VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
- pParserTempData->SourceData32 =
- ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
- DelayMicroseconds(pParserTempData);
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
-}
-
-VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->SourceData32 =
- ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
- PostCharOutput(pParserTempData);
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
-}
-
-VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->SourceData32 =
- ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination;
- CallerDebugFunc(pParserTempData);
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
-}
-
-
-VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
-}
-
-
-VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
- UINT16* MasterTableOffset;
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
- MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData);
- if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO
- {
- pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value);
- pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable =
- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2);
- pParserTempData->pDeviceData->pParameterSpace+=
- pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable;
- pParserTempData->Status=CD_CALL_TABLE;
- pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset;
- }
-}
-
-
-VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
-}
-
-
-static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- pParserTempData->Status = CD_NOT_IMPLEMENTED;
-}
-
-
-VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- if ((pParserTempData->ParametersType.Destination == NoCondition) ||
- (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags ))
- {
-
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
- } else
- {
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
- }
-}
-
-VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- if ((pParserTempData->CompareFlags == Equal) ||
- (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination))
- {
-
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
- } else
- {
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
- }
-}
-
-VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- if (pParserTempData->CompareFlags != Equal)
- {
-
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
- } else
- {
- pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
- }
-}
-
-
-
-COMMANDS_PROPERTIES CallTable[] =
-{
- { NULL, 0,0},
- { ProcessMove, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessMove, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessMove, destMC, sizeof(COMMAND_HEADER)},
- { ProcessAnd, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessAnd, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessAnd, destMC, sizeof(COMMAND_HEADER)},
- { ProcessOr, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessOr, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessOr, destMC, sizeof(COMMAND_HEADER)},
- { ProcessShift, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessShift, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessShift, destMC, sizeof(COMMAND_HEADER)},
- { ProcessShift, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessShift, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessShift, destMC, sizeof(COMMAND_HEADER)},
- { ProcessMUL, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessMUL, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessMUL, destMC, sizeof(COMMAND_HEADER)},
- { ProcessDIV, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessDIV, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessDIV, destMC, sizeof(COMMAND_HEADER)},
- { ProcessADD, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessADD, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessADD, destMC, sizeof(COMMAND_HEADER)},
- { ProcessSUB, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessSUB, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessSUB, destMC, sizeof(COMMAND_HEADER)},
- { cmdSet_ATI_Port, ATI_RegsPort, 0},
- { cmdSet_X_Port, PCI_Port, 0},
- { cmdSet_X_Port, SystemIO_Port, 0},
- { cmdSet_Reg_Block, 0, 0},
- { ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)},
- { ProcessCompare, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessCompare, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessCompare, destMC, sizeof(COMMAND_HEADER)},
- { ProcessSwitch, 0, sizeof(COMMAND_HEADER)},
- { ProcessJump, NoCondition, 0},
- { ProcessJump, Equal, 0},
- { ProcessJump, Below, 0},
- { ProcessJump, Above, 0},
- { ProcessJumpE, Below, 0},
- { ProcessJumpE, Above, 0},
- { ProcessJumpNE, 0, 0},
- { ProcessTest, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessTest, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessTest, destMC, sizeof(COMMAND_HEADER)},
- { cmdDelay_Millisec,0, 0},
- { cmdDelay_Microsec,0, 0},
- { cmdCall_Table, 0, 0},
- /*cmdRepeat*/ { NotImplemented, 0, 0},
- { ProcessClear, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessClear, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessClear, destMC, sizeof(COMMAND_HEADER)},
- { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)},
- /*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)},
- { ProcessMask, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessMask, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessMask, destMC, sizeof(COMMAND_HEADER)},
- /*cmdPost_Card*/ { ProcessPostChar, 0, 0},
- /*cmdBeep*/ { NotImplemented, 0, 0},
- /*cmdSave_Reg*/ { NotImplemented, 0, 0},
- /*cmdRestore_Reg*/{ NotImplemented, 0, 0},
- { cmdSetDataBlock, 0, 0},
- { ProcessXor, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessXor, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessXor, destMC, sizeof(COMMAND_HEADER)},
-
- { ProcessShl, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessShl, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessShl, destMC, sizeof(COMMAND_HEADER)},
-
- { ProcessShr, destRegister, sizeof(COMMAND_HEADER)},
- { ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)},
- { ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)},
- { ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)},
- { ProcessShr, destPLL, sizeof(COMMAND_HEADER)},
- { ProcessShr, destMC, sizeof(COMMAND_HEADER)},
- /*cmdDebug*/ { ProcessDebug, 0, 0},
- { ProcessDS, 0, 0},
-
-};
-
-// EOF
diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c
deleted file mode 100644
index cdaa9ef..0000000
--- a/src/AtomBios/Decoder.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/**
-
-Module Name:
-
- Decoder.c
-
-Abstract:
-
- Commands Decoder
-
-Revision History:
-
- NEG:24.09.2002 Initiated.
---*/
-//#include "AtomBios.h"
-#include "Decoder.h"
-#include "atombios.h"
-#include "CD_binding.h"
-#include "CD_Common_Types.h"
-
-#ifndef DISABLE_EASF
- #include "easf.h"
-#endif
-
-
-
-#define INDIRECT_IO_TABLE (((UINT16)(ULONG_PTR)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) )
-extern COMMANDS_PROPERTIES CallTable[];
-
-
-UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
- UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode;
- pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize;
- pParserTempData->ParametersType.Destination=CallTable[opcode].destination;
- pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source;
- pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment;
- pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment;
- return opcode;
-}
-
-UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
-{
- UINT16 *MasterTableOffset;
-#ifndef DISABLE_EASF
- if (pDeviceData->format == TABLE_FORMAT_EASF)
- {
- /*
- make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize.
- */
- MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset);
- } else
-#endif
- {
-#ifndef UEFI_BUILD
- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image);
- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image );
- MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables);
-#else
- MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables));
-#endif
- }
- return MasterTableOffset;
-}
-
-UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
-{
- UINT16 *MasterTableOffset;
-
-#ifndef UEFI_BUILD
- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image);
- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image );
- MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables);
-#else
- MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables));
-#endif
- return MasterTableOffset;
-}
-
-
-UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable)
-{
-#ifndef DISABLE_EASF
- UINT16 i;
- if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF)
- {
-/*
- Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[]
- ((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize;
- ((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID;
- usFunctionID has to be shifted left by 2 before compare it to the value provided by caller.
-*/
- for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4)
- if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK));
- return 1;
- } else
-#endif
- {
- return IndexInMasterTable;
- }
-}
-
-CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable)
-{
- PARSER_TEMP_DATA ParserTempData;
- WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData;
-
- ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData;
-#ifndef DISABLE_EASF
- if (pDeviceData->format == TABLE_FORMAT_EASF)
- {
- ParserTempData.IndirectIOTablePointer = 0;
- } else
-#endif
- {
- ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData);
- ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image);
- ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER);
- }
-
- ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData);
- IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable);
- if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO
- {
- ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable;
- ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort;
- ParserTempData.CurrentPortID=INDIRECT_IO_MM;
- ParserTempData.CurrentRegBlock=0;
- ParserTempData.CurrentFB_Window=0;
- prevWorkingTableData=NULL;
- ParserTempData.Status=CD_CALL_TABLE;
-
- do{
-
- if (ParserTempData.Status==CD_CALL_TABLE)
- {
- IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable;
- if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO
- {
-#ifndef UEFI_BUILD
- ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
-#else
- ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
-#endif
- if (ParserTempData.pWorkingTableData!=NULL)
- {
- ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA));
-#ifndef UEFI_BUILD
- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image);
-#else
- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]);
-#endif
- ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER);
- ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData;
- prevWorkingTableData=ParserTempData.pWorkingTableData;
- ParserTempData.Status = CD_SUCCESS;
- } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR;
- } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND;
- }
- if (!CD_ERROR(ParserTempData.Status))
- {
- ParserTempData.Status = CD_SUCCESS;
- while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status))
- {
-
- if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
- {
- ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP;
-
- if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
- {
- ParserTempData.Status=CD_COMPLETED;
- prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData;
-
- FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData);
- ParserTempData.pWorkingTableData=prevWorkingTableData;
- if (prevWorkingTableData!=NULL)
- {
- ParserTempData.pDeviceData->pParameterSpace-=
- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData->
- pTableHead)->TableAttribute.PS_SizeInBytes>>2);
- }
- // if there is a parent table where to return, then restore PS_pointer to the original state
- }
- else
- {
- IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
- (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
-#if (PARSER_TYPE!=DRIVER_TYPE_PARSER)
- BIOS_STACK_MODIFIER();
-#endif
- }
- }
- else
- {
- ParserTempData.Status=CD_INVALID_OPCODE;
- break;
- }
-
- } // while
- } // if
- else
- break;
- } while (prevWorkingTableData!=NULL);
- if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS;
- return ParserTempData.Status;
- } else return CD_SUCCESS;
-}
-
-// EOF
-
diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c
deleted file mode 100644
index a5f5a5b..0000000
--- a/src/AtomBios/hwserv_drv.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/**
-
-Module Name:
-
- hwserv_drv.c
-
-Abstract:
-
- Functions defined in the Command Decoder Specification document
-
-Revision History:
-
- NEG:27.09.2002 Initiated.
---*/
-#include "CD_binding.h"
-#include "CD_hw_services.h"
-
-//trace settings
-#if DEBUG_OUTPUT_DEVICE & 1
- #define TRACE_USING_STDERR //define it to use stderr as trace output,
-#endif
-#if DEBUG_OUTPUT_DEVICE & 2
- #define TRACE_USING_RS232
-#endif
-#if DEBUG_OUTPUT_DEVICE & 4
- #define TRACE_USING_LPT
-#endif
-
-
-#if DEBUG_PARSER == 4
- #define IO_TRACE //IO access trace switch, undefine it to turn off
- #define PCI_TRACE //PCI access trace switch, undefine it to turn off
- #define MEM_TRACE //MEM access trace switch, undefine it to turn off
-#endif
-
-UINT32 CailReadATIRegister(VOID*,UINT32);
-VOID CailWriteATIRegister(VOID*,UINT32,UINT32);
-VOID* CailAllocateMemory(VOID*,UINT16);
-VOID CailReleaseMemory(VOID *,VOID *);
-VOID CailDelayMicroSeconds(VOID *,UINT32 );
-VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16);
-VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16);
-UINT32 CailReadFBData(VOID*,UINT32);
-VOID CailWriteFBData(VOID*,UINT32,UINT32);
-ULONG CailReadPLL(VOID *Context ,ULONG Address);
-VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data);
-ULONG CailReadMC(VOID *Context ,ULONG Address);
-VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data);
-
-
-#if DEBUG_PARSER>0
-VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16);
-#endif
-// Delay function
-#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-
-VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000);
-}
-
-VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32);
-}
-#endif
-
-VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
-}
-
-VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
-{
-}
-
-
-// PCI READ Access
-
-#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- UINT8 rvl;
- CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8));
- return rvl;
-}
-#endif
-
-
-#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- UINT16 rvl;
- CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16));
- return rvl;
-
-}
-#endif
-
-
-
-#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- UINT32 rvl;
- CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32));
- return rvl;
-}
-#endif
-
-
-// PCI WRITE Access
-
-#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8));
-
-}
-
-#endif
-
-
-#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16));
-}
-
-#endif
-
-
-#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32));
-}
-#endif
-
-
-
-
-// System IO Access
-#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- UINT8 rvl;
- rvl=0;
- //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8));
- return rvl;
-}
-#endif
-
-
-#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- UINT16 rvl;
- rvl=0;
- //rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16));
- return rvl;
-
-}
-#endif
-
-
-
-#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- UINT32 rvl;
- rvl=0;
- //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32));
- return rvl;
-}
-#endif
-
-
-// PCI WRITE Access
-
-#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value);
-}
-
-#endif
-
-
-#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value);
-}
-
-#endif
-
-
-#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value);
-}
-#endif
-
-// ATI Registers Memory Mapped Access
-
-#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS)
-
-UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
-}
-
-VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 );
-}
-
-
-VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1));
-}
-
-VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData );
-}
-
-#endif
-
-// ATI Registers IO Mapped Access
-
-#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS )
-UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- //return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
- return 0;
-}
-VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 );
-}
-#endif
-
-// access to Frame buffer, dummy function, need more information to implement it
-UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
-
- return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 ));
-
-}
-
-VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32);
-
-}
-
-
-VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize)
-{
- if(MemSize)
- return(CailAllocateMemory(pDeviceData->CAIL,MemSize));
- else
- return NULL;
-}
-
-
-VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData)
-{
- if( pWorkingTableData)
- CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData);
-}
-
-
-UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- UINT32 ReadData;
- ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
- return ReadData;
-}
-
-VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32);
-}
-
-UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- UINT32 ReadData;
- ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index);
- return ReadData;
-
-}
-
-VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
-{
- CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32);
-
-}
-
-
-
-#if DEBUG_PARSER>0
-VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str)
-{
- CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS);
-}
-
-VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type )
-{
- CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type);
-}
-
-#endif
-
-// EOF
diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h
deleted file mode 100644
index 44a0b35..0000000
--- a/src/AtomBios/includes/CD_Common_Types.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*++
-
-Module Name:
-
- CD_Common_Types.h
-
-Abstract:
-
- Defines common data types to use across platforms/SW components
-
-Revision History:
-
- NEG:17.09.2002 Initiated.
---*/
-#ifndef _COMMON_TYPES_H_
- #define _COMMON_TYPES_H_
-
- #ifndef LINUX
- #if _MSC_EXTENSIONS
-
- //
- // use Microsoft* C complier dependent interger width types
- //
- // typedef unsigned __int64 uint64_t;
- // typedef __int64 int64_t;
- typedef unsigned __int32 uint32_t;
- typedef __int32 int32_t;
-#elif defined (__linux__) || defined (__NetBSD__) || defined(__sun) || defined(__OpenBSD__) || defined (__FreeBSD__)
- typedef unsigned int uint32_t;
- typedef int int32_t;
- #else
- typedef unsigned long uint32_t;
- typedef signed long int32_t;
- #endif
- typedef unsigned char uint8_t;
-#if (defined(__sun) && defined(_CHAR_IS_SIGNED))
- typedef char int8_t;
-#else
- typedef signed char int8_t;
-#endif
- typedef unsigned short uint16_t;
- typedef signed short int16_t;
- #endif
-#ifndef UEFI_BUILD
- typedef signed int intn_t;
- typedef unsigned int uintn_t;
-#else
-#ifndef EFIX64
- typedef signed int intn_t;
- typedef unsigned int uintn_t;
-#endif
-#endif
-#ifndef FGL_LINUX
-#pragma warning ( disable : 4142 )
-#endif
-
-
-#ifndef VOID
-typedef void VOID;
-#endif
-#ifndef UEFI_BUILD
- typedef intn_t INTN;
- typedef uintn_t UINTN;
-#else
-#ifndef EFIX64
- typedef intn_t INTN;
- typedef uintn_t UINTN;
-#endif
-#endif
-#ifndef BOOLEAN
-typedef uint8_t BOOLEAN;
-#endif
-#ifndef INT8
-typedef int8_t INT8;
-#endif
-#ifndef UINT8
-typedef uint8_t UINT8;
-#endif
-#ifndef INT16
-typedef int16_t INT16;
-#endif
-#ifndef UINT16
-typedef uint16_t UINT16;
-#endif
-#ifndef INT32
-typedef int32_t INT32;
-#endif
-#ifndef UINT32
-typedef uint32_t UINT32;
-#endif
-//typedef int64_t INT64;
-//typedef uint64_t UINT64;
-typedef uint8_t CHAR8;
-typedef uint16_t CHAR16;
-#ifndef USHORT
-typedef UINT16 USHORT;
-#endif
-#ifndef UCHAR
-typedef UINT8 UCHAR;
-#endif
-#ifndef ULONG
-typedef UINT32 ULONG;
-#endif
-
-#ifndef _WIN64
-#ifndef ULONG_PTR
-typedef unsigned long ULONG_PTR;
-#endif // ULONG_PTR
-#endif // _WIN64
-
-//#define FAR __far
-#ifndef TRUE
- #define TRUE ((BOOLEAN) 1 == 1)
-#endif
-
-#ifndef FALSE
- #define FALSE ((BOOLEAN) 0 == 1)
-#endif
-
-#ifndef NULL
- #define NULL ((VOID *) 0)
-#endif
-
-//typedef UINTN CD_STATUS;
-
-
-#ifndef FGL_LINUX
-#pragma warning ( default : 4142 )
-#endif
-#endif // _COMMON_TYPES_H_
-
-// EOF
diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h
deleted file mode 100644
index 98fd495..0000000
--- a/src/AtomBios/includes/CD_Definitions.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*++
-
-Module Name:
-
-CD_Definitions.h
-
-Abstract:
-
-Defines Script Language commands
-
-Revision History:
-
-NEG:27.08.2002 Initiated.
---*/
-
-#include "CD_Structs.h"
-#ifndef _CD_DEFINITIONS_H
-#define _CD_DEFINITIONS_H_
-#ifdef DRIVER_PARSER
-VOID *AllocateMemory(VOID *, UINT16);
-VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* );
-#endif
-CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable);
-//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData);
-CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable);
-UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData);
-#endif //CD_DEFINITIONS
diff --git a/src/AtomBios/includes/CD_Opcodes.h b/src/AtomBios/includes/CD_Opcodes.h
deleted file mode 100644
index 2f3bec5..0000000
--- a/src/AtomBios/includes/CD_Opcodes.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*++
-
-Module Name:
-
-CD_OPCODEs.h
-
-Abstract:
-
-Defines Command Decoder OPCODEs
-
-Revision History:
-
-NEG:24.09.2002 Initiated.
---*/
-#ifndef _CD_OPCODES_H_
-#define _CD_OPCODES_H_
-
-typedef enum _OPCODE {
- Reserved_00= 0, // 0 = 0x00
- // MOVE_ group
- MOVE_REG_OPCODE, // 1 = 0x01
- FirstValidCommand=MOVE_REG_OPCODE,
- MOVE_PS_OPCODE, // 2 = 0x02
- MOVE_WS_OPCODE, // 3 = 0x03
- MOVE_FB_OPCODE, // 4 = 0x04
- MOVE_PLL_OPCODE, // 5 = 0x05
- MOVE_MC_OPCODE, // 6 = 0x06
- // Logic group
- AND_REG_OPCODE, // 7 = 0x07
- AND_PS_OPCODE, // 8 = 0x08
- AND_WS_OPCODE, // 9 = 0x09
- AND_FB_OPCODE, // 10 = 0x0A
- AND_PLL_OPCODE, // 11 = 0x0B
- AND_MC_OPCODE, // 12 = 0x0C
- OR_REG_OPCODE, // 13 = 0x0D
- OR_PS_OPCODE, // 14 = 0x0E
- OR_WS_OPCODE, // 15 = 0x0F
- OR_FB_OPCODE, // 16 = 0x10
- OR_PLL_OPCODE, // 17 = 0x11
- OR_MC_OPCODE, // 18 = 0x12
- SHIFT_LEFT_REG_OPCODE, // 19 = 0x13
- SHIFT_LEFT_PS_OPCODE, // 20 = 0x14
- SHIFT_LEFT_WS_OPCODE, // 21 = 0x15
- SHIFT_LEFT_FB_OPCODE, // 22 = 0x16
- SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17
- SHIFT_LEFT_MC_OPCODE, // 24 = 0x18
- SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19
- SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A
- SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B
- SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C
- SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D
- SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E
- // Arithmetic group
- MUL_REG_OPCODE, // 31 = 0x1F
- MUL_PS_OPCODE, // 32 = 0x20
- MUL_WS_OPCODE, // 33 = 0x21
- MUL_FB_OPCODE, // 34 = 0x22
- MUL_PLL_OPCODE, // 35 = 0x23
- MUL_MC_OPCODE, // 36 = 0x24
- DIV_REG_OPCODE, // 37 = 0x25
- DIV_PS_OPCODE, // 38 = 0x26
- DIV_WS_OPCODE, // 39 = 0x27
- DIV_FB_OPCODE, // 40 = 0x28
- DIV_PLL_OPCODE, // 41 = 0x29
- DIV_MC_OPCODE, // 42 = 0x2A
- ADD_REG_OPCODE, // 43 = 0x2B
- ADD_PS_OPCODE, // 44 = 0x2C
- ADD_WS_OPCODE, // 45 = 0x2D
- ADD_FB_OPCODE, // 46 = 0x2E
- ADD_PLL_OPCODE, // 47 = 0x2F
- ADD_MC_OPCODE, // 48 = 0x30
- SUB_REG_OPCODE, // 49 = 0x31
- SUB_PS_OPCODE, // 50 = 0x32
- SUB_WS_OPCODE, // 51 = 0x33
- SUB_FB_OPCODE, // 52 = 0x34
- SUB_PLL_OPCODE, // 53 = 0x35
- SUB_MC_OPCODE, // 54 = 0x36
- // Control grouop
- SET_ATI_PORT_OPCODE, // 55 = 0x37
- SET_PCI_PORT_OPCODE, // 56 = 0x38
- SET_SYS_IO_PORT_OPCODE, // 57 = 0x39
- SET_REG_BLOCK_OPCODE, // 58 = 0x3A
- SET_FB_BASE_OPCODE, // 59 = 0x3B
- COMPARE_REG_OPCODE, // 60 = 0x3C
- COMPARE_PS_OPCODE, // 61 = 0x3D
- COMPARE_WS_OPCODE, // 62 = 0x3E
- COMPARE_FB_OPCODE, // 63 = 0x3F
- COMPARE_PLL_OPCODE, // 64 = 0x40
- COMPARE_MC_OPCODE, // 65 = 0x41
- SWITCH_OPCODE, // 66 = 0x42
- JUMP__OPCODE, // 67 = 0x43
- JUMP_EQUAL_OPCODE, // 68 = 0x44
- JUMP_BELOW_OPCODE, // 69 = 0x45
- JUMP_ABOVE_OPCODE, // 70 = 0x46
- JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47
- JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48
- JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49
- TEST_REG_OPCODE, // 74 = 0x4A
- TEST_PS_OPCODE, // 75 = 0x4B
- TEST_WS_OPCODE, // 76 = 0x4C
- TEST_FB_OPCODE, // 77 = 0x4D
- TEST_PLL_OPCODE, // 78 = 0x4E
- TEST_MC_OPCODE, // 79 = 0x4F
- DELAY_MILLISEC_OPCODE, // 80 = 0x50
- DELAY_MICROSEC_OPCODE, // 81 = 0x51
- CALL_TABLE_OPCODE, // 82 = 0x52
- REPEAT_OPCODE, // 83 = 0x53
- // Miscellaneous group
- CLEAR_REG_OPCODE, // 84 = 0x54
- CLEAR_PS_OPCODE, // 85 = 0x55
- CLEAR_WS_OPCODE, // 86 = 0x56
- CLEAR_FB_OPCODE, // 87 = 0x57
- CLEAR_PLL_OPCODE, // 88 = 0x58
- CLEAR_MC_OPCODE, // 89 = 0x59
- NOP_OPCODE, // 90 = 0x5A
- EOT_OPCODE, // 91 = 0x5B
- MASK_REG_OPCODE, // 92 = 0x5C
- MASK_PS_OPCODE, // 93 = 0x5D
- MASK_WS_OPCODE, // 94 = 0x5E
- MASK_FB_OPCODE, // 95 = 0x5F
- MASK_PLL_OPCODE, // 96 = 0x60
- MASK_MC_OPCODE, // 97 = 0x61
- // BIOS dedicated group
- POST_CARD_OPCODE, // 98 = 0x62
- BEEP_OPCODE, // 99 = 0x63
- SAVE_REG_OPCODE, // 100 = 0x64
- RESTORE_REG_OPCODE, // 101 = 0x65
- SET_DATA_BLOCK_OPCODE, // 102 = 0x66
-
- XOR_REG_OPCODE, // 103 = 0x67
- XOR_PS_OPCODE, // 104 = 0x68
- XOR_WS_OPCODE, // 105 = 0x69
- XOR_FB_OPCODE, // 106 = 0x6a
- XOR_PLL_OPCODE, // 107 = 0x6b
- XOR_MC_OPCODE, // 108 = 0x6c
-
- SHL_REG_OPCODE, // 109 = 0x6d
- SHL_PS_OPCODE, // 110 = 0x6e
- SHL_WS_OPCODE, // 111 = 0x6f
- SHL_FB_OPCODE, // 112 = 0x70
- SHL_PLL_OPCODE, // 113 = 0x71
- SHL_MC_OPCODE, // 114 = 0x72
-
- SHR_REG_OPCODE, // 115 = 0x73
- SHR_PS_OPCODE, // 116 = 0x74
- SHR_WS_OPCODE, // 117 = 0x75
- SHR_FB_OPCODE, // 118 = 0x76
- SHR_PLL_OPCODE, // 119 = 0x77
- SHR_MC_OPCODE, // 120 = 0x78
-
- DEBUG_OPCODE, // 121 = 0x79
- CTB_DS_OPCODE, // 122 = 0x7A
-
- LastValidCommand = CTB_DS_OPCODE,
- // Extension specificaTOR
- Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well
- Reserved_FF = 255 // 255 = 0xFF
-}OPCODE;
-#endif // _CD_OPCODES_H_
diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h
deleted file mode 100644
index c43f81d..0000000
--- a/src/AtomBios/includes/CD_Structs.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*++
-
-Module Name:
-
-CD_Struct.h
-
-Abstract:
-
-Defines Script Language commands
-
-Revision History:
-
-NEG:26.08.2002 Initiated.
---*/
-
-#include "CD_binding.h"
-#ifndef _CD_STRUCTS_H_
-#define _CD_STRUCTS_H_
-
-#ifdef UEFI_BUILD
-typedef UINT16** PTABLE_UNIT_TYPE;
-typedef UINTN TABLE_UNIT_TYPE;
-#else
-typedef UINT16* PTABLE_UNIT_TYPE;
-typedef UINT16 TABLE_UNIT_TYPE;
-#endif
-
-#include <regsdef.h> //This important file is dynamically generated based on the ASIC!!!!
-
-#define PARSER_MAJOR_REVISION 5
-#define PARSER_MINOR_REVISION 0
-
-//#include "atombios.h"
-#if (PARSER_TYPE==DRIVER_TYPE_PARSER)
-#ifdef FGL_LINUX
-#pragma pack(push,1)
-#else
-#pragma pack(push)
-#pragma pack(1)
-#endif
-#endif
-
-#include "CD_Common_Types.h"
-#include "CD_Opcodes.h"
-typedef UINT16 WORK_SPACE_SIZE;
-typedef enum _CD_STATUS{
- CD_SUCCESS,
- CD_CALL_TABLE,
- CD_COMPLETED=0x10,
- CD_GENERAL_ERROR=0x80,
- CD_INVALID_OPCODE,
- CD_NOT_IMPLEMENTED,
- CD_EXEC_TABLE_NOT_FOUND,
- CD_EXEC_PARAMETER_ERROR,
- CD_EXEC_PARSER_ERROR,
- CD_INVALID_DESTINATION_TYPE,
- CD_UNEXPECTED_BEHAVIOR,
- CD_INVALID_SWITCH_OPERAND_SIZE
-}CD_STATUS;
-
-#define PARSER_STRINGS 0
-#define PARSER_DEC 1
-#define PARSER_HEX 2
-
-#define DB_CURRENT_COMMAND_TABLE 0xFF
-
-#define TABLE_FORMAT_BIOS 0
-#define TABLE_FORMAT_EASF 1
-
-#define EASF_TABLE_INDEX_MASK 0xfc
-#define EASF_TABLE_ATTR_MASK 0x03
-
-#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED)
-#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS)
-
-
-#if (BIOS_PARSER==1)
-#ifdef _H2INC
-#define STACK_BASED
-#else
-extern __segment farstack;
-#define STACK_BASED __based(farstack)
-#endif
-#else
-#define STACK_BASED
-#endif
-
-typedef enum _COMPARE_FLAGS{
- Below,
- Equal,
- Above,
- NotEqual,
- Overflow,
- NoCondition
-}COMPARE_FLAGS;
-
-typedef UINT16 IO_BASE_ADDR;
-
-typedef struct _BUS_DEV_FUNC_PCI_ADDR{
- UINT8 Register;
- UINT8 Function;
- UINT8 Device;
- UINT8 Bus;
-} BUS_DEV_FUNC_PCI_ADDR;
-
-typedef struct _BUS_DEV_FUNC{
- UINT8 Function : 3;
- UINT8 Device : 5;
- UINT8 Bus;
-} BUS_DEV_FUNC;
-
-#ifndef UEFI_BUILD
-typedef struct _PCI_CONFIG_ACCESS_CF8{
- UINT32 Reg : 8;
- UINT32 Func : 3;
- UINT32 Dev : 5;
- UINT32 Bus : 8;
- UINT32 Reserved: 7;
- UINT32 Enable : 1;
-} PCI_CONFIG_ACCESS_CF8;
-#endif
-
-typedef enum _MEM_RESOURCE {
- Stack_Resource,
- FrameBuffer_Resource,
- BIOS_Image_Resource
-}MEM_RESOURCE;
-
-typedef enum _PORTS{
- ATI_RegsPort,
- PCI_Port,
- SystemIO_Port
-}PORTS;
-
-typedef enum _OPERAND_TYPE {
- typeRegister,
- typeParamSpace,
- typeWorkSpace,
- typeFrameBuffer,
- typeIndirect,
- typeDirect,
- typePLL,
- typeMC
-}OPERAND_TYPE;
-
-typedef enum _DESTINATION_OPERAND_TYPE {
- destRegister,
- destParamSpace,
- destWorkSpace,
- destFrameBuffer,
- destPLL,
- destMC
-}DESTINATION_OPERAND_TYPE;
-
-typedef enum _SOURCE_OPERAND_TYPE {
- sourceRegister,
- sourceParamSpace,
- sourceWorkSpace,
- sourceFrameBuffer,
- sourceIndirect,
- sourceDirect,
- sourcePLL,
- sourceMC
-}SOURCE_OPERAND_TYPE;
-
-typedef enum _ALIGNMENT_TYPE {
- alignmentDword,
- alignmentLowerWord,
- alignmentMiddleWord,
- alignmentUpperWord,
- alignmentByte0,
- alignmentByte1,
- alignmentByte2,
- alignmentByte3
-}ALIGNMENT_TYPE;
-
-
-#define INDIRECT_IO_READ 0
-#define INDIRECT_IO_WRITE 0x80
-#define INDIRECT_IO_MM 0
-#define INDIRECT_IO_PLL 1
-#define INDIRECT_IO_MC 2
-
-typedef struct _PARAMETERS_TYPE{
- UINT8 Destination;
- UINT8 Source;
-}PARAMETERS_TYPE;
-/* The following structures don't used to allocate any type of objects(variables).
- they are serve the only purpose: Get proper access to data(commands), found in the tables*/
-typedef struct _PA_BYTE_BYTE{
- UINT8 PA_Destination;
- UINT8 PA_Source;
- UINT8 PA_Padding[8];
-}PA_BYTE_BYTE;
-typedef struct _PA_BYTE_WORD{
- UINT8 PA_Destination;
- UINT16 PA_Source;
- UINT8 PA_Padding[7];
-}PA_BYTE_WORD;
-typedef struct _PA_BYTE_DWORD{
- UINT8 PA_Destination;
- UINT32 PA_Source;
- UINT8 PA_Padding[5];
-}PA_BYTE_DWORD;
-typedef struct _PA_WORD_BYTE{
- UINT16 PA_Destination;
- UINT8 PA_Source;
- UINT8 PA_Padding[7];
-}PA_WORD_BYTE;
-typedef struct _PA_WORD_WORD{
- UINT16 PA_Destination;
- UINT16 PA_Source;
- UINT8 PA_Padding[6];
-}PA_WORD_WORD;
-typedef struct _PA_WORD_DWORD{
- UINT16 PA_Destination;
- UINT32 PA_Source;
- UINT8 PA_Padding[4];
-}PA_WORD_DWORD;
-typedef struct _PA_WORD_XX{
- UINT16 PA_Destination;
- UINT8 PA_Padding[8];
-}PA_WORD_XX;
-typedef struct _PA_BYTE_XX{
- UINT8 PA_Destination;
- UINT8 PA_Padding[9];
-}PA_BYTE_XX;
-/*The following 6 definitions used for Mask operation*/
-typedef struct _PA_BYTE_BYTE_BYTE{
- UINT8 PA_Destination;
- UINT8 PA_AndMaskByte;
- UINT8 PA_OrMaskByte;
- UINT8 PA_Padding[7];
-}PA_BYTE_BYTE_BYTE;
-typedef struct _PA_BYTE_WORD_WORD{
- UINT8 PA_Destination;
- UINT16 PA_AndMaskWord;
- UINT16 PA_OrMaskWord;
- UINT8 PA_Padding[5];
-}PA_BYTE_WORD_WORD;
-typedef struct _PA_BYTE_DWORD_DWORD{
- UINT8 PA_Destination;
- UINT32 PA_AndMaskDword;
- UINT32 PA_OrMaskDword;
- UINT8 PA_Padding;
-}PA_BYTE_DWORD_DWORD;
-typedef struct _PA_WORD_BYTE_BYTE{
- UINT16 PA_Destination;
- UINT8 PA_AndMaskByte;
- UINT8 PA_OrMaskByte;
- UINT8 PA_Padding[6];
-}PA_WORD_BYTE_BYTE;
-typedef struct _PA_WORD_WORD_WORD{
- UINT16 PA_Destination;
- UINT16 PA_AndMaskWord;
- UINT16 PA_OrMaskWord;
- UINT8 PA_Padding[4];
-}PA_WORD_WORD_WORD;
-typedef struct _PA_WORD_DWORD_DWORD{
- UINT16 PA_Destination;
- UINT32 PA_AndMaskDword;
- UINT32 PA_OrMaskDword;
-}PA_WORD_DWORD_DWORD;
-
-
-typedef union _PARAMETER_ACCESS {
- PA_BYTE_XX ByteXX;
- PA_BYTE_BYTE ByteByte;
- PA_BYTE_WORD ByteWord;
- PA_BYTE_DWORD ByteDword;
- PA_WORD_BYTE WordByte;
- PA_WORD_WORD WordWord;
- PA_WORD_DWORD WordDword;
- PA_WORD_XX WordXX;
-/*The following 6 definitions used for Mask operation*/
- PA_BYTE_BYTE_BYTE ByteByteAndByteOr;
- PA_BYTE_WORD_WORD ByteWordAndWordOr;
- PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr;
- PA_WORD_BYTE_BYTE WordByteAndByteOr;
- PA_WORD_WORD_WORD WordWordAndWordOr;
- PA_WORD_DWORD_DWORD WordDwordAndDwordOr;
-}PARAMETER_ACCESS;
-
-typedef struct _COMMAND_ATTRIBUTE {
- UINT8 Source:3;
- UINT8 SourceAlignment:3;
- UINT8 DestinationAlignment:2;
-}COMMAND_ATTRIBUTE;
-
-typedef struct _SOURCE_DESTINATION_ALIGNMENT{
- UINT8 DestAlignment;
- UINT8 SrcAlignment;
-}SOURCE_DESTINATION_ALIGNMENT;
-typedef struct _MULTIPLICATION_RESULT{
- UINT32 Low32Bit;
- UINT32 High32Bit;
-}MULTIPLICATION_RESULT;
-typedef struct _DIVISION_RESULT{
- UINT32 Quotient32;
- UINT32 Reminder32;
-}DIVISION_RESULT;
-typedef union _DIVISION_MULTIPLICATION_RESULT{
- MULTIPLICATION_RESULT Multiplication;
- DIVISION_RESULT Division;
-}DIVISION_MULTIPLICATION_RESULT;
-typedef struct _COMMAND_HEADER {
- UINT8 Opcode;
- COMMAND_ATTRIBUTE Attribute;
-}COMMAND_HEADER;
-
-typedef struct _GENERIC_ATTRIBUTE_COMMAND{
- COMMAND_HEADER Header;
- PARAMETER_ACCESS Parameters;
-} GENERIC_ATTRIBUTE_COMMAND;
-
-typedef struct _COMMAND_TYPE_1{
- UINT8 Opcode;
- PARAMETER_ACCESS Parameters;
-} COMMAND_TYPE_1;
-
-typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{
- UINT8 Opcode;
- UINT16 CD_Offset16;
-} COMMAND_TYPE_OPCODE_OFFSET16;
-
-typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{
- UINT8 Opcode;
- UINT32 CD_Offset32;
-} COMMAND_TYPE_OPCODE_OFFSET32;
-
-typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{
- UINT8 Opcode;
- UINT8 Value;
-} COMMAND_TYPE_OPCODE_VALUE_BYTE;
-
-typedef union _COMMAND_SPECIFIC_UNION{
- UINT8 ContinueSwitch;
- UINT8 ControlOperandSourcePosition;
- UINT8 IndexInMasterTable;
-} COMMAND_SPECIFIC_UNION;
-
-
-typedef struct _CD_GENERIC_BYTE{
- UINT16 CommandType:3;
- UINT16 CurrentParameterSize:3;
- UINT16 CommandAccessType:3;
- UINT16 CurrentPort:2;
- UINT16 PS_SizeInDwordsUsedByCallingTable:5;
-}CD_GENERIC_BYTE;
-
-typedef UINT8 COMMAND_TYPE_OPCODE_ONLY;
-
-typedef UINT8 COMMAND_HEADER_POINTER;
-
-
-#if (PARSER_TYPE==BIOS_TYPE_PARSER)
-
-typedef struct _DEVICE_DATA {
- UINT32 STACK_BASED *pParameterSpace;
- UINT8 *pBIOS_Image;
- UINT8 format;
-#if (IO_INTERFACE==PARSER_INTERFACE)
- IO_BASE_ADDR IOBase;
-#endif
-} DEVICE_DATA;
-
-#else
-
-typedef struct _DEVICE_DATA {
- UINT32 *pParameterSpace;
- VOID *CAIL;
- UINT8 *pBIOS_Image;
- UINT32 format;
-} DEVICE_DATA;
-
-#endif
-
-struct _PARSER_TEMP_DATA;
-typedef UINT32 WORKSPACE_POINTER;
-
-struct _WORKING_TABLE_DATA{
- UINT8 * pTableHead;
- COMMAND_HEADER_POINTER * IP; // Commands pointer
- WORKSPACE_POINTER STACK_BASED * pWorkSpace;
- struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData;
-};
-
-
-
-typedef struct _PARSER_TEMP_DATA{
- DEVICE_DATA STACK_BASED *pDeviceData;
- struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData;
- UINT32 SourceData32;
- UINT32 DestData32;
- DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision;
- UINT32 Index;
- UINT32 CurrentFB_Window;
- UINT32 IndirectData;
- UINT16 CurrentRegBlock;
- TABLE_UNIT_TYPE CurrentDataBlock;
- UINT16 AttributesData;
-// UINT8 *IndirectIOTable;
- UINT8 *IndirectIOTablePointer;
- GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand;
- SOURCE_DESTINATION_ALIGNMENT CD_Mask;
- PARAMETERS_TYPE ParametersType;
- CD_GENERIC_BYTE Multipurpose;
- UINT8 CompareFlags;
- COMMAND_SPECIFIC_UNION CommandSpecific;
- CD_STATUS Status;
- UINT8 Shift2MaskConverter;
- UINT8 CurrentPortID;
-} PARSER_TEMP_DATA;
-
-
-typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA;
-
-
-
-typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-typedef struct _COMMANDS_PROPERTIES
-{
- COMMANDS_DECODER function;
- UINT8 destination;
- UINT8 headersize;
-} COMMANDS_PROPERTIES;
-
-typedef struct _INDIRECT_IO_PARSER_COMMANDS
-{
- COMMANDS_DECODER func;
- UINT8 csize;
-} INDIRECT_IO_PARSER_COMMANDS;
-
-#if (PARSER_TYPE==DRIVER_TYPE_PARSER)
-#pragma pack(pop)
-#endif
-
-#endif
diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h
deleted file mode 100644
index 7b021d3..0000000
--- a/src/AtomBios/includes/CD_binding.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef NT_BUILD
-#ifdef LH_BUILD
-#include <ntddk.h>
-#else
-#include <miniport.h>
-#endif // LH_BUILD
-#endif // NT_BUILD
-
-
-#if ((defined DBG) || (defined DEBUG))
-#define DEBUG_PARSER 1 // enable parser debug output
-#endif
-
-#define USE_SWITCH_COMMAND 1
-#define DRIVER_TYPE_PARSER 0x48
-
-#define PARSER_TYPE DRIVER_TYPE_PARSER
-
-#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y)
-#define FreeWorkSpace(x,y) ReleaseMemory(x,y)
-
-#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image))
-#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead))
-
diff --git a/src/AtomBios/includes/CD_hw_services.h b/src/AtomBios/includes/CD_hw_services.h
deleted file mode 100644
index 529fde5..0000000
--- a/src/AtomBios/includes/CD_hw_services.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _HW_SERVICES_INTERFACE_
-#define _HW_SERVICES_INTERFACE_
-
-#include "CD_Common_Types.h"
-#include "CD_Structs.h"
-
-
-// CD - from Command Decoder
-typedef UINT16 CD_REG_INDEX;
-typedef UINT8 CD_PCI_OFFSET;
-typedef UINT16 CD_FB_OFFSET;
-typedef UINT16 CD_SYS_IO_PORT;
-typedef UINT8 CD_MEM_TYPE;
-typedef UINT8 CD_MEM_SIZE;
-
-typedef VOID * CD_VIRT_ADDR;
-typedef UINT32 CD_PHYS_ADDR;
-typedef UINT32 CD_IO_ADDR;
-
-/***********************ATI Registers access routines**************************/
-
- VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-/************************PCI Registers access routines*************************/
-
- UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-/***************************Frame buffer access routines************************/
-
- UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-/******************System IO Registers access routines********************/
-
- UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-/****************************Delay routines****************************************/
-
- VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value
-
- VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
- VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
-
-
-//************************Tracing/Debugging routines and macroses******************/
-#define KEYPRESSED -1
-
-#if (DEBUG_PARSER != 0)
-
-#ifdef DRIVER_PARSER
-
-VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str);
-VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type );
-
-// Level 1 : can use WorkingTableData or pDeviceData
-#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string);
-#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string)
-#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC);
-#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX);
-
-// Level 2:can use pWorkingTableData
-#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string);
-#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string)
-#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC);
-#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX);
-
-// Level 3:can use pWorkingTableData
-#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string);
-#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string)
-#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC);
-#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX);
-
-#define CD_TRACE(string)
-#define CD_WAIT(what)
-#define CD_BREAKPOINT()
-
-#else
-
-
-VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console
-VOID CD_postcode(UINT8 value); //output post code to debug console
-VOID CD_print (UINT8 *str); //output text to debug console
-VOID CD_print_dec(UINTN value); //output value in decimal format to debug console
-VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console
-VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console
-VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires
-VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium)
-
-#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
-#define CD_POSTCODE(value) CD_postcode(value)
-#define CD_TRACE(string) CD_print(string)
-#define CD_TRACETAB(string) CD_print(string)
-#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value))
-#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) )
-#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
-#define CD_WAIT(what) CD_wait((INT32)what)
-#define CD_BREAKPOINT() CD_breakpoint()
-
-#if (DEBUG_PARSER == 4)
-#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
-#define CD_POSTCODE_DL4(value) CD_postcode(value)
-#define CD_TRACE_DL4(string) CD_print(string)
-#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string)
-#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value))
-#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) )
-#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
-#define CD_WAIT_DL4(what) CD_wait((INT32)what)
-#define CD_BREAKPOINT_DL4() CD_breakpoint()
-#else
-#define CD_ASSERT_DL4(condition)
-#define CD_POSTCODE_DL4(value)
-#define CD_TRACE_DL4(string)
-#define CD_TRACETAB_DL4(string)
-#define CD_TRACEDEC_DL4(value)
-#define CD_TRACEHEX_DL4(value)
-#define CD_TRACEBUF_DL4(pointer, len)
-#define CD_WAIT_DL4(what)
-#define CD_BREAKPOINT_DL4()
-#endif
-
-#if (DEBUG_PARSER >= 3)
-#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
-#define CD_POSTCODE_DL3(value) CD_postcode(value)
-#define CD_TRACE_DL3(string) CD_print(string)
-#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string)
-#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value))
-#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) )
-#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
-#define CD_WAIT_DL3(what) CD_wait((INT32)what)
-#define CD_BREAKPOINT_DL3() CD_breakpoint()
-#else
-#define CD_ASSERT_DL3(condition)
-#define CD_POSTCODE_DL3(value)
-#define CD_TRACE_DL3(string)
-#define CD_TRACETAB_DL3(string)
-#define CD_TRACEDEC_DL3(value)
-#define CD_TRACEHEX_DL3(value)
-#define CD_TRACEBUF_DL3(pointer, len)
-#define CD_WAIT_DL3(what)
-#define CD_BREAKPOINT_DL3()
-#endif
-
-
-#if (DEBUG_PARSER >= 2)
-#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
-#define CD_POSTCODE_DL2(value) CD_postcode(value)
-#define CD_TRACE_DL2(string) CD_print(string)
-#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string)
-#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value))
-#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) )
-#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
-#define CD_WAIT_DL2(what) CD_wait((INT32)what)
-#define CD_BREAKPOINT_DL2() CD_breakpoint()
-#else
-#define CD_ASSERT_DL2(condition)
-#define CD_POSTCODE_DL2(value)
-#define CD_TRACE_DL2(string)
-#define CD_TRACETAB_DL2(string)
-#define CD_TRACEDEC_DL2(value)
-#define CD_TRACEHEX_DL2(value)
-#define CD_TRACEBUF_DL2(pointer, len)
-#define CD_WAIT_DL2(what)
-#define CD_BREAKPOINT_DL2()
-#endif
-
-
-#if (DEBUG_PARSER >= 1)
-#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__)
-#define CD_POSTCODE_DL1(value) CD_postcode(value)
-#define CD_TRACE_DL1(string) CD_print(string)
-#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string)
-#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value))
-#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) )
-#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len)
-#define CD_WAIT_DL1(what) CD_wait((INT32)what)
-#define CD_BREAKPOINT_DL1() CD_breakpoint()
-#else
-#define CD_ASSERT_DL1(condition)
-#define CD_POSTCODE_DL1(value)
-#define CD_TRACE_DL1(string)
-#define CD_TRACETAB_DL1(string)
-#define CD_TRACEDEC_DL1(value)
-#define CD_TRACEHEX_DL1(value)
-#define CD_TRACEBUF_DL1(pointer, len)
-#define CD_WAIT_DL1(what)
-#define CD_BREAKPOINT_DL1()
-#endif
-
-#endif //#ifdef DRIVER_PARSER
-
-
-#else
-
-#define CD_ASSERT(condition)
-#define CD_POSTCODE(value)
-#define CD_TRACE(string)
-#define CD_TRACEDEC(value)
-#define CD_TRACEHEX(value)
-#define CD_TRACEBUF(pointer, len)
-#define CD_WAIT(what)
-#define CD_BREAKPOINT()
-
-#define CD_ASSERT_DL4(condition)
-#define CD_POSTCODE_DL4(value)
-#define CD_TRACE_DL4(string)
-#define CD_TRACETAB_DL4(string)
-#define CD_TRACEDEC_DL4(value)
-#define CD_TRACEHEX_DL4(value)
-#define CD_TRACEBUF_DL4(pointer, len)
-#define CD_WAIT_DL4(what)
-#define CD_BREAKPOINT_DL4()
-
-#define CD_ASSERT_DL3(condition)
-#define CD_POSTCODE_DL3(value)
-#define CD_TRACE_DL3(string)
-#define CD_TRACETAB_DL3(string)
-#define CD_TRACEDEC_DL3(value)
-#define CD_TRACEHEX_DL3(value)
-#define CD_TRACEBUF_DL3(pointer, len)
-#define CD_WAIT_DL3(what)
-#define CD_BREAKPOINT_DL3()
-
-#define CD_ASSERT_DL2(condition)
-#define CD_POSTCODE_DL2(value)
-#define CD_TRACE_DL2(string)
-#define CD_TRACETAB_DL2(string)
-#define CD_TRACEDEC_DL2(value)
-#define CD_TRACEHEX_DL2(value)
-#define CD_TRACEBUF_DL2(pointer, len)
-#define CD_WAIT_DL2(what)
-#define CD_BREAKPOINT_DL2()
-
-#define CD_ASSERT_DL1(condition)
-#define CD_POSTCODE_DL1(value)
-#define CD_TRACE_DL1(string)
-#define CD_TRACETAB_DL1(string)
-#define CD_TRACEDEC_DL1(value)
-#define CD_TRACEHEX_DL1(value)
-#define CD_TRACEBUF_DL1(pointer, len)
-#define CD_WAIT_DL1(what)
-#define CD_BREAKPOINT_DL1()
-
-
-#endif //#if (DEBUG_PARSER > 0)
-
-
-#ifdef CHECKSTACK
-VOID CD_fillstack(UINT16 size);
-UINT16 CD_checkstack(UINT16 size);
-#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize)
-#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize)
-#else
-#define CD_CHECKSTACK(stacksize) 0
-#define CD_FILLSTACK(stacksize)
-#endif
-
-
-#endif
diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h
deleted file mode 100644
index 24c25fc..0000000
--- a/src/AtomBios/includes/Decoder.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*++
-
-Module Name:
-
-Decoder.h
-
-Abstract:
-
-Includes all helper headers
-
-Revision History:
-
-NEG:27.08.2002 Initiated.
---*/
-#ifndef _DECODER_H_
-#define _DECODER_H_
-#define WS_QUOTIENT_C 64
-#define WS_REMINDER_C (WS_QUOTIENT_C+1)
-#define WS_DATAPTR_C (WS_REMINDER_C+1)
-#define WS_SHIFT_C (WS_DATAPTR_C+1)
-#define WS_OR_MASK_C (WS_SHIFT_C+1)
-#define WS_AND_MASK_C (WS_OR_MASK_C+1)
-#define WS_FB_WINDOW_C (WS_AND_MASK_C+1)
-#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1)
-#define PARSER_VERSION_MAJOR 0x00000000
-#define PARSER_VERSION_MINOR 0x0000000E
-#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR)
-#include "CD_binding.h"
-#include "CD_Common_Types.h"
-#include "CD_hw_services.h"
-#include "CD_Structs.h"
-#include "CD_Definitions.h"
-#include "CD_Opcodes.h"
-
-#define SOURCE_ONLY_CMD_TYPE 0//0xFE
-#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD
-#define DESTINATION_ONLY_CMD_TYPE 2//0xFC
-
-#define ACCESS_TYPE_BYTE 0//0xF9
-#define ACCESS_TYPE_WORD 1//0xF8
-#define ACCESS_TYPE_DWORD 2//0xF7
-#define SWITCH_TYPE_ACCESS 3//0xF6
-
-#define CD_CONTINUE 0//0xFB
-#define CD_STOP 1//0xFA
-
-
-#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE)
-#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand))
-#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE))
-#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE))
-#define CheckCaseAndAdjustIP_Macro(size) \
- if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\
- pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\
- pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\
- }else{\
- pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\
- +sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\
- }
-
-#endif
-/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/
-
-// EOF
diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h
deleted file mode 100644
index e6d41fe..0000000
--- a/src/AtomBios/includes/ObjectID.h
+++ /dev/null
@@ -1,484 +0,0 @@
-/*
-* Copyright 2006-2007 Advanced Micro Devices, Inc.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a
-* copy of this software and associated documentation files (the "Software"),
-* to deal in the Software without restriction, including without limitation
-* the rights to use, copy, modify, merge, publish, distribute, sublicense,
-* and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-* OTHER DEALINGS IN THE SOFTWARE.
-*/
-/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
-
-#ifndef _OBJECTID_H
-#define _OBJECTID_H
-
-#if defined(_X86_)
-#pragma pack(1)
-#endif
-
-/****************************************************/
-/* Graphics Object Type Definition */
-/****************************************************/
-#define GRAPH_OBJECT_TYPE_NONE 0x0
-#define GRAPH_OBJECT_TYPE_GPU 0x1
-#define GRAPH_OBJECT_TYPE_ENCODER 0x2
-#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
-#define GRAPH_OBJECT_TYPE_ROUTER 0x4
-/* deleted */
-
-/****************************************************/
-/* Encoder Object ID Definition */
-/****************************************************/
-#define ENCODER_OBJECT_ID_NONE 0x00
-
-/* Radeon Class Display Hardware */
-#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
-#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02
-#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03
-#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04
-#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */
-#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06
-#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07
-
-/* External Third Party Encoders */
-#define ENCODER_OBJECT_ID_SI170B 0x08
-#define ENCODER_OBJECT_ID_CH7303 0x09
-#define ENCODER_OBJECT_ID_CH7301 0x0A
-#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */
-#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C
-#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D
-#define ENCODER_OBJECT_ID_TITFP513 0x0E
-#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */
-#define ENCODER_OBJECT_ID_VT1623 0x10
-#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
-#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
-/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */
-#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */
-#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
-#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19
-#define ENCODER_OBJECT_ID_VT1625 0x1A
-#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B
-#define ENCODER_OBJECT_ID_DP_AN9801 0x1C
-#define ENCODER_OBJECT_ID_DP_DP501 0x1D
-#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F
-
-/****************************************************/
-/* Connector Object ID Definition */
-/****************************************************/
-#define CONNECTOR_OBJECT_ID_NONE 0x00
-#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
-#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
-#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
-#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04
-#define CONNECTOR_OBJECT_ID_VGA 0x05
-#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06
-#define CONNECTOR_OBJECT_ID_SVIDEO 0x07
-#define CONNECTOR_OBJECT_ID_YPbPr 0x08
-#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09
-#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */
-#define CONNECTOR_OBJECT_ID_SCART 0x0B
-#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C
-#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D
-#define CONNECTOR_OBJECT_ID_LVDS 0x0E
-#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F
-#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10
-#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
-#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
-#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
-
-/* deleted */
-
-/****************************************************/
-/* Router Object ID Definition */
-/****************************************************/
-#define ROUTER_OBJECT_ID_NONE 0x00
-#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
-
-/****************************************************/
-// Graphics Object ENUM ID Definition */
-/****************************************************/
-#define GRAPH_OBJECT_ENUM_ID1 0x01
-#define GRAPH_OBJECT_ENUM_ID2 0x02
-#define GRAPH_OBJECT_ENUM_ID3 0x03
-#define GRAPH_OBJECT_ENUM_ID4 0x04
-
-/****************************************************/
-/* Graphics Object ID Bit definition */
-/****************************************************/
-#define OBJECT_ID_MASK 0x00FF
-#define ENUM_ID_MASK 0x0700
-#define RESERVED1_ID_MASK 0x0800
-#define OBJECT_TYPE_MASK 0x7000
-#define RESERVED2_ID_MASK 0x8000
-
-#define OBJECT_ID_SHIFT 0x00
-#define ENUM_ID_SHIFT 0x08
-#define OBJECT_TYPE_SHIFT 0x0C
-
-
-/****************************************************/
-/* Graphics Object family definition */
-/****************************************************/
-#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
- GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
-/****************************************************/
-/* GPU Object ID definition - Shared with BIOS */
-/****************************************************/
-#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
-
-/****************************************************/
-/* Encoder Object ID definition - Shared with BIOS */
-/****************************************************/
-/*
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
-#define ENCODER_SIL170B_ENUM_ID1 0x2108
-#define ENCODER_CH7303_ENUM_ID1 0x2109
-#define ENCODER_CH7301_ENUM_ID1 0x210A
-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C
-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D
-#define ENCODER_TITFP513_ENUM_ID1 0x210E
-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F
-#define ENCODER_VT1623_ENUM_ID1 0x2110
-#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111
-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
-#define ENCODER_SI178_ENUM_ID1 0x2117
-#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
-#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
-#define ENCODER_VT1625_ENUM_ID1 0x211A
-#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B
-#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C
-#define ENCODER_DP_DP501_ENUM_ID1 0x211D
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E
-*/
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT
-
-#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
-
-#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
-
-/****************************************************/
-/* Connector Object ID definition - Shared with BIOS */
-/****************************************************/
-/*
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104
-#define CONNECTOR_VGA_ENUM_ID1 0x3105
-#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106
-#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107
-#define CONNECTOR_YPbPr_ENUM_ID1 0x3108
-#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109
-#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A
-#define CONNECTOR_SCART_ENUM_ID1 0x310B
-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C
-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D
-#define CONNECTOR_LVDS_ENUM_ID1 0x310E
-#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110
-*/
-#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-/****************************************************/
-/* Router Object ID definition - Shared with BIOS */
-/****************************************************/
-#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
-
-/* deleted */
-
-/****************************************************/
-/* Object Cap definition - Shared with BIOS */
-/****************************************************/
-#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
-#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L
-
-
-#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01
-#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02
-#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03
-
-#if defined(_X86_)
-#pragma pack()
-#endif
-
-#endif /*GRAPHICTYPE */
-
-
-
-
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
deleted file mode 100644
index 16fcf2d..0000000
--- a/src/AtomBios/includes/atombios.h
+++ /dev/null
@@ -1,4436 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-/****************************************************************************/
-/*Portion I: Definitions shared between VBIOS and Driver */
-/****************************************************************************/
-
-
-#ifndef _ATOMBIOS_H
-#define _ATOMBIOS_H
-
-#define ATOM_VERSION_MAJOR 0x00020000
-#define ATOM_VERSION_MINOR 0x00000002
-
-#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
-
-
-#ifdef _H2INC
- #ifndef ULONG
- typedef unsigned long ULONG;
- #endif
-
- #ifndef UCHAR
- typedef unsigned char UCHAR;
- #endif
-
- #ifndef USHORT
- typedef unsigned short USHORT;
- #endif
-#endif
-
-#define ATOM_DAC_A 0
-#define ATOM_DAC_B 1
-#define ATOM_EXT_DAC 2
-
-#define ATOM_CRTC1 0
-#define ATOM_CRTC2 1
-
-#define ATOM_DIGA 0
-#define ATOM_DIGB 1
-
-#define ATOM_PPLL1 0
-#define ATOM_PPLL2 1
-
-#define ATOM_SCALER1 0
-#define ATOM_SCALER2 1
-
-#define ATOM_SCALER_DISABLE 0
-#define ATOM_SCALER_CENTER 1
-#define ATOM_SCALER_EXPANSION 2
-#define ATOM_SCALER_MULTI_EX 3
-
-#define ATOM_DISABLE 0
-#define ATOM_ENABLE 1
-#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
-#define ATOM_LCD_BLON (ATOM_ENABLE+2)
-#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
-#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
-#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
-#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
-
-#define ATOM_BLANKING 1
-#define ATOM_BLANKING_OFF 0
-
-#define ATOM_CURSOR1 0
-#define ATOM_CURSOR2 1
-
-#define ATOM_ICON1 0
-#define ATOM_ICON2 1
-
-#define ATOM_CRT1 0
-#define ATOM_CRT2 1
-
-#define ATOM_TV_NTSC 1
-#define ATOM_TV_NTSCJ 2
-#define ATOM_TV_PAL 3
-#define ATOM_TV_PALM 4
-#define ATOM_TV_PALCN 5
-#define ATOM_TV_PALN 6
-#define ATOM_TV_PAL60 7
-#define ATOM_TV_SECAM 8
-#define ATOM_TV_CV 16
-
-#define ATOM_DAC1_PS2 1
-#define ATOM_DAC1_CV 2
-#define ATOM_DAC1_NTSC 3
-#define ATOM_DAC1_PAL 4
-
-#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
-#define ATOM_DAC2_CV ATOM_DAC1_CV
-#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
-#define ATOM_DAC2_PAL ATOM_DAC1_PAL
-
-#define ATOM_PM_ON 0
-#define ATOM_PM_STANDBY 1
-#define ATOM_PM_SUSPEND 2
-#define ATOM_PM_OFF 3
-
-/* Bit0:{=0:single, =1:dual},
- Bit1 {=0:666RGB, =1:888RGB},
- Bit2:3:{Grey level}
- Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
-
-#define ATOM_PANEL_MISC_DUAL 0x00000001
-#define ATOM_PANEL_MISC_888RGB 0x00000002
-#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
-#define ATOM_PANEL_MISC_FPDI 0x00000010
-#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
-#define ATOM_PANEL_MISC_SPATIAL 0x00000020
-#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
-#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
-
-
-#define MEMTYPE_DDR1 "DDR1"
-#define MEMTYPE_DDR2 "DDR2"
-#define MEMTYPE_DDR3 "DDR3"
-#define MEMTYPE_DDR4 "DDR4"
-
-#define ASIC_BUS_TYPE_PCI "PCI"
-#define ASIC_BUS_TYPE_AGP "AGP"
-#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
-
-/* Maximum size of that FireGL flag string */
-
-#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
-#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
-
-#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
-#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
-
-#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
-#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
-
-#define HW_ASSISTED_I2C_STATUS_FAILURE 2
-#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
-
-#pragma pack(1) /* BIOS data must use byte aligment */
-
-/* Define offset to location of ROM header. */
-
-#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
-#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
-
-#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
-#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
-#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
-#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
-
-/* Common header for all ROM Data tables.
- Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
- And the pointer actually points to this header. */
-
-typedef struct _ATOM_COMMON_TABLE_HEADER
-{
- USHORT usStructureSize;
- UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
- UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
- /*Image can't be updated, while Driver needs to carry the new table! */
-}ATOM_COMMON_TABLE_HEADER;
-
-typedef struct _ATOM_ROM_HEADER
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
- atombios should init it as "ATOM", don't change the position */
- USHORT usBiosRuntimeSegmentAddress;
- USHORT usProtectedModeInfoOffset;
- USHORT usConfigFilenameOffset;
- USHORT usCRC_BlockOffset;
- USHORT usBIOS_BootupMessageOffset;
- USHORT usInt10Offset;
- USHORT usPciBusDevInitCode;
- USHORT usIoBaseAddress;
- USHORT usSubsystemVendorID;
- USHORT usSubsystemID;
- USHORT usPCI_InfoOffset;
- USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
- USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
- UCHAR ucExtendedFunctionCode;
- UCHAR ucReserved;
-}ATOM_ROM_HEADER;
-
-/*==============================Command Table Portion==================================== */
-
-#ifdef UEFI_BUILD
- #define UTEMP USHORT
- #define USHORT void*
-#endif
-
-typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
- USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
- USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
- USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
- USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
- USHORT DIGxEncoderControl; //Only used by Bios
- USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
- USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
- USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
- USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
- USHORT GPIOPinControl; //Atomic Table, only used by Bios
- USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
- USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
- USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
- USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
- USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
- USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
- USHORT MemoryPLLInit;
- USHORT AdjustDisplayPll; //only used by Bios
- USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
- USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
- USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios
- USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
- USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
- USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT CV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT GetConditionalGoldenSetting; //only used by Bios
- USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
- USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
- USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3
- USHORT TV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT EnableScaler; //Atomic Table, used only by Bios
- USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
- USHORT EnableVGA_Access; //Obsolete , only used by Bios
- USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
- USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
- USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
- USHORT UpdateCRTC_DoubleBufferRegisters;
- USHORT LUT_AutoFill; //Atomic Table, only used by Bios
- USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
- USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
- USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT VRAM_BlockDetectionByStrap;
- USHORT MemoryCleanUp; //Atomic Table, only used by Bios
- USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
- USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
- USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
- USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
- USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
- USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
- USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
- USHORT VRAM_GetCurrentInfoBlock;
- USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
- USHORT MemoryTraining;
- USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
- USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
- USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
- USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
- USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
- USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
- USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
- USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
- USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
- USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
- USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
- USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
- USHORT DPEncoderService; //Function Table,only used by Bios
-}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
-
-#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
-
-#define UNIPHYTransmitterControl DIG1TransmitterControl
-#define LVTMATransmitterControl DIG2TransmitterControl
-#define SetCRTC_DPM_State GetConditionalGoldenSetting
-
-typedef struct _ATOM_MASTER_COMMAND_TABLE
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
-}ATOM_MASTER_COMMAND_TABLE;
-
-typedef struct _ATOM_TABLE_ATTRIBUTE
-{
- USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
- USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
- USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
-}ATOM_TABLE_ATTRIBUTE;
-
-// Common header for all command tables.
-//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
-//And the pointer actually points to this header.
-
-typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
-{
- ATOM_COMMON_TABLE_HEADER CommonHeader;
- ATOM_TABLE_ATTRIBUTE TableAttribute;
-}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
-
-
-typedef struct _ASIC_INIT_PARAMETERS
-{
- ULONG ulDefaultEngineClock; //In 10Khz unit
- ULONG ulDefaultMemoryClock; //In 10Khz unit
-}ASIC_INIT_PARAMETERS;
-
-#define COMPUTE_MEMORY_PLL_PARAM 1
-#define COMPUTE_ENGINE_PLL_PARAM 2
-
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
-{
- ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
- UCHAR ucAction; //0:reserved //1:Memory //2:Engine
- UCHAR ucReserved; //may expand to return larger Fbdiv later
- UCHAR ucFbDiv; //return value
- UCHAR ucPostDiv; //return value
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
-
-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
-{
- ULONG ulClock; //When return, [23:0] return real clock
- UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
- USHORT usFbDiv; //return Feedback value to be written to register
- UCHAR ucPostDiv; //return post div to be written to register
-}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
-#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
-
-
-#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
-#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
-#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
-#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
-#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
-#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
-#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
-
-#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
-#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
-#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
-#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
-#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
-
-typedef struct _SET_ENGINE_CLOCK_PARAMETERS
-{
- ULONG ulTargetEngineClock; //In 10Khz unit
-}SET_ENGINE_CLOCK_PARAMETERS;
-
-typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
-{
- ULONG ulTargetEngineClock; //In 10Khz unit
- COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
-}SET_ENGINE_CLOCK_PS_ALLOCATION;
-
-
-typedef struct _SET_MEMORY_CLOCK_PARAMETERS
-{
- ULONG ulTargetMemoryClock; //In 10Khz unit
-}SET_MEMORY_CLOCK_PARAMETERS;
-
-typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
-{
- ULONG ulTargetMemoryClock; //In 10Khz unit
- COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
-}SET_MEMORY_CLOCK_PS_ALLOCATION;
-
-typedef struct _ASIC_INIT_PS_ALLOCATION
-{
- ASIC_INIT_PARAMETERS sASICInitClocks;
- SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
-}ASIC_INIT_PS_ALLOCATION;
-
-
-typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
-{
- UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucPadding[3];
-}DYNAMIC_CLOCK_GATING_PARAMETERS;
-#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
-
-
-typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
-{
- UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucPadding[3];
-}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
-#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
-
-
-typedef struct _DAC_LOAD_DETECTION_PARAMETERS
-{
- USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
- UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
- UCHAR ucMisc; //Valid only when table revision =1.3 and above
-}DAC_LOAD_DETECTION_PARAMETERS;
-
-// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
-#define DAC_LOAD_MISC_YPrPb 0x01
-
-
-typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
-{
- DAC_LOAD_DETECTION_PARAMETERS sDacload;
- ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
-}DAC_LOAD_DETECTION_PS_ALLOCATION;
-
-
-typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
-{
- USHORT usPixelClock; // in 10KHz; for bios convenient
- UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
- UCHAR ucAction; // 0: turn off encoder
- // 1: setup and turn on encoder
- // 7: ATOM_ENCODER_INIT Initialize DAC
-}DAC_ENCODER_CONTROL_PARAMETERS;
-
-#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
-
-typedef struct _TV_ENCODER_CONTROL_PARAMETERS
-{
- USHORT usPixelClock; // in 10KHz; for bios convenient
- UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
- UCHAR ucAction; // 0: turn off encoder
- // 1: setup and turn on encoder
-}TV_ENCODER_CONTROL_PARAMETERS;
-
-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
-{
- USHORT usPixelClock; // in 10KHz; for bios convenient
- UCHAR ucConfig;
- // [2] Link Select:
- // =0: PHY linkA if bfLane<3
- // =1: PHY linkB if bfLanes<3
- // =0: PHY linkA+B if bfLanes=3
- // [3] Transmitter Sel
- // =0: UNIPHY or PCIEPHY
- // =1: LVTMA
- UCHAR ucAction; // =0: turn off encoder
- // =1: turn on encoder
- UCHAR ucEncoderMode;
- // =0: DP encoder
- // =1: LVDS encoder
- // =2: DVI encoder
- // =3: HDMI encoder
- // =4: SDVO encoder
- UCHAR ucLaneNum; // how many lanes to enable
- UCHAR ucReserved[2];
-}DIG_ENCODER_CONTROL_PARAMETERS;
-#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
-#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
-#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION
-
-//ucConfig
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
-#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
-#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
-#define ATOM_ENCODER_CONFIG_LINKA 0x00
-#define ATOM_ENCODER_CONFIG_LINKB 0x04
-#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
-#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
-#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
-#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
-#define ATOM_ENCODER_CONFIG_LVTMA 0x08
-#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
-#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
-#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
-// ucAction
-// ATOM_ENABLE: Enable Encoder
-// ATOM_DISABLE: Disable Encoder
-
-//ucEncoderMode
-#define ATOM_ENCODER_MODE_DP 0
-#define ATOM_ENCODER_MODE_LVDS 1
-#define ATOM_ENCODER_MODE_DVI 2
-#define ATOM_ENCODER_MODE_HDMI 3
-#define ATOM_ENCODER_MODE_SDVO 4
-#define ATOM_ENCODER_MODE_TV 13
-#define ATOM_ENCODER_MODE_CV 14
-#define ATOM_ENCODER_MODE_CRT 15
-
-typedef struct _ATOM_DP_VS_MODE
-{
- UCHAR ucLaneSel;
- UCHAR ucLaneSet;
-}ATOM_DP_VS_MODE;
-
-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
-{
- union
- {
- USHORT usPixelClock; // in 10KHz; for bios convenient
- USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
- ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
- };
- UCHAR ucConfig;
- // [0]=0: 4 lane Link,
- // =1: 8 lane Link ( Dual Links TMDS )
- // [1]=0: InCoherent mode
- // =1: Coherent Mode
- // [2] Link Select:
- // =0: PHY linkA if bfLane<3
- // =1: PHY linkB if bfLanes<3
- // =0: PHY linkA+B if bfLanes=3
- // [5:4]PCIE lane Sel
- // =0: lane 0~3 or 0~7
- // =1: lane 4~7
- // =2: lane 8~11 or 8~15
- // =3: lane 12~15
- UCHAR ucAction; // =0: turn off encoder
- // =1: turn on encoder
- UCHAR ucReserved[4];
-}DIG_TRANSMITTER_CONTROL_PARAMETERS;
-
-#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
-
-//ucInitInfo
-#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
-
-//ucConfig
-#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
-#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
-#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
-#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
-#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
-#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
-#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
-
-#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
-#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
-#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
-
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
-#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
-#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
-#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
-#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
-#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
-#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
-#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
-#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
-
-//ucAction
-#define ATOM_TRANSMITTER_ACTION_DISABLE 0
-#define ATOM_TRANSMITTER_ACTION_ENABLE 1
-#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
-#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
-#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
-#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
-#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
-#define ATOM_TRANSMITTER_ACTION_INIT 7
-#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
-#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
-#define ATOM_TRANSMITTER_ACTION_SETUP 10
-#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
-
-/****************************Device Output Control Command Table Definitions**********************/
-typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-{
- UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
- // When the display is LCD, in addition to above:
- // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
- // ATOM_LCD_SELFTEST_STOP
-
- UCHAR aucPadding[3]; // padding to DWORD aligned
-}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
-
-#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-
-
-#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
-#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
-#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
-
-/**************************************************************************/
-typedef struct _BLANK_CRTC_PARAMETERS
-{
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
- USHORT usBlackColorRCr;
- USHORT usBlackColorGY;
- USHORT usBlackColorBCb;
-}BLANK_CRTC_PARAMETERS;
-#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
-
-
-typedef struct _ENABLE_CRTC_PARAMETERS
-{
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucPadding[2];
-}ENABLE_CRTC_PARAMETERS;
-#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
-
-
-typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
-{
- USHORT usOverscanRight; // right
- USHORT usOverscanLeft; // left
- USHORT usOverscanBottom; // bottom
- USHORT usOverscanTop; // top
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucPadding[3];
-}SET_CRTC_OVERSCAN_PARAMETERS;
-#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
-
-
-typedef struct _SET_CRTC_REPLICATION_PARAMETERS
-{
- UCHAR ucH_Replication; // horizontal replication
- UCHAR ucV_Replication; // vertical replication
- UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucPadding;
-}SET_CRTC_REPLICATION_PARAMETERS;
-#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
-
-
-typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
-{
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
- UCHAR ucPadding[2];
-}SELECT_CRTC_SOURCE_PARAMETERS;
-#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
-
-typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
-{
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
- UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
- UCHAR ucPadding;
-}SELECT_CRTC_SOURCE_PARAMETERS_V2;
-
-//ucEncoderID
-//#define ASIC_INT_DAC1_ENCODER_ID 0x00
-//#define ASIC_INT_TV_ENCODER_ID 0x02
-//#define ASIC_INT_DIG1_ENCODER_ID 0x03
-//#define ASIC_INT_DAC2_ENCODER_ID 0x04
-//#define ASIC_EXT_TV_ENCODER_ID 0x06
-//#define ASIC_INT_DVO_ENCODER_ID 0x07
-//#define ASIC_INT_DIG2_ENCODER_ID 0x09
-//#define ASIC_EXT_DIG_ENCODER_ID 0x05
-
-//ucEncodeMode
-//#define ATOM_ENCODER_MODE_DP 0
-//#define ATOM_ENCODER_MODE_LVDS 1
-//#define ATOM_ENCODER_MODE_DVI 2
-//#define ATOM_ENCODER_MODE_HDMI 3
-//#define ATOM_ENCODER_MODE_SDVO 4
-//#define ATOM_ENCODER_MODE_TV 13
-//#define ATOM_ENCODER_MODE_CV 14
-//#define ATOM_ENCODER_MODE_CRT 15
-
-//Major revision=1., Minor revision=1
-typedef struct _PIXEL_CLOCK_PARAMETERS
-{
- USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
- // 0 means disable PPLL
- USHORT usRefDiv; // Reference divider
- USHORT usFbDiv; // feedback divider
- UCHAR ucPostDiv; // post divider
- UCHAR ucFracFbDiv; // fractional feedback divider
- UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
- UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
- UCHAR ucCRTC; // Which CRTC uses this Ppll
- UCHAR ucPadding;
-}PIXEL_CLOCK_PARAMETERS;
-
-
-//Major revision=1., Minor revision=2, add ucMiscIfno
-//ucMiscInfo:
-#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
-#define MISC_DEVICE_INDEX_MASK 0xF0
-#define MISC_DEVICE_INDEX_SHIFT 4
-
-typedef struct _PIXEL_CLOCK_PARAMETERS_V2
-{
- USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
- // 0 means disable PPLL
- USHORT usRefDiv; // Reference divider
- USHORT usFbDiv; // feedback divider
- UCHAR ucPostDiv; // post divider
- UCHAR ucFracFbDiv; // fractional feedback divider
- UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
- UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
- UCHAR ucCRTC; // Which CRTC uses this Ppll
- UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
-}PIXEL_CLOCK_PARAMETERS_V2;
-
-//Major revision=1., Minor revision=3, structure/definition change
-//ucEncoderMode:
-//ATOM_ENCODER_MODE_DP
-//ATOM_ENOCDER_MODE_LVDS
-//ATOM_ENOCDER_MODE_DVI
-//ATOM_ENOCDER_MODE_HDMI
-//ATOM_ENOCDER_MODE_SDVO
-//ATOM_ENCODER_MODE_TV 13
-//ATOM_ENCODER_MODE_CV 14
-//ATOM_ENCODER_MODE_CRT 15
-
-//ucDVOConfig
-//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
-//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
-//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
-//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
-//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
-//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
-//#define DVO_ENCODER_CONFIG_24BIT 0x08
-
-//ucMiscInfo: also changed, see below
-#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
-#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
-#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
-#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
-#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
-#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
-
-typedef struct _PIXEL_CLOCK_PARAMETERS_V3
-{
- USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
- // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
- USHORT usRefDiv; // Reference divider
- USHORT usFbDiv; // feedback divider
- UCHAR ucPostDiv; // post divider
- UCHAR ucFracFbDiv; // fractional feedback divider
- UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
- UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
- union
- {
- UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
- UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
- };
- UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
- // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
-}PIXEL_CLOCK_PARAMETERS_V3;
-
-#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
-#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
-
-typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
-{
- USHORT usPixelClock;
- UCHAR ucTransmitterID;
- UCHAR ucEncodeMode;
- union
- {
- UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
- UCHAR ucConfig; //if none DVO, not defined yet
- };
- UCHAR ucReserved[3];
-}ADJUST_DISPLAY_PLL_PARAMETERS;
-
-#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
-
-#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
-
-typedef struct _ENABLE_YUV_PARAMETERS
-{
- UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
- UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
- UCHAR ucPadding[2];
-}ENABLE_YUV_PARAMETERS;
-#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
-
-typedef struct _GET_MEMORY_CLOCK_PARAMETERS
-{
- ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
-} GET_MEMORY_CLOCK_PARAMETERS;
-#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
-
-
-typedef struct _GET_ENGINE_CLOCK_PARAMETERS
-{
- ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
-} GET_ENGINE_CLOCK_PARAMETERS;
-#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
-
-
-//Maxium 8 bytes,the data read in will be placed in the parameter space.
-//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
-typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
-{
- USHORT usPrescale; //Ratio between Engine clock and I2C clock
- USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
- USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
- //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
- UCHAR ucSlaveAddr; //Read from which slave
- UCHAR ucLineNumber; //Read from which HW assisted line
-}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
-#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
-
-
-#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
-#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
-#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
-#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
-#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
-
-typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-{
- USHORT usPrescale; //Ratio between Engine clock and I2C clock
- USHORT usByteOffset; //Write to which byte
- //Upper portion of usByteOffset is Format of data
- //1bytePS+offsetPS
- //2bytesPS+offsetPS
- //blockID+offsetPS
- //blockID+offsetID
- //blockID+counterID+offsetID
- UCHAR ucData; //PS data1
- UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
- UCHAR ucSlaveAddr; //Write to which slave
- UCHAR ucLineNumber; //Write from which HW assisted line
-}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
-
-#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-
-typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
-{
- USHORT usPrescale; //Ratio between Engine clock and I2C clock
- UCHAR ucSlaveAddr; //Write to which slave
- UCHAR ucLineNumber; //Write from which HW assisted line
-}SET_UP_HW_I2C_DATA_PARAMETERS;
-
-
-/**************************************************************************/
-#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-
-typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
-{
- UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
- UCHAR ucPwrBehaviorId;
- USHORT usPwrBudget; //how much power currently boot to in unit of watt
-}POWER_CONNECTOR_DETECTION_PARAMETERS;
-
-typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
-{
- UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
- UCHAR ucReserved;
- USHORT usPwrBudget; //how much power currently boot to in unit of watt
- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
-}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
-
-/****************************LVDS SS Command Table Definitions**********************/
-typedef struct _ENABLE_LVDS_SS_PARAMETERS
-{
- USHORT usSpreadSpectrumPercentage;
- UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
- UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
- UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucPadding[3];
-}ENABLE_LVDS_SS_PARAMETERS;
-
-//ucTableFormatRevision=1,ucTableContentRevision=2
-typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
-{
- USHORT usSpreadSpectrumPercentage;
- UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
- UCHAR ucSpreadSpectrumStep; //
- UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucSpreadSpectrumDelay;
- UCHAR ucSpreadSpectrumRange;
- UCHAR ucPadding;
-}ENABLE_LVDS_SS_PARAMETERS_V2;
-
-//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
-typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
-{
- USHORT usSpreadSpectrumPercentage;
- UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
- UCHAR ucSpreadSpectrumStep; //
- UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucSpreadSpectrumDelay;
- UCHAR ucSpreadSpectrumRange;
- UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
-}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
-
-#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
-
-/**************************************************************************/
-
-typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
-{
- PIXEL_CLOCK_PARAMETERS sPCLKInput;
- ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
-}SET_PIXEL_CLOCK_PS_ALLOCATION;
-
-#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
-
-typedef struct _MEMORY_TRAINING_PARAMETERS
-{
- ULONG ulTargetMemoryClock; //In 10Khz unit
-}MEMORY_TRAINING_PARAMETERS;
-#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
-
-
-
-/****************************LVDS and other encoder command table definitions **********************/
-typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
-{
- USHORT usPixelClock; // in 10KHz; for bios convenient
- UCHAR ucMisc; // bit0=0: Enable single link
- // =1: Enable dual link
- // Bit1=0: 666RGB
- // =1: 888RGB
- UCHAR ucAction; // 0: turn off encoder
- // 1: setup and turn on encoder
-}LVDS_ENCODER_CONTROL_PARAMETERS;
-
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
-
-#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
-
-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
-{
- UCHAR ucEnable; // Enable or Disable External TMDS encoder
- UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
- UCHAR ucPadding[2];
-}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
-
-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
-{
- ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
-}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
-
-
-//ucTableFormatRevision=1,ucTableContentRevision=2
-typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
-{
- USHORT usPixelClock; // in 10KHz; for bios convenient
- UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
- UCHAR ucAction; // 0: turn off encoder
- // 1: setup and turn on encoder
- UCHAR ucTruncate; // bit0=0: Disable truncate
- // =1: Enable truncate
- // bit4=0: 666RGB
- // =1: 888RGB
- UCHAR ucSpatial; // bit0=0: Disable spatial dithering
- // =1: Enable spatial dithering
- // bit4=0: 666RGB
- // =1: 888RGB
- UCHAR ucTemporal; // bit0=0: Disable temporal dithering
- // =1: Enable temporal dithering
- // bit4=0: 666RGB
- // =1: 888RGB
- // bit5=0: Gray level 2
- // =1: Gray level 4
- UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
- // =1: 25FRC_SEL pattern F
- // bit6:5=0: 50FRC_SEL pattern A
- // =1: 50FRC_SEL pattern B
- // =2: 50FRC_SEL pattern C
- // =3: 50FRC_SEL pattern D
- // bit7=0: 75FRC_SEL pattern E
- // =1: 75FRC_SEL pattern F
-}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
-
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
-
-#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
-#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
-
-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
-{
- ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
-}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
-
-
-//ucTableFormatRevision=1,ucTableContentRevision=3
-
-//ucDVOConfig:
-#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
-#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
-#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
-#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
-#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
-#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
-#define DVO_ENCODER_CONFIG_24BIT 0x08
-
-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
-{
- USHORT usPixelClock;
- UCHAR ucDVOConfig;
- UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
- UCHAR ucReseved[4];
-}DVO_ENCODER_CONTROL_PARAMETERS_V3;
-#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
-// bit1=0: non-coherent mode
-// =1: coherent mode
-
-#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
-
-#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
-
-//==========================================================================================
-//Only change is here next time when changing encoder parameter definitions again!
-#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
-
-#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
-
-#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
-#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
-
-#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
-#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
-
-//==========================================================================================
-#define PANEL_ENCODER_MISC_DUAL 0x01
-#define PANEL_ENCODER_MISC_COHERENT 0x02
-#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
-#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
-
-#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
-#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
-#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
-
-#define PANEL_ENCODER_TRUNCATE_EN 0x01
-#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
-#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
-#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
-#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
-#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
-#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
-#define PANEL_ENCODER_25FRC_MASK 0x10
-#define PANEL_ENCODER_25FRC_E 0x00
-#define PANEL_ENCODER_25FRC_F 0x10
-#define PANEL_ENCODER_50FRC_MASK 0x60
-#define PANEL_ENCODER_50FRC_A 0x00
-#define PANEL_ENCODER_50FRC_B 0x20
-#define PANEL_ENCODER_50FRC_C 0x40
-#define PANEL_ENCODER_50FRC_D 0x60
-#define PANEL_ENCODER_75FRC_MASK 0x80
-#define PANEL_ENCODER_75FRC_E 0x00
-#define PANEL_ENCODER_75FRC_F 0x80
-
-/**************************************************************************/
-
-#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
-#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
-#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
-#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
-
-#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
-#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
-#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
-
-#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
-#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
-#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
-
-typedef struct _SET_VOLTAGE_PARAMETERS
-{
- UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
- UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
- UCHAR ucVoltageIndex; // An index to tell which voltage level
- UCHAR ucReserved;
-}SET_VOLTAGE_PARAMETERS;
-
-
-typedef struct _SET_VOLTAGE_PARAMETERS_V2
-{
- UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
- UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
- USHORT usVoltageLevel; // real voltage level
-}SET_VOLTAGE_PARAMETERS_V2;
-
-
-typedef struct _SET_VOLTAGE_PS_ALLOCATION
-{
- SET_VOLTAGE_PARAMETERS sASICSetVoltage;
- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
-}SET_VOLTAGE_PS_ALLOCATION;
-
-typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
-{
- TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
-}TV_ENCODER_CONTROL_PS_ALLOCATION;
-
-//==============================Data Table Portion====================================
-
-#ifdef UEFI_BUILD
- #define UTEMP USHORT
- #define USHORT void*
-#endif
-
-typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
-{
- USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
- USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
- USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
- USHORT StandardVESA_Timing; // Only used by Bios
- USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
- USHORT DAC_Info; // Will be obsolete from R600
- USHORT LVDS_Info; // Shared by various SW components,latest version 1.1
- USHORT TMDS_Info; // Will be obsolete from R600
- USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
- USHORT SupportedDevicesInfo; // Will be obsolete from R600
- USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
- USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
- USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
- USHORT VESA_ToInternalModeLUT; // Only used by Bios
- USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
- USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
- USHORT CompassionateData; // Will be obsolete from R600
- USHORT SaveRestoreInfo; // Only used by Bios
- USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
- USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
- USHORT XTMDS_Info; // Will be obsolete from R600
- USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
- USHORT Object_Header; // Shared by various SW components,latest version 1.1
- USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
- USHORT MC_InitParameter; // Only used by command table
- USHORT ASIC_VDDC_Info; // Will be obsolete from R600
- USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
- USHORT TV_VideoMode; // Only used by command table
- USHORT VRAM_Info; // Only used by command table, latest version 1.3
- USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
- USHORT IntegratedSystemInfo; // Shared by various SW components
- USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
- USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
- USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
-}ATOM_MASTER_LIST_OF_DATA_TABLES;
-
-#ifdef UEFI_BUILD
- #define USHORT UTEMP
-#endif
-
-
-typedef struct _ATOM_MASTER_DATA_TABLE
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
-}ATOM_MASTER_DATA_TABLE;
-
-
-typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulSignature; // HW info table signature string "$ATI"
- UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
- UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
- UCHAR ucVideoPortInfo; // Provides the video port capabilities
- UCHAR ucHostPortInfo; // Provides host port configuration information
-}ATOM_MULTIMEDIA_CAPABILITY_INFO;
-
-
-typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulSignature; // MM info table signature sting "$MMT"
- UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
- UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
- UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
- UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
- UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
- UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
- UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
- UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
- UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
- UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
- UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
- UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
-}ATOM_MULTIMEDIA_CONFIG_INFO;
-
-/****************************Firmware Info Table Definitions**********************/
-
-// usBIOSCapability Defintion:
-// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
-// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
-// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
-// Others: Reserved
-#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
-#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
-#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
-#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008
-#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010
-#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
-#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
-#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
-#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
-#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
-#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
-#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
-
-
-#ifndef _H2INC
-
-//Please don't add or expand this bitfield structure below, this one will retire soon.!
-typedef struct _ATOM_FIRMWARE_CAPABILITY
-{
- USHORT FirmwarePosted:1;
- USHORT DualCRTC_Support:1;
- USHORT ExtendedDesktopSupport:1;
- USHORT MemoryClockSS_Support:1;
- USHORT EngineClockSS_Support:1;
- USHORT GPUControlsBL:1;
- USHORT WMI_SUPPORT:1;
- USHORT PPMode_Assigned:1;
- USHORT HyperMemory_Support:1;
- USHORT HyperMemory_Size:4;
- USHORT Reserved:3;
-}ATOM_FIRMWARE_CAPABILITY;
-
-typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
-{
- ATOM_FIRMWARE_CAPABILITY sbfAccess;
- USHORT susAccess;
-}ATOM_FIRMWARE_CAPABILITY_ACCESS;
-
-#else
-
-typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
-{
- USHORT susAccess;
-}ATOM_FIRMWARE_CAPABILITY_ACCESS;
-
-#endif
-
-typedef struct _ATOM_FIRMWARE_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulFirmwareRevision;
- ULONG ulDefaultEngineClock; //In 10Khz unit
- ULONG ulDefaultMemoryClock; //In 10Khz unit
- ULONG ulDriverTargetEngineClock; //In 10Khz unit
- ULONG ulDriverTargetMemoryClock; //In 10Khz unit
- ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
- ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
- ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
- ULONG ulASICMaxEngineClock; //In 10Khz unit
- ULONG ulASICMaxMemoryClock; //In 10Khz unit
- UCHAR ucASICMaxTemperature;
- UCHAR ucPadding[3]; //Don't use them
- ULONG aulReservedForBIOS[3]; //Don't use them
- USHORT usMinEngineClockPLL_Input; //In 10Khz unit
- USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
- USHORT usMinEngineClockPLL_Output; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
- USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
- USHORT usMinPixelClockPLL_Input; //In 10Khz unit
- USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
- USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
- USHORT usReferenceClock; //In 10Khz unit
- USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
- UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
- UCHAR ucDesign_ID; //Indicate what is the board design
- UCHAR ucMemoryModule_ID; //Indicate what is the board design
-}ATOM_FIRMWARE_INFO;
-
-typedef struct _ATOM_FIRMWARE_INFO_V1_2
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulFirmwareRevision;
- ULONG ulDefaultEngineClock; //In 10Khz unit
- ULONG ulDefaultMemoryClock; //In 10Khz unit
- ULONG ulDriverTargetEngineClock; //In 10Khz unit
- ULONG ulDriverTargetMemoryClock; //In 10Khz unit
- ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
- ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
- ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
- ULONG ulASICMaxEngineClock; //In 10Khz unit
- ULONG ulASICMaxMemoryClock; //In 10Khz unit
- UCHAR ucASICMaxTemperature;
- UCHAR ucMinAllowedBL_Level;
- UCHAR ucPadding[2]; //Don't use them
- ULONG aulReservedForBIOS[2]; //Don't use them
- ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
- USHORT usMinEngineClockPLL_Input; //In 10Khz unit
- USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
- USHORT usMinEngineClockPLL_Output; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
- USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
- USHORT usMinPixelClockPLL_Input; //In 10Khz unit
- USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
- USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
- USHORT usReferenceClock; //In 10Khz unit
- USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
- UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
- UCHAR ucDesign_ID; //Indicate what is the board design
- UCHAR ucMemoryModule_ID; //Indicate what is the board design
-}ATOM_FIRMWARE_INFO_V1_2;
-
-typedef struct _ATOM_FIRMWARE_INFO_V1_3
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulFirmwareRevision;
- ULONG ulDefaultEngineClock; //In 10Khz unit
- ULONG ulDefaultMemoryClock; //In 10Khz unit
- ULONG ulDriverTargetEngineClock; //In 10Khz unit
- ULONG ulDriverTargetMemoryClock; //In 10Khz unit
- ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
- ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
- ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
- ULONG ulASICMaxEngineClock; //In 10Khz unit
- ULONG ulASICMaxMemoryClock; //In 10Khz unit
- UCHAR ucASICMaxTemperature;
- UCHAR ucMinAllowedBL_Level;
- UCHAR ucPadding[2]; //Don't use them
- ULONG aulReservedForBIOS; //Don't use them
- ULONG ul3DAccelerationEngineClock;//In 10Khz unit
- ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
- USHORT usMinEngineClockPLL_Input; //In 10Khz unit
- USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
- USHORT usMinEngineClockPLL_Output; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
- USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
- USHORT usMinPixelClockPLL_Input; //In 10Khz unit
- USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
- USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
- USHORT usReferenceClock; //In 10Khz unit
- USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
- UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
- UCHAR ucDesign_ID; //Indicate what is the board design
- UCHAR ucMemoryModule_ID; //Indicate what is the board design
-}ATOM_FIRMWARE_INFO_V1_3;
-
-typedef struct _ATOM_FIRMWARE_INFO_V1_4
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulFirmwareRevision;
- ULONG ulDefaultEngineClock; //In 10Khz unit
- ULONG ulDefaultMemoryClock; //In 10Khz unit
- ULONG ulDriverTargetEngineClock; //In 10Khz unit
- ULONG ulDriverTargetMemoryClock; //In 10Khz unit
- ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
- ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
- ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
- ULONG ulASICMaxEngineClock; //In 10Khz unit
- ULONG ulASICMaxMemoryClock; //In 10Khz unit
- UCHAR ucASICMaxTemperature;
- UCHAR ucMinAllowedBL_Level;
- USHORT usBootUpVDDCVoltage; //In MV unit
- USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
- USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
- ULONG ul3DAccelerationEngineClock;//In 10Khz unit
- ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
- USHORT usMinEngineClockPLL_Input; //In 10Khz unit
- USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
- USHORT usMinEngineClockPLL_Output; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
- USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
- USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
- USHORT usMinPixelClockPLL_Input; //In 10Khz unit
- USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
- USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
- USHORT usReferenceClock; //In 10Khz unit
- USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
- UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
- UCHAR ucDesign_ID; //Indicate what is the board design
- UCHAR ucMemoryModule_ID; //Indicate what is the board design
-}ATOM_FIRMWARE_INFO_V1_4;
-
-#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4
-
-#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
-#define IGP_CAP_FLAG_AC_CARD 0x4
-#define IGP_CAP_FLAG_SDVO_CARD 0x8
-#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
-
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulBootUpEngineClock; //in 10kHz unit
- ULONG ulBootUpMemoryClock; //in 10kHz unit
- ULONG ulMaxSystemMemoryClock; //in 10kHz unit
- ULONG ulMinSystemMemoryClock; //in 10kHz unit
- UCHAR ucNumberOfCyclesInPeriodHi;
- UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
- USHORT usReserved1;
- USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
- USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
- ULONG ulReserved[2];
-
- USHORT usFSBClock; //In MHz unit
- USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
- //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
- //Bit[4]==1: P/2 mode, ==0: P/1 mode
- USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
- USHORT usK8MemoryClock; //in MHz unit
- USHORT usK8SyncStartDelay; //in 0.01 us unit
- USHORT usK8DataReturnTime; //in 0.01 us unit
- UCHAR ucMaxNBVoltage;
- UCHAR ucMinNBVoltage;
- UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
- UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
- UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
- UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
- UCHAR ucMaxNBVoltageHigh;
- UCHAR ucMinNBVoltageHigh;
-}ATOM_INTEGRATED_SYSTEM_INFO;
-
-/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
-ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
- For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
-ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
- For AMD IGP,for now this can be 0
-ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
- For AMD IGP,for now this can be 0
-
-usFSBClock: For Intel IGP,it's FSB Freq
- For AMD IGP,it's HT Link Speed
-
-usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
-usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
-usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
-
-VC:Voltage Control
-ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
-ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
-
-ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
-ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
-
-ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
-ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
-
-
-usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
-usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
-*/
-
-
-/*
-The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
-Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
-The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
-
-SW components can access the IGP system infor structure in the same way as before
-*/
-
-
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ULONG ulBootUpEngineClock; //in 10kHz unit
- ULONG ulReserved1[2]; //must be 0x0 for the reserved
- ULONG ulBootUpUMAClock; //in 10kHz unit
- ULONG ulBootUpSidePortClock; //in 10kHz unit
- ULONG ulMinSidePortClock; //in 10kHz unit
- ULONG ulReserved2[6]; //must be 0x0 for the reserved
- ULONG ulSystemConfig; //see explanation below
- ULONG ulBootUpReqDisplayVector;
- ULONG ulOtherDisplayMisc;
- ULONG ulDDISlot1Config;
- ULONG ulDDISlot2Config;
- UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
- UCHAR ucUMAChannelNumber;
- UCHAR ucDockingPinBit;
- UCHAR ucDockingPinPolarity;
- ULONG ulDockingPinCFGInfo;
- ULONG ulCPUCapInfo;
- USHORT usNumberOfCyclesInPeriod;
- USHORT usMaxNBVoltage;
- USHORT usMinNBVoltage;
- USHORT usBootUpNBVoltage;
- ULONG ulHTLinkFreq; //in 10Khz
- USHORT usMinHTLinkWidth;
- USHORT usMaxHTLinkWidth;
- USHORT usUMASyncStartDelay;
- USHORT usUMADataReturnTime;
- USHORT usLinkStatusZeroTime;
- USHORT usReserved;
- ULONG ulReserved3[101]; //must be 0x0
-}ATOM_INTEGRATED_SYSTEM_INFO_V2;
-
-/*
-ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
-ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
-ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
-
-ulSystemConfig:
-Bit[0]: =1 PowerExpress mode =0 Non-PowerExpress mode;
-Bit[1]=1: system is running at overdrived engine clock =0:system is not running at overdrived engine clock
-
-ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
-
-ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
- [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
-
-ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
- [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
- [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
- [15:8] - Lane configuration attribute;
- [23:16]- Connector type, possible value:
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
- CONNECTOR_OBJECT_ID_HDMI_TYPE_A
- CONNECTOR_OBJECT_ID_DISPLAYPORT
- [31:24]- Reserved
-
-ulDDISlot2Config: Same as Slot1.
-ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
-For IGP, Hypermemory is the only memory type showed in CCC.
-
-ucUMAChannelNumber: how many channels for the UMA;
-
-ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
-ucDockingPinBit: which bit in this register to read the pin status;
-ucDockingPinPolarity:Polarity of the pin when docked;
-
-ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
-
-usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
-usMaxNBVoltage:Voltage regulator dependent PWM value.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
-usMinNBVoltage:Voltage regulator dependent PWM value.Set this one to 0x00 if VC without PWM or no VC at all.
-usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
-
-
-ulHTLinkFreq: Current HT link Frequency in 10Khz.
-usMinHTLinkWidth:
-usMaxHTLinkWidth:
-usUMASyncStartDelay: Memory access latency, required for watermark calculation
-usUMADataReturnTime: Memory access latency, required for watermark calculation
-usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
-for Griffin or Greyhound. SBIOS needs to convert to actual time by:
- if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
- if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
- if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
- if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
-*/
-
-#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
-#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
-
-#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
-
-#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
-#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
-#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
-#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
-#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
-#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
-
-#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
-#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
-#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
-
-#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
-
-#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
-#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
-#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
-#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
-#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
-#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
-#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
-#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
-#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
-#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
-#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
-#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
-#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
-#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
-
-// define ASIC internal encoder id ( bit vector )
-#define ASIC_INT_DAC1_ENCODER_ID 0x00
-#define ASIC_INT_TV_ENCODER_ID 0x02
-#define ASIC_INT_DIG1_ENCODER_ID 0x03
-#define ASIC_INT_DAC2_ENCODER_ID 0x04
-#define ASIC_EXT_TV_ENCODER_ID 0x06
-#define ASIC_INT_DVO_ENCODER_ID 0x07
-#define ASIC_INT_DIG2_ENCODER_ID 0x09
-#define ASIC_EXT_DIG_ENCODER_ID 0x05
-
-//define Encoder attribute
-#define ATOM_ANALOG_ENCODER 0
-#define ATOM_DIGITAL_ENCODER 1
-
-#define ATOM_DEVICE_CRT1_INDEX 0x00000000
-#define ATOM_DEVICE_LCD1_INDEX 0x00000001
-#define ATOM_DEVICE_TV1_INDEX 0x00000002
-#define ATOM_DEVICE_DFP1_INDEX 0x00000003
-#define ATOM_DEVICE_CRT2_INDEX 0x00000004
-#define ATOM_DEVICE_LCD2_INDEX 0x00000005
-#define ATOM_DEVICE_TV2_INDEX 0x00000006
-#define ATOM_DEVICE_DFP2_INDEX 0x00000007
-#define ATOM_DEVICE_CV_INDEX 0x00000008
-#define ATOM_DEVICE_DFP3_INDEX 0x00000009
-#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A
-#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B
-#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
-#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
-#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
-#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
-#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_CV_INDEX+2)
-#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
-#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
-
-#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
-#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
-#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
-#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX)
-#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
-#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
-#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX )
-#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX)
-#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
-#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
-
-#define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT
-#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT
-#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT
-#define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT
-
-#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
-#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
-#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
-#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
-#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
-#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
-#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
-#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
-#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
-#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
-#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
-#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
-#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
-#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
-#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
-
-
-#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
-#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
-#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
-#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
-#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
-#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
-
-#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
-
-#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
-#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
-
-#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
-#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
-#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
-#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
-#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
-#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
-
-#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
-#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
-#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
-#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
-
-// usDeviceSupport:
-// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
-// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
-// Bit 2 = 0 - no TV1 support= 1- TV1 is supported
-// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
-// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
-// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
-// Bit 6 = 0 - no TV2 support= 1- TV2 is supported
-// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
-// Bit 8 = 0 - no CV support= 1- CV is supported
-// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
-// Byte1 (Supported Device Info)
-// Bit 0 = = 0 - no CV support= 1- CV is supported
-//
-//
-
-// ucI2C_ConfigID
-// [7:0] - I2C LINE Associate ID
-// = 0 - no I2C
-// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
-// = 0, [6:0]=SW assisted I2C ID
-// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
-// = 2, HW engine for Multimedia use
-// = 3-7 Reserved for future I2C engines
-// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
-
-
-typedef struct _ATOM_I2C_ID_CONFIG
-{
- UCHAR bfI2C_LineMux:4;
- UCHAR bfHW_EngineID:3;
- UCHAR bfHW_Capable:1;
-}ATOM_I2C_ID_CONFIG;
-
-typedef union _ATOM_I2C_ID_CONFIG_ACCESS
-{
- ATOM_I2C_ID_CONFIG sbfAccess;
- UCHAR ucAccess;
-}ATOM_I2C_ID_CONFIG_ACCESS;
-
-
-typedef struct _ATOM_GPIO_I2C_ASSIGMENT
-{
- USHORT usClkMaskRegisterIndex;
- USHORT usClkEnRegisterIndex;
- USHORT usClkY_RegisterIndex;
- USHORT usClkA_RegisterIndex;
- USHORT usDataMaskRegisterIndex;
- USHORT usDataEnRegisterIndex;
- USHORT usDataY_RegisterIndex;
- USHORT usDataA_RegisterIndex;
- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
- UCHAR ucClkMaskShift;
- UCHAR ucClkEnShift;
- UCHAR ucClkY_Shift;
- UCHAR ucClkA_Shift;
- UCHAR ucDataMaskShift;
- UCHAR ucDataEnShift;
- UCHAR ucDataY_Shift;
- UCHAR ucDataA_Shift;
- UCHAR ucReserved1;
- UCHAR ucReserved2;
-}ATOM_GPIO_I2C_ASSIGMENT;
-
-typedef struct _ATOM_GPIO_I2C_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
-}ATOM_GPIO_I2C_INFO;
-
-
-#ifndef _H2INC
-
-//Please don't add or expand this bitfield structure below, this one will retire soon.!
-typedef struct _ATOM_MODE_MISC_INFO
-{
- USHORT HorizontalCutOff:1;
- USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
- USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
- USHORT VerticalCutOff:1;
- USHORT H_ReplicationBy2:1;
- USHORT V_ReplicationBy2:1;
- USHORT CompositeSync:1;
- USHORT Interlace:1;
- USHORT DoubleClock:1;
- USHORT RGB888:1;
- USHORT Reserved:6;
-}ATOM_MODE_MISC_INFO;
-
-typedef union _ATOM_MODE_MISC_INFO_ACCESS
-{
- ATOM_MODE_MISC_INFO sbfAccess;
- USHORT usAccess;
-}ATOM_MODE_MISC_INFO_ACCESS;
-
-#else
-
-typedef union _ATOM_MODE_MISC_INFO_ACCESS
-{
- USHORT usAccess;
-}ATOM_MODE_MISC_INFO_ACCESS;
-
-#endif
-
-// usModeMiscInfo-
-#define ATOM_H_CUTOFF 0x01
-#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
-#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
-#define ATOM_V_CUTOFF 0x08
-#define ATOM_H_REPLICATIONBY2 0x10
-#define ATOM_V_REPLICATIONBY2 0x20
-#define ATOM_COMPOSITESYNC 0x40
-#define ATOM_INTERLACE 0x80
-#define ATOM_DOUBLE_CLOCK_MODE 0x100
-#define ATOM_RGB888_MODE 0x200
-
-//usRefreshRate-
-#define ATOM_REFRESH_43 43
-#define ATOM_REFRESH_47 47
-#define ATOM_REFRESH_56 56
-#define ATOM_REFRESH_60 60
-#define ATOM_REFRESH_65 65
-#define ATOM_REFRESH_70 70
-#define ATOM_REFRESH_72 72
-#define ATOM_REFRESH_75 75
-#define ATOM_REFRESH_85 85
-
-// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
-// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
-//
-// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
-// = EDID_HA + EDID_HBL
-// VESA_HDISP = VESA_ACTIVE = EDID_HA
-// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
-// = EDID_HA + EDID_HSO
-// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
-// VESA_BORDER = EDID_BORDER
-
-
-typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
-{
- USHORT usH_Size;
- USHORT usH_Blanking_Time;
- USHORT usV_Size;
- USHORT usV_Blanking_Time;
- USHORT usH_SyncOffset;
- USHORT usH_SyncWidth;
- USHORT usV_SyncOffset;
- USHORT usV_SyncWidth;
- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
- UCHAR ucH_Border; // From DFP EDID
- UCHAR ucV_Border;
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucPadding[3];
-}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
-
-typedef struct _SET_CRTC_TIMING_PARAMETERS
-{
- USHORT usH_Total; // horizontal total
- USHORT usH_Disp; // horizontal display
- USHORT usH_SyncStart; // horozontal Sync start
- USHORT usH_SyncWidth; // horizontal Sync width
- USHORT usV_Total; // vertical total
- USHORT usV_Disp; // vertical display
- USHORT usV_SyncStart; // vertical Sync start
- USHORT usV_SyncWidth; // vertical Sync width
- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
- UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
- UCHAR ucOverscanRight; // right
- UCHAR ucOverscanLeft; // left
- UCHAR ucOverscanBottom; // bottom
- UCHAR ucOverscanTop; // top
- UCHAR ucReserved;
-}SET_CRTC_TIMING_PARAMETERS;
-#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
-
-
-typedef struct _ATOM_MODE_TIMING
-{
- USHORT usCRTC_H_Total;
- USHORT usCRTC_H_Disp;
- USHORT usCRTC_H_SyncStart;
- USHORT usCRTC_H_SyncWidth;
- USHORT usCRTC_V_Total;
- USHORT usCRTC_V_Disp;
- USHORT usCRTC_V_SyncStart;
- USHORT usCRTC_V_SyncWidth;
- USHORT usPixelClock; //in 10Khz unit
- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
- USHORT usCRTC_OverscanRight;
- USHORT usCRTC_OverscanLeft;
- USHORT usCRTC_OverscanBottom;
- USHORT usCRTC_OverscanTop;
- USHORT usReserve;
- UCHAR ucInternalModeNumber;
- UCHAR ucRefreshRate;
-}ATOM_MODE_TIMING;
-
-
-typedef struct _ATOM_DTD_FORMAT
-{
- USHORT usPixClk;
- USHORT usHActive;
- USHORT usHBlanking_Time;
- USHORT usVActive;
- USHORT usVBlanking_Time;
- USHORT usHSyncOffset;
- USHORT usHSyncWidth;
- USHORT usVSyncOffset;
- USHORT usVSyncWidth;
- USHORT usImageHSize;
- USHORT usImageVSize;
- UCHAR ucHBorder;
- UCHAR ucVBorder;
- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
- UCHAR ucInternalModeNumber;
- UCHAR ucRefreshRate;
-}ATOM_DTD_FORMAT;
-
-#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
-#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
-#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
-#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
-
-/****************************LVDS Info Table Definitions **********************/
-//ucTableFormatRevision=1
-//ucTableContentRevision=1
-typedef struct _ATOM_LVDS_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_DTD_FORMAT sLCDTiming;
- USHORT usModePatchTableOffset;
- USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
- USHORT usOffDelayInMs;
- UCHAR ucPowerSequenceDigOntoDEin10Ms;
- UCHAR ucPowerSequenceDEtoBLOnin10Ms;
- UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
- // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
- // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
- // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
- UCHAR ucPanelDefaultRefreshRate;
- UCHAR ucPanelIdentification;
- UCHAR ucSS_Id;
-}ATOM_LVDS_INFO;
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=2
-typedef struct _ATOM_LVDS_INFO_V12
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_DTD_FORMAT sLCDTiming;
- USHORT usExtInfoTableOffset;
- USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
- USHORT usOffDelayInMs;
- UCHAR ucPowerSequenceDigOntoDEin10Ms;
- UCHAR ucPowerSequenceDEtoBLOnin10Ms;
- UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
- // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
- // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
- // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
- UCHAR ucPanelDefaultRefreshRate;
- UCHAR ucPanelIdentification;
- UCHAR ucSS_Id;
- USHORT usLCDVenderID;
- USHORT usLCDProductID;
- UCHAR ucLCDPanel_SpecialHandlingCap;
- UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
- UCHAR ucReserved[2];
-}ATOM_LVDS_INFO_V12;
-
-#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12
-
-typedef struct _ATOM_PATCH_RECORD_MODE
-{
- UCHAR ucRecordType;
- USHORT usHDisp;
- USHORT usVDisp;
-}ATOM_PATCH_RECORD_MODE;
-
-typedef struct _ATOM_LCD_RTS_RECORD
-{
- UCHAR ucRecordType;
- UCHAR ucRTSValue;
-}ATOM_LCD_RTS_RECORD;
-
-//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
-typedef struct _ATOM_LCD_MODE_CONTROL_CAP
-{
- UCHAR ucRecordType;
- USHORT usLCDCap;
-}ATOM_LCD_MODE_CONTROL_CAP;
-
-#define LCD_MODE_CAP_BL_OFF 1
-#define LCD_MODE_CAP_CRTC_OFF 2
-#define LCD_MODE_CAP_PANEL_OFF 4
-
-typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
-{
- UCHAR ucRecordType;
- UCHAR ucFakeEDIDLength;
- UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
-} ATOM_FAKE_EDID_PATCH_RECORD;
-
-typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
-{
- UCHAR ucRecordType;
- USHORT usHSize;
- USHORT usVSize;
-}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
-
-#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
-#define LCD_RTS_RECORD_TYPE 2
-#define LCD_CAP_RECORD_TYPE 3
-#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
-#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
-#define ATOM_RECORD_END_TYPE 0xFF
-
-/****************************Spread Spectrum Info Table Definitions **********************/
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=2
-typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
-{
- USHORT usSpreadSpectrumPercentage;
- UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
- UCHAR ucSS_Step;
- UCHAR ucSS_Delay;
- UCHAR ucSS_Id;
- UCHAR ucRecommandedRef_Div;
- UCHAR ucSS_Range; //it was reserved for V11
-}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
-
-#define ATOM_MAX_SS_ENTRY 16
-#define ATOM_DP_SS_ID1 0x0f1 // SS modulation freq=30k
-#define ATOM_DP_SS_ID2 0x0f2 // SS modulation freq=33k
-
-
-#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
-#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
-#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
-#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
-#define ATOM_INTERNAL_SS_MASK 0x00000000
-#define ATOM_EXTERNAL_SS_MASK 0x00000002
-#define EXEC_SS_STEP_SIZE_SHIFT 2
-#define EXEC_SS_DELAY_SHIFT 4
-#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
-
-typedef struct _ATOM_SPREAD_SPECTRUM_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
-}ATOM_SPREAD_SPECTRUM_INFO;
-
-
-
-
-//ucTVBootUpDefaultStd definiton:
-
-//ATOM_TV_NTSC 1
-//ATOM_TV_NTSCJ 2
-//ATOM_TV_PAL 3
-//ATOM_TV_PALM 4
-//ATOM_TV_PALCN 5
-//ATOM_TV_PALN 6
-//ATOM_TV_PAL60 7
-//ATOM_TV_SECAM 8
-
-
-//ucTVSuppportedStd definition:
-#define NTSC_SUPPORT 0x1
-#define NTSCJ_SUPPORT 0x2
-
-#define PAL_SUPPORT 0x4
-#define PALM_SUPPORT 0x8
-#define PALCN_SUPPORT 0x10
-#define PALN_SUPPORT 0x20
-#define PAL60_SUPPORT 0x40
-#define SECAM_SUPPORT 0x80
-
-#define MAX_SUPPORTED_TV_TIMING 2
-
-typedef struct _ATOM_ANALOG_TV_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucTV_SupportedStandard;
- UCHAR ucTV_BootUpDefaultStandard;
- UCHAR ucExt_TV_ASIC_ID;
- UCHAR ucExt_TV_ASIC_SlaveAddr;
- /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
- ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
-}ATOM_ANALOG_TV_INFO;
-
-
-/**************************************************************************/
-// VRAM usage and their defintions
-
-// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
-// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
-// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
-// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
-// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
-
-#ifndef VESA_MEMORY_IN_64K_BLOCK
-#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
-#endif
-
-#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
-#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
-#define ATOM_HWICON_INFOTABLE_SIZE 32
-#define MAX_DTD_MODE_IN_VRAM 6
-#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
-#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
-#define DFP_ENCODER_TYPE_OFFSET 0x80
-#define DP_ENCODER_LANE_NUM_OFFSET 0x84
-#define DP_ENCODER_LINK_RATE_OFFSET 0x88
-
-#define ATOM_HWICON1_SURFACE_ADDR 0
-#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
-#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
-#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
-#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
-#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)
-
-#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256)
-#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512
-
-//The size below is in Kb!
-#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
-
-#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
-#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
-#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
-#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
-
-#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
-
-typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
-{
- ULONG ulStartAddrUsedByFirmware;
- USHORT usFirmwareUseInKb;
- USHORT usReserved;
-}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
-
-typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
-}ATOM_VRAM_USAGE_BY_FIRMWARE;
-
-/**************************************************************************/
-//GPIO Pin lut table definition
-typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
-{
- USHORT usGpioPin_AIndex;
- UCHAR ucGpioPinBitShift;
- UCHAR ucGPIO_ID;
-}ATOM_GPIO_PIN_ASSIGNMENT;
-
-typedef struct _ATOM_GPIO_PIN_LUT
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
-}ATOM_GPIO_PIN_LUT;
-
-/**************************************************************************/
-
-
-#define GPIO_PIN_ACTIVE_HIGH 0x1
-
-#define MAX_SUPPORTED_CV_STANDARDS 5
-
-// definitions for ATOM_D_INFO.ucSettings
-#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
-#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
-#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
-
-typedef struct _ATOM_GPIO_INFO
-{
- USHORT usAOffset;
- UCHAR ucSettings;
- UCHAR ucReserved;
-}ATOM_GPIO_INFO;
-
-// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
-#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
-
-// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
-#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
-#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
-
-// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
-//Line 3 out put 5V.
-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
-
-//Line 3 out put 2.2V
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
-
-//Line 3 out put 0V
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
-
-#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
-
-#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
-
-//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
-#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
-#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
-
-
-typedef struct _ATOM_COMPONENT_VIDEO_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usMask_PinRegisterIndex;
- USHORT usEN_PinRegisterIndex;
- USHORT usY_PinRegisterIndex;
- USHORT usA_PinRegisterIndex;
- UCHAR ucBitShift;
- UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
- ATOM_DTD_FORMAT sReserved; // must be zeroed out
- UCHAR ucMiscInfo;
- UCHAR uc480i;
- UCHAR uc480p;
- UCHAR uc720p;
- UCHAR uc1080i;
- UCHAR ucLetterBoxMode;
- UCHAR ucReserved[3];
- UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
- ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
- ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
-}ATOM_COMPONENT_VIDEO_INFO;
-
-//ucTableFormatRevision=2
-//ucTableContentRevision=1
-typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucMiscInfo;
- UCHAR uc480i;
- UCHAR uc480p;
- UCHAR uc720p;
- UCHAR uc1080i;
- UCHAR ucReserved;
- UCHAR ucLetterBoxMode;
- UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
- ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
- ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
-}ATOM_COMPONENT_VIDEO_INFO_V21;
-
-#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
-
-/**************************************************************************/
-//Object table starts here
-typedef struct _ATOM_OBJECT_HEADER
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usDeviceSupport;
- USHORT usConnectorObjectTableOffset;
- USHORT usRouterObjectTableOffset;
- USHORT usEncoderObjectTableOffset;
- USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
- USHORT usDisplayPathTableOffset;
-}ATOM_OBJECT_HEADER;
-
-
-typedef struct _ATOM_DISPLAY_OBJECT_PATH
-{
- USHORT usDeviceTag; //supported device
- USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
- USHORT usConnObjectId; //Connector Object ID
- USHORT usGPUObjectId; //GPU ID
- USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
-}ATOM_DISPLAY_OBJECT_PATH;
-
-typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
-{
- UCHAR ucNumOfDispPath;
- UCHAR ucVersion;
- UCHAR ucPadding[2];
- ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
-}ATOM_DISPLAY_OBJECT_PATH_TABLE;
-
-
-typedef struct _ATOM_OBJECT //each object has this structure
-{
- USHORT usObjectID;
- USHORT usSrcDstTableOffset;
- USHORT usRecordOffset; //this pointing to a bunch of records defined below
- USHORT usReserved;
-}ATOM_OBJECT;
-
-typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
-{
- UCHAR ucNumberOfObjects;
- UCHAR ucPadding[3];
- ATOM_OBJECT asObjects[1];
-}ATOM_OBJECT_TABLE;
-
-typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
-{
- UCHAR ucNumberOfSrc;
- USHORT usSrcObjectID[1];
- UCHAR ucNumberOfDst;
- USHORT usDstObjectID[1];
-}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
-
-
-//Related definitions, all records are differnt but they have a commond header
-typedef struct _ATOM_COMMON_RECORD_HEADER
-{
- UCHAR ucRecordType; //An emun to indicate the record type
- UCHAR ucRecordSize; //The size of the whole record in byte
-}ATOM_COMMON_RECORD_HEADER;
-
-
-#define ATOM_I2C_RECORD_TYPE 1
-#define ATOM_HPD_INT_RECORD_TYPE 2
-#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
-#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
-#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
-#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
-#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
-#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
-#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
-#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
-#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
-#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
-#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
-#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
-#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
-
-//Must be updated when new record type is added,equal to that record definition!
-#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE
-
-typedef struct _ATOM_I2C_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- ATOM_I2C_ID_CONFIG sucI2cId;
- UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
-}ATOM_I2C_RECORD;
-
-typedef struct _ATOM_HPD_INT_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
- UCHAR ucPluggged_PinState;
-}ATOM_HPD_INT_RECORD;
-
-
-typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucProtectionFlag;
- UCHAR ucReserved;
-}ATOM_OUTPUT_PROTECTION_RECORD;
-
-typedef struct _ATOM_CONNECTOR_DEVICE_TAG
-{
- ULONG ulACPIDeviceEnum; //Reserved for now
- USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
- USHORT usPadding;
-}ATOM_CONNECTOR_DEVICE_TAG;
-
-typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucNumberOfDevice;
- UCHAR ucReserved;
- ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
-}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
-
-
-typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucConfigGPIOID;
- UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
- UCHAR ucFlowinGPIPID;
- UCHAR ucExtInGPIPID;
-}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
-
-typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucCTL1GPIO_ID;
- UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
- UCHAR ucCTL2GPIO_ID;
- UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
- UCHAR ucCTL3GPIO_ID;
- UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
- UCHAR ucCTLFPGA_IN_ID;
- UCHAR ucPadding[3];
-}ATOM_ENCODER_FPGA_CONTROL_RECORD;
-
-typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
- UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
-}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
-
-typedef struct _ATOM_JTAG_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucTMSGPIO_ID;
- UCHAR ucTMSGPIOState; //Set to 1 when it's active high
- UCHAR ucTCKGPIO_ID;
- UCHAR ucTCKGPIOState; //Set to 1 when it's active high
- UCHAR ucTDOGPIO_ID;
- UCHAR ucTDOGPIOState; //Set to 1 when it's active high
- UCHAR ucTDIGPIO_ID;
- UCHAR ucTDIGPIOState; //Set to 1 when it's active high
- UCHAR ucPadding[2];
-}ATOM_JTAG_RECORD;
-
-
-//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
-typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
-{
- UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
- UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
-}ATOM_GPIO_PIN_CONTROL_PAIR;
-
-typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucFlags; // Future expnadibility
- UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
- ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
-}ATOM_OBJECT_GPIO_CNTL_RECORD;
-
-//Definitions for GPIO pin state
-#define GPIO_PIN_TYPE_INPUT 0x00
-#define GPIO_PIN_TYPE_OUTPUT 0x10
-#define GPIO_PIN_TYPE_HW_CONTROL 0x20
-
-//For GPIO_PIN_TYPE_OUTPUT the following is defined
-#define GPIO_PIN_OUTPUT_STATE_MASK 0x01
-#define GPIO_PIN_OUTPUT_STATE_SHIFT 0
-#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
-#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
-
-typedef struct _ATOM_ENCODER_DVO_CF_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- ULONG ulStrengthControl; // DVOA strength control for CF
- UCHAR ucPadding[2];
-}ATOM_ENCODER_DVO_CF_RECORD;
-
-// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
-#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
-#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
-
-typedef struct _ATOM_CONNECTOR_CF_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- USHORT usMaxPixClk;
- UCHAR ucFlowCntlGpioId;
- UCHAR ucSwapCntlGpioId;
- UCHAR ucConnectedDvoBundle;
- UCHAR ucPadding;
-}ATOM_CONNECTOR_CF_RECORD;
-
-typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- ATOM_DTD_FORMAT asTiming;
-}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
-
-typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
- UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
- UCHAR ucReserved;
-}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
-
-
-typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
- UCHAR ucMuxControlPin;
- UCHAR ucMuxState[2]; //for alligment purpose
-}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
-
-typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
-{
- ATOM_COMMON_RECORD_HEADER sheader;
- UCHAR ucMuxType;
- UCHAR ucMuxControlPin;
- UCHAR ucMuxState[2]; //for alligment purpose
-}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
-
-// define ucMuxType
-#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
-#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
-
-/**************************************************************************/
-//ASIC voltage data table starts here
-
-typedef struct _ATOM_VOLTAGE_INFO_HEADER
-{
- USHORT usVDDCBaseLevel; //In number of 50mv unit
- USHORT usReserved; //For possible extension table offset
- UCHAR ucNumOfVoltageEntries;
- UCHAR ucBytesPerVoltageEntry;
- UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
- UCHAR ucDefaultVoltageEntry;
- UCHAR ucVoltageControlI2cLine;
- UCHAR ucVoltageControlAddress;
- UCHAR ucVoltageControlOffset;
-}ATOM_VOLTAGE_INFO_HEADER;
-
-typedef struct _ATOM_VOLTAGE_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_VOLTAGE_INFO_HEADER viHeader;
- UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
-}ATOM_VOLTAGE_INFO;
-
-
-typedef struct _ATOM_VOLTAGE_FORMULA
-{
- USHORT usVoltageBaseLevel; // In number of 1mv unit
- USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
- UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
- UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
- UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
- UCHAR ucReserved;
- UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
-}ATOM_VOLTAGE_FORMULA;
-
-typedef struct _ATOM_VOLTAGE_CONTROL
-{
- UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
- UCHAR ucVoltageControlI2cLine;
- UCHAR ucVoltageControlAddress;
- UCHAR ucVoltageControlOffset;
- USHORT usGpioPin_AIndex; //GPIO_PAD register index
- UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
- UCHAR ucReserved;
-}ATOM_VOLTAGE_CONTROL;
-
-// Define ucVoltageControlId
-#define VOLTAGE_CONTROLLED_BY_HW 0x00
-#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
-#define VOLTAGE_CONTROLLED_BY_GPIO 0x80
-#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
-#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
-#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
-#define VOLTAGE_CONTROL_ID_DS4402 0x04
-
-typedef struct _ATOM_VOLTAGE_OBJECT
-{
- UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
- UCHAR ucSize; //Size of Object
- ATOM_VOLTAGE_CONTROL asControl; //describ how to control
- ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
-}ATOM_VOLTAGE_OBJECT;
-
-typedef struct _ATOM_VOLTAGE_OBJECT_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
-}ATOM_VOLTAGE_OBJECT_INFO;
-
-typedef struct _ATOM_LEAKID_VOLTAGE
-{
- UCHAR ucLeakageId;
- UCHAR ucReserved;
- USHORT usVoltage;
-}ATOM_LEAKID_VOLTAGE;
-
-typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
-{
- UCHAR ucProfileId;
- UCHAR ucReserved;
- USHORT usSize;
- USHORT usEfuseSpareStartAddr;
- USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
- ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
-}ATOM_ASIC_PROFILE_VOLTAGE;
-
-//ucProfileId
-#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
-#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
-#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
-
-typedef struct _ATOM_ASIC_PROFILING_INFO
-{
- ATOM_COMMON_TABLE_HEADER asHeader;
- ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
-}ATOM_ASIC_PROFILING_INFO;
-
-typedef struct _ATOM_POWER_SOURCE_OBJECT
-{
- UCHAR ucPwrSrcId; // Power source
- UCHAR ucPwrSensorType; // GPIO, I2C or none
- UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
- UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
- UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
- UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
- UCHAR ucPwrSensActiveState; // high active or low active
- UCHAR ucReserve[3]; // reserve
- USHORT usSensPwr; // in unit of watt
-}ATOM_POWER_SOURCE_OBJECT;
-
-typedef struct _ATOM_POWER_SOURCE_INFO
-{
- ATOM_COMMON_TABLE_HEADER asHeader;
- UCHAR asPwrbehave[16];
- ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
-}ATOM_POWER_SOURCE_INFO;
-
-
-//Define ucPwrSrcId
-#define POWERSOURCE_PCIE_ID1 0x00
-#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
-#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
-#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
-#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
-
-//define ucPwrSensorId
-#define POWER_SENSOR_ALWAYS 0x00
-#define POWER_SENSOR_GPIO 0x01
-#define POWER_SENSOR_I2C 0x02
-
-/**************************************************************************/
-// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
-//Memory SS Info Table
-//Define Memory Clock SS chip ID
-#define ICS91719 1
-#define ICS91720 2
-
-//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
-typedef struct _ATOM_I2C_DATA_RECORD
-{
- UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
- UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
-}ATOM_I2C_DATA_RECORD;
-
-
-//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
-typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
-{
- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
- UCHAR ucSSChipID; //SS chip being used
- UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
- UCHAR ucNumOfI2CDataRecords; //number of data block
- ATOM_I2C_DATA_RECORD asI2CData[1];
-}ATOM_I2C_DEVICE_SETUP_INFO;
-
-//==========================================================================================
-typedef struct _ATOM_ASIC_MVDD_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
-}ATOM_ASIC_MVDD_INFO;
-
-//==========================================================================================
-#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
-
-//==========================================================================================
-/**************************************************************************/
-
-typedef struct _ATOM_ASIC_SS_ASSIGNMENT
-{
- ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
- USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
- USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
- UCHAR ucClockIndication; //Indicate which clock source needs SS
- UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
- UCHAR ucReserved[2];
-}ATOM_ASIC_SS_ASSIGNMENT;
-
-//Define ucSpreadSpectrumType
-#define ASIC_INTERNAL_MEMORY_SS 1
-#define ASIC_INTERNAL_ENGINE_SS 2
-#define ASIC_INTERNAL_UVD_SS 3
-
-typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
-}ATOM_ASIC_INTERNAL_SS_INFO;
-
-//==============================Scratch Pad Definition Portion===============================
-#define ATOM_DEVICE_CONNECT_INFO_DEF 0
-#define ATOM_ROM_LOCATION_DEF 1
-#define ATOM_TV_STANDARD_DEF 2
-#define ATOM_ACTIVE_INFO_DEF 3
-#define ATOM_LCD_INFO_DEF 4
-#define ATOM_DOS_REQ_INFO_DEF 5
-#define ATOM_ACC_CHANGE_INFO_DEF 6
-#define ATOM_DOS_MODE_INFO_DEF 7
-#define ATOM_I2C_CHANNEL_STATUS_DEF 8
-#define ATOM_I2C_CHANNEL_STATUS1_DEF 9
-
-
-// BIOS_0_SCRATCH Definition
-#define ATOM_S0_CRT1_MONO 0x00000001L
-#define ATOM_S0_CRT1_COLOR 0x00000002L
-#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
-
-#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
-#define ATOM_S0_TV1_SVIDEO_A 0x00000008L
-#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
-
-#define ATOM_S0_CV_A 0x00000010L
-#define ATOM_S0_CV_DIN_A 0x00000020L
-#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
-
-
-#define ATOM_S0_CRT2_MONO 0x00000100L
-#define ATOM_S0_CRT2_COLOR 0x00000200L
-#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
-
-#define ATOM_S0_TV1_COMPOSITE 0x00000400L
-#define ATOM_S0_TV1_SVIDEO 0x00000800L
-#define ATOM_S0_TV1_SCART 0x00004000L
-#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
-
-#define ATOM_S0_CV 0x00001000L
-#define ATOM_S0_CV_DIN 0x00002000L
-#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
-
-
-#define ATOM_S0_DFP1 0x00010000L
-#define ATOM_S0_DFP2 0x00020000L
-#define ATOM_S0_LCD1 0x00040000L
-#define ATOM_S0_LCD2 0x00080000L
-#define ATOM_S0_TV2 0x00100000L
-#define ATOM_S0_DFP3 0x00200000L
-
-#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
- // the FAD/HDP reg access bug. Bit is read by DAL
-
-#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
-#define ATOM_S0_THERMAL_STATE_SHIFT 26
-
-#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
-#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
-
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
-#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
-
-//Byte aligned defintion for BIOS usage
-#define ATOM_S0_CRT1_MONOb0 0x01
-#define ATOM_S0_CRT1_COLORb0 0x02
-#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
-
-#define ATOM_S0_TV1_COMPOSITEb0 0x04
-#define ATOM_S0_TV1_SVIDEOb0 0x08
-#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
-
-#define ATOM_S0_CVb0 0x10
-#define ATOM_S0_CV_DINb0 0x20
-#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
-
-#define ATOM_S0_CRT2_MONOb1 0x01
-#define ATOM_S0_CRT2_COLORb1 0x02
-#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
-
-#define ATOM_S0_TV1_COMPOSITEb1 0x04
-#define ATOM_S0_TV1_SVIDEOb1 0x08
-#define ATOM_S0_TV1_SCARTb1 0x40
-#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
-
-#define ATOM_S0_CVb1 0x10
-#define ATOM_S0_CV_DINb1 0x20
-#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
-
-#define ATOM_S0_DFP1b2 0x01
-#define ATOM_S0_DFP2b2 0x02
-#define ATOM_S0_LCD1b2 0x04
-#define ATOM_S0_LCD2b2 0x08
-#define ATOM_S0_TV2b2 0x10
-#define ATOM_S0_DFP3b2 0x20
-
-#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
-#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
-
-#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
-#define ATOM_S0_LCD1_SHIFT 18
-
-// BIOS_1_SCRATCH Definition
-#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
-#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
-
-
-// BIOS_2_SCRATCH Definition
-#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
-#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
-#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
-
-#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
-#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L
-#define ATOM_S2_TV1_DPMS_STATE 0x00040000L
-#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L
-#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L
-#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L
-#define ATOM_S2_TV2_DPMS_STATE 0x00400000L
-#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L
-#define ATOM_S2_CV_DPMS_STATE 0x01000000L
-#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L
-
-#define ATOM_S2_DEVICE_DPMS_STATE (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\
- ATOM_S2_DFP1I_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\
- ATOM_S2_TV2_DPMS_STATE+ATOM_S2_DFP1X_DPMS_STATE+ATOM_S2_CV_DPMS_STATE+\
- ATOM_S2_DFP3_DPMS_STATE)
-
-
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
-
-#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
-
-#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
-#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
-#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
-#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
-#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
-#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
-
-
-//Byte aligned defintion for BIOS usage
-#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
-#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
-#define ATOM_S2_CRT1_DPMS_STATEb2 0x01
-#define ATOM_S2_LCD1_DPMS_STATEb2 0x02
-#define ATOM_S2_TV1_DPMS_STATEb2 0x04
-#define ATOM_S2_DFP1_DPMS_STATEb2 0x08
-#define ATOM_S2_CRT2_DPMS_STATEb2 0x10
-#define ATOM_S2_LCD2_DPMS_STATEb2 0x20
-#define ATOM_S2_TV2_DPMS_STATEb2 0x40
-#define ATOM_S2_DFP2_DPMS_STATEb2 0x80
-#define ATOM_S2_CV_DPMS_STATEb3 0x01
-#define ATOM_S2_DFP3_DPMS_STATEb3 0x02
-
-#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C
-#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10
-#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
-#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
-
-
-// BIOS_3_SCRATCH Definition
-#define ATOM_S3_CRT1_ACTIVE 0x00000001L
-#define ATOM_S3_LCD1_ACTIVE 0x00000002L
-#define ATOM_S3_TV1_ACTIVE 0x00000004L
-#define ATOM_S3_DFP1_ACTIVE 0x00000008L
-#define ATOM_S3_CRT2_ACTIVE 0x00000010L
-#define ATOM_S3_LCD2_ACTIVE 0x00000020L
-#define ATOM_S3_TV2_ACTIVE 0x00000040L
-#define ATOM_S3_DFP2_ACTIVE 0x00000080L
-#define ATOM_S3_CV_ACTIVE 0x00000100L
-#define ATOM_S3_DFP3_ACTIVE 0x00000200L
-
-#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL
-
-#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
-#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
-
-#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
-#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
-#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
-#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
-#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
-#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
-#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L
-#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
-#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
-#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
-
-#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x03FF0000L
-#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
-#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
-#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
-
-//Byte aligned defintion for BIOS usage
-#define ATOM_S3_CRT1_ACTIVEb0 0x01
-#define ATOM_S3_LCD1_ACTIVEb0 0x02
-#define ATOM_S3_TV1_ACTIVEb0 0x04
-#define ATOM_S3_DFP1_ACTIVEb0 0x08
-#define ATOM_S3_CRT2_ACTIVEb0 0x10
-#define ATOM_S3_LCD2_ACTIVEb0 0x20
-#define ATOM_S3_TV2_ACTIVEb0 0x40
-#define ATOM_S3_DFP2_ACTIVEb0 0x80
-#define ATOM_S3_CV_ACTIVEb1 0x01
-#define ATOM_S3_DFP3_ACTIVEb1 0x02
-
-#define ATOM_S3_ACTIVE_CRTC1w0 0x3FF
-
-#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
-#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
-#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
-#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
-#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
-#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
-#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40
-#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
-#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
-#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
-
-#define ATOM_S3_ACTIVE_CRTC2w1 0x3FF
-
-#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20
-#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
-#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80
-
-// BIOS_4_SCRATCH Definition
-#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
-#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
-#define ATOM_S4_LCD1_REFRESH_SHIFT 8
-
-
-//Byte aligned defintion for BIOS usage
-#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
-#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
-#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
-
-
-// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
-#define ATOM_S5_DOS_REQ_CRT1b0 0x01
-#define ATOM_S5_DOS_REQ_LCD1b0 0x02
-#define ATOM_S5_DOS_REQ_TV1b0 0x04
-#define ATOM_S5_DOS_REQ_DFP1b0 0x08
-#define ATOM_S5_DOS_REQ_CRT2b0 0x10
-#define ATOM_S5_DOS_REQ_LCD2b0 0x20
-#define ATOM_S5_DOS_REQ_TV2b0 0x40
-#define ATOM_S5_DOS_REQ_DFP2b0 0x80
-#define ATOM_S5_DOS_REQ_CVb1 0x01
-#define ATOM_S5_DOS_REQ_DFP3b1 0x02
-
-#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF
-
-#define ATOM_S5_DOS_REQ_CRT1 0x0001
-#define ATOM_S5_DOS_REQ_LCD1 0x0002
-#define ATOM_S5_DOS_REQ_TV1 0x0004
-#define ATOM_S5_DOS_REQ_DFP1 0x0008
-#define ATOM_S5_DOS_REQ_CRT2 0x0010
-#define ATOM_S5_DOS_REQ_LCD2 0x0020
-#define ATOM_S5_DOS_REQ_TV2 0x0040
-#define ATOM_S5_DOS_REQ_DFP2 0x0080
-#define ATOM_S5_DOS_REQ_CV 0x0100
-#define ATOM_S5_DOS_REQ_DFP3 0x0200
-
-#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
-#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
-#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
-#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
-#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
- (ATOM_S5_DOS_FORCE_CVb3<<8))
-
-// BIOS_6_SCRATCH Definition
-#define ATOM_S6_DEVICE_CHANGE 0x00000001L
-#define ATOM_S6_SCALER_CHANGE 0x00000002L
-#define ATOM_S6_LID_CHANGE 0x00000004L
-#define ATOM_S6_DOCKING_CHANGE 0x00000008L
-#define ATOM_S6_ACC_MODE 0x00000010L
-#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
-#define ATOM_S6_LID_STATE 0x00000040L
-#define ATOM_S6_DOCK_STATE 0x00000080L
-#define ATOM_S6_CRITICAL_STATE 0x00000100L
-#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
-#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
-#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
-#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
-#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
-
-#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
-#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
-
-
-#define ATOM_S6_ACC_REQ_CRT1 0x00010000L
-#define ATOM_S6_ACC_REQ_LCD1 0x00020000L
-#define ATOM_S6_ACC_REQ_TV1 0x00040000L
-#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
-#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
-#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
-#define ATOM_S6_ACC_REQ_TV2 0x00400000L
-#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
-#define ATOM_S6_ACC_REQ_CV 0x01000000L
-#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
-
-#define ATOM_S6_ACC_REQ_MASK 0x03FF0000L
-#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
-#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
-#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
-#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
-
-//Byte aligned defintion for BIOS usage
-#define ATOM_S6_DEVICE_CHANGEb0 0x01
-#define ATOM_S6_SCALER_CHANGEb0 0x02
-#define ATOM_S6_LID_CHANGEb0 0x04
-#define ATOM_S6_DOCKING_CHANGEb0 0x08
-#define ATOM_S6_ACC_MODEb0 0x10
-#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
-#define ATOM_S6_LID_STATEb0 0x40
-#define ATOM_S6_DOCK_STATEb0 0x80
-#define ATOM_S6_CRITICAL_STATEb1 0x01
-#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
-#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
-#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
-#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
-#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
-
-#define ATOM_S6_ACC_REQ_CRT1b2 0x01
-#define ATOM_S6_ACC_REQ_LCD1b2 0x02
-#define ATOM_S6_ACC_REQ_TV1b2 0x04
-#define ATOM_S6_ACC_REQ_DFP1b2 0x08
-#define ATOM_S6_ACC_REQ_CRT2b2 0x10
-#define ATOM_S6_ACC_REQ_LCD2b2 0x20
-#define ATOM_S6_ACC_REQ_TV2b2 0x40
-#define ATOM_S6_ACC_REQ_DFP2b2 0x80
-#define ATOM_S6_ACC_REQ_CVb3 0x01
-#define ATOM_S6_ACC_REQ_DFP3b3 0x02
-
-#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
-#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
-#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
-#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
-#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
-
-#define ATOM_S6_DEVICE_CHANGE_SHIFT 0
-#define ATOM_S6_SCALER_CHANGE_SHIFT 1
-#define ATOM_S6_LID_CHANGE_SHIFT 2
-#define ATOM_S6_DOCKING_CHANGE_SHIFT 3
-#define ATOM_S6_ACC_MODE_SHIFT 4
-#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
-#define ATOM_S6_LID_STATE_SHIFT 6
-#define ATOM_S6_DOCK_STATE_SHIFT 7
-#define ATOM_S6_CRITICAL_STATE_SHIFT 8
-#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
-#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
-#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
-#define ATOM_S6_REQ_SCALER_SHIFT 12
-#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
-#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
-#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
-#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
-#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
-#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
-#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
-
-// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
-#define ATOM_S7_DOS_MODE_TYPEb0 0x03
-#define ATOM_S7_DOS_MODE_VGAb0 0x00
-#define ATOM_S7_DOS_MODE_VESAb0 0x01
-#define ATOM_S7_DOS_MODE_EXTb0 0x02
-#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
-#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
-#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
-#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
-
-#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
-
-// BIOS_8_SCRATCH Definition
-#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
-#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
-
-#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
-#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
-
-// BIOS_9_SCRATCH Definition
-#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
-#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
-#endif
-#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
-#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
-#endif
-#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
-#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
-#endif
-#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
-#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
-#endif
-
-
-#define ATOM_FLAG_SET 0x20
-#define ATOM_FLAG_CLEAR 0
-#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
-#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
-
-#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
-
-#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
-
-#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
-
-#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
-
-#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
-
-#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
-#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
-
-#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
-
-#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
-
-#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
-#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
-#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
-#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
-
-/****************************************************************************/
-//Portion II: Definitinos only used in Driver
-/****************************************************************************/
-
-// Macros used by driver
-
-#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
-
-#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
-#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
-
-#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
-#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
-
-/****************************************************************************/
-//Portion III: Definitinos only used in VBIOS
-/****************************************************************************/
-#define ATOM_DAC_SRC 0x80
-#define ATOM_SRC_DAC1 0
-#define ATOM_SRC_DAC2 0x80
-
-
-#ifdef UEFI_BUILD
- #define USHORT UTEMP
-#endif
-
-typedef struct _MEMORY_PLLINIT_PARAMETERS
-{
- ULONG ulTargetMemoryClock; //In 10Khz unit
- UCHAR ucAction; //not define yet
- UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
- UCHAR ucFbDiv; //FB value
- UCHAR ucPostDiv; //Post div
-}MEMORY_PLLINIT_PARAMETERS;
-
-#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
-
-
-#define GPIO_PIN_WRITE 0x01
-#define GPIO_PIN_READ 0x00
-
-typedef struct _GPIO_PIN_CONTROL_PARAMETERS
-{
- UCHAR ucGPIO_ID; //return value, read from GPIO pins
- UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
- UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
- UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
-}GPIO_PIN_CONTROL_PARAMETERS;
-
-typedef struct _ENABLE_SCALER_PARAMETERS
-{
- UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
- UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
- UCHAR ucTVStandard; //
- UCHAR ucPadding[1];
-}ENABLE_SCALER_PARAMETERS;
-#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
-
-//ucEnable:
-#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
-#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
-#define SCALER_ENABLE_2TAP_ALPHA_MODE 2
-#define SCALER_ENABLE_MULTITAP_MODE 3
-
-typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
-{
- ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
- UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
- UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
- UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
- UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
-}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
-
-typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
-{
- ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
- ENABLE_CRTC_PARAMETERS sReserved;
-}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
-{
- USHORT usHight; // Image Hight
- USHORT usWidth; // Image Width
- UCHAR ucSurface; // Surface 1 or 2
- UCHAR ucPadding[3];
-}ENABLE_GRAPH_SURFACE_PARAMETERS;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
-{
- USHORT usHight; // Image Hight
- USHORT usWidth; // Image Width
- UCHAR ucSurface; // Surface 1 or 2
- UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
- UCHAR ucPadding[2];
-}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
-
-typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
-{
- ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
- ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
-}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
-
-typedef struct _MEMORY_CLEAN_UP_PARAMETERS
-{
- USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
- USHORT usMemorySize; //8Kb blocks aligned
-}MEMORY_CLEAN_UP_PARAMETERS;
-#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
-
-typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
-{
- USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
- USHORT usY_Size;
-}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
-
-typedef struct _INDIRECT_IO_ACCESS
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR IOAccessSequence[256];
-} INDIRECT_IO_ACCESS;
-
-#define INDIRECT_READ 0x00
-#define INDIRECT_WRITE 0x80
-
-#define INDIRECT_IO_MM 0
-#define INDIRECT_IO_PLL 1
-#define INDIRECT_IO_MC 2
-#define INDIRECT_IO_PCIE 3
-#define INDIRECT_IO_PCIEP 4
-#define INDIRECT_IO_NBMISC 5
-
-#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
-#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
-#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
-#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
-#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
-#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
-#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
-#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
-#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ
-#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE
-
-typedef struct _ATOM_OEM_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
-}ATOM_OEM_INFO;
-
-typedef struct _ATOM_TV_MODE
-{
- UCHAR ucVMode_Num; //Video mode number
- UCHAR ucTV_Mode_Num; //Internal TV mode number
-}ATOM_TV_MODE;
-
-typedef struct _ATOM_BIOS_INT_TVSTD_MODE
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
- USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
- USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
- USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
- USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
-}ATOM_BIOS_INT_TVSTD_MODE;
-
-
-typedef struct _ATOM_TV_MODE_SCALER_PTR
-{
- USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
- USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
- UCHAR ucTV_Mode_Num;
-}ATOM_TV_MODE_SCALER_PTR;
-
-typedef struct _ATOM_STANDARD_VESA_TIMING
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_MODE_TIMING aModeTimings[16]; // 16 is not the real array number, just for initial allocation
-}ATOM_STANDARD_VESA_TIMING;
-
-
-typedef struct _ATOM_STD_FORMAT
-{
- USHORT usSTD_HDisp;
- USHORT usSTD_VDisp;
- USHORT usSTD_RefreshRate;
- USHORT usReserved;
-}ATOM_STD_FORMAT;
-
-typedef struct _ATOM_VESA_TO_EXTENDED_MODE
-{
- USHORT usVESA_ModeNumber;
- USHORT usExtendedModeNumber;
-}ATOM_VESA_TO_EXTENDED_MODE;
-
-typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
-}ATOM_VESA_TO_INTENAL_MODE_LUT;
-
-/*************** ATOM Memory Related Data Structure ***********************/
-typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
- UCHAR ucMemoryType;
- UCHAR ucMemoryVendor;
- UCHAR ucAdjMCId;
- UCHAR ucDynClkId;
- ULONG ulDllResetClkRange;
-}ATOM_MEMORY_VENDOR_BLOCK;
-
-
-typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
- ULONG ulMemClockRange:24;
- ULONG ucMemBlkId:8;
-}ATOM_MEMORY_SETTING_ID_CONFIG;
-
-typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
-{
- ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
- ULONG ulAccess;
-}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
-
-
-typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
- ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
- ULONG aulMemData[1];
-}ATOM_MEMORY_SETTING_DATA_BLOCK;
-
-
-typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
- USHORT usRegIndex; // MC register index
- UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
-}ATOM_INIT_REG_INDEX_FORMAT;
-
-
-typedef struct _ATOM_INIT_REG_BLOCK{
- USHORT usRegIndexTblSize; //size of asRegIndexBuf
- USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
- ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
- ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
-}ATOM_INIT_REG_BLOCK;
-
-#define END_OF_REG_INDEX_BLOCK 0x0ffff
-#define END_OF_REG_DATA_BLOCK 0x00000000
-#define ATOM_INIT_REG_MASK_FLAG 0x80
-#define CLOCK_RANGE_HIGHEST 0x00ffffff
-
-#define VALUE_DWORD SIZEOF ULONG
-#define VALUE_SAME_AS_ABOVE 0
-#define VALUE_MASK_DWORD 0x84
-
-typedef struct _ATOM_MC_INIT_PARAM_TABLE
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usAdjustARB_SEQDataOffset;
- USHORT usMCInitMemTypeTblOffset;
- USHORT usMCInitCommonTblOffset;
- USHORT usMCInitPowerDownTblOffset;
- ULONG ulARB_SEQDataBuf[32];
- ATOM_INIT_REG_BLOCK asMCInitMemType;
- ATOM_INIT_REG_BLOCK asMCInitCommon;
-}ATOM_MC_INIT_PARAM_TABLE;
-
-
-#define _4Mx16 0x2
-#define _4Mx32 0x3
-#define _8Mx16 0x12
-#define _8Mx32 0x13
-#define _16Mx16 0x22
-#define _16Mx32 0x23
-#define _32Mx16 0x32
-#define _32Mx32 0x33
-#define _64Mx8 0x41
-#define _64Mx16 0x42
-
-#define SAMSUNG 0x1
-#define INFINEON 0x2
-#define ELPIDA 0x3
-#define ETRON 0x4
-#define NANYA 0x5
-#define HYNIX 0x6
-#define MOSEL 0x7
-#define WINBOND 0x8
-#define ESMT 0x9
-#define MICRON 0xF
-
-#define QIMONDA INFINEON
-#define PROMOS MOSEL
-
-#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
-
-#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
-typedef struct _ATOM_VRAM_MODULE_V1
-{
- ULONG ulReserved;
- USHORT usEMRSValue;
- USHORT usMRSValue;
- USHORT usReserved;
- UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
- UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
- UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
- UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
- UCHAR ucRow; // Number of Row,in power of 2;
- UCHAR ucColumn; // Number of Column,in power of 2;
- UCHAR ucBank; // Nunber of Bank;
- UCHAR ucRank; // Number of Rank, in power of 2
- UCHAR ucChannelNum; // Number of channel;
- UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
- UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
- UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
- UCHAR ucReserved[2];
-}ATOM_VRAM_MODULE_V1;
-
-
-typedef struct _ATOM_VRAM_MODULE_V2
-{
- ULONG ulReserved;
- ULONG ulFlags; // To enable/disable functionalities based on memory type
- ULONG ulEngineClock; // Override of default engine clock for particular memory type
- ULONG ulMemoryClock; // Override of default memory clock for particular memory type
- USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
- USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
- USHORT usEMRSValue;
- USHORT usMRSValue;
- USHORT usReserved;
- UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
- UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
- UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
- UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
- UCHAR ucRow; // Number of Row,in power of 2;
- UCHAR ucColumn; // Number of Column,in power of 2;
- UCHAR ucBank; // Nunber of Bank;
- UCHAR ucRank; // Number of Rank, in power of 2
- UCHAR ucChannelNum; // Number of channel;
- UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
- UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
- UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
- UCHAR ucRefreshRateFactor;
- UCHAR ucReserved[3];
-}ATOM_VRAM_MODULE_V2;
-
-
-typedef struct _ATOM_MEMORY_TIMING_FORMAT
-{
- ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
- USHORT usMRS; // mode register
- USHORT usEMRS; // extended mode register
- UCHAR ucCL; // CAS latency
- UCHAR ucWL; // WRITE Latency
- UCHAR uctRAS; // tRAS
- UCHAR uctRC; // tRC
- UCHAR uctRFC; // tRFC
- UCHAR uctRCDR; // tRCDR
- UCHAR uctRCDW; // tRCDW
- UCHAR uctRP; // tRP
- UCHAR uctRRD; // tRRD
- UCHAR uctWR; // tWR
- UCHAR uctWTR; // tWTR
- UCHAR uctPDIX; // tPDIX
- UCHAR uctFAW; // tFAW
- UCHAR uctAOND; // tAOND
- UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
- UCHAR ucReserved; //
-}ATOM_MEMORY_TIMING_FORMAT;
-
-#define MEM_TIMING_FLAG_APP_MODE 0x01 // =0 mid clock range =1 high clock range
-
-typedef struct _ATOM_MEMORY_FORMAT
-{
- ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
- USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
- USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
- UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
- UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
- UCHAR ucRow; // Number of Row,in power of 2;
- UCHAR ucColumn; // Number of Column,in power of 2;
- UCHAR ucBank; // Nunber of Bank;
- UCHAR ucRank; // Number of Rank, in power of 2
- UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
- UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
- UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
- UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
- UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
- UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
- ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock
-}ATOM_MEMORY_FORMAT;
-
-
-typedef struct _ATOM_VRAM_MODULE_V3
-{
- ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
- USHORT usSize; // size of ATOM_VRAM_MODULE_V3
- USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
- USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
- UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
- UCHAR ucChannelNum; // board dependent parameter:Number of channel;
- UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
- UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
- UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
- UCHAR ucFlag; // To enable/disable functionalities based on memory type
- ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
-}ATOM_VRAM_MODULE_V3;
-
-
-//ATOM_VRAM_MODULE_V3.ucNPL_RT
-#define NPL_RT_MASK 0x0f
-#define BATTERY_ODT_MASK 0xc0
-
-#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
-
-typedef struct _ATOM_VRAM_INFO_V2
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucNumOfVRAMModule;
- ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
-}ATOM_VRAM_INFO_V2;
-
-typedef struct _ATOM_VRAM_INFO_V3
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
- USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
- USHORT usRerseved;
- UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
- UCHAR ucNumOfVRAMModule;
- ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
- ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
- // ATOM_INIT_REG_BLOCK aMemAdjust;
-}ATOM_VRAM_INFO_V3;
-
-#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
-
-typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
-}ATOM_VRAM_GPIO_DETECTION_INFO;
-
-
-typedef struct _ATOM_MEMORY_TRAINING_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucTrainingLoop;
- UCHAR ucReserved[3];
- ATOM_INIT_REG_BLOCK asMemTrainingSetting;
-}ATOM_MEMORY_TRAINING_INFO;
-
-
-typedef struct SW_I2C_CNTL_DATA_PARAMETERS
-{
- UCHAR ucControl;
- UCHAR ucData;
- UCHAR ucSatus;
- UCHAR ucTemp;
-} SW_I2C_CNTL_DATA_PARAMETERS;
-
-#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
-
-typedef struct _SW_I2C_IO_DATA_PARAMETERS
-{
- USHORT GPIO_Info;
- UCHAR ucAct;
- UCHAR ucData;
- } SW_I2C_IO_DATA_PARAMETERS;
-
-#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
-
-/****************************SW I2C CNTL DEFINITIONS**********************/
-#define SW_I2C_IO_RESET 0
-#define SW_I2C_IO_GET 1
-#define SW_I2C_IO_DRIVE 2
-#define SW_I2C_IO_SET 3
-#define SW_I2C_IO_START 4
-
-#define SW_I2C_IO_CLOCK 0
-#define SW_I2C_IO_DATA 0x80
-
-#define SW_I2C_IO_ZERO 0
-#define SW_I2C_IO_ONE 0x100
-
-#define SW_I2C_CNTL_READ 0
-#define SW_I2C_CNTL_WRITE 1
-#define SW_I2C_CNTL_START 2
-#define SW_I2C_CNTL_STOP 3
-#define SW_I2C_CNTL_OPEN 4
-#define SW_I2C_CNTL_CLOSE 5
-#define SW_I2C_CNTL_WRITE1BIT 6
-
-//==============================VESA definition Portion===============================
-#define VESA_OEM_PRODUCT_REV '01.00'
-#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
-#define VESA_MODE_WIN_ATTRIBUTE 7
-#define VESA_WIN_SIZE 64
-
-typedef struct _PTR_32_BIT_STRUCTURE
-{
- USHORT Offset16;
- USHORT Segment16;
-} PTR_32_BIT_STRUCTURE;
-
-typedef union _PTR_32_BIT_UNION
-{
- PTR_32_BIT_STRUCTURE SegmentOffset;
- ULONG Ptr32_Bit;
-} PTR_32_BIT_UNION;
-
-typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
-{
- UCHAR VbeSignature[4];
- USHORT VbeVersion;
- PTR_32_BIT_UNION OemStringPtr;
- UCHAR Capabilities[4];
- PTR_32_BIT_UNION VideoModePtr;
- USHORT TotalMemory;
-} VBE_1_2_INFO_BLOCK_UPDATABLE;
-
-
-typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
-{
- VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
- USHORT OemSoftRev;
- PTR_32_BIT_UNION OemVendorNamePtr;
- PTR_32_BIT_UNION OemProductNamePtr;
- PTR_32_BIT_UNION OemProductRevPtr;
-} VBE_2_0_INFO_BLOCK_UPDATABLE;
-
-typedef union _VBE_VERSION_UNION
-{
- VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
- VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
-} VBE_VERSION_UNION;
-
-typedef struct _VBE_INFO_BLOCK
-{
- VBE_VERSION_UNION UpdatableVBE_Info;
- UCHAR Reserved[222];
- UCHAR OemData[256];
-} VBE_INFO_BLOCK;
-
-typedef struct _VBE_FP_INFO
-{
- USHORT HSize;
- USHORT VSize;
- USHORT FPType;
- UCHAR RedBPP;
- UCHAR GreenBPP;
- UCHAR BlueBPP;
- UCHAR ReservedBPP;
- ULONG RsvdOffScrnMemSize;
- ULONG RsvdOffScrnMEmPtr;
- UCHAR Reserved[14];
-} VBE_FP_INFO;
-
-typedef struct _VESA_MODE_INFO_BLOCK
-{
-// Mandatory information for all VBE revisions
- USHORT ModeAttributes; // dw ? ; mode attributes
- UCHAR WinAAttributes; // db ? ; window A attributes
- UCHAR WinBAttributes; // db ? ; window B attributes
- USHORT WinGranularity; // dw ? ; window granularity
- USHORT WinSize; // dw ? ; window size
- USHORT WinASegment; // dw ? ; window A start segment
- USHORT WinBSegment; // dw ? ; window B start segment
- ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
- USHORT BytesPerScanLine;// dw ? ; bytes per scan line
-
-//; Mandatory information for VBE 1.2 and above
- USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
- USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
- UCHAR XCharSize; // db ? ; character cell width in pixels
- UCHAR YCharSize; // db ? ; character cell height in pixels
- UCHAR NumberOfPlanes; // db ? ; number of memory planes
- UCHAR BitsPerPixel; // db ? ; bits per pixel
- UCHAR NumberOfBanks; // db ? ; number of banks
- UCHAR MemoryModel; // db ? ; memory model type
- UCHAR BankSize; // db ? ; bank size in KB
- UCHAR NumberOfImagePages;// db ? ; number of images
- UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
-
-//; Direct Color fields(required for direct/6 and YUV/7 memory models)
- UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
- UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
- UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
- UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
- UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
- UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
- UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
- UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
- UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
-
-//; Mandatory information for VBE 2.0 and above
- ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
- ULONG Reserved_1; // dd 0 ; reserved - always set to 0
- USHORT Reserved_2; // dw 0 ; reserved - always set to 0
-
-//; Mandatory information for VBE 3.0 and above
- USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
- UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
- UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
- UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
- UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
- UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
- UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
- UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
- UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
- UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
- UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
- ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
- UCHAR Reserved; // db 190 dup (0)
-} VESA_MODE_INFO_BLOCK;
-
-// BIOS function CALLS
-#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
-#define ATOM_BIOS_FUNCTION_COP_MODE 0x00
-#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
-#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
-#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
-#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
-#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
-#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
-#define ATOM_BIOS_FUNCTION_STV_STD 0x16
-#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
-#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
-
-#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
-#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
-#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
-#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
-#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
-#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
-#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
-
-#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
-#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
-#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
-#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
-#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
-#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
-#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
-#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
-#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
-#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
-
-
-#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
-#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
-#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
-#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
-#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
-#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
-#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
-#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
-
-#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
-#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
-#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
-
-// structure used for VBIOS only
-
-//DispOutInfoTable
-typedef struct _ASIC_TRANSMITTER_INFO
-{
- USHORT usTransmitterObjId;
- USHORT usSupportDevice;
- UCHAR ucTransmitterCmdTblId;
- UCHAR ucConfig;
- UCHAR ucEncoderID; //available 1st encoder ( default )
- UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
- UCHAR uc2ndEncoderID;
- UCHAR ucReserved;
-}ASIC_TRANSMITTER_INFO;
-
-typedef struct _ASIC_ENCODER_INFO
-{
- UCHAR ucEncoderID;
- UCHAR ucEncoderConfig;
- USHORT usEncoderCmdTblId;
-}ASIC_ENCODER_INFO;
-
-typedef struct _ATOM_DISP_OUT_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT ptrTransmitterInfo;
- USHORT ptrEncoderInfo;
- ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
- ASIC_ENCODER_INFO asEncoderInfo[1];
-}ATOM_DISP_OUT_INFO;
-
-// DispDevicePriorityInfo
-typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT asDevicePriority[16];
-}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
-
-//ProcessAuxChannelTransactionTable
-typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
-{
- USHORT lpAuxRequest;
- USHORT lpDataOut;
- UCHAR ucChannelID;
- union
- {
- UCHAR ucReplyStatus;
- UCHAR ucDelay;
- };
- UCHAR ucDataOutLen;
- UCHAR ucReserved;
-}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
-
-#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
-
-//GetSinkType
-
-typedef struct _DP_ENCODER_SERVICE_PARAMETERS
-{
- USHORT ucLinkClock;
- union
- {
- UCHAR ucConfig; // for DP training command
- UCHAR ucI2cId; // use for GET_SINK_TYPE command
- };
- UCHAR ucAction;
- UCHAR ucStatus;
- UCHAR ucLaneNum;
- UCHAR ucReserved[2];
-}DP_ENCODER_SERVICE_PARAMETERS;
-
-// ucAction
-#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
-#define ATOM_DP_ACTION_TRAINING_START 0x02
-#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03
-#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04
-#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05
-#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06
-
-// ucConfig
-#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03
-#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00
-#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01
-#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02
-#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04
-#define ATOM_DP_CONFIG_LINK_A 0x00
-#define ATOM_DP_CONFIG_LINK_B 0x04
-
-#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
-
-// DP_TRAINING_TABLE
-#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
-#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
-#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
-#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
-#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
-#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
-#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
-#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
-#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
-#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
-#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
-#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
-
-
-typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
-{
- UCHAR ucI2CSpeed;
- union
- {
- UCHAR ucRegIndex;
- UCHAR ucStatus;
- };
- USHORT lpI2CDataOut;
- UCHAR ucFlag;
- UCHAR ucTransBytes;
- UCHAR ucSlaveAddr;
- UCHAR ucLineNumber;
-}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
-
-#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
-
-//ucFlag
-#define HW_I2C_WRITE 1
-#define HW_I2C_READ 0
-
-
-/****************************************************************************/
-//Portion VI: Definitinos being oboselete
-/****************************************************************************/
-
-//==========================================================================================
-//Remove the definitions below when driver is ready!
-typedef struct _ATOM_DAC_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usMaxFrequency; // in 10kHz unit
- USHORT usReserved;
-}ATOM_DAC_INFO;
-
-
-typedef struct _COMPASSIONATE_DATA
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
-
- //============================== DAC1 portion
- UCHAR ucDAC1_BG_Adjustment;
- UCHAR ucDAC1_DAC_Adjustment;
- USHORT usDAC1_FORCE_Data;
- //============================== DAC2 portion
- UCHAR ucDAC2_CRT2_BG_Adjustment;
- UCHAR ucDAC2_CRT2_DAC_Adjustment;
- USHORT usDAC2_CRT2_FORCE_Data;
- USHORT usDAC2_CRT2_MUX_RegisterIndex;
- UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
- UCHAR ucDAC2_NTSC_BG_Adjustment;
- UCHAR ucDAC2_NTSC_DAC_Adjustment;
- USHORT usDAC2_TV1_FORCE_Data;
- USHORT usDAC2_TV1_MUX_RegisterIndex;
- UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
- UCHAR ucDAC2_CV_BG_Adjustment;
- UCHAR ucDAC2_CV_DAC_Adjustment;
- USHORT usDAC2_CV_FORCE_Data;
- USHORT usDAC2_CV_MUX_RegisterIndex;
- UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
- UCHAR ucDAC2_PAL_BG_Adjustment;
- UCHAR ucDAC2_PAL_DAC_Adjustment;
- USHORT usDAC2_TV2_FORCE_Data;
-}COMPASSIONATE_DATA;
-
-/****************************Supported Device Info Table Definitions**********************/
-// ucConnectInfo:
-// [7:4] - connector type
-// = 1 - VGA connector
-// = 2 - DVI-I
-// = 3 - DVI-D
-// = 4 - DVI-A
-// = 5 - SVIDEO
-// = 6 - COMPOSITE
-// = 7 - LVDS
-// = 8 - DIGITAL LINK
-// = 9 - SCART
-// = 0xA - HDMI_type A
-// = 0xB - HDMI_type B
-// = 0xE - Special case1 (DVI+DIN)
-// Others=TBD
-// [3:0] - DAC Associated
-// = 0 - no DAC
-// = 1 - DACA
-// = 2 - DACB
-// = 3 - External DAC
-// Others=TBD
-//
-
-typedef struct _ATOM_CONNECTOR_INFO
-{
- UCHAR bfAssociatedDAC:4;
- UCHAR bfConnectorType:4;
-}ATOM_CONNECTOR_INFO;
-
-typedef union _ATOM_CONNECTOR_INFO_ACCESS
-{
- ATOM_CONNECTOR_INFO sbfAccess;
- UCHAR ucAccess;
-}ATOM_CONNECTOR_INFO_ACCESS;
-
-typedef struct _ATOM_CONNECTOR_INFO_I2C
-{
- ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
-}ATOM_CONNECTOR_INFO_I2C;
-
-
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usDeviceSupport;
- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
-}ATOM_SUPPORTED_DEVICES_INFO;
-
-#define NO_INT_SRC_MAPPED 0xFF
-
-typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
-{
- UCHAR ucIntSrcBitmap;
-}ATOM_CONNECTOR_INC_SRC_BITMAP;
-
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usDeviceSupport;
- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
- ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
-}ATOM_SUPPORTED_DEVICES_INFO_2;
-
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usDeviceSupport;
- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
- ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
-}ATOM_SUPPORTED_DEVICES_INFO_2d1;
-
-#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
-
-
-
-typedef struct _ATOM_MISC_CONTROL_INFO
-{
- USHORT usFrequency;
- UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
- UCHAR ucPLL_DutyCycle; // PLL duty cycle control
- UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
- UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
-}ATOM_MISC_CONTROL_INFO;
-
-
-#define ATOM_MAX_MISC_INFO 4
-
-typedef struct _ATOM_TMDS_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usMaxFrequency; // in 10Khz
- ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
-}ATOM_TMDS_INFO;
-
-
-typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
-{
- UCHAR ucTVStandard; //Same as TV standards defined above,
- UCHAR ucPadding[1];
-}ATOM_ENCODER_ANALOG_ATTRIBUTE;
-
-typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
-{
- UCHAR ucAttribute; //Same as other digital encoder attributes defined above
- UCHAR ucPadding[1];
-}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
-
-typedef union _ATOM_ENCODER_ATTRIBUTE
-{
- ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
- ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
-}ATOM_ENCODER_ATTRIBUTE;
-
-
-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
-{
- USHORT usPixelClock;
- USHORT usEncoderID;
- UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
- UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
- ATOM_ENCODER_ATTRIBUTE usDevAttr;
-}DVO_ENCODER_CONTROL_PARAMETERS;
-
-typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
-{
- DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
-}DVO_ENCODER_CONTROL_PS_ALLOCATION;
-
-
-#define ATOM_XTMDS_ASIC_SI164_ID 1
-#define ATOM_XTMDS_ASIC_SI178_ID 2
-#define ATOM_XTMDS_ASIC_TFP513_ID 3
-#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
-#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
-#define ATOM_XTMDS_MVPU_FPGA 0x00000004
-
-
-typedef struct _ATOM_XTMDS_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usSingleLinkMaxFrequency;
- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
- UCHAR ucXtransimitterID;
- UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
- UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
- // due to design. This ID is used to alert driver that the sequence is not "standard"!
- UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
- UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
-}ATOM_XTMDS_INFO;
-
-typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
-{
- UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
- UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
- UCHAR ucPadding[2];
-}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
-
-/****************************Legacy Power Play Table Definitions **********************/
-
-//Definitions for ulPowerPlayMiscInfo
-#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
-#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
-#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
-
-#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
-#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
-
-#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
-
-#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
-#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
-#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
-
-#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
-#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
-#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
-#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
-#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
-#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
-#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
-
-#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
-#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
-#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
-#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
-#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
-
-#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
-#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
-
-#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
-#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
-#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
-#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
-#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
-#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
-
-#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
-#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
-#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
-
-#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
-#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
-#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
-#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
-#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
-#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
-#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
- //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
-#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
-#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
-#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
-
-//ucTableFormatRevision=1
-//ucTableContentRevision=1
-typedef struct _ATOM_POWERMODE_INFO
-{
- ULONG ulMiscInfo; //The power level should be arranged in ascending order
- ULONG ulReserved1; // must set to 0
- ULONG ulReserved2; // must set to 0
- USHORT usEngineClock;
- USHORT usMemoryClock;
- UCHAR ucVoltageDropIndex; // index to GPIO table
- UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
- UCHAR ucMinTemperature;
- UCHAR ucMaxTemperature;
- UCHAR ucNumPciELanes; // number of PCIE lanes
-}ATOM_POWERMODE_INFO;
-
-//ucTableFormatRevision=2
-//ucTableContentRevision=1
-typedef struct _ATOM_POWERMODE_INFO_V2
-{
- ULONG ulMiscInfo; //The power level should be arranged in ascending order
- ULONG ulMiscInfo2;
- ULONG ulEngineClock;
- ULONG ulMemoryClock;
- UCHAR ucVoltageDropIndex; // index to GPIO table
- UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
- UCHAR ucMinTemperature;
- UCHAR ucMaxTemperature;
- UCHAR ucNumPciELanes; // number of PCIE lanes
-}ATOM_POWERMODE_INFO_V2;
-
-//ucTableFormatRevision=2
-//ucTableContentRevision=2
-typedef struct _ATOM_POWERMODE_INFO_V3
-{
- ULONG ulMiscInfo; //The power level should be arranged in ascending order
- ULONG ulMiscInfo2;
- ULONG ulEngineClock;
- ULONG ulMemoryClock;
- UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
- UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
- UCHAR ucMinTemperature;
- UCHAR ucMaxTemperature;
- UCHAR ucNumPciELanes; // number of PCIE lanes
- UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
-}ATOM_POWERMODE_INFO_V3;
-
-
-#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
-
-#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
-#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
-
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
-
-
-typedef struct _ATOM_POWERPLAY_INFO
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucOverdriveThermalController;
- UCHAR ucOverdriveI2cLine;
- UCHAR ucOverdriveIntBitmap;
- UCHAR ucOverdriveControllerAddress;
- UCHAR ucSizeOfPowerModeEntry;
- UCHAR ucNumOfPowerModeEntries;
- ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
-}ATOM_POWERPLAY_INFO;
-
-typedef struct _ATOM_POWERPLAY_INFO_V2
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucOverdriveThermalController;
- UCHAR ucOverdriveI2cLine;
- UCHAR ucOverdriveIntBitmap;
- UCHAR ucOverdriveControllerAddress;
- UCHAR ucSizeOfPowerModeEntry;
- UCHAR ucNumOfPowerModeEntries;
- ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
-}ATOM_POWERPLAY_INFO_V2;
-
-typedef struct _ATOM_POWERPLAY_INFO_V3
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- UCHAR ucOverdriveThermalController;
- UCHAR ucOverdriveI2cLine;
- UCHAR ucOverdriveIntBitmap;
- UCHAR ucOverdriveControllerAddress;
- UCHAR ucSizeOfPowerModeEntry;
- UCHAR ucNumOfPowerModeEntries;
- ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
-}ATOM_POWERPLAY_INFO_V3;
-
-
-
-/**************************************************************************/
-
-
-// Following definitions are for compatiblity issue in different SW components.
-#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
-#define Object_Info Object_Header
-#define AdjustARB_SEQ MC_InitParameter
-#define VRAM_GPIO_DetectionInfo VoltageObjectInfo
-#define ASIC_VDDCI_Info ASIC_ProfilingInfo
-#define ASIC_MVDDQ_Info MemoryTrainingInfo
-#define SS_Info PPLL_SS_Info
-#define ASIC_MVDDC_Info ASIC_InternalSS_Info
-#define DispDevicePriorityInfo SaveRestoreInfo
-#define DispOutInfo TV_VideoMode
-
-
-#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
-#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
-
-//New device naming, remove them when both DAL/VBIOS is ready
-#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
-#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
-
-#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
-#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
-
-#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
-#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
-
-#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
-#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
-
-#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
-#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
-
-#define ATOM_DEVICE_DFP2I_INDEX 0x00000009
-#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
-
-#define ATOM_S0_DFP1I ATOM_S0_DFP1
-#define ATOM_S0_DFP1X ATOM_S0_DFP2
-
-#define ATOM_S0_DFP2I 0x00200000L
-#define ATOM_S0_DFP2Ib2 0x20
-
-#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
-#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
-
-#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
-#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
-
-#define ATOM_S3_DFP2I_ACTIVEb1 0x02
-
-#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
-#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
-
-#define ATOM_S3_DFP2I_ACTIVE 0x00000200L
-
-#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
-#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
-#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
-
-#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
-#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
-
-#define ATOM_S5_DOS_REQ_DFP2I 0x0200
-#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
-#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
-
-#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
-#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
-
-#define TMDS1XEncoderControl DVOEncoderControl
-#define DFP1XOutputControl DVOOutputControl
-
-#define ExternalDFPOutputControl DFP1XOutputControl
-#define EnableExternalTMDS_Encoder TMDS1XEncoderControl
-
-#define DFP1IOutputControl TMDSAOutputControl
-#define DFP2IOutputControl LVTMAOutputControl
-
-#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
-#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
-
-#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
-#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
-
-#define ucDac1Standard ucDacStandard
-#define ucDac2Standard ucDacStandard
-
-#define TMDS1EncoderControl TMDSAEncoderControl
-#define TMDS2EncoderControl LVTMAEncoderControl
-
-#define DFP1OutputControl TMDSAOutputControl
-#define DFP2OutputControl LVTMAOutputControl
-#define CRT1OutputControl DAC1OutputControl
-#define CRT2OutputControl DAC2OutputControl
-
-//These two lines will be removed for sure in a few days, will follow up with Michael V.
-#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
-#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
-
-/*********************************************************************************/
-#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L
-#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L
-#define ATOM_S6_REQ_SCALER2_H 0x00004000L
-#define ATOM_S6_REQ_SCALER2_V 0x00008000L
-
-#define ATOM_S3_SCALER1_ACTIVE_H ATOM_S3_LCD_FULLEXPANSION_ACTIVE
-#define ATOM_S3_SCALER1_ACTIVE_V ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE
-
-#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL
-#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO
-//==========================================================================================
-
-#pragma pack() // BIOS data must use byte aligment
-
-#endif /* _ATOMBIOS_H */
diff --git a/src/AtomBios/includes/regsdef.h b/src/AtomBios/includes/regsdef.h
deleted file mode 100644
index e557ac0..0000000
--- a/src/AtomBios/includes/regsdef.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2006-2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-//This is a dummy file used by driver-parser during compilation.
-//Without this file, compatibility will be broken among ASICs and BIOs vs. driver
-//James H. Apr. 22/03
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
deleted file mode 100644
index 330d1a9..0000000
--- a/src/ati_pciids_gen.h
+++ /dev/null
@@ -1,358 +0,0 @@
-#define PCI_CHIP_RV380_3150 0x3150
-#define PCI_CHIP_RV380_3152 0x3152
-#define PCI_CHIP_RV380_3154 0x3154
-#define PCI_CHIP_RV380_3E50 0x3E50
-#define PCI_CHIP_RV380_3E54 0x3E54
-#define PCI_CHIP_RS100_4136 0x4136
-#define PCI_CHIP_RS200_4137 0x4137
-#define PCI_CHIP_R300_AD 0x4144
-#define PCI_CHIP_R300_AE 0x4145
-#define PCI_CHIP_R300_AF 0x4146
-#define PCI_CHIP_R300_AG 0x4147
-#define PCI_CHIP_R350_AH 0x4148
-#define PCI_CHIP_R350_AI 0x4149
-#define PCI_CHIP_R350_AJ 0x414A
-#define PCI_CHIP_R350_AK 0x414B
-#define PCI_CHIP_RV350_AP 0x4150
-#define PCI_CHIP_RV350_AQ 0x4151
-#define PCI_CHIP_RV360_AR 0x4152
-#define PCI_CHIP_RV350_AS 0x4153
-#define PCI_CHIP_RV350_AT 0x4154
-#define PCI_CHIP_RV350_4155 0x4155
-#define PCI_CHIP_RV350_AV 0x4156
-#define PCI_CHIP_MACH32 0x4158
-#define PCI_CHIP_RS250_4237 0x4237
-#define PCI_CHIP_R200_BB 0x4242
-#define PCI_CHIP_R200_BC 0x4243
-#define PCI_CHIP_RS100_4336 0x4336
-#define PCI_CHIP_RS200_4337 0x4337
-#define PCI_CHIP_MACH64CT 0x4354
-#define PCI_CHIP_MACH64CX 0x4358
-#define PCI_CHIP_RS250_4437 0x4437
-#define PCI_CHIP_MACH64ET 0x4554
-#define PCI_CHIP_MACH64GB 0x4742
-#define PCI_CHIP_MACH64GD 0x4744
-#define PCI_CHIP_MACH64GI 0x4749
-#define PCI_CHIP_MACH64GL 0x474C
-#define PCI_CHIP_MACH64GM 0x474D
-#define PCI_CHIP_MACH64GN 0x474E
-#define PCI_CHIP_MACH64GO 0x474F
-#define PCI_CHIP_MACH64GP 0x4750
-#define PCI_CHIP_MACH64GQ 0x4751
-#define PCI_CHIP_MACH64GR 0x4752
-#define PCI_CHIP_MACH64GS 0x4753
-#define PCI_CHIP_MACH64GT 0x4754
-#define PCI_CHIP_MACH64GU 0x4755
-#define PCI_CHIP_MACH64GV 0x4756
-#define PCI_CHIP_MACH64GW 0x4757
-#define PCI_CHIP_MACH64GX 0x4758
-#define PCI_CHIP_MACH64GY 0x4759
-#define PCI_CHIP_MACH64GZ 0x475A
-#define PCI_CHIP_RV250_If 0x4966
-#define PCI_CHIP_RV250_Ig 0x4967
-#define PCI_CHIP_R420_JH 0x4A48
-#define PCI_CHIP_R420_JI 0x4A49
-#define PCI_CHIP_R420_JJ 0x4A4A
-#define PCI_CHIP_R420_JK 0x4A4B
-#define PCI_CHIP_R420_JL 0x4A4C
-#define PCI_CHIP_R420_JM 0x4A4D
-#define PCI_CHIP_R420_JN 0x4A4E
-#define PCI_CHIP_R420_4A4F 0x4A4F
-#define PCI_CHIP_R420_JP 0x4A50
-#define PCI_CHIP_R481_4B49 0x4B49
-#define PCI_CHIP_R481_4B4A 0x4B4A
-#define PCI_CHIP_R481_4B4B 0x4B4B
-#define PCI_CHIP_R481_4B4C 0x4B4C
-#define PCI_CHIP_MACH64LB 0x4C42
-#define PCI_CHIP_MACH64LD 0x4C44
-#define PCI_CHIP_RAGE128LE 0x4C45
-#define PCI_CHIP_RAGE128LF 0x4C46
-#define PCI_CHIP_MACH64LG 0x4C47
-#define PCI_CHIP_MACH64LI 0x4C49
-#define PCI_CHIP_MACH64LM 0x4C4D
-#define PCI_CHIP_MACH64LN 0x4C4E
-#define PCI_CHIP_MACH64LP 0x4C50
-#define PCI_CHIP_MACH64LQ 0x4C51
-#define PCI_CHIP_MACH64LR 0x4C52
-#define PCI_CHIP_MACH64LS 0x4C53
-#define PCI_CHIP_RADEON_LW 0x4C57
-#define PCI_CHIP_RADEON_LX 0x4C58
-#define PCI_CHIP_RADEON_LY 0x4C59
-#define PCI_CHIP_RADEON_LZ 0x4C5A
-#define PCI_CHIP_RV250_Ld 0x4C64
-#define PCI_CHIP_RV250_Lf 0x4C66
-#define PCI_CHIP_RV250_Lg 0x4C67
-#define PCI_CHIP_RAGE128MF 0x4D46
-#define PCI_CHIP_RAGE128ML 0x4D4C
-#define PCI_CHIP_R300_ND 0x4E44
-#define PCI_CHIP_R300_NE 0x4E45
-#define PCI_CHIP_R300_NF 0x4E46
-#define PCI_CHIP_R300_NG 0x4E47
-#define PCI_CHIP_R350_NH 0x4E48
-#define PCI_CHIP_R350_NI 0x4E49
-#define PCI_CHIP_R360_NJ 0x4E4A
-#define PCI_CHIP_R350_NK 0x4E4B
-#define PCI_CHIP_RV350_NP 0x4E50
-#define PCI_CHIP_RV350_NQ 0x4E51
-#define PCI_CHIP_RV350_NR 0x4E52
-#define PCI_CHIP_RV350_NS 0x4E53
-#define PCI_CHIP_RV350_NT 0x4E54
-#define PCI_CHIP_RV350_NV 0x4E56
-#define PCI_CHIP_RAGE128PA 0x5041
-#define PCI_CHIP_RAGE128PB 0x5042
-#define PCI_CHIP_RAGE128PC 0x5043
-#define PCI_CHIP_RAGE128PD 0x5044
-#define PCI_CHIP_RAGE128PE 0x5045
-#define PCI_CHIP_RAGE128PF 0x5046
-#define PCI_CHIP_RAGE128PG 0x5047
-#define PCI_CHIP_RAGE128PH 0x5048
-#define PCI_CHIP_RAGE128PI 0x5049
-#define PCI_CHIP_RAGE128PJ 0x504A
-#define PCI_CHIP_RAGE128PK 0x504B
-#define PCI_CHIP_RAGE128PL 0x504C
-#define PCI_CHIP_RAGE128PM 0x504D
-#define PCI_CHIP_RAGE128PN 0x504E
-#define PCI_CHIP_RAGE128PO 0x504F
-#define PCI_CHIP_RAGE128PP 0x5050
-#define PCI_CHIP_RAGE128PQ 0x5051
-#define PCI_CHIP_RAGE128PR 0x5052
-#define PCI_CHIP_RAGE128PS 0x5053
-#define PCI_CHIP_RAGE128PT 0x5054
-#define PCI_CHIP_RAGE128PU 0x5055
-#define PCI_CHIP_RAGE128PV 0x5056
-#define PCI_CHIP_RAGE128PW 0x5057
-#define PCI_CHIP_RAGE128PX 0x5058
-#define PCI_CHIP_RADEON_QD 0x5144
-#define PCI_CHIP_RADEON_QE 0x5145
-#define PCI_CHIP_RADEON_QF 0x5146
-#define PCI_CHIP_RADEON_QG 0x5147
-#define PCI_CHIP_R200_QH 0x5148
-#define PCI_CHIP_R200_QL 0x514C
-#define PCI_CHIP_R200_QM 0x514D
-#define PCI_CHIP_RV200_QW 0x5157
-#define PCI_CHIP_RV200_QX 0x5158
-#define PCI_CHIP_RV100_QY 0x5159
-#define PCI_CHIP_RV100_QZ 0x515A
-#define PCI_CHIP_RN50_515E 0x515E
-#define PCI_CHIP_RAGE128RE 0x5245
-#define PCI_CHIP_RAGE128RF 0x5246
-#define PCI_CHIP_RAGE128RG 0x5247
-#define PCI_CHIP_RAGE128RK 0x524B
-#define PCI_CHIP_RAGE128RL 0x524C
-#define PCI_CHIP_RAGE128SE 0x5345
-#define PCI_CHIP_RAGE128SF 0x5346
-#define PCI_CHIP_RAGE128SG 0x5347
-#define PCI_CHIP_RAGE128SH 0x5348
-#define PCI_CHIP_RAGE128SK 0x534B
-#define PCI_CHIP_RAGE128SL 0x534C
-#define PCI_CHIP_RAGE128SM 0x534D
-#define PCI_CHIP_RAGE128SN 0x534E
-#define PCI_CHIP_RAGE128TF 0x5446
-#define PCI_CHIP_RAGE128TL 0x544C
-#define PCI_CHIP_RAGE128TR 0x5452
-#define PCI_CHIP_RAGE128TS 0x5453
-#define PCI_CHIP_RAGE128TT 0x5454
-#define PCI_CHIP_RAGE128TU 0x5455
-#define PCI_CHIP_RV370_5460 0x5460
-#define PCI_CHIP_RV370_5462 0x5462
-#define PCI_CHIP_RV370_5464 0x5464
-#define PCI_CHIP_R423_UH 0x5548
-#define PCI_CHIP_R423_UI 0x5549
-#define PCI_CHIP_R423_UJ 0x554A
-#define PCI_CHIP_R423_UK 0x554B
-#define PCI_CHIP_R430_554C 0x554C
-#define PCI_CHIP_R430_554D 0x554D
-#define PCI_CHIP_R430_554E 0x554E
-#define PCI_CHIP_R430_554F 0x554F
-#define PCI_CHIP_R423_5550 0x5550
-#define PCI_CHIP_R423_UQ 0x5551
-#define PCI_CHIP_R423_UR 0x5552
-#define PCI_CHIP_R423_UT 0x5554
-#define PCI_CHIP_RV410_564A 0x564A
-#define PCI_CHIP_RV410_564B 0x564B
-#define PCI_CHIP_RV410_564F 0x564F
-#define PCI_CHIP_RV410_5652 0x5652
-#define PCI_CHIP_RV410_5653 0x5653
-#define PCI_CHIP_MACH64VT 0x5654
-#define PCI_CHIP_MACH64VU 0x5655
-#define PCI_CHIP_MACH64VV 0x5656
-#define PCI_CHIP_RS300_5834 0x5834
-#define PCI_CHIP_RS300_5835 0x5835
-#define PCI_CHIP_RS480_5954 0x5954
-#define PCI_CHIP_RS480_5955 0x5955
-#define PCI_CHIP_RV280_5960 0x5960
-#define PCI_CHIP_RV280_5961 0x5961
-#define PCI_CHIP_RV280_5962 0x5962
-#define PCI_CHIP_RV280_5964 0x5964
-#define PCI_CHIP_RV280_5965 0x5965
-#define PCI_CHIP_RN50_5969 0x5969
-#define PCI_CHIP_RS482_5974 0x5974
-#define PCI_CHIP_RS485_5975 0x5975
-#define PCI_CHIP_RS400_5A41 0x5A41
-#define PCI_CHIP_RS400_5A42 0x5A42
-#define PCI_CHIP_RC410_5A61 0x5A61
-#define PCI_CHIP_RC410_5A62 0x5A62
-#define PCI_CHIP_RV370_5B60 0x5B60
-#define PCI_CHIP_RV370_5B62 0x5B62
-#define PCI_CHIP_RV370_5B63 0x5B63
-#define PCI_CHIP_RV370_5657 0x5657
-#define PCI_CHIP_RV370_5B64 0x5B64
-#define PCI_CHIP_RV370_5B65 0x5B65
-#define PCI_CHIP_RV280_5C61 0x5C61
-#define PCI_CHIP_RV280_5C63 0x5C63
-#define PCI_CHIP_R430_5D48 0x5D48
-#define PCI_CHIP_R430_5D49 0x5D49
-#define PCI_CHIP_R430_5D4A 0x5D4A
-#define PCI_CHIP_R480_5D4C 0x5D4C
-#define PCI_CHIP_R480_5D4D 0x5D4D
-#define PCI_CHIP_R480_5D4E 0x5D4E
-#define PCI_CHIP_R480_5D4F 0x5D4F
-#define PCI_CHIP_R480_5D50 0x5D50
-#define PCI_CHIP_R480_5D52 0x5D52
-#define PCI_CHIP_R423_5D57 0x5D57
-#define PCI_CHIP_RV410_5E48 0x5E48
-#define PCI_CHIP_RV410_5E4A 0x5E4A
-#define PCI_CHIP_RV410_5E4B 0x5E4B
-#define PCI_CHIP_RV410_5E4C 0x5E4C
-#define PCI_CHIP_RV410_5E4D 0x5E4D
-#define PCI_CHIP_RV410_5E4F 0x5E4F
-#define PCI_CHIP_R520_7100 0x7100
-#define PCI_CHIP_R520_7101 0x7101
-#define PCI_CHIP_R520_7102 0x7102
-#define PCI_CHIP_R520_7103 0x7103
-#define PCI_CHIP_R520_7104 0x7104
-#define PCI_CHIP_R520_7105 0x7105
-#define PCI_CHIP_R520_7106 0x7106
-#define PCI_CHIP_R520_7108 0x7108
-#define PCI_CHIP_R520_7109 0x7109
-#define PCI_CHIP_R520_710A 0x710A
-#define PCI_CHIP_R520_710B 0x710B
-#define PCI_CHIP_R520_710C 0x710C
-#define PCI_CHIP_R520_710E 0x710E
-#define PCI_CHIP_R520_710F 0x710F
-#define PCI_CHIP_RV515_7140 0x7140
-#define PCI_CHIP_RV515_7141 0x7141
-#define PCI_CHIP_RV515_7142 0x7142
-#define PCI_CHIP_RV515_7143 0x7143
-#define PCI_CHIP_RV515_7144 0x7144
-#define PCI_CHIP_RV515_7145 0x7145
-#define PCI_CHIP_RV515_7146 0x7146
-#define PCI_CHIP_RV515_7147 0x7147
-#define PCI_CHIP_RV515_7149 0x7149
-#define PCI_CHIP_RV515_714A 0x714A
-#define PCI_CHIP_RV515_714B 0x714B
-#define PCI_CHIP_RV515_714C 0x714C
-#define PCI_CHIP_RV515_714D 0x714D
-#define PCI_CHIP_RV515_714E 0x714E
-#define PCI_CHIP_RV515_714F 0x714F
-#define PCI_CHIP_RV515_7151 0x7151
-#define PCI_CHIP_RV515_7152 0x7152
-#define PCI_CHIP_RV515_7153 0x7153
-#define PCI_CHIP_RV515_715E 0x715E
-#define PCI_CHIP_RV515_715F 0x715F
-#define PCI_CHIP_RV515_7180 0x7180
-#define PCI_CHIP_RV515_7181 0x7181
-#define PCI_CHIP_RV515_7183 0x7183
-#define PCI_CHIP_RV515_7186 0x7186
-#define PCI_CHIP_RV515_7187 0x7187
-#define PCI_CHIP_RV515_7188 0x7188
-#define PCI_CHIP_RV515_718A 0x718A
-#define PCI_CHIP_RV515_718B 0x718B
-#define PCI_CHIP_RV515_718C 0x718C
-#define PCI_CHIP_RV515_718D 0x718D
-#define PCI_CHIP_RV515_718F 0x718F
-#define PCI_CHIP_RV515_7193 0x7193
-#define PCI_CHIP_RV515_7196 0x7196
-#define PCI_CHIP_RV515_719B 0x719B
-#define PCI_CHIP_RV515_719F 0x719F
-#define PCI_CHIP_RV530_71C0 0x71C0
-#define PCI_CHIP_RV530_71C1 0x71C1
-#define PCI_CHIP_RV530_71C2 0x71C2
-#define PCI_CHIP_RV530_71C3 0x71C3
-#define PCI_CHIP_RV530_71C4 0x71C4
-#define PCI_CHIP_RV530_71C5 0x71C5
-#define PCI_CHIP_RV530_71C6 0x71C6
-#define PCI_CHIP_RV530_71C7 0x71C7
-#define PCI_CHIP_RV530_71CD 0x71CD
-#define PCI_CHIP_RV530_71CE 0x71CE
-#define PCI_CHIP_RV530_71D2 0x71D2
-#define PCI_CHIP_RV530_71D4 0x71D4
-#define PCI_CHIP_RV530_71D5 0x71D5
-#define PCI_CHIP_RV530_71D6 0x71D6
-#define PCI_CHIP_RV530_71DA 0x71DA
-#define PCI_CHIP_RV530_71DE 0x71DE
-#define PCI_CHIP_RV530_7200 0x7200
-#define PCI_CHIP_RV530_7210 0x7210
-#define PCI_CHIP_RV530_7211 0x7211
-#define PCI_CHIP_R580_7240 0x7240
-#define PCI_CHIP_R580_7243 0x7243
-#define PCI_CHIP_R580_7244 0x7244
-#define PCI_CHIP_R580_7245 0x7245
-#define PCI_CHIP_R580_7246 0x7246
-#define PCI_CHIP_R580_7247 0x7247
-#define PCI_CHIP_R580_7248 0x7248
-#define PCI_CHIP_R580_7249 0x7249
-#define PCI_CHIP_R580_724A 0x724A
-#define PCI_CHIP_R580_724B 0x724B
-#define PCI_CHIP_R580_724C 0x724C
-#define PCI_CHIP_R580_724D 0x724D
-#define PCI_CHIP_R580_724E 0x724E
-#define PCI_CHIP_R580_724F 0x724F
-#define PCI_CHIP_RV570_7280 0x7280
-#define PCI_CHIP_RV560_7281 0x7281
-#define PCI_CHIP_RV560_7283 0x7283
-#define PCI_CHIP_R580_7284 0x7284
-#define PCI_CHIP_RV560_7287 0x7287
-#define PCI_CHIP_RV570_7288 0x7288
-#define PCI_CHIP_RV570_7289 0x7289
-#define PCI_CHIP_RV570_728B 0x728B
-#define PCI_CHIP_RV570_728C 0x728C
-#define PCI_CHIP_RV560_7290 0x7290
-#define PCI_CHIP_RV560_7291 0x7291
-#define PCI_CHIP_RV560_7293 0x7293
-#define PCI_CHIP_RV560_7297 0x7297
-#define PCI_CHIP_RS350_7834 0x7834
-#define PCI_CHIP_RS350_7835 0x7835
-#define PCI_CHIP_RS690_791E 0x791E
-#define PCI_CHIP_RS690_791F 0x791F
-#define PCI_CHIP_RS740_796C 0x796C
-#define PCI_CHIP_RS740_796D 0x796D
-#define PCI_CHIP_RS740_796E 0x796E
-#define PCI_CHIP_RS740_796F 0x796F
-#define PCI_CHIP_R600_9400 0x9400
-#define PCI_CHIP_R600_9401 0x9401
-#define PCI_CHIP_R600_9402 0x9402
-#define PCI_CHIP_R600_9403 0x9403
-#define PCI_CHIP_R600_9405 0x9405
-#define PCI_CHIP_R600_940A 0x940A
-#define PCI_CHIP_R600_940B 0x940B
-#define PCI_CHIP_R600_940F 0x940F
-#define PCI_CHIP_RV610_94C0 0x94C0
-#define PCI_CHIP_RV610_94C1 0x94C1
-#define PCI_CHIP_RV610_94C3 0x94C3
-#define PCI_CHIP_RV610_94C4 0x94C4
-#define PCI_CHIP_RV610_94C5 0x94C5
-#define PCI_CHIP_RV610_94C6 0x94C6
-#define PCI_CHIP_RV610_94C7 0x94C7
-#define PCI_CHIP_RV610_94C8 0x94C8
-#define PCI_CHIP_RV610_94C9 0x94C9
-#define PCI_CHIP_RV610_94CB 0x94CB
-#define PCI_CHIP_RV610_94CC 0x94CC
-#define PCI_CHIP_RV670_9500 0x9500
-#define PCI_CHIP_RV670_9501 0x9501
-#define PCI_CHIP_RV670_9505 0x9505
-#define PCI_CHIP_RV670_9507 0x9507
-#define PCI_CHIP_RV670_950F 0x950F
-#define PCI_CHIP_RV670_9511 0x9511
-#define PCI_CHIP_RV630_9580 0x9580
-#define PCI_CHIP_RV630_9581 0x9581
-#define PCI_CHIP_RV630_9583 0x9583
-#define PCI_CHIP_RV630_9586 0x9586
-#define PCI_CHIP_RV630_9587 0x9587
-#define PCI_CHIP_RV630_9588 0x9588
-#define PCI_CHIP_RV630_9589 0x9589
-#define PCI_CHIP_RV630_958A 0x958A
-#define PCI_CHIP_RV630_958B 0x958B
-#define PCI_CHIP_RV630_958C 0x958C
-#define PCI_CHIP_RV630_958D 0x958D
-#define PCI_CHIP_RV630_958E 0x958E
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
deleted file mode 100644
index 5a2191a..0000000
--- a/src/pcidb/ati_pciids.csv
+++ /dev/null
@@ -1,359 +0,0 @@
-"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name"
-"0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)"
-"0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)"
-"0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)"
-"0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)"
-"0x3E54","RV380_3E54","RV380",,,,,,"ATI FireGL V3200 (RV380) 3E54 (PCIE)"
-"0x4136","RS100_4136","RS100",,1,,,1,"ATI Radeon IGP320 (A3) 4136"
-"0x4137","RS200_4137","RS200",,1,,,1,"ATI Radeon IGP330/340/350 (A4) 4137"
-"0x4144","R300_AD","R300",,,,,,"ATI Radeon 9500 AD (AGP)"
-"0x4145","R300_AE","R300",,,,,,"ATI Radeon 9500 AE (AGP)"
-"0x4146","R300_AF","R300",,,,,,"ATI Radeon 9600TX AF (AGP)"
-"0x4147","R300_AG","R300",,,,,,"ATI FireGL Z1 AG (AGP)"
-"0x4148","R350_AH","R350",,,,,,"ATI Radeon 9800SE AH (AGP)"
-"0x4149","R350_AI","R350",,,,,,"ATI Radeon 9800 AI (AGP)"
-"0x414A","R350_AJ","R350",,,,,,"ATI Radeon 9800 AJ (AGP)"
-"0x414B","R350_AK","R350",,,,,,"ATI FireGL X2 AK (AGP)"
-"0x4150","RV350_AP","RV350",,,,,,"ATI Radeon 9600 AP (AGP)"
-"0x4151","RV350_AQ","RV350",,,,,,"ATI Radeon 9600SE AQ (AGP)"
-"0x4152","RV360_AR","RV350",,,,,,"ATI Radeon 9600XT AR (AGP)"
-"0x4153","RV350_AS","RV350",,,,,,"ATI Radeon 9600 AS (AGP)"
-"0x4154","RV350_AT","RV350",,,,,,"ATI FireGL T2 AT (AGP)"
-"0x4155","RV350_4155","RV350",,,,,,"ATI Radeon 9650"
-"0x4156","RV350_AV","RV350",,,,,,"ATI FireGL RV360 AV (AGP)"
-"0x4158","MACH32","MACH32",,,,,,
-"0x4237","RS250_4237","RS200",,1,,,1,"ATI Radeon 7000 IGP (A4+) 4237"
-"0x4242","R200_BB","R200",,,,1,,"ATI Radeon 8500 AIW BB (AGP)"
-"0x4243","R200_BC","R200",,,,1,,"ATI Radeon 8500 AIW BC (AGP)"
-"0x4336","RS100_4336","RS100",1,1,,,1,"ATI Radeon IGP320M (U1) 4336"
-"0x4337","RS200_4337","RS200",1,1,,,1,"ATI Radeon IGP330M/340M/350M (U2) 4337"
-"0x4354","MACH64CT","MACH64",,,,,,
-"0x4358","MACH64CX","MACH64",,,,,,
-"0x4437","RS250_4437","RS200",1,1,,,1,"ATI Radeon Mobility 7000 IGP 4437"
-"0x4554","MACH64ET","MACH64",,,,,,
-"0x4742","MACH64GB","MACH64",,,,,,
-"0x4744","MACH64GD","MACH64",,,,,,
-"0x4749","MACH64GI","MACH64",,,,,,
-"0x474C","MACH64GL","MACH64",,,,,,
-"0x474D","MACH64GM","MACH64",,,,,,
-"0x474E","MACH64GN","MACH64",,,,,,
-"0x474F","MACH64GO","MACH64",,,,,,
-"0x4750","MACH64GP","MACH64",,,,,,
-"0x4751","MACH64GQ","MACH64",,,,,,
-"0x4752","MACH64GR","MACH64",,,,,,
-"0x4753","MACH64GS","MACH64",,,,,,
-"0x4754","MACH64GT","MACH64",,,,,,
-"0x4755","MACH64GU","MACH64",,,,,,
-"0x4756","MACH64GV","MACH64",,,,,,
-"0x4757","MACH64GW","MACH64",,,,,,
-"0x4758","MACH64GX","MACH64",,,,,,
-"0x4759","MACH64GY","MACH64",,,,,,
-"0x475A","MACH64GZ","MACH64",,,,,,
-"0x4966","RV250_If","RV250",,,,,,"ATI Radeon 9000/PRO If (AGP/PCI)"
-"0x4967","RV250_Ig","RV250",,,,,,"ATI Radeon 9000 Ig (AGP/PCI)"
-"0x4A48","R420_JH","R420",,,,,,"ATI Radeon X800 (R420) JH (AGP)"
-"0x4A49","R420_JI","R420",,,,,,"ATI Radeon X800PRO (R420) JI (AGP)"
-"0x4A4A","R420_JJ","R420",,,,,,"ATI Radeon X800SE (R420) JJ (AGP)"
-"0x4A4B","R420_JK","R420",,,,,,"ATI Radeon X800 (R420) JK (AGP)"
-"0x4A4C","R420_JL","R420",,,,,,"ATI Radeon X800 (R420) JL (AGP)"
-"0x4A4D","R420_JM","R420",,,,,,"ATI FireGL X3 (R420) JM (AGP)"
-"0x4A4E","R420_JN","R420",1,,,,,"ATI Radeon Mobility 9800 (M18) JN (AGP)"
-"0x4A4F","R420_4A4F","R420",,,,,,"ATI Radeon X800 SE (R420) (AGP)"
-"0x4A50","R420_JP","R420",,,,,,"ATI Radeon X800XT (R420) JP (AGP)"
-"0x4B49","R481_4B49","R420",,,,,,"ATI Radeon X850 XT (R480) (AGP)"
-"0x4B4A","R481_4B4A","R420",,,,,,"ATI Radeon X850 SE (R480) (AGP)"
-"0x4B4B","R481_4B4B","R420",,,,,,"ATI Radeon X850 PRO (R480) (AGP)"
-"0x4B4C","R481_4B4C","R420",,,,,,"ATI Radeon X850 XT PE (R480) (AGP)"
-"0x4C42","MACH64LB","MACH64",,,,,,
-"0x4C44","MACH64LD","MACH64",,,,,,
-"0x4C45","RAGE128LE","R128",,,,,,
-"0x4C46","RAGE128LF","R128",,,,,,
-"0x4C47","MACH64LG","MACH64",,,,,,
-"0x4C49","MACH64LI","MACH64",,,,,,
-"0x4C4D","MACH64LM","MACH64",,,,,,
-"0x4C4E","MACH64LN","MACH64",,,,,,
-"0x4C50","MACH64LP","MACH64",,,,,,
-"0x4C51","MACH64LQ","MACH64",,,,,,
-"0x4C52","MACH64LR","MACH64",,,,,,
-"0x4C53","MACH64LS","MACH64",,,,,,
-"0x4C57","RADEON_LW","RV200",1,,,,,"ATI Radeon Mobility M7 LW (AGP)"
-"0x4C58","RADEON_LX","RV200",1,,,,,"ATI Mobility FireGL 7800 M7 LX (AGP)"
-"0x4C59","RADEON_LY","RV100",1,,,,,"ATI Radeon Mobility M6 LY (AGP)"
-"0x4C5A","RADEON_LZ","RV100",1,,,,,"ATI Radeon Mobility M6 LZ (AGP)"
-"0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9) Ld (AGP)"
-"0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lf (AGP)"
-"0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lg (AGP)"
-"0x4D46","RAGE128MF","R128",,,,,,
-"0x4D4C","RAGE128ML","R128",,,,,,
-"0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro ND (AGP)"
-"0x4E45","R300_NE","R300",,,,,,"ATI Radeon 9700/9500Pro NE (AGP)"
-"0x4E46","R300_NF","R300",,,,,,"ATI Radeon 9600TX NF (AGP)"
-"0x4E47","R300_NG","R300",,,,,,"ATI FireGL X1 NG (AGP)"
-"0x4E48","R350_NH","R350",,,,,,"ATI Radeon 9800PRO NH (AGP)"
-"0x4E49","R350_NI","R350",,,,,,"ATI Radeon 9800 NI (AGP)"
-"0x4E4A","R360_NJ","R350",,,,,,"ATI FireGL X2 NK (AGP)"
-"0x4E4B","R350_NK","R350",,,,,,"ATI Radeon 9800XT NJ (AGP)"
-"0x4E50","RV350_NP","RV350",1,,,,,"ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)"
-"0x4E51","RV350_NQ","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NQ (AGP)"
-"0x4E52","RV350_NR","RV350",1,,,,,"ATI Radeon Mobility 9600 (M11) NR (AGP)"
-"0x4E53","RV350_NS","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NS (AGP)"
-"0x4E54","RV350_NT","RV350",1,,,,,"ATI FireGL Mobility T2 (M10) NT (AGP)"
-"0x4E56","RV350_NV","RV350",1,,,,,"ATI FireGL Mobility T2e (M11) NV (AGP)"
-"0x5041","RAGE128PA","R128",,,,,,
-"0x5042","RAGE128PB","R128",,,,,,
-"0x5043","RAGE128PC","R128",,,,,,
-"0x5044","RAGE128PD","R128",,,,,,
-"0x5045","RAGE128PE","R128",,,,,,
-"0x5046","RAGE128PF","R128",,,,,,
-"0x5047","RAGE128PG","R128",,,,,,
-"0x5048","RAGE128PH","R128",,,,,,
-"0x5049","RAGE128PI","R128",,,,,,
-"0x504A","RAGE128PJ","R128",,,,,,
-"0x504B","RAGE128PK","R128",,,,,,
-"0x504C","RAGE128PL","R128",,,,,,
-"0x504D","RAGE128PM","R128",,,,,,
-"0x504E","RAGE128PN","R128",,,,,,
-"0x504F","RAGE128PO","R128",,,,,,
-"0x5050","RAGE128PP","R128",,,,,,
-"0x5051","RAGE128PQ","R128",,,,,,
-"0x5052","RAGE128PR","R128",,,,,,
-"0x5053","RAGE128PS","R128",,,,,,
-"0x5054","RAGE128PT","R128",,,,,,
-"0x5055","RAGE128PU","R128",,,,,,
-"0x5056","RAGE128PV","R128",,,,,,
-"0x5057","RAGE128PW","R128",,,,,,
-"0x5058","RAGE128PX","R128",,,,,,
-"0x5144","RADEON_QD","RADEON",,,1,1,,"ATI Radeon QD (AGP)"
-"0x5145","RADEON_QE","RADEON",,,1,1,,"ATI Radeon QE (AGP)"
-"0x5146","RADEON_QF","RADEON",,,1,1,,"ATI Radeon QF (AGP)"
-"0x5147","RADEON_QG","RADEON",,,1,1,,"ATI Radeon QG (AGP)"
-"0x5148","R200_QH","R200",,,,1,,"ATI FireGL 8700/8800 QH (AGP)"
-"0x514C","R200_QL","R200",,,,1,,"ATI Radeon 8500 QL (AGP)"
-"0x514D","R200_QM","R200",,,,1,,"ATI Radeon 9100 QM (AGP)"
-"0x5157","RV200_QW","RV200",,,,,,"ATI Radeon 7500 QW (AGP/PCI)"
-"0x5158","RV200_QX","RV200",,,,,,"ATI Radeon 7500 QX (AGP/PCI)"
-"0x5159","RV100_QY","RV100",,,,,,"ATI Radeon VE/7000 QY (AGP/PCI)"
-"0x515A","RV100_QZ","RV100",,,,,,"ATI Radeon VE/7000 QZ (AGP/PCI)"
-"0x515E","RN50_515E","RV100",,,1,,,"ATI ES1000 515E (PCI)"
-"0x5245","RAGE128RE","R128",,,,,,
-"0x5246","RAGE128RF","R128",,,,,,
-"0x5247","RAGE128RG","R128",,,,,,
-"0x524B","RAGE128RK","R128",,,,,,
-"0x524C","RAGE128RL","R128",,,,,,
-"0x5345","RAGE128SE","R128",,,,,,
-"0x5346","RAGE128SF","R128",,,,,,
-"0x5347","RAGE128SG","R128",,,,,,
-"0x5348","RAGE128SH","R128",,,,,,
-"0x534B","RAGE128SK","R128",,,,,,
-"0x534C","RAGE128SL","R128",,,,,,
-"0x534D","RAGE128SM","R128",,,,,,
-"0x534E","RAGE128SN","R128",,,,,,
-"0x5446","RAGE128TF","R128",,,,,,
-"0x544C","RAGE128TL","R128",,,,,,
-"0x5452","RAGE128TR","R128",,,,,,
-"0x5453","RAGE128TS","R128",,,,,,
-"0x5454","RAGE128TT","R128",,,,,,
-"0x5455","RAGE128TU","R128",,,,,,
-"0x5460","RV370_5460","RV380",1,,,,,"ATI Radeon Mobility X300 (M22) 5460 (PCIE)"
-"0x5462","RV370_5462","RV380",1,,,,,"ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)"
-"0x5464","RV370_5464","RV380",1,,,,,"ATI FireGL M22 GL 5464 (PCIE)"
-"0x5548","R423_UH","R420",,,,,,"ATI Radeon X800 (R423) UH (PCIE)"
-"0x5549","R423_UI","R420",,,,,,"ATI Radeon X800PRO (R423) UI (PCIE)"
-"0x554A","R423_UJ","R420",,,,,,"ATI Radeon X800LE (R423) UJ (PCIE)"
-"0x554B","R423_UK","R420",,,,,,"ATI Radeon X800SE (R423) UK (PCIE)"
-"0x554C","R430_554C","R420",,,,,,"ATI Radeon X800 XTP (R430) (PCIE)"
-"0x554D","R430_554D","R420",,,,,,"ATI Radeon X800 XL (R430) (PCIE)"
-"0x554E","R430_554E","R420",,,,,,"ATI Radeon X800 SE (R430) (PCIE)"
-"0x554F","R430_554F","R420",,,,,,"ATI Radeon X800 (R430) (PCIE)"
-"0x5550","R423_5550","R420",,,,,,"ATI FireGL V7100 (R423) (PCIE)"
-"0x5551","R423_UQ","R420",,,,,,"ATI FireGL V5100 (R423) UQ (PCIE)"
-"0x5552","R423_UR","R420",,,,,,"ATI FireGL unknown (R423) UR (PCIE)"
-"0x5554","R423_UT","R420",,,,,,"ATI FireGL unknown (R423) UT (PCIE)"
-"0x564A","RV410_564A","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)"
-"0x564B","RV410_564B","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)"
-"0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)"
-"0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)"
-"0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)"
-"0x5654","MACH64VT","MACH64",,,,,,
-"0x5655","MACH64VU","MACH64",,,,,,
-"0x5656","MACH64VV","MACH64",,,,,,
-"0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834"
-"0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835"
-"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)"
-"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)"
-"0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)"
-"0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)"
-"0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)"
-"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)"
-"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)"
-"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)"
-"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)"
-"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)"
-"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)"
-"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)"
-"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)"
-"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)"
-"0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)"
-"0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)"
-"0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)"
-"0x5657","RV370_5657","RV380",,,,,,"ATI Radeon X550XTX (RV370) 5657 (PCIE)"
-"0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)"
-"0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)"
-"0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)"
-"0x5C63","RV280_5C63","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)"
-"0x5D48","R430_5D48","R420",1,,,,,"ATI Mobility Radeon X800 XT (M28) (PCIE)"
-"0x5D49","R430_5D49","R420",1,,,,,"ATI Mobility FireGL V5100 (M28) (PCIE)"
-"0x5D4A","R430_5D4A","R420",1,,,,,"ATI Mobility Radeon X800 (M28) (PCIE)"
-"0x5D4C","R480_5D4C","R420",,,,,,"ATI Radeon X850 5D4C (PCIE)"
-"0x5D4D","R480_5D4D","R420",,,,,,"ATI Radeon X850 XT PE (R480) (PCIE)"
-"0x5D4E","R480_5D4E","R420",,,,,,"ATI Radeon X850 SE (R480) (PCIE)"
-"0x5D4F","R480_5D4F","R420",,,,,,"ATI Radeon X850 PRO (R480) (PCIE)"
-"0x5D50","R480_5D50","R420",,,,,,"ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)"
-"0x5D52","R480_5D52","R420",,,,,,"ATI Radeon X850 XT (R480) (PCIE)"
-"0x5D57","R423_5D57","R420",,,,,,"ATI Radeon X800XT (R423) 5D57 (PCIE)"
-"0x5E48","RV410_5E48","RV410",,,,,,"ATI FireGL V5000 (RV410) (PCIE)"
-"0x5E4A","RV410_5E4A","RV410",,,,,,"ATI Radeon X700 XT (RV410) (PCIE)"
-"0x5E4B","RV410_5E4B","RV410",,,,,,"ATI Radeon X700 PRO (RV410) (PCIE)"
-"0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)"
-"0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)"
-"0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)"
-"0x7100","R520_7100","R520",,,,,,"ATI Radeon X1800"
-"0x7101","R520_7101","R520",1,,,,,"ATI Mobility Radeon X1800 XT"
-"0x7102","R520_7102","R520",1,,,,,"ATI Mobility Radeon X1800"
-"0x7103","R520_7103","R520",1,,,,,"ATI Mobility FireGL V7200"
-"0x7104","R520_7104","R520",,,,,,"ATI FireGL V7200"
-"0x7105","R520_7105","R520",,,,,,"ATI FireGL V5300"
-"0x7106","R520_7106","R520",1,,,,,"ATI Mobility FireGL V7100"
-"0x7108","R520_7108","R520",,,,,,"ATI Radeon X1800"
-"0x7109","R520_7109","R520",,,,,,"ATI Radeon X1800"
-"0x710A","R520_710A","R520",,,,,,"ATI Radeon X1800"
-"0x710B","R520_710B","R520",,,,,,"ATI Radeon X1800"
-"0x710C","R520_710C","R520",,,,,,"ATI Radeon X1800"
-"0x710E","R520_710E","R520",,,,,,"ATI FireGL V7300"
-"0x710F","R520_710F","R520",,,,,,"ATI FireGL V7350"
-"0x7140","RV515_7140","RV515",,,,,,"ATI Radeon X1600"
-"0x7141","RV515_7141","RV515",,,,,,"ATI RV505"
-"0x7142","RV515_7142","RV515",,,,,,"ATI Radeon X1300/X1550"
-"0x7143","RV515_7143","RV515",,,,,,"ATI Radeon X1550"
-"0x7144","RV515_7144","RV515",1,,,,,"ATI M54-GL"
-"0x7145","RV515_7145","RV515",1,,,,,"ATI Mobility Radeon X1400"
-"0x7146","RV515_7146","RV515",,,,,,"ATI Radeon X1300/X1550"
-"0x7147","RV515_7147","RV515",,,,,,"ATI Radeon X1550 64-bit"
-"0x7149","RV515_7149","RV515",1,,,,,"ATI Mobility Radeon X1300"
-"0x714A","RV515_714A","RV515",1,,,,,"ATI Mobility Radeon X1300"
-"0x714B","RV515_714B","RV515",1,,,,,"ATI Mobility Radeon X1300"
-"0x714C","RV515_714C","RV515",1,,,,,"ATI Mobility Radeon X1300"
-"0x714D","RV515_714D","RV515",,,,,,"ATI Radeon X1300"
-"0x714E","RV515_714E","RV515",,,,,,"ATI Radeon X1300"
-"0x714F","RV515_714F","RV515",,,,,,"ATI RV505"
-"0x7151","RV515_7151","RV515",,,,,,"ATI RV505"
-"0x7152","RV515_7152","RV515",,,,,,"ATI FireGL V3300"
-"0x7153","RV515_7153","RV515",,,,,,"ATI FireGL V3350"
-"0x715E","RV515_715E","RV515",,,,,,"ATI Radeon X1300"
-"0x715F","RV515_715F","RV515",,,,,,"ATI Radeon X1550 64-bit"
-"0x7180","RV515_7180","RV515",,,,,,"ATI Radeon X1300/X1550"
-"0x7181","RV515_7181","RV515",,,,,,"ATI Radeon X1600"
-"0x7183","RV515_7183","RV515",,,,,,"ATI Radeon X1300/X1550"
-"0x7186","RV515_7186","RV515",1,,,,,"ATI Mobility Radeon X1450"
-"0x7187","RV515_7187","RV515",,,,,,"ATI Radeon X1300/X1550"
-"0x7188","RV515_7188","RV515",1,,,,,"ATI Mobility Radeon X2300"
-"0x718A","RV515_718A","RV515",1,,,,,"ATI Mobility Radeon X2300"
-"0x718B","RV515_718B","RV515",1,,,,,"ATI Mobility Radeon X1350"
-"0x718C","RV515_718C","RV515",1,,,,,"ATI Mobility Radeon X1350"
-"0x718D","RV515_718D","RV515",1,,,,,"ATI Mobility Radeon X1450"
-"0x718F","RV515_718F","RV515",,,,,,"ATI Radeon X1300"
-"0x7193","RV515_7193","RV515",,,,,,"ATI Radeon X1550"
-"0x7196","RV515_7196","RV515",1,,,,,"ATI Mobility Radeon X1350"
-"0x719B","RV515_719B","RV515",,,,,,"ATI FireMV 2250"
-"0x719F","RV515_719F","RV515",,,,,,"ATI Radeon X1550 64-bit"
-"0x71C0","RV530_71C0","RV530",,,,,,"ATI Radeon X1600"
-"0x71C1","RV530_71C1","RV530",,,,,,"ATI Radeon X1650"
-"0x71C2","RV530_71C2","RV530",,,,,,"ATI Radeon X1600"
-"0x71C3","RV530_71C3","RV530",,,,,,"ATI Radeon X1600"
-"0x71C4","RV530_71C4","RV530",1,,,,,"ATI Mobility FireGL V5200"
-"0x71C5","RV530_71C5","RV530",1,,,,,"ATI Mobility Radeon X1600"
-"0x71C6","RV530_71C6","RV530",,,,,,"ATI Radeon X1650"
-"0x71C7","RV530_71C7","RV530",,,,,,"ATI Radeon X1650"
-"0x71CD","RV530_71CD","RV530",,,,,,"ATI Radeon X1600"
-"0x71CE","RV530_71CE","RV530",,,,,,"ATI Radeon X1300 XT/X1600 Pro"
-"0x71D2","RV530_71D2","RV530",,,,,,"ATI FireGL V3400"
-"0x71D4","RV530_71D4","RV530",1,,,,,"ATI Mobility FireGL V5250"
-"0x71D5","RV530_71D5","RV530",1,,,,,"ATI Mobility Radeon X1700"
-"0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT"
-"0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200"
-"0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700"
-"0x7200","RV530_7200","RV530",,,,,,"ATI Radeon X2300HD"
-"0x7210","RV530_7210","RV530",1,,,,,"ATI Mobility Radeon HD 2300"
-"0x7211","RV530_7211","RV530",1,,,,,"ATI Mobility Radeon HD 2300"
-"0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950"
-"0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900"
-"0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950"
-"0x7245","R580_7245","R580",,,,,,"ATI Radeon X1900"
-"0x7246","R580_7246","R580",,,,,,"ATI Radeon X1900"
-"0x7247","R580_7247","R580",,,,,,"ATI Radeon X1900"
-"0x7248","R580_7248","R580",,,,,,"ATI Radeon X1900"
-"0x7249","R580_7249","R580",,,,,,"ATI Radeon X1900"
-"0x724A","R580_724A","R580",,,,,,"ATI Radeon X1900"
-"0x724B","R580_724B","R580",,,,,,"ATI Radeon X1900"
-"0x724C","R580_724C","R580",,,,,,"ATI Radeon X1900"
-"0x724D","R580_724D","R580",,,,,,"ATI Radeon X1900"
-"0x724E","R580_724E","R580",,,,,,"ATI AMD Stream Processor"
-"0x724F","R580_724F","R580",,,,,,"ATI Radeon X1900"
-"0x7280","RV570_7280","RV570",,,,,,"ATI Radeon X1950"
-"0x7281","RV560_7281","RV560",,,,,,"ATI RV560"
-"0x7283","RV560_7283","RV560",,,,,,"ATI RV560"
-"0x7284","R580_7284","R580",1,,,,,"ATI Mobility Radeon X1900"
-"0x7287","RV560_7287","RV560",,,,,,"ATI RV560"
-"0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT"
-"0x7289","RV570_7289","RV570",,,,,,"ATI RV570"
-"0x728B","RV570_728B","RV570",,,,,,"ATI RV570"
-"0x728C","RV570_728C","RV570",,,,,,"ATI ATI FireGL V7400"
-"0x7290","RV560_7290","RV560",,,,,,"ATI RV560"
-"0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650"
-"0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650"
-"0x7297","RV560_7297","RV560",,,,,,"ATI RV560"
-"0x7834","RS350_7834","RS300",,1,,,1,"ATI Radeon 9100 PRO IGP 7834"
-"0x7835","RS350_7835","RS300",1,1,,,1,"ATI Radeon Mobility 9200 IGP 7835"
-"0x791E","RS690_791E","RS690",,1,,,1,"ATI Radeon X1200"
-"0x791F","RS690_791F","RS690",,1,,,1,"ATI Radeon X1200"
-"0x796C","RS740_796C","RS740",,1,,,1,"ATI RS740"
-"0x796D","RS740_796D","RS740",,1,,,1,"ATI RS740M"
-"0x796E","RS740_796E","RS740",,1,,,1,"ATI RS740"
-"0x796F","RS740_796F","RS740",,1,,,1,"ATI RS740M"
-"0x9400","R600_9400","R600",,,,,,"ATI Radeon HD 2900 XT"
-"0x9401","R600_9401","R600",,,,,,"ATI Radeon HD 2900 XT"
-"0x9402","R600_9402","R600",,,,,,"ATI Radeon HD 2900 XT"
-"0x9403","R600_9403","R600",,,,,,"ATI Radeon HD 2900 Pro"
-"0x9405","R600_9405","R600",,,,,,"ATI Radeon HD 2900 GT"
-"0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650"
-"0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600"
-"0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600"
-"0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610"
-"0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT"
-"0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro"
-"0x94C4","RV610_94C4","RV610",,,,,,"ATI ATI Radeon HD 2400 PRO AGP"
-"0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000"
-"0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610"
-"0x94C7","RV610_94C7","RV610",,,,,,"ATI ATI Radeon HD 2350"
-"0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT"
-"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400"
-"0x94CB","RV610_94CB","RV610",1,,,,,"ATI ATI RADEON E2400"
-"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610"
-"0x9500","RV670_9500","RV670",,,,,,"ATI RV670"
-"0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870"
-"0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850"
-"0x9507","RV670_9507","RV670",,,,,,"ATI RV670"
-"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2"
-"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700"
-"0x9580","RV630_9580","RV630",,,,,,"ATI RV630"
-"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600"
-"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT"
-"0x9586","RV630_9586","RV630",,,,,,"ATI ATI Radeon HD 2600 XT AGP"
-"0x9587","RV630_9587","RV630",,,,,,"ATI ATI Radeon HD 2600 Pro AGP"
-"0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT"
-"0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro"
-"0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630"
-"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini ATI Mobility Radeon HD 2600 XT"
-"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600"
-"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600"
-"0x958E","RV630_958E","RV630",,,,,,"ATI ATI Radeon HD 2600 LE"
diff --git a/src/pcidb/parse_pci_ids.pl b/src/pcidb/parse_pci_ids.pl
deleted file mode 100755
index a3a8af8..0000000
--- a/src/pcidb/parse_pci_ids.pl
+++ /dev/null
@@ -1,102 +0,0 @@
-#!/usr/bin/perl
-#
-# Copyright 2007 Red Hat Inc.
-# This crappy script written by Dave Airlie to avoid hassle of adding
-# ids in every place.
-#
-use strict;
-use warnings;
-use Text::CSV_XS;
-
-my $file = $ARGV[0];
-
-my $atioutfile = 'ati_pciids_gen.h';
-my $radeonpcichipsetfile = 'radeon_pci_chipset_gen.h';
-my $radeonpcidevicematchfile = 'radeon_pci_device_match_gen.h';
-my $radeonchipsetfile = 'radeon_chipset_gen.h';
-my $radeonchipinfofile = 'radeon_chipinfo_gen.h';
-
-my $csv = Text::CSV_XS->new();
-
-open (CSV, "<", $file) or die $!;
-
-open (ATIOUT, ">", $atioutfile) or die;
-open (PCICHIPSET, ">", $radeonpcichipsetfile) or die;
-open (PCIDEVICEMATCH, ">", $radeonpcidevicematchfile) or die;
-open (RADEONCHIPSET, ">", $radeonchipsetfile) or die;
-open (RADEONCHIPINFO, ">", $radeonchipinfofile) or die;
-
-print RADEONCHIPSET "/* This file is autogenerated please do not edit */\n";
-print RADEONCHIPSET "static SymTabRec RADEONChipsets[] = {\n";
-print PCICHIPSET "/* This file is autogenerated please do not edit */\n";
-print PCICHIPSET "PciChipsets RADEONPciChipsets[] = {\n";
-print PCIDEVICEMATCH "/* This file is autogenerated please do not edit */\n";
-print PCIDEVICEMATCH "static const struct pci_id_match radeon_device_match[] = {\n";
-print RADEONCHIPINFO "/* This file is autogenerated please do not edit */\n";
-print RADEONCHIPINFO "RADEONCardInfo RADEONCards[] = {\n";
-while (<CSV>) {
- if ($csv->parse($_)) {
- my @columns = $csv->fields();
-
- if ((substr($columns[0], 0, 1) ne "#")) {
-
- print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n";
-
- if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) {
- print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n";
-
- print PCIDEVICEMATCH " ATI_DEVICE_MATCH( PCI_CHIP_$columns[1], 0 ),\n";
-
- print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n";
-
- print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], ";
-
- if ($columns[3] eq "1") {
- print RADEONCHIPINFO "1, ";
- } else {
- print RADEONCHIPINFO "0, ";
- }
-
- if ($columns[4] eq "1") {
- print RADEONCHIPINFO "1, ";
- } else {
- print RADEONCHIPINFO "0, ";
- }
-
- if ($columns[5] eq "1") {
- print RADEONCHIPINFO "1, ";
- } else {
- print RADEONCHIPINFO "0, ";
- }
-
- if ($columns[6] eq "1") {
- print RADEONCHIPINFO "1, ";
- } else {
- print RADEONCHIPINFO "0, ";
- }
-
- if ($columns[7] eq "1") {
- print RADEONCHIPINFO "1 ";
- } else {
- print RADEONCHIPINFO "0 ";
- }
-
- print RADEONCHIPINFO "},\n";
- }
- }
- } else {
- my $err = $csv->error_input;
- print "Failed to parse line: $err";
- }
-}
-
-print RADEONCHIPINFO "};\n";
-print RADEONCHIPSET " { -1, NULL }\n};\n";
-print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n";
-print PCIDEVICEMATCH " { 0, 0, 0 }\n};\n";
-close CSV;
-close ATIOUT;
-close PCICHIPSET;
-close PCIDEVICEMATCH;
-close RADEONCHIPSET;
-close RADEONCHIPINFO;
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
deleted file mode 100644
index 420f5d8..0000000
--- a/src/radeon_chipinfo_gen.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* This file is autogenerated please do not edit */
-RADEONCardInfo RADEONCards[] = {
- { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
- { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
- { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
- { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 1 },
- { 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 },
- { 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
- { 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 },
- { 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
- { 0x4243, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
- { 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 1 },
- { 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 },
- { 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 },
- { 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
- { 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
- { 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
- { 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
- { 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
- { 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
- { 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
- { 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
- { 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
- { 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
- { 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
- { 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
- { 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
- { 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
- { 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
- { 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
- { 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
- { 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
- { 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
- { 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
- { 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
- { 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
- { 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
- { 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
- { 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
- { 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
- { 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
- { 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
- { 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
- { 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
- { 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
- { 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
- { 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
- { 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
- { 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
- { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
- { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
- { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
- { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
- { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
- { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
- { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
- { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
- { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
- { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
- { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
- { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
- { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
- { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
- { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
- { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
- { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5657, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
- { 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
- { 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
- { 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
- { 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
- { 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
- { 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
- { 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
- { 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
- { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
- { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
- { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
- { 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
- { 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
- { 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
- { 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
- { 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
- { 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
- { 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
- { 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x7200, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x7210, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x7211, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
- { 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
- { 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 },
- { 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
- { 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
- { 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
- { 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
- { 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
- { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
- { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
- { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 },
- { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 },
- { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
- { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
- { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
- { 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
- { 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
- { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
- { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
- { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
- { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
- { 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
- { 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
- { 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
- { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
- { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
- { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
- { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
- { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
- { 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
- { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
-};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
deleted file mode 100644
index e6890be..0000000
--- a/src/radeon_chipset_gen.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/* This file is autogenerated please do not edit */
-static SymTabRec RADEONChipsets[] = {
- { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" },
- { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" },
- { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" },
- { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" },
- { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" },
- { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" },
- { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" },
- { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" },
- { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" },
- { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" },
- { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" },
- { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" },
- { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" },
- { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" },
- { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" },
- { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" },
- { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" },
- { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" },
- { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" },
- { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" },
- { PCI_CHIP_RV350_4155, "ATI Radeon 9650" },
- { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" },
- { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" },
- { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" },
- { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" },
- { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" },
- { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" },
- { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" },
- { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" },
- { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" },
- { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" },
- { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" },
- { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" },
- { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" },
- { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" },
- { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" },
- { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" },
- { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" },
- { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" },
- { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" },
- { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" },
- { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" },
- { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
- { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" },
- { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" },
- { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" },
- { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" },
- { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" },
- { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" },
- { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" },
- { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" },
- { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" },
- { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" },
- { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" },
- { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" },
- { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" },
- { PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" },
- { PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" },
- { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" },
- { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" },
- { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" },
- { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" },
- { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" },
- { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" },
- { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" },
- { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" },
- { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" },
- { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" },
- { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" },
- { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" },
- { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" },
- { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" },
- { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" },
- { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" },
- { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" },
- { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" },
- { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" },
- { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" },
- { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" },
- { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" },
- { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" },
- { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" },
- { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" },
- { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" },
- { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" },
- { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" },
- { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" },
- { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" },
- { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" },
- { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" },
- { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" },
- { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
- { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
- { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" },
- { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" },
- { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" },
- { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" },
- { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" },
- { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" },
- { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" },
- { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" },
- { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" },
- { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" },
- { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" },
- { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" },
- { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" },
- { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" },
- { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" },
- { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" },
- { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" },
- { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" },
- { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" },
- { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" },
- { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" },
- { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" },
- { PCI_CHIP_RV370_5657, "ATI Radeon X550XTX (RV370) 5657 (PCIE)" },
- { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" },
- { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" },
- { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" },
- { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" },
- { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" },
- { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" },
- { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" },
- { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" },
- { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" },
- { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" },
- { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" },
- { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" },
- { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" },
- { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" },
- { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" },
- { PCI_CHIP_R520_7100, "ATI Radeon X1800" },
- { PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" },
- { PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" },
- { PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" },
- { PCI_CHIP_R520_7104, "ATI FireGL V7200" },
- { PCI_CHIP_R520_7105, "ATI FireGL V5300" },
- { PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" },
- { PCI_CHIP_R520_7108, "ATI Radeon X1800" },
- { PCI_CHIP_R520_7109, "ATI Radeon X1800" },
- { PCI_CHIP_R520_710A, "ATI Radeon X1800" },
- { PCI_CHIP_R520_710B, "ATI Radeon X1800" },
- { PCI_CHIP_R520_710C, "ATI Radeon X1800" },
- { PCI_CHIP_R520_710E, "ATI FireGL V7300" },
- { PCI_CHIP_R520_710F, "ATI FireGL V7350" },
- { PCI_CHIP_RV515_7140, "ATI Radeon X1600" },
- { PCI_CHIP_RV515_7141, "ATI RV505" },
- { PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" },
- { PCI_CHIP_RV515_7143, "ATI Radeon X1550" },
- { PCI_CHIP_RV515_7144, "ATI M54-GL" },
- { PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" },
- { PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" },
- { PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" },
- { PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" },
- { PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" },
- { PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" },
- { PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" },
- { PCI_CHIP_RV515_714D, "ATI Radeon X1300" },
- { PCI_CHIP_RV515_714E, "ATI Radeon X1300" },
- { PCI_CHIP_RV515_714F, "ATI RV505" },
- { PCI_CHIP_RV515_7151, "ATI RV505" },
- { PCI_CHIP_RV515_7152, "ATI FireGL V3300" },
- { PCI_CHIP_RV515_7153, "ATI FireGL V3350" },
- { PCI_CHIP_RV515_715E, "ATI Radeon X1300" },
- { PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" },
- { PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" },
- { PCI_CHIP_RV515_7181, "ATI Radeon X1600" },
- { PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" },
- { PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" },
- { PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" },
- { PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" },
- { PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" },
- { PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" },
- { PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" },
- { PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" },
- { PCI_CHIP_RV515_718F, "ATI Radeon X1300" },
- { PCI_CHIP_RV515_7193, "ATI Radeon X1550" },
- { PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" },
- { PCI_CHIP_RV515_719B, "ATI FireMV 2250" },
- { PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" },
- { PCI_CHIP_RV530_71C0, "ATI Radeon X1600" },
- { PCI_CHIP_RV530_71C1, "ATI Radeon X1650" },
- { PCI_CHIP_RV530_71C2, "ATI Radeon X1600" },
- { PCI_CHIP_RV530_71C3, "ATI Radeon X1600" },
- { PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" },
- { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" },
- { PCI_CHIP_RV530_71C6, "ATI Radeon X1650" },
- { PCI_CHIP_RV530_71C7, "ATI Radeon X1650" },
- { PCI_CHIP_RV530_71CD, "ATI Radeon X1600" },
- { PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" },
- { PCI_CHIP_RV530_71D2, "ATI FireGL V3400" },
- { PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" },
- { PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" },
- { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" },
- { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" },
- { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" },
- { PCI_CHIP_RV530_7200, "ATI Radeon X2300HD" },
- { PCI_CHIP_RV530_7210, "ATI Mobility Radeon HD 2300" },
- { PCI_CHIP_RV530_7211, "ATI Mobility Radeon HD 2300" },
- { PCI_CHIP_R580_7240, "ATI Radeon X1950" },
- { PCI_CHIP_R580_7243, "ATI Radeon X1900" },
- { PCI_CHIP_R580_7244, "ATI Radeon X1950" },
- { PCI_CHIP_R580_7245, "ATI Radeon X1900" },
- { PCI_CHIP_R580_7246, "ATI Radeon X1900" },
- { PCI_CHIP_R580_7247, "ATI Radeon X1900" },
- { PCI_CHIP_R580_7248, "ATI Radeon X1900" },
- { PCI_CHIP_R580_7249, "ATI Radeon X1900" },
- { PCI_CHIP_R580_724A, "ATI Radeon X1900" },
- { PCI_CHIP_R580_724B, "ATI Radeon X1900" },
- { PCI_CHIP_R580_724C, "ATI Radeon X1900" },
- { PCI_CHIP_R580_724D, "ATI Radeon X1900" },
- { PCI_CHIP_R580_724E, "ATI AMD Stream Processor" },
- { PCI_CHIP_R580_724F, "ATI Radeon X1900" },
- { PCI_CHIP_RV570_7280, "ATI Radeon X1950" },
- { PCI_CHIP_RV560_7281, "ATI RV560" },
- { PCI_CHIP_RV560_7283, "ATI RV560" },
- { PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" },
- { PCI_CHIP_RV560_7287, "ATI RV560" },
- { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" },
- { PCI_CHIP_RV570_7289, "ATI RV570" },
- { PCI_CHIP_RV570_728B, "ATI RV570" },
- { PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" },
- { PCI_CHIP_RV560_7290, "ATI RV560" },
- { PCI_CHIP_RV560_7291, "ATI Radeon X1650" },
- { PCI_CHIP_RV560_7293, "ATI Radeon X1650" },
- { PCI_CHIP_RV560_7297, "ATI RV560" },
- { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" },
- { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" },
- { PCI_CHIP_RS690_791E, "ATI Radeon X1200" },
- { PCI_CHIP_RS690_791F, "ATI Radeon X1200" },
- { PCI_CHIP_RS740_796C, "ATI RS740" },
- { PCI_CHIP_RS740_796D, "ATI RS740M" },
- { PCI_CHIP_RS740_796E, "ATI RS740" },
- { PCI_CHIP_RS740_796F, "ATI RS740M" },
- { PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" },
- { PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" },
- { PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" },
- { PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" },
- { PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" },
- { PCI_CHIP_R600_940A, "ATI FireGL V8650" },
- { PCI_CHIP_R600_940B, "ATI FireGL V8600" },
- { PCI_CHIP_R600_940F, "ATI FireGL V7600" },
- { PCI_CHIP_RV610_94C0, "ATI RV610" },
- { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" },
- { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" },
- { PCI_CHIP_RV610_94C4, "ATI ATI Radeon HD 2400 PRO AGP" },
- { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" },
- { PCI_CHIP_RV610_94C6, "ATI RV610" },
- { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" },
- { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" },
- { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" },
- { PCI_CHIP_RV610_94CB, "ATI ATI RADEON E2400" },
- { PCI_CHIP_RV610_94CC, "ATI RV610" },
- { PCI_CHIP_RV670_9500, "ATI RV670" },
- { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" },
- { PCI_CHIP_RV670_9505, "ATI Radeon HD3850" },
- { PCI_CHIP_RV670_9507, "ATI RV670" },
- { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" },
- { PCI_CHIP_RV670_9511, "ATI FireGL V7700" },
- { PCI_CHIP_RV630_9580, "ATI RV630" },
- { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" },
- { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" },
- { PCI_CHIP_RV630_9586, "ATI ATI Radeon HD 2600 XT AGP" },
- { PCI_CHIP_RV630_9587, "ATI ATI Radeon HD 2600 Pro AGP" },
- { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" },
- { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" },
- { PCI_CHIP_RV630_958A, "ATI Gemini RV630" },
- { PCI_CHIP_RV630_958B, "ATI Gemini ATI Mobility Radeon HD 2600 XT" },
- { PCI_CHIP_RV630_958C, "ATI FireGL V5600" },
- { PCI_CHIP_RV630_958D, "ATI FireGL V3600" },
- { PCI_CHIP_RV630_958E, "ATI ATI Radeon HD 2600 LE" },
- { -1, NULL }
-};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
deleted file mode 100644
index ab6b62a..0000000
--- a/src/radeon_pci_chipset_gen.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/* This file is autogenerated please do not edit */
-PciChipsets RADEONPciChipsets[] = {
- { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA },
- { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA },
- { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA },
- { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA },
- { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA },
- { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA },
- { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA },
- { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA },
- { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA },
- { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA },
- { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA },
- { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA },
- { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA },
- { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA },
- { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA },
- { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA },
- { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA },
- { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA },
- { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA },
- { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA },
- { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA },
- { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA },
- { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA },
- { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA },
- { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA },
- { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA },
- { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA },
- { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA },
- { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA },
- { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA },
- { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA },
- { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA },
- { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA },
- { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA },
- { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA },
- { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA },
- { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA },
- { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA },
- { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA },
- { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA },
- { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA },
- { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA },
- { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA },
- { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA },
- { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA },
- { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA },
- { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA },
- { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA },
- { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA },
- { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA },
- { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA },
- { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA },
- { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA },
- { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA },
- { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA },
- { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA },
- { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA },
- { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA },
- { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA },
- { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA },
- { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA },
- { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA },
- { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA },
- { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA },
- { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA },
- { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA },
- { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA },
- { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA },
- { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA },
- { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA },
- { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5657, PCI_CHIP_RV370_5657, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA },
- { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA },
- { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA },
- { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA },
- { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA },
- { PCI_CHIP_R520_7100, PCI_CHIP_R520_7100, RES_SHARED_VGA },
- { PCI_CHIP_R520_7101, PCI_CHIP_R520_7101, RES_SHARED_VGA },
- { PCI_CHIP_R520_7102, PCI_CHIP_R520_7102, RES_SHARED_VGA },
- { PCI_CHIP_R520_7103, PCI_CHIP_R520_7103, RES_SHARED_VGA },
- { PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA },
- { PCI_CHIP_R520_7105, PCI_CHIP_R520_7105, RES_SHARED_VGA },
- { PCI_CHIP_R520_7106, PCI_CHIP_R520_7106, RES_SHARED_VGA },
- { PCI_CHIP_R520_7108, PCI_CHIP_R520_7108, RES_SHARED_VGA },
- { PCI_CHIP_R520_7109, PCI_CHIP_R520_7109, RES_SHARED_VGA },
- { PCI_CHIP_R520_710A, PCI_CHIP_R520_710A, RES_SHARED_VGA },
- { PCI_CHIP_R520_710B, PCI_CHIP_R520_710B, RES_SHARED_VGA },
- { PCI_CHIP_R520_710C, PCI_CHIP_R520_710C, RES_SHARED_VGA },
- { PCI_CHIP_R520_710E, PCI_CHIP_R520_710E, RES_SHARED_VGA },
- { PCI_CHIP_R520_710F, PCI_CHIP_R520_710F, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7140, PCI_CHIP_RV515_7140, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7141, PCI_CHIP_RV515_7141, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7143, PCI_CHIP_RV515_7143, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7144, PCI_CHIP_RV515_7144, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7145, PCI_CHIP_RV515_7145, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7146, PCI_CHIP_RV515_7146, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7147, PCI_CHIP_RV515_7147, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7149, PCI_CHIP_RV515_7149, RES_SHARED_VGA },
- { PCI_CHIP_RV515_714A, PCI_CHIP_RV515_714A, RES_SHARED_VGA },
- { PCI_CHIP_RV515_714B, PCI_CHIP_RV515_714B, RES_SHARED_VGA },
- { PCI_CHIP_RV515_714C, PCI_CHIP_RV515_714C, RES_SHARED_VGA },
- { PCI_CHIP_RV515_714D, PCI_CHIP_RV515_714D, RES_SHARED_VGA },
- { PCI_CHIP_RV515_714E, PCI_CHIP_RV515_714E, RES_SHARED_VGA },
- { PCI_CHIP_RV515_714F, PCI_CHIP_RV515_714F, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7151, PCI_CHIP_RV515_7151, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7152, PCI_CHIP_RV515_7152, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7153, PCI_CHIP_RV515_7153, RES_SHARED_VGA },
- { PCI_CHIP_RV515_715E, PCI_CHIP_RV515_715E, RES_SHARED_VGA },
- { PCI_CHIP_RV515_715F, PCI_CHIP_RV515_715F, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7180, PCI_CHIP_RV515_7180, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7181, PCI_CHIP_RV515_7181, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7186, PCI_CHIP_RV515_7186, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7187, PCI_CHIP_RV515_7187, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7188, PCI_CHIP_RV515_7188, RES_SHARED_VGA },
- { PCI_CHIP_RV515_718A, PCI_CHIP_RV515_718A, RES_SHARED_VGA },
- { PCI_CHIP_RV515_718B, PCI_CHIP_RV515_718B, RES_SHARED_VGA },
- { PCI_CHIP_RV515_718C, PCI_CHIP_RV515_718C, RES_SHARED_VGA },
- { PCI_CHIP_RV515_718D, PCI_CHIP_RV515_718D, RES_SHARED_VGA },
- { PCI_CHIP_RV515_718F, PCI_CHIP_RV515_718F, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7193, PCI_CHIP_RV515_7193, RES_SHARED_VGA },
- { PCI_CHIP_RV515_7196, PCI_CHIP_RV515_7196, RES_SHARED_VGA },
- { PCI_CHIP_RV515_719B, PCI_CHIP_RV515_719B, RES_SHARED_VGA },
- { PCI_CHIP_RV515_719F, PCI_CHIP_RV515_719F, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C0, PCI_CHIP_RV530_71C0, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C1, PCI_CHIP_RV530_71C1, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C2, PCI_CHIP_RV530_71C2, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C3, PCI_CHIP_RV530_71C3, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C4, PCI_CHIP_RV530_71C4, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C6, PCI_CHIP_RV530_71C6, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71C7, PCI_CHIP_RV530_71C7, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71CD, PCI_CHIP_RV530_71CD, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71CE, PCI_CHIP_RV530_71CE, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71D2, PCI_CHIP_RV530_71D2, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71D4, PCI_CHIP_RV530_71D4, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71D5, PCI_CHIP_RV530_71D5, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA },
- { PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA },
- { PCI_CHIP_RV530_7200, PCI_CHIP_RV530_7200, RES_SHARED_VGA },
- { PCI_CHIP_RV530_7210, PCI_CHIP_RV530_7210, RES_SHARED_VGA },
- { PCI_CHIP_RV530_7211, PCI_CHIP_RV530_7211, RES_SHARED_VGA },
- { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA },
- { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA },
- { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA },
- { PCI_CHIP_R580_7245, PCI_CHIP_R580_7245, RES_SHARED_VGA },
- { PCI_CHIP_R580_7246, PCI_CHIP_R580_7246, RES_SHARED_VGA },
- { PCI_CHIP_R580_7247, PCI_CHIP_R580_7247, RES_SHARED_VGA },
- { PCI_CHIP_R580_7248, PCI_CHIP_R580_7248, RES_SHARED_VGA },
- { PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA },
- { PCI_CHIP_R580_724A, PCI_CHIP_R580_724A, RES_SHARED_VGA },
- { PCI_CHIP_R580_724B, PCI_CHIP_R580_724B, RES_SHARED_VGA },
- { PCI_CHIP_R580_724C, PCI_CHIP_R580_724C, RES_SHARED_VGA },
- { PCI_CHIP_R580_724D, PCI_CHIP_R580_724D, RES_SHARED_VGA },
- { PCI_CHIP_R580_724E, PCI_CHIP_R580_724E, RES_SHARED_VGA },
- { PCI_CHIP_R580_724F, PCI_CHIP_R580_724F, RES_SHARED_VGA },
- { PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7281, PCI_CHIP_RV560_7281, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7283, PCI_CHIP_RV560_7283, RES_SHARED_VGA },
- { PCI_CHIP_R580_7284, PCI_CHIP_R580_7284, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7287, PCI_CHIP_RV560_7287, RES_SHARED_VGA },
- { PCI_CHIP_RV570_7288, PCI_CHIP_RV570_7288, RES_SHARED_VGA },
- { PCI_CHIP_RV570_7289, PCI_CHIP_RV570_7289, RES_SHARED_VGA },
- { PCI_CHIP_RV570_728B, PCI_CHIP_RV570_728B, RES_SHARED_VGA },
- { PCI_CHIP_RV570_728C, PCI_CHIP_RV570_728C, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7290, PCI_CHIP_RV560_7290, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7291, PCI_CHIP_RV560_7291, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7293, PCI_CHIP_RV560_7293, RES_SHARED_VGA },
- { PCI_CHIP_RV560_7297, PCI_CHIP_RV560_7297, RES_SHARED_VGA },
- { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA },
- { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA },
- { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA },
- { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA },
- { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA },
- { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA },
- { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA },
- { PCI_CHIP_RS740_796F, PCI_CHIP_RS740_796F, RES_SHARED_VGA },
- { PCI_CHIP_R600_9400, PCI_CHIP_R600_9400, RES_SHARED_VGA },
- { PCI_CHIP_R600_9401, PCI_CHIP_R600_9401, RES_SHARED_VGA },
- { PCI_CHIP_R600_9402, PCI_CHIP_R600_9402, RES_SHARED_VGA },
- { PCI_CHIP_R600_9403, PCI_CHIP_R600_9403, RES_SHARED_VGA },
- { PCI_CHIP_R600_9405, PCI_CHIP_R600_9405, RES_SHARED_VGA },
- { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA },
- { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA },
- { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C4, PCI_CHIP_RV610_94C4, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C5, PCI_CHIP_RV610_94C5, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C6, PCI_CHIP_RV610_94C6, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C7, PCI_CHIP_RV610_94C7, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C8, PCI_CHIP_RV610_94C8, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA },
- { PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA },
- { PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA },
- { PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA },
- { PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA },
- { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA },
- { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA },
- { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9586, PCI_CHIP_RV630_9586, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9587, PCI_CHIP_RV630_9587, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9588, PCI_CHIP_RV630_9588, RES_SHARED_VGA },
- { PCI_CHIP_RV630_9589, PCI_CHIP_RV630_9589, RES_SHARED_VGA },
- { PCI_CHIP_RV630_958A, PCI_CHIP_RV630_958A, RES_SHARED_VGA },
- { PCI_CHIP_RV630_958B, PCI_CHIP_RV630_958B, RES_SHARED_VGA },
- { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA },
- { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA },
- { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA },
- { -1, -1, RES_UNDEFINED }
-};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
deleted file mode 100644
index 04393da..0000000
--- a/src/radeon_pci_device_match_gen.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/* This file is autogenerated please do not edit */
-static const struct pci_id_match radeon_device_match[] = {
- ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E54, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS100_4136, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS200_4137, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_AD, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_AE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_AF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_AG, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_AH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_AI, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_AJ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_AK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_AP, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_AQ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV360_AR, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_AS, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_AT, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_4155, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_AV, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS250_4237, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R200_BB, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R200_BC, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS100_4336, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS200_4337, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS250_4437, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV250_If, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ig, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JI, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JJ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JL, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JM, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JN, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_4A4F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R420_JP, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R481_4B49, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LW, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LX, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LY, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LZ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ld, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lf, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lg, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_ND, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_NE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_NF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R300_NG, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_NH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_NI, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R360_NJ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R350_NK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_NP, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_NQ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_NR, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_NS, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_NT, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV350_NV, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QD, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QF, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QG, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R200_QH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R200_QL, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R200_QM, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV200_QW, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV200_QX, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV100_QY, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV100_QZ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RN50_515E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5460, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5462, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5464, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UH, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UI, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UJ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UK, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_554C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_554D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_554E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_554F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_5550, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UQ, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UR, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_UT, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_564A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_564B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS480_5955, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5960, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5961, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5962, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5964, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5965, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RN50_5969, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS482_5974, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS485_5975, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A41, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A42, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A61, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A62, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5657, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C63, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_5D48, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_5D49, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R430_5D4A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R480_5D50, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R480_5D52, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R423_5D57, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E48, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7100, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7101, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7102, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7103, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7104, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7105, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7106, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7108, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_7109, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_710A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_710B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_710C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_710E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R520_710F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7140, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7141, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7142, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7143, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7144, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7145, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7146, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7147, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7149, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_714A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_714B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_714C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_714D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_714E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_714F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7151, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7152, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7153, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_715E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_715F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7180, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7181, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7183, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7186, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7187, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7188, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_718A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_718B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_718C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_718D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_718F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7193, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_7196, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_719B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV515_719F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C0, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C1, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C2, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C3, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C4, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C5, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C6, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C7, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CD, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D2, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D4, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D5, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7200, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7210, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7211, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7245, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7246, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7247, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7248, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7249, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_724A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_724B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_724C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_724D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_724E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_724F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV570_7280, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7281, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7283, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R580_7284, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7287, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV570_7288, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV570_7289, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV570_728B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV570_728C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7290, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7291, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7293, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV560_7297, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS350_7834, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS350_7835, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS690_791E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS690_791F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS740_796C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS740_796D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS740_796E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RS740_796F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_9400, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_9401, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_9402, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_9403, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_9405, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C4, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C5, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C6, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C7, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C8, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C9, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CB, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CC, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV670_9500, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV670_9501, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV670_9505, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9586, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9587, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9588, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_9589, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_958A, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_958B, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ),
- { 0, 0, 0 }
-};
commit 713a2241495b9a3818c06974838477d9f28fe52b
Author: George Sapountzis <gsap7 at yahoo.gr>
Date: Wed Feb 27 18:47:45 2008 +0200
drop radeon, theatre
diff --git a/man/radeon.man b/man/radeon.man
deleted file mode 100644
index 86be965..0000000
--- a/man/radeon.man
+++ /dev/null
@@ -1,514 +0,0 @@
-.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.0 2003/01/31 23:04:50 $
-.ds q \N'34'
-.TH RADEON __drivermansuffix__ __vendorversion__
-.SH NAME
-radeon \- ATI RADEON video driver
-.SH SYNOPSIS
-.nf
-.B "Section \*qDevice\*q"
-.BI " Identifier \*q" devname \*q
-.B " Driver \*qradeon\*q"
-\ \ ...
-.B EndSection
-.fi
-.SH DESCRIPTION
-.B radeon
-is an __xservername__ driver for ATI RADEON based video cards. It contains
-full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup,
-flat panel, hardware 2D acceleration, hardware 3D acceleration, hardware cursor,
-XV extension, and the Xinerama extension.
-.SH SUPPORTED HARDWARE
-The
-.B radeon
-driver supports PCI and AGP video cards based on the following ATI chips
-.TP 12
-.B R100
-Radeon 7200
-.TP 12
-.B RV100
-Radeon 7000(VE), M6, RN50/ES1000
-.TP 12
-.B RS100
-Radeon IGP320(M)
-.TP 12
-.B RV200
-Radeon 7500, M7, FireGL 7800
-.TP 12
-.B RS200
-Radeon IGP330(M)/IGP340(M)
-.TP 12
-.B RS250
-Radeon Mobility 7000 IGP
-.TP 12
-.B R200
-Radeon 8500, 9100, FireGL 8800/8700
-.TP 12
-.B RV250
-Radeon 9000PRO/9000, M9
-.TP 12
-.B RS300
-Radeon 9100 IGP
-.TP 12
-.B RS350
-Radeon 9200 IGP
-.TP 12
-.B RS400
-Radeon XPRESS 200/200M IGP
-.TP 12
-.B RV280
-Radeon 9200PRO/9200/9200SE, M9+
-.TP 12
-.B R300
-Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1
-.TP 12
-.B R350
-Radeon 9800PRO/9800SE/9800, FireGL X2
-.TP 12
-.B R360
-Radeon 9800XT
-.TP 12
-.B RV350
-Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2
-.TP 12
-.B RV360
-Radeon 9600XT
-.TP 12
-.B RV370
-Radeon X300, M22
-.TP 12
-.B RV380
-Radeon X600, M24
-.TP 12
-.B RV410
-Radeon X700, M26 PCIE
-.TP 12
-.B R420
-Radeon X800 AGP
-.TP 12
-.B R423/R430
-Radeon X800, M28 PCIE
-.TP 12
-.B R480/R481
-Radeon X850 PCIE/AGP
-.TP 12
-.B RV515
-Radeon X1300/X1400/X1500
-.TP 12
-.B R520
-Radeon X1800
-.TP 12
-.B RV530/RV560
-Radeon X1600/X1650/X1700
-.TP 12
-.B RV570/R580
-Radeon X1900/X1950
-.TP 12
-.B RS600/RS690
-Radeon X1200
-.TP 12
-.B R600
-Radeon HD 2900
-.TP 12
-.B RV610/RV630
-Radeon HD 2400/2600
-.TP 12
-.B RV670
-Radeon HD 3850/3870
-
-.SH CONFIGURATION DETAILS
-Please refer to __xconfigfile__(__filemansuffix__) for general configuration
-details. This section only covers configuration details specific to this
-driver.
-.PP
-The driver auto\-detects all device information necessary to initialize
-the card. However, if you have problems with auto\-detection, you can
-specify:
-.PP
-.RS 4
-VideoRam \- in kilobytes
-.br
-MemBase \- physical address of the linear framebuffer
-.br
-IOBase \- physical address of the MMIO registers
-.br
-ChipID \- PCI DEVICE ID
-.RE
-.PP
-In addition, the following driver
-.B Options
-are supported:
-.TP
-.BI "Option \*qSWcursor\*q \*q" boolean \*q
-Selects software cursor. The default is
-.B off.
-.TP
-.BI "Option \*qNoAccel\*q \*q" boolean \*q
-Enables or disables all hardware acceleration.
-.br
-The default is to
-.B enable
-hardware acceleration.
-.TP
-.BI "Option \*qDac6Bit\*q \*q" boolean \*q
-Enables or disables the use of 6 bits per color component when in 8 bpp
-mode (emulates VGA mode). By default, all 8 bits per color component
-are used.
-.br
-The default is
-.B off.
-.TP
-.BI "Option \*qVideoKey\*q \*q" integer \*q
-This overrides the default pixel value for the YUV video overlay key.
-.br
-The default value is
-.B 0x1E.
-.TP
-.BI "Option \*qScalerWidth\*q \*q" integer \*q
-This sets the overlay scaler buffer width. Accepted values range from 1024 to
-2048, divisible by 64, values other than 1536 and 1920 may not make sense
-though. Should be set automatically, but noone has a clue what the limit is
-for which chip. If you think quality is not optimal when playing back HD video
-(with horizontal resolution larger than this setting), increase this value, if
-you get an empty area at the right (usually pink), decrease it. Note this only
-affects the "true" overlay via xv, it won't affect things like textured video.
-.br
-The default value is either 1536 (for most chips) or 1920.
-.TP
-.BI "Option \*qAGPMode\*q \*q" integer \*q
-Set AGP data transfer rate.
-(used only when DRI is enabled)
-.br
-1 \-\- 1x (before AGP v3 only)
-.br
-2 \-\- 2x (before AGP v3 only)
-.br
-4 \-\- 4x
-.br
-8 \-\- 8x (AGP v3 only)
-.br
-others \-\- invalid
-.br
-The default is to
-.B leave it unchanged.
-.TP
-.BI "Option \*qAGPFastWrite\*q \*q" boolean \*q
-Enable AGP fast writes. Enabling this is frequently the cause of
-instability. Used only when the DRI is enabled. If you enable
-this option you will get *NO* support from developers.
-.br
-The default is
-.B off.
-.TP
-.BI "Option \*qBusType\*q \*q" string \*q
-Used to replace previous ForcePCIMode option.
-Should only be used when driver's bus detection is incorrect
-or you want to force a AGP card to PCI mode. Should NEVER force
-a PCI card to AGP bus.
-.br
-PCI \-\- PCI bus
-.br
-AGP \-\- AGP bus
-.br
-PCIE \-\- PCI Express (falls back to PCI at present)
-.br
-(used only when DRI is enabled)
-.br
-The default is
-.B auto detect.
-.TP
-.BI "Option \*qDDCMode\*q \*q" boolean \*q
-Force to use the modes queried from the connected monitor.
-.br
-The default is
-.B off.
-.TP
-.BI "Option \*qDisplayPriority\*q \*q" string \*q
-.br
-Used to prevent flickering or tearing problem caused by display buffer underflow.
-.br
-AUTO \-\- Driver calculated (default).
-.br
-BIOS \-\- Remain unchanged from BIOS setting.
- Use this if the calculation is not correct
- for your card.
-.br
-HIGH \-\- Force to the highest priority.
- Use this if you have problem with above options.
- This may affect performance slightly.
-.br
-The default value is
-.B AUTO.
-.TP
-.BI "Option \*qColorTiling\*q \*q" "boolean" \*q
-Frame buffer can be addressed either in linear or tiled mode. Tiled mode can provide
-significant performance benefits with 3D applications, for 2D it shouldn't matter
-much. Tiling will be disabled if the virtual x resolution exceeds 2048 (3968 for R300
-and above), if option
-.B UseFBDev
-is used, or (if DRI is enabled) the drm module is too old.
-.br
-If this option is enabled, a new dri driver is required for direct rendering too.
-.br
-Color tiling will be automatically disabled in interlaced or doublescan screen modes.
-.br
-The default value is
-.B on.
-.TP
-.BI "Option \*qIgnoreEDID\*q \*q" boolean \*q
-Do not use EDID data for mode validation, but DDC is still used
-for monitor detection. This is different from NoDDC option.
-.br
-The default value is
-.B off.
-.TP
-.BI "Option \*qPanelSize\*q \*q" "string" \*q
-Should only be used when driver cannot detect the correct panel size.
-Apply to both desktop (TMDS) and laptop (LVDS) digital panels.
-When a valid panel size is specified, the timings collected from
-DDC and BIOS will not be used. If you have a panel with timings
-different from that of a standard VESA mode, you have to provide
-this information through the Modeline.
-.br
-For example, Option "PanelSize" "1400x1050"
-.br
-The default value is
-.B none.
-.TP
-.BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
-Enable page flipping for 3D acceleration. This will increase performance
-but not work correctly in some rare cases, hence the default is
-.B off.
-.TP
-.BI "Option \*qForceMinDotClock\*q \*q" frequency \*q
-Override minimum dot clock. Some Radeon BIOSes report a minimum dot
-clock unsuitable (too high) for use with television sets even when they
-actually can produce lower dot clocks. If this is the case you can
-override the value here.
-.B Note that using this option may damage your hardware.
-You have been warned. The
-.B frequency
-parameter may be specified as a float value with standard suffixes like
-"k", "kHz", "M", "MHz".
-.TP
-.BI "Option \*qRenderAccel\*q \*q" boolean \*q
-Enables or disables hardware Render acceleration. This driver does not
-support component alpha (subpixel) rendering. It is only supported on
-Radeon series up to and including 9200 (9500/9700 and newer
-unsupported). The default is to
-.B enable
-Render acceleration.
-.TP
-.BI "Option \*qAccelMethod\*q \*q" "string" \*q
-Chooses between available acceleration architectures. Valid options are
-.B XAA
-and
-.B EXA.
-XAA is the traditional acceleration architecture and support for it is very
-stable. EXA is a newer acceleration architecture with better performance for
-the Render and Composite extensions, but the rendering code for it is newer and
-possibly unstable. The default is
-.B XAA.
-.TP
-.BI "Option \*qAccelDFS\*q \*q" boolean \*q
-Use or don't use accelerated EXA DownloadFromScreen hook when possible (only
-when Direct Rendering is enabled, e.g.).
-Default:
-.B off
-with AGP due to issues with GPU->host transfers with some AGP bridges,
-.B on
-otherwise.
-.TP
-.BI "Option \*qFBTexPercent\*q \*q" integer \*q
-Amount of video RAM to reserve for OpenGL textures, in percent. With EXA, the
-remainder of video RAM is reserved for EXA offscreen management. Specifying 0
-results in all offscreen video RAM being reserved for EXA and only GART memory
-being available for OpenGL textures. This may improve EXA performance, but
-beware that it may cause problems with OpenGL drivers from Mesa versions older
-than 6.4. With XAA, specifying lower percentage than what gets reserved without
-this option has no effect, but the driver tries to increase the video RAM
-reserved for textures to the amount specified roughly.
-Default:
-.B 50.
-.TP
-.BI "Option \*qDepthBits\*q \*q" integer \*q
-Precision in bits per pixel of the shared depth buffer used for 3D acceleration.
-Valid values are 16 and 24. When this is 24, there will also be a hardware
-accelerated stencil buffer, but the combined depth/stencil buffer will take up
-twice as much video RAM as when it's 16.
-Default:
-.B The same as the screen depth.
-.TP
-.BI "Option \*qDMAForXv\*q \*q" boolean \*q
-Try or don't try to use DMA for Xv image transfers. This will reduce CPU
-usage when playing big videos like DVDs, but may cause instabilities.
-Default:
-.B on.
-.TP
-.BI "Option \*qSubPixelOrder\*q \*q" "string" \*q
-Force subpixel order to specified order.
-Subpixel order is used for subpixel decimation on flat panels.
-.br
-NONE \-\- No subpixel (CRT like displays)
-.br
-RGB \-\- in horizontal RGB order (most flat panels)
-.br
-BGR \-\- in horizontal BGR order (some flat panels)
-
-.br
-This option is intended to be used in following cases:
-.br
-1. The default subpixel order is incorrect for your panel.
-.br
-2. Enable subpixel decimation on analog panels.
-.br
-3. Adjust to one display type in dual-head clone mode setup.
-.br
-4. Get better performance with Render acceleration on
-digital panels (use NONE setting).
-.br
-The default is
-.B NONE
-for CRT,
-.B RGB
-for digital panels
-.TP
-.BI "Option \*qDynamicClocks\*q \*q" boolean \*q
-Enable dynamic clock scaling. The on-chip clocks will scale dynamically
-based on usage. This can help reduce heat and increase battery
-life by reducing power usage. Some users report reduced 3D performance
-with this enabled. The default is
-.B off.
-.TP
-.BI "Option \*qVGAAccess\*q \*q" boolean \*q
-Tell the driver if it can do legacy VGA IOs to the card. This is
-necessary for properly resuming consoles when in VGA text mode, but
-shouldn't be if the console is using radeonfb or some other graphic
-mode driver. Some platforms like PowerPC have issues with those, and they aren't
-necessary unless you have a real text mode in console. The default is
-.B off
-on PowerPC and SPARC and
-.B on
-on other architectures.
-.TP
-.BI "Option \*qReverseDDC\*q \*q" boolean \*q
-When BIOS connector informations aren't available, use this option to
-reverse the mapping of the 2 main DDC ports. Use this if the X serve
-obviously detects the wrong display for each connector. This is
-typically needed on the Radeon 9600 cards bundled with Apple G5s. The
-default is
-.B off.
-.TP
-.BI "Option \*qLVDSProbePLL\*q \*q" boolean \*q
-When BIOS panel informations aren't available (like on PowerBooks), it
-may still be necessary to use the firmware provided PLL values for the
-panel or flickering will happen. This option will force probing of
-the current value programmed in the chip when X is launched in that
-case. This is only useful for LVDS panels (laptop internal panels).
-The default is
-.B on.
-.TP
-.BI "Option \*qTVDACLoadDetect\*q \*q" boolean \*q
-Enable load detection on the TV DAC. The TV DAC is used to drive both
-TV-OUT and analog monitors. Load detection is often unreliable in the
-TV DAC so it is disabled by default.
-The default is
-.B off.
-.TP
-.BI "Option \*qDefaultTMDSPLL\*q \*q" boolean \*q
-Use the default driver provided TMDS PLL values rather than the ones
-provided by the bios. This option has no effect on Mac cards. Enable
-this option if you are having problems with a DVI monitor using the
-internal TMDS controller.
-The default is
-.B off.
-.TP
-.BI "Option \*qDRI\*q \*q" boolean \*q
-Enable DRI support. This option allows you to enable to disable the DRI.
-The default is
-.B off
-for RN50/ES1000 and
-.B on
-for others.
-.TP
-.BI "Option \*qDefaultConnectorTable\*q \*q" boolean \*q
-Enable this option to skip the BIOS connector table parsing and use the
-driver defaults for each chip.
-The default is
-.B off
-.TP
-.BI "Option \*qMacModel\*q \*q" string \*q
-.br
-Used to specify Mac models for connector tables and quirks. If you have
-a powerbook or mini with DVI that does not work properly, try the alternate
- options as Apple does not seem to provide a good way of knowing whether
- they use internal or external TMDS for DVI. Only valid on PowerPC.
-.br
-ibook \-\- ibooks
-.br
-powerbook-external \-\- Powerbooks with external DVI
-.br
-powerbook-internal \-\- Powerbooks with integrated DVI
-.br
-powerbook-vga \-\- Powerbooks with VGA rather than DVI
-.br
-powerbook-duallink \-\- powerbook-external alias
-.br
-powerbook \-\- powerbook-internal alias
-.br
-mini-external \-\- Mac Mini with external DVI
-.br
-mini-internal \-\- Mac Mini with integrated DVI
-.br
-mini \-\- mini-external alias
-.br
-imac-g5-isight \-\- iMac G5 iSight
-.br
-The default value is
-.B undefined.
-.TP
-.BI "Option \*qTVStandard\*q \*q" string \*q
-.br
-Used to specify the default TV standard if you want to use something other than
-the bios default. Valid options are:
-.br
-ntsc
-.br
-pal
-.br
-pal-m
-.br
-pal-60
-.br
-ntsc-j
-.br
-scart-pal
-.br
-The default value is
-.B undefined.
-.TP
-.BI "Option \*qForceTVOut\*q \*q" boolean \*q
-Enable this option to force TV Out to always be detected as attached.
-The default is
-.B off
-.TP
-.BI "Option \*qIgnoreLidStatus\*q \*q" boolean \*q
-Enable this option to ignore lid status on laptops and always detect
-LVDS as attached.
-The default is
-.B on.
-.TP
-
-.SH SEE ALSO
-__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
-.SH AUTHORS
-.nf
-Authors include:
-Rickard E. (Rik) Faith \fIfaith at precisioninsight.com\fP
-Kevin E. Martin \fIkem at freedesktop.org\fP
-Alan Hourihane \fIalanh at fairlite.demon.co.uk\fP
-Marc Aurele La France \fItsi at xfree86.org\fP
-Benjamin Herrenschmidt \fIbenh at kernel.crashing.org\fP
-Michel D\(:anzer \fImichel at tungstengraphics.com\fP
-Alex Deucher \fIalexdeucher at gmail.com\fP
-Bogdan D. \fIbogdand at users.sourceforge.net\fP
-Eric Anholt \fIeric at anholt.net\fP
diff --git a/src/atipciids.h b/src/atipciids.h
deleted file mode 100644
index f24f8fb..0000000
--- a/src/atipciids.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 1995-2003 by The XFree86 Project, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of the copyright holder(s)
- * and author(s) shall not be used in advertising or otherwise to promote
- * the sale, use or other dealings in this Software without prior written
- * authorization from the copyright holder(s) and author(s).
- */
-
-/*
- * This file is a replacement for xf86PciInfo.h moving ATI related PCI IDs
- * locally to the driver module
- */
-
-#ifndef _ATIPCIIDS_H
-#define _ATIPCIIDS_H
-
-/* PCI Vendor */
-#define PCI_VENDOR_ATI 0x1002
-#define PCI_VENDOR_AMD 0x1022
-#define PCI_VENDOR_DELL 0x1028
-
-#include "ati_pciids_gen.h"
-
-/* Misc */
-#define PCI_CHIP_AMD761 0x700E
-
-#endif /* _ATIPCIIDS_H */
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
deleted file mode 100644
index bc2df18..0000000
--- a/src/atombios_crtc.c
+++ /dev/null
@@ -1,426 +0,0 @@
- /*
- * Copyright © 2007 Red Hat, Inc.
- *
- * PLL code is:
- * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
- * Copyright 2007 Matthias Hopf <mhopf at novell.com>
- * Copyright 2007 Egbert Eich <eich at novell.com>
- * Copyright 2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Authors:
- * Dave Airlie <airlied at redhat.com>
- *
- */
-/*
- * avivo crtc handling functions.
- */
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-/* DPMS */
-#define DPMS_SERVER
-#include <X11/extensions/dpms.h>
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_atombios.h"
-
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
-#include "sarea.h"
-#endif
-
-AtomBiosResult
-atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
-{
- ENABLE_CRTC_PS_ALLOCATION crtc_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- crtc_data.ucCRTC = crtc;
- crtc_data.ucEnable = state;
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_data;
-
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc);
- return ATOM_SUCCESS ;
- }
-
- ErrorF("Enable CRTC failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-AtomBiosResult
-atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
-{
- BLANK_CRTC_PS_ALLOCATION crtc_data;
- unsigned char *space;
- AtomBiosArgRec data;
-
- memset(&crtc_data, 0, sizeof(crtc_data));
- crtc_data.ucCRTC = crtc;
- crtc_data.ucBlanking = state;
-
- data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_data;
-
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc);
- return ATOM_SUCCESS ;
- }
-
- ErrorF("Blank CRTC failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-#if 0
-static void
-atombios_crtc_enable(xf86CrtcPtr crtc, int enable)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
-
- atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable);
-
- //TODOavivo_wait_idle(avivo);
-}
-#endif
-
-void
-atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- switch (mode) {
- case DPMSModeOn:
- case DPMSModeStandby:
- case DPMSModeSuspend:
- atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
- atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
- break;
- case DPMSModeOff:
- atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
- atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
- break;
- }
-}
-
-static AtomBiosResult
-atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
-{
- AtomBiosArgRec data;
- unsigned char *space;
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = crtc_param;
-
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC Timing success\n");
- return ATOM_SUCCESS ;
- }
-
- ErrorF("Set CRTC Timing failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-void
-atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
- CARD32 sclock = mode->Clock;
- CARD32 ref_div = 0, fb_div = 0, post_div = 0;
- int major, minor;
- SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
- void *ptr;
- AtomBiosArgRec data;
- unsigned char *space;
- RADEONSavePtr save = info->ModeReg;
-
- if (IS_AVIVO_VARIANT) {
- CARD32 temp;
- RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0);
- sclock = temp;
-
- /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
- if (radeon_crtc->crtc_id == 0) {
- temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
- } else {
- temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
- }
- } else {
- sclock = save->dot_clock_freq;
- fb_div = save->feedback_div;
- post_div = save->post_div;
- ref_div = save->ppll_ref_div;
- }
-
- xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) Clock: mode %d, PLL %lu\n",
- radeon_crtc->crtc_id, mode->Clock, (long unsigned int)sclock * 10);
- xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
- "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n",
- radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned int)fb_div, (unsigned int)fb_div, (unsigned int)post_div);
-
- atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
-
- ErrorF("table is %d %d\n", major, minor);
- switch(major) {
- case 1:
- switch(minor) {
- case 1:
- case 2: {
- spc_param.sPCLKInput.usPixelClock = sclock;
- spc_param.sPCLKInput.usRefDiv = ref_div;
- spc_param.sPCLKInput.usFbDiv = fb_div;
- spc_param.sPCLKInput.ucPostDiv = post_div;
- spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
- spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id;
- spc_param.sPCLKInput.ucRefDivSrc = 1;
-
- ptr = &spc_param;
- break;
- }
- default:
- ErrorF("Unknown table version\n");
- exit(-1);
- }
- break;
- default:
- ErrorF("Unknown table version\n");
- exit(-1);
- }
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = ptr;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC PLL success\n");
- return;
- }
-
- ErrorF("Set CRTC PLL failed\n");
- return;
-}
-
-void
-atombios_crtc_mode_set(xf86CrtcPtr crtc,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode,
- int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
- Bool tilingOld = info->tilingEnabled;
- int need_tv_timings = 0;
- int i, ret;
- SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
-
- memset(&crtc_timing, 0, sizeof(crtc_timing));
-
- if (info->allowColorTiling) {
- info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
-#ifdef XF86DRI
- if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
- RADEONSAREAPrivPtr pSAREAPriv;
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failed changing tiling status\n");
- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
- info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
- }
-#endif
- }
-
- for (i = 0; i < xf86_config->num_output; i++) {
- xf86OutputPtr output = xf86_config->output[i];
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (output->crtc == crtc) {
- if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- need_tv_timings = 1;
- else
- need_tv_timings = 2;
-
- }
- }
- }
-
- crtc_timing.ucCRTC = radeon_crtc->crtc_id;
- if (need_tv_timings) {
- ret = RADEONATOMGetTVTimings(pScrn, need_tv_timings - 1, &crtc_timing, &adjusted_mode->Clock);
- if (ret == FALSE) {
- need_tv_timings = 0;
- } else {
- adjusted_mode->CrtcHDisplay = crtc_timing.usH_Disp;
- adjusted_mode->CrtcHTotal = crtc_timing.usH_Total;
- adjusted_mode->CrtcVDisplay = crtc_timing.usV_Disp;
- adjusted_mode->CrtcVTotal = crtc_timing.usV_Total;
- }
- }
-
- if (!need_tv_timings) {
- crtc_timing.usH_Total = adjusted_mode->CrtcHTotal;
- crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay;
- crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart;
- crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart;
-
- crtc_timing.usV_Total = adjusted_mode->CrtcVTotal;
- crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay;
- crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart;
- crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart;
-
- if (adjusted_mode->Flags & V_NVSYNC)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
-
- if (adjusted_mode->Flags & V_NHSYNC)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
-
- if (adjusted_mode->Flags & V_CSYNC)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
-
- if (adjusted_mode->Flags & V_INTERLACE)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
-
- if (adjusted_mode->Flags & V_DBLSCAN)
- crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
-
- }
-
- ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
- adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
-
- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
-
- if (IS_AVIVO_VARIANT) {
- radeon_crtc->fb_width = mode->CrtcHDisplay;
- radeon_crtc->fb_height = pScrn->virtualY;
- radeon_crtc->fb_pitch = mode->CrtcHDisplay;
- radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4;
- switch (crtc->scrn->bitsPerPixel) {
- case 15:
- radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
- break;
- case 16:
- radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
- break;
- case 24:
- case 32:
- radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
- break;
- default:
- FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
- }
-
- if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
- radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
- }
-
- if (radeon_crtc->crtc_id == 0)
- OUTREG(AVIVO_D1VGA_CONTROL, 0);
- else
- OUTREG(AVIVO_D2VGA_CONTROL, 0);
-
- /* setup fb format and location
- */
- if (crtc->rotatedData != NULL) {
- /* x/y offset is already included */
- x = 0;
- y = 0;
- fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
- }
-
- /* lock the grph regs */
- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
-
- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
- OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
- OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
- radeon_crtc->fb_format);
-
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
- crtc->scrn->virtualX);
- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
- crtc->scrn->virtualY);
- OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
- crtc->scrn->displayWidth);
- OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
-
- /* unlock the grph regs */
- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
-
- /* lock the mode regs */
- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
-
- OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
- crtc->scrn->virtualY);
- OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
- (mode->HDisplay << 16) | mode->VDisplay);
- /* unlock the mode regs */
- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
-
- }
-
- atombios_crtc_set_pll(crtc, adjusted_mode);
-
- atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
-
- if (info->tilingEnabled != tilingOld) {
- /* need to redraw front buffer, I guess this can be considered a hack ? */
- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
- if (pScrn->pScreen)
- xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
- RADEONChangeSurfaces(pScrn);
- if (pScrn->pScreen)
- xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
- /* xf86SetRootClip would do, but can't access that here */
- }
-
-}
-
diff --git a/src/atombios_output.c b/src/atombios_output.c
deleted file mode 100644
index 07d212f..0000000
--- a/src/atombios_output.c
+++ /dev/null
@@ -1,703 +0,0 @@
-/*
- * Copyright © 2007 Red Hat, Inc.
- * Copyright 2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Authors:
- * Dave Airlie <airlied at redhat.com>
- * Alex Deucher <alexdeucher at gmail.com>
- *
- */
-
-/*
- * avivo output handling functions.
- */
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-/* DPMS */
-#define DPMS_SERVER
-#include <X11/extensions/dpms.h>
-#include <unistd.h>
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_atombios.h"
-
-static int
-atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucAction = 1;
-
- if (radeon_output->MonType == MT_CRT)
- disp_data.ucDacStandard = ATOM_DAC1_PS2;
- else if (radeon_output->MonType == MT_CV)
- disp_data.ucDacStandard = ATOM_DAC1_CV;
- else if (OUTPUT_IS_TV) {
- switch (radeon_output->tvStd) {
- case TV_STD_NTSC:
- case TV_STD_NTSC_J:
- case TV_STD_PAL_60:
- disp_data.ucDacStandard = ATOM_DAC1_NTSC;
- break;
- case TV_STD_PAL:
- case TV_STD_PAL_M:
- case TV_STD_SCART_PAL:
- case TV_STD_SECAM:
- case TV_STD_PAL_CN:
- disp_data.ucDacStandard = ATOM_DAC1_PAL;
- break;
- default:
- disp_data.ucDacStandard = ATOM_DAC1_NTSC;
- break;
- }
- }
-
- disp_data.usPixelClock = mode->Clock / 10;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output DAC1 setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output DAC1 setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-
-}
-
-static int
-atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucAction = 1;
-
- if (radeon_output->MonType == MT_CRT)
- disp_data.ucDacStandard = ATOM_DAC2_PS2;
- else if (radeon_output->MonType == MT_CV)
- disp_data.ucDacStandard = ATOM_DAC2_CV;
- else if (OUTPUT_IS_TV) {
- switch (radeon_output->tvStd) {
- case TV_STD_NTSC:
- case TV_STD_NTSC_J:
- case TV_STD_PAL_60:
- disp_data.ucDacStandard = ATOM_DAC2_NTSC;
- break;
- case TV_STD_PAL:
- case TV_STD_PAL_M:
- case TV_STD_SCART_PAL:
- case TV_STD_SECAM:
- case TV_STD_PAL_CN:
- disp_data.ucDacStandard = ATOM_DAC2_PAL;
- break;
- default:
- disp_data.ucDacStandard = ATOM_DAC2_NTSC;
- break;
- }
- }
-
- disp_data.usPixelClock = mode->Clock / 10;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output DAC2 setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output DAC2 setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-
-}
-
-static int
-atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- TV_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.sTVEncoder.ucAction = 1;
-
- if (radeon_output->MonType == MT_CV)
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV;
- else {
- switch (radeon_output->tvStd) {
- case TV_STD_NTSC:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
- break;
- case TV_STD_PAL:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
- break;
- case TV_STD_PAL_M:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
- break;
- case TV_STD_PAL_60:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
- break;
- case TV_STD_NTSC_J:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
- break;
- case TV_STD_SCART_PAL:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
- break;
- case TV_STD_SECAM:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
- break;
- case TV_STD_PAL_CN:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
- break;
- default:
- disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
- break;
- }
- }
-
- disp_data.sTVEncoder.usPixelClock = mode->Clock / 10;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output TV1 setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output TV1 setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-
-}
-
-int
-atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.sXTmdsEncoder.ucEnable = 1;
-
- if (mode->Clock > 165000)
- disp_data.sXTmdsEncoder.ucMisc = 1;
- else
- disp_data.sXTmdsEncoder.ucMisc = 0;
-
- if (!info->dac6bits)
- disp_data.sXTmdsEncoder.ucMisc |= (1 << 1);
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("External TMDS setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("External TMDS setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-static int
-atombios_ddia_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.sDVOEncoder.ucAction = ATOM_ENABLE;
- disp_data.sDVOEncoder.usPixelClock = mode->Clock / 10;
-
- if (mode->Clock > 165000)
- disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
- else
- disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = 0;
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("DDIA setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("DDIA setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-static int
-atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- TMDS1_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucAction = 1;
- if (mode->Clock > 165000)
- disp_data.ucMisc = 1;
- else
- disp_data.ucMisc = 0;
- disp_data.usPixelClock = mode->Clock / 10;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output TMDS1 setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output TMDS1 setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-
-}
-
-static int
-atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- TMDS2_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucAction = 1;
- if (mode->Clock > 165000)
- disp_data.ucMisc = 1;
- else
- disp_data.ucMisc = 0;
- disp_data.usPixelClock = mode->Clock / 10;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output TMDS2 setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output TMDS2 setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-static int
-atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- LVDS_ENCODER_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucAction = 1;
- if (mode->Clock > 165000)
- disp_data.ucMisc = 1;
- else
- disp_data.ucMisc = 0;
- disp_data.usPixelClock = mode->Clock / 10;
- data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output LVDS setup success\n");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output LVDS setup failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-static int
-atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
- ENABLE_SCALER_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucScaler = radeon_crtc->crtc_id;
-
- if (radeon_output->Flags & RADEON_USE_RMX) {
- ErrorF("Using RMX\n");
- if (radeon_output->rmx_type == RMX_FULL)
- disp_data.ucEnable = ATOM_SCALER_EXPANSION;
- else if (radeon_output->rmx_type == RMX_CENTER)
- disp_data.ucEnable = ATOM_SCALER_CENTER;
- } else {
- ErrorF("Not using RMX\n");
- disp_data.ucEnable = ATOM_SCALER_DISABLE;
- }
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("scaler %d setup success\n", radeon_crtc->crtc_id);
- return ATOM_SUCCESS;
- }
-
- ErrorF("scaler %d setup failed\n", radeon_crtc->crtc_id);
- return ATOM_NOT_IMPLEMENTED;
-
-}
-
-static AtomBiosResult
-atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state)
-{
- DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- disp_data.ucAction = state;
- data.exec.index = device;
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &disp_data;
-
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Output %d %s success\n", device, state? "enable":"disable");
- return ATOM_SUCCESS;
- }
-
- ErrorF("Output %d %s failed\n", device, state? "enable":"disable");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-static void
-atombios_device_dpms(xf86OutputPtr output, int device, int mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- int index = 0;
-
- switch (device) {
- case ATOM_DEVICE_CRT1_SUPPORT:
- case ATOM_DEVICE_CRT2_SUPPORT:
- if (radeon_output->DACType == DAC_PRIMARY)
- index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
- else if (radeon_output->DACType == DAC_TVDAC)
- index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
- break;
- case ATOM_DEVICE_DFP1_SUPPORT:
- index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
- break;
- case ATOM_DEVICE_DFP2_SUPPORT:
- index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
- break;
- case ATOM_DEVICE_DFP3_SUPPORT:
- index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
- break;
- case ATOM_DEVICE_LCD1_SUPPORT:
- index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
- break;
- case ATOM_DEVICE_TV1_SUPPORT:
- index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
- break;
- case ATOM_DEVICE_CV_SUPPORT:
- index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
- break;
- default:
- return;
- }
-
- switch (mode) {
- case DPMSModeOn:
- atombios_display_device_control(info->atomBIOS, index, ATOM_ENABLE);
- break;
- case DPMSModeStandby:
- case DPMSModeSuspend:
- case DPMSModeOff:
- atombios_display_device_control(info->atomBIOS, index, ATOM_DISABLE);
- break;
- }
-}
-
-void
-atombios_output_dpms(xf86OutputPtr output, int mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- ErrorF("AGD: output dpms %d\n", mode);
-
- if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_LCD1_SUPPORT, mode);
- } else if (radeon_output->MonType == MT_DFP) {
- ErrorF("AGD: tmds dpms\n");
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_DFP1_SUPPORT, mode);
- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_DFP2_SUPPORT, mode);
- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_DFP3_SUPPORT, mode);
- } else if (radeon_output->MonType == MT_CRT) {
- ErrorF("AGD: dac dpms\n");
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_CRT1_SUPPORT, mode);
- else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_CRT2_SUPPORT, mode);
- } else if (radeon_output->MonType == MT_CV) {
- ErrorF("AGD: cv dpms\n");
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_CV_SUPPORT, mode);
- } else if (0 /*radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV*/) {
- ErrorF("AGD: tv dpms\n");
- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT)
- atombios_device_dpms(output, ATOM_DEVICE_TV1_SUPPORT, mode);
- }
-
-}
-
-static void
-atombios_set_output_crtc_source(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- AtomBiosArgRec data;
- unsigned char *space;
- SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
- int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
- int major, minor;
-
- atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
-
- ErrorF("select crtc source table is %d %d\n", major, minor);
-
- crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
- crtc_src_param.ucDevice = 0;
-
- switch(major) {
- case 1: {
- switch(minor) {
- case 0:
- case 1:
- default:
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX;
- else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_CRT2_INDEX;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_DFP1_INDEX;
- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX;
- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX;
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX;
- } else if (OUTPUT_IS_TV) {
- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_TV1_INDEX;
- } else if (radeon_output->MonType == MT_CV) {
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT)
- crtc_src_param.ucDevice = ATOM_DEVICE_CV_INDEX;
- }
- break;
- }
- break;
- }
- default:
- break;
- }
-
- ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice);
-
- data.exec.index = index;
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &crtc_src_param;
-
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id);
- return;
- }
-
- ErrorF("Set CRTC Source failed\n");
- return;
-}
-
-void
-atombios_output_mode_set(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(output->scrn);
-
- atombios_output_scaler_setup(output, mode);
- atombios_set_output_crtc_source(output);
-
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT ||
- radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- if (radeon_output->DACType == DAC_PRIMARY)
- atombios_output_dac1_setup(output, adjusted_mode);
- else if (radeon_output->DACType == DAC_TVDAC)
- atombios_output_dac2_setup(output, adjusted_mode);
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
- atombios_output_tmds1_setup(output, adjusted_mode);
- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) {
- if (info->IsIGP)
- atombios_ddia_setup(output, adjusted_mode);
- else
- atombios_external_tmds_setup(output, adjusted_mode);
- } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
- atombios_output_tmds2_setup(output, adjusted_mode);
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
- atombios_output_lvds_setup(output, adjusted_mode);
- } else if (OUTPUT_IS_TV || (radeon_output->MonType == MT_CV)) {
- if (radeon_output->DACType == DAC_PRIMARY)
- atombios_output_dac1_setup(output, adjusted_mode);
- else if (radeon_output->DACType == DAC_TVDAC)
- atombios_output_dac2_setup(output, adjusted_mode);
- atombios_output_tv1_setup(output, adjusted_mode);
- }
-
-}
-
-static AtomBiosResult
-atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- DAC_LOAD_DETECTION_PS_ALLOCATION dac_data;
- AtomBiosArgRec data;
- unsigned char *space;
-
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT;
- if (radeon_output->DACType == DAC_PRIMARY)
- dac_data.sDacload.ucDacType = ATOM_DAC_A;
- else if (radeon_output->DACType == DAC_TVDAC)
- dac_data.sDacload.ucDacType = ATOM_DAC_B;
- } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT2_SUPPORT;
- if (radeon_output->DACType == DAC_PRIMARY)
- dac_data.sDacload.ucDacType = ATOM_DAC_A;
- else if (radeon_output->DACType == DAC_TVDAC)
- dac_data.sDacload.ucDacType = ATOM_DAC_B;
- } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CV_SUPPORT;
- if (radeon_output->DACType == DAC_PRIMARY)
- dac_data.sDacload.ucDacType = ATOM_DAC_A;
- else if (radeon_output->DACType == DAC_TVDAC)
- dac_data.sDacload.ucDacType = ATOM_DAC_B;
- } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_TV1_SUPPORT;
- if (radeon_output->DACType == DAC_PRIMARY)
- dac_data.sDacload.ucDacType = ATOM_DAC_A;
- else if (radeon_output->DACType == DAC_TVDAC)
- dac_data.sDacload.ucDacType = ATOM_DAC_B;
- } else {
- ErrorF("invalid output device for dac detection\n");
- return ATOM_NOT_IMPLEMENTED;
- }
-
- dac_data.sDacload.ucMisc = 0;
-
- data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
- data.exec.dataSpace = (void *)&space;
- data.exec.pspace = &dac_data;
-
- if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
-
- ErrorF("Dac detection success\n");
- return ATOM_SUCCESS ;
- }
-
- ErrorF("DAC detection failed\n");
- return ATOM_NOT_IMPLEMENTED;
-}
-
-RADEONMonitorType
-atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONMonitorType MonType = MT_NONE;
- AtomBiosResult ret;
- uint32_t bios_0_scratch;
-
- if (OUTPUT_IS_TV) {
- if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
- if (radeon_output->type == OUTPUT_STV)
- return MT_STV;
- else
- return MT_CTV;
- }
- }
-
- ret = atom_bios_dac_load_detect(info->atomBIOS, output);
- if (ret == ATOM_SUCCESS) {
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- bios_0_scratch = INREG(R600_BIOS_0_SCRATCH);
- else
- bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
- ErrorF("DAC connect %08X\n", (unsigned int)bios_0_scratch);
-
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- if (bios_0_scratch & ATOM_S0_CRT1_MASK)
- MonType = MT_CRT;
- } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- if (bios_0_scratch & ATOM_S0_CRT2_MASK)
- MonType = MT_CRT;
- } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
- if (bios_0_scratch & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A))
- MonType = MT_CV;
- } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
- if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
- MonType = MT_CTV;
- else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
- MonType = MT_STV;
- }
- }
-
- return MonType;
-}
-
diff --git a/src/generic_bus.h b/src/generic_bus.h
deleted file mode 100644
index 6197eab..0000000
--- a/src/generic_bus.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __GENERIC_BUS_H__
-#define __GENERIC_BUS_H__
-
-/* this is meant to be used for proprietary buses where abstraction is needed
- but they don't occur often enough to warrant a separate helper library */
-
-
-#define GB_IOCTL_GET_NAME 1
- /* third argument is size of the buffer, fourth argument is pointer
- to the buffer. Returns the name of the bus */
-#define GB_IOCTL_GET_TYPE 2
- /* third argument is size of the buffer, fourth argument is pointer
- to the buffer. Returns the type of the bus, driver should check
- this at initialization time to find out whether they are compatible
- */
-
-
-typedef struct _GENERIC_BUS_Rec *GENERIC_BUS_Ptr;
-
-typedef struct _GENERIC_BUS_Rec{
- int scrnIndex;
- DevUnion DriverPrivate;
- Bool (*ioctl)(GENERIC_BUS_Ptr, long, long, char *);
- Bool (*read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *);
- Bool (*write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *);
- Bool (*fifo_read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *);
- Bool (*fifo_write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *);
-
- } GENERIC_BUS_Rec;
-
-
-
-
-
-#endif
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
deleted file mode 100644
index 06ad60c..0000000
--- a/src/legacy_crtc.c
+++ /dev/null
@@ -1,1793 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include <stdio.h>
-
-/* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "vgaHW.h"
-#include "xf86Modes.h"
-
-/* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
-#include "sarea.h"
-#endif
-
-/* Write common registers */
-void
-RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->IsSecondary)
- return;
-
- OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
- OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
- OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
- OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
- OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
- OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
- OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
- OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
- OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
- OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
- OUTREG(RADEON_BUS_CNTL, restore->bus_cntl);
- OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
-
- /* Workaround for the VT switching problem in dual-head mode. This
- * problem only occurs on RV style chips, typically when a FP and
- * CRT are connected.
- */
- if (pRADEONEnt->HasCRTC2 &&
- info->ChipFamily != CHIP_FAMILY_R200 &&
- !IS_R300_VARIANT) {
- CARD32 tmp;
-
- tmp = INREG(RADEON_DAC_CNTL2);
- OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL);
- usleep(100000);
- }
-}
-
-
-/* Write CRTC registers */
-void
-RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Programming CRTC1, offset: 0x%08x\n",
- (unsigned)restore->crtc_offset);
-
- /* We prevent the CRTC from hitting the memory controller until
- * fully programmed
- */
- OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl |
- RADEON_CRTC_DISP_REQ_EN_B);
-
- OUTREGP(RADEON_CRTC_EXT_CNTL,
- restore->crtc_ext_cntl,
- RADEON_CRTC_VSYNC_DIS |
- RADEON_CRTC_HSYNC_DIS |
- RADEON_CRTC_DISPLAY_DIS);
-
- OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
- OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
- OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
- OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
-
- if (IS_R300_VARIANT)
- OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0);
- OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
- OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
-
- OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
- OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
-
- if (info->IsDellServer) {
- OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
- OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
- OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
- OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
- }
-
- OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
-}
-
-/* Write CRTC2 registers */
-void
-RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- /* CARD32 crtc2_gen_cntl;*/
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Programming CRTC2, offset: 0x%08x\n",
- (unsigned)restore->crtc2_offset);
-
- /* We prevent the CRTC from hitting the memory controller until
- * fully programmed
- */
- OUTREG(RADEON_CRTC2_GEN_CNTL,
- restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
- RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
- RADEON_CRTC2_DISP_REQ_EN_B);
-
- OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
- OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
- OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
- OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
-
- OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid);
- OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid);
-
- if (IS_R300_VARIANT)
- OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0);
- OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
- OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
-
- OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
- OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
-
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
- OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30);
- OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34);
- OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
- OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c);
- }
- OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
-
-}
-
-static void
-RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
-{
- int i = 0;
-
- /* FIXME: Certain revisions of R300 can't recover here. Not sure of
- the cause yet, but this workaround will mask the problem for now.
- Other chips usually will pass at the very first test, so the
- workaround shouldn't have any effect on them. */
- for (i = 0;
- (i < 10000 &&
- INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
- i++);
-}
-
-static void
-RADEONPLLWriteUpdate(ScrnInfoPtr pScrn)
-{
- while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
-
- OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
- RADEON_PPLL_ATOMIC_UPDATE_W,
- ~(RADEON_PPLL_ATOMIC_UPDATE_W));
-}
-
-static void
-RADEONPLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn)
-{
- int i = 0;
-
- /* FIXME: Certain revisions of R300 can't recover here. Not sure of
- the cause yet, but this workaround will mask the problem for now.
- Other chips usually will pass at the very first test, so the
- workaround shouldn't have any effect on them. */
- for (i = 0;
- (i < 10000 &&
- INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
- i++);
-}
-
-static void
-RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn)
-{
- while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
-
- OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV,
- RADEON_P2PLL_ATOMIC_UPDATE_W,
- ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
-}
-
-static CARD8
-RADEONComputePLLGain(CARD16 reference_freq, CARD16 ref_div,
- CARD16 fb_div)
-{
- unsigned vcoFreq;
-
- if (!ref_div)
- return 1;
-
- vcoFreq = ((unsigned)reference_freq * fb_div) / ref_div;
-
- /*
- * This is horribly crude: the VCO frequency range is divided into
- * 3 parts, each part having a fixed PLL gain value.
- */
- if (vcoFreq >= 30000)
- /*
- * [300..max] MHz : 7
- */
- return 7;
- else if (vcoFreq >= 18000)
- /*
- * [180..300) MHz : 4
- */
- return 4;
- else
- /*
- * [0..180) MHz : 1
- */
- return 1;
-}
-
-/* Write PLL registers */
-void
-RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD8 pllGain;
-
-#if defined(__powerpc__)
- /* apparently restoring the pll causes a hang??? */
- if (info->MacModel == RADEON_MAC_IBOOK)
- return;
-#endif
-
- pllGain = RADEONComputePLLGain(info->pll.reference_freq,
- restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
-
- if (info->IsMobility) {
- /* A temporal workaround for the occational blanking on certain laptop panels.
- This appears to related to the PLL divider registers (fail to lock?).
- It occurs even when all dividers are the same with their old settings.
- In this case we really don't need to fiddle with PLL registers.
- By doing this we can avoid the blanking problem with some panels.
- */
- if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
- (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) &
- (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
- OUTREGP(RADEON_CLOCK_CNTL_INDEX,
- RADEON_PLL_DIV_SEL,
- ~(RADEON_PLL_DIV_SEL));
- RADEONPllErrataAfterIndex(info);
- return;
- }
- }
-
- OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
- RADEON_VCLK_SRC_SEL_CPUCLK,
- ~(RADEON_VCLK_SRC_SEL_MASK));
-
- OUTPLLP(pScrn,
- RADEON_PPLL_CNTL,
- RADEON_PPLL_RESET
- | RADEON_PPLL_ATOMIC_UPDATE_EN
- | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
- | ((CARD32)pllGain << RADEON_PPLL_PVG_SHIFT),
- ~(RADEON_PPLL_RESET
- | RADEON_PPLL_ATOMIC_UPDATE_EN
- | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
- | RADEON_PPLL_PVG_MASK));
-
- OUTREGP(RADEON_CLOCK_CNTL_INDEX,
- RADEON_PLL_DIV_SEL,
- ~(RADEON_PLL_DIV_SEL));
- RADEONPllErrataAfterIndex(info);
-
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
- if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
- /* When restoring console mode, use saved PPLL_REF_DIV
- * setting.
- */
- OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
- restore->ppll_ref_div,
- 0);
- } else {
- /* R300 uses ref_div_acc field as real ref divider */
- OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
- (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
- ~R300_PPLL_REF_DIV_ACC_MASK);
- }
- } else {
- OUTPLLP(pScrn, RADEON_PPLL_REF_DIV,
- restore->ppll_ref_div,
- ~RADEON_PPLL_REF_DIV_MASK);
- }
-
- OUTPLLP(pScrn, RADEON_PPLL_DIV_3,
- restore->ppll_div_3,
- ~RADEON_PPLL_FB3_DIV_MASK);
-
- OUTPLLP(pScrn, RADEON_PPLL_DIV_3,
- restore->ppll_div_3,
- ~RADEON_PPLL_POST3_DIV_MASK);
-
- RADEONPLLWriteUpdate(pScrn);
- RADEONPLLWaitForReadUpdateComplete(pScrn);
-
- OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl);
-
- OUTPLLP(pScrn, RADEON_PPLL_CNTL,
- 0,
- ~(RADEON_PPLL_RESET
- | RADEON_PPLL_SLEEP
- | RADEON_PPLL_ATOMIC_UPDATE_EN
- | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- restore->ppll_ref_div,
- restore->ppll_div_3,
- (unsigned)restore->htotal_cntl,
- INPLL(pScrn, RADEON_PPLL_CNTL));
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote: rd=%d, fd=%d, pd=%d\n",
- restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
- (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
-
- usleep(50000); /* Let the clock to lock */
-
- OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
- RADEON_VCLK_SRC_SEL_PPLLCLK,
- ~(RADEON_VCLK_SRC_SEL_MASK));
-
- /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/
-
- ErrorF("finished PLL1\n");
-
-}
-
-/* Write PLL2 registers */
-void
-RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD8 pllGain;
-
- pllGain = RADEONComputePLLGain(info->pll.reference_freq,
- restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
-
-
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
- RADEON_PIX2CLK_SRC_SEL_CPUCLK,
- ~(RADEON_PIX2CLK_SRC_SEL_MASK));
-
- OUTPLLP(pScrn,
- RADEON_P2PLL_CNTL,
- RADEON_P2PLL_RESET
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | ((CARD32)pllGain << RADEON_P2PLL_PVG_SHIFT),
- ~(RADEON_P2PLL_RESET
- | RADEON_P2PLL_ATOMIC_UPDATE_EN
- | RADEON_P2PLL_PVG_MASK));
-
-
- OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV,
- restore->p2pll_ref_div,
- ~RADEON_P2PLL_REF_DIV_MASK);
-
- OUTPLLP(pScrn, RADEON_P2PLL_DIV_0,
- restore->p2pll_div_0,
- ~RADEON_P2PLL_FB0_DIV_MASK);
-
- OUTPLLP(pScrn, RADEON_P2PLL_DIV_0,
- restore->p2pll_div_0,
- ~RADEON_P2PLL_POST0_DIV_MASK);
-
- RADEONPLL2WriteUpdate(pScrn);
- RADEONPLL2WaitForReadUpdateComplete(pScrn);
-
- OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2);
-
- OUTPLLP(pScrn, RADEON_P2PLL_CNTL,
- 0,
- ~(RADEON_P2PLL_RESET
- | RADEON_P2PLL_SLEEP
- | RADEON_P2PLL_ATOMIC_UPDATE_EN));
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
- (unsigned)restore->p2pll_ref_div,
- (unsigned)restore->p2pll_div_0,
- (unsigned)restore->htotal_cntl2,
- INPLL(pScrn, RADEON_P2PLL_CNTL));
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Wrote2: rd=%u, fd=%u, pd=%u\n",
- (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
- (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
- (unsigned)((restore->p2pll_div_0 &
- RADEON_P2PLL_POST0_DIV_MASK) >>16));
-
- usleep(5000); /* Let the clock to lock */
-
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
- ~(RADEON_PIX2CLK_SRC_SEL_MASK));
-
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);
-
- ErrorF("finished PLL2\n");
-
-}
-
-/* Read common registers */
-void
-RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- save->ovr_clr = INREG(RADEON_OVR_CLR);
- save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT);
- save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM);
- save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
- save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL);
- save->viph_control = INREG(RADEON_VIPH_CONTROL);
- save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1);
- save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
- save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL);
- save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL);
- save->bus_cntl = INREG(RADEON_BUS_CNTL);
- save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
- save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
- save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
-}
-
-/* Read CRTC registers */
-void
-RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
- save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
- save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP);
- save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID);
- save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP);
- save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID);
-
- save->crtc_offset = INREG(RADEON_CRTC_OFFSET);
- save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
- save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
- save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
-
- if (IS_R300_VARIANT)
- save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0);
-
- if (info->IsDellServer) {
- save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
- save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
- save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- }
-
- /* track if the crtc is enabled for text restore */
- if (save->crtc_ext_cntl & RADEON_CRTC_DISPLAY_DIS)
- info->crtc_on = FALSE;
- else
- info->crtc_on = TRUE;
-
-}
-
-/* Read CRTC2 registers */
-void
-RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP);
- save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
- save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP);
- save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
- save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET);
- save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
- save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH);
-
- if (IS_R300_VARIANT)
- save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0);
-
- save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
- save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
-
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
- save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30);
- save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34);
- save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38);
- save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c);
- }
-
- save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
-
- /* track if the crtc is enabled for text restore */
- if (save->crtc2_gen_cntl & RADEON_CRTC2_DISP_DIS)
- info->crtc2_on = FALSE;
- else
- info->crtc2_on = TRUE;
-
-}
-
-/* Read PLL registers */
-void
-RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV);
- save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3);
- save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL);
- save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: 0x%08x 0x%08x 0x%08x\n",
- save->ppll_ref_div,
- save->ppll_div_3,
- (unsigned)save->htotal_cntl);
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: rd=%d, fd=%d, pd=%d\n",
- save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
- save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
- (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
-}
-
-/* Read PLL registers */
-void
-RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV);
- save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0);
- save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL);
- save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: 0x%08x 0x%08x 0x%08x\n",
- (unsigned)save->p2pll_ref_div,
- (unsigned)save->p2pll_div_0,
- (unsigned)save->htotal_cntl2);
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Read: rd=%u, fd=%u, pd=%u\n",
- (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK),
- (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK),
- (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK)
- >> 16));
-}
-
-void
-legacy_crtc_dpms(xf86CrtcPtr crtc, int mode)
-{
- int mask;
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
-
-
- switch(mode) {
- case DPMSModeOn:
- if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
- } else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
- OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask);
- }
- break;
- case DPMSModeStandby:
- if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
- } else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
- OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
- }
- break;
- case DPMSModeSuspend:
- if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
- } else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
- OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
- }
- break;
- case DPMSModeOff:
- if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
- } else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
- OUTREGP(RADEON_CRTC_EXT_CNTL, mask, ~mask);
- }
- break;
- }
-
- if (mode != DPMSModeOff)
- radeon_crtc_load_lut(crtc);
-}
-
-
-/* Define common registers for requested video mode */
-static void
-RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
-{
- save->ovr_clr = 0;
- save->ovr_wid_left_right = 0;
- save->ovr_wid_top_bottom = 0;
- save->ov0_scale_cntl = 0;
- save->subpic_cntl = 0;
- save->viph_control = 0;
- save->i2c_cntl_1 = 0;
- save->rbbm_soft_reset = 0;
- save->cap0_trig_cntl = 0;
- save->cap1_trig_cntl = 0;
- save->bus_cntl = info->BusCntl;
- /*
- * If bursts are enabled, turn on discards
- * Radeon doesn't have write bursts
- */
- if (save->bus_cntl & (RADEON_BUS_READ_BURST))
- save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
-}
-
-static void
-RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
-{
- save->surface_cntl = 0;
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* We must set both apertures as they can be both used to map the entire
- * video memory. -BenH.
- */
- switch (crtc->scrn->bitsPerPixel) {
- case 16:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
- save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
- break;
-
- case 32:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
- save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- }
-#endif
-
-}
-
-
-static Bool
-RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
- int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int Base;
-#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
- XF86DRISAREAPtr pSAREA;
-#endif
-
- save->crtc_offset = pScrn->fbOffset;
-#ifdef XF86DRI
- if (info->allowPageFlip)
- save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
- else
-#endif
- save->crtc_offset_cntl = 0;
-
- if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
- if (IS_R300_VARIANT)
- save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- else
- save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
- }
- else {
- if (IS_R300_VARIANT)
- save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- else
- save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
- }
-
- Base = pScrn->fbOffset;
-
- if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
- if (IS_R300_VARIANT) {
- /* On r300/r400 when tiling is enabled crtc_offset is set to the address of
- * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
- * Makes tiling MUCH easier.
- */
- save->crtc_tile_x0_y0 = x | (y << 16);
- Base &= ~0x7ff;
- } else {
- /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
- drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes
- flickering when scrolling vertically in a virtual screen, possibly because crtc will
- pick up the new offset value at the end of each scanline, but the new offset_cntl value
- only after a vsync. We'd probably need to wait (in drm) for vsync and only then update
- OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
- /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/
-#if 0
- /* try to get rid of flickering when scrolling at least for 2d */
-#ifdef XF86DRI
- if (!info->have3DWindows)
-#endif
- save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
-#endif
-
- int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
- /* crtc uses 256(bytes)x8 "half-tile" start addresses? */
- int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11;
- Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
- save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16);
- }
- }
- else {
- int offset = y * info->CurrentLayout.displayWidth + x;
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: offset *= 2; break;
- case 24: offset *= 3; break;
- case 32: offset *= 4; break;
- }
- Base += offset;
- }
-
- if (crtc->rotatedData != NULL) {
- Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB;
- }
-
- Base &= ~7; /* 3 lower bits are always 0 */
-
-
-#ifdef XF86DRI
- if (info->directRenderingInited) {
- /* note cannot use pScrn->pScreen since this is unitialized when called from
- RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */
- /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for
- *** pageflipping!
- ***/
- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
- /* can't get at sarea in a semi-sane way? */
- pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
-
- pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes)
- % info->CurrentLayout.displayWidth;
- pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes)
- / info->CurrentLayout.displayWidth;
- pSAREA->frame.width = pScrn->frameX1 - x + 1;
- pSAREA->frame.height = pScrn->frameY1 - y + 1;
-
- if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
- }
- }
-#endif
- save->crtc_offset = Base;
-
- return TRUE;
-
-}
-
-/* Define CRTC registers for requested video mode */
-static Bool
-RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
- DisplayModePtr mode)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int format;
- int hsync_start;
- int hsync_wid;
- int vsync_wid;
-
- switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; break;
- case 8: format = 2; break;
- case 15: format = 3; break; /* 555 */
- case 16: format = 4; break; /* 565 */
- case 24: format = 5; break; /* RGB */
- case 32: format = 6; break; /* xRGB */
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Unsupported pixel depth (%d)\n",
- info->CurrentLayout.bitsPerPixel);
- return FALSE;
- }
-
- /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/
- save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
- | RADEON_CRTC_EN
- | (format << 8)
- | ((mode->Flags & V_DBLSCAN)
- ? RADEON_CRTC_DBL_SCAN_EN
- : 0)
- | ((mode->Flags & V_CSYNC)
- ? RADEON_CRTC_CSYNC_EN
- : 0)
- | ((mode->Flags & V_INTERLACE)
- ? RADEON_CRTC_INTERLACE_EN
- : 0));
-
- save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
- RADEON_CRTC_VSYNC_DIS |
- RADEON_CRTC_HSYNC_DIS |
- RADEON_CRTC_DISPLAY_DIS);
-
- save->disp_merge_cntl = info->SavedReg->disp_merge_cntl;
- save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
-
- save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
- | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff)
- << 16));
-
- hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
- if (!hsync_wid) hsync_wid = 1;
- hsync_start = mode->CrtcHSyncStart - 8;
-
- save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
- | ((hsync_wid & 0x3f) << 16)
- | ((mode->Flags & V_NHSYNC)
- ? RADEON_CRTC_H_SYNC_POL
- : 0));
-
- /* This works for double scan mode. */
- save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay - 1) << 16));
-
- vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
- if (!vsync_wid) vsync_wid = 1;
-
- save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
- | ((vsync_wid & 0x1f) << 16)
- | ((mode->Flags & V_NVSYNC)
- ? RADEON_CRTC_V_SYNC_POL
- : 0));
-
- save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
- ((pScrn->bitsPerPixel * 8) -1)) /
- (pScrn->bitsPerPixel * 8));
- save->crtc_pitch |= save->crtc_pitch << 16;
-
- if (info->IsDellServer) {
- save->dac2_cntl = info->SavedReg->dac2_cntl;
- save->tv_dac_cntl = info->SavedReg->tv_dac_cntl;
- save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl;
- save->disp_hw_debug = info->SavedReg->disp_hw_debug;
-
- save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
- save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
-
- /* For CRT on DAC2, don't turn it on if BIOS didn't
- enable it, even it's detected.
- */
- save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
- save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
- save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
- }
-
- return TRUE;
-}
-
-
-static Bool
-RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
- int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int Base;
-#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
- XF86DRISAREAPtr pSAREA;
-#endif
-
- /* It seems all fancy options apart from pflip can be safely disabled
- */
- save->crtc2_offset = pScrn->fbOffset;
-#ifdef XF86DRI
- if (info->allowPageFlip)
- save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
- else
-#endif
- save->crtc2_offset_cntl = 0;
-
- if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
- if (IS_R300_VARIANT)
- save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- else
- save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
- }
- else {
- if (IS_R300_VARIANT)
- save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
- R300_CRTC_MICRO_TILE_BUFFER_DIS |
- R300_CRTC_MACRO_TILE_EN);
- else
- save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
- }
-
- Base = pScrn->fbOffset;
-
- if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
- if (IS_R300_VARIANT) {
- /* On r300/r400 when tiling is enabled crtc_offset is set to the address of
- * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
- * Makes tiling MUCH easier.
- */
- save->crtc2_tile_x0_y0 = x | (y << 16);
- Base &= ~0x7ff;
- } else {
- /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
- drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes
- flickering when scrolling vertically in a virtual screen, possibly because crtc will
- pick up the new offset value at the end of each scanline, but the new offset_cntl value
- only after a vsync. We'd probably need to wait (in drm) for vsync and only then update
- OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
- /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/
-#if 0
- /* try to get rid of flickering when scrolling at least for 2d */
-#ifdef XF86DRI
- if (!info->have3DWindows)
-#endif
- save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
-#endif
-
- int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
- /* crtc uses 256(bytes)x8 "half-tile" start addresses? */
- int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11;
- Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
- save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16);
- }
- }
- else {
- int offset = y * info->CurrentLayout.displayWidth + x;
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: offset *= 2; break;
- case 24: offset *= 3; break;
- case 32: offset *= 4; break;
- }
- Base += offset;
- }
-
- if (crtc->rotatedData != NULL) {
- Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB;
- }
-
- Base &= ~7; /* 3 lower bits are always 0 */
-
-#ifdef XF86DRI
- if (info->directRenderingInited) {
- /* note cannot use pScrn->pScreen since this is unitialized when called from
- RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */
- /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for
- *** pageflipping!
- ***/
- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
- /* can't get at sarea in a semi-sane way? */
- pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
-
- pSAREAPriv->crtc2_base = Base;
-
- if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
- }
- }
-#endif
- save->crtc2_offset = Base;
-
- return TRUE;
-}
-
-
-/* Define CRTC2 registers for requested video mode */
-static Bool
-RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
- DisplayModePtr mode)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int format;
- int hsync_start;
- int hsync_wid;
- int vsync_wid;
-
- switch (info->CurrentLayout.pixel_code) {
- case 4: format = 1; break;
- case 8: format = 2; break;
- case 15: format = 3; break; /* 555 */
- case 16: format = 4; break; /* 565 */
- case 24: format = 5; break; /* RGB */
- case 32: format = 6; break; /* xRGB */
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Unsupported pixel depth (%d)\n",
- info->CurrentLayout.bitsPerPixel);
- return FALSE;
- }
-
- save->crtc2_h_total_disp =
- ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
- | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16));
-
- hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
- if (!hsync_wid) hsync_wid = 1;
- hsync_start = mode->CrtcHSyncStart - 8;
-
- save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
- | ((hsync_wid & 0x3f) << 16)
- | ((mode->Flags & V_NHSYNC)
- ? RADEON_CRTC_H_SYNC_POL
- : 0));
-
- /* This works for double scan mode. */
- save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay - 1) << 16));
-
- vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
- if (!vsync_wid) vsync_wid = 1;
-
- save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
- | ((vsync_wid & 0x1f) << 16)
- | ((mode->Flags & V_NVSYNC)
- ? RADEON_CRTC2_V_SYNC_POL
- : 0));
-
- save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) +
- ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8);
- save->crtc2_pitch |= save->crtc2_pitch << 16;
-
- /* check to see if TV DAC is enabled for another crtc and keep it enabled */
- if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON)
- save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
- else
- save->crtc2_gen_cntl = 0;
-
- save->crtc2_gen_cntl |= (RADEON_CRTC2_EN
- | (format << 8)
- | RADEON_CRTC2_VSYNC_DIS
- | RADEON_CRTC2_HSYNC_DIS
- | RADEON_CRTC2_DISP_DIS
- | ((mode->Flags & V_DBLSCAN)
- ? RADEON_CRTC2_DBL_SCAN_EN
- : 0)
- | ((mode->Flags & V_CSYNC)
- ? RADEON_CRTC2_CSYNC_EN
- : 0)
- | ((mode->Flags & V_INTERLACE)
- ? RADEON_CRTC2_INTERLACE_EN
- : 0));
-
- save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl;
- save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
-
- save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
- save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
-
- if (info->ChipFamily == CHIP_FAMILY_RS400) {
- save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */
- save->rs480_unk_e34 = 0x2749D000; /* AMD really should */
- save->rs480_unk_e38 = 0x29ca71dc; /* release docs */
- save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */
- }
-
- return TRUE;
-}
-
-
-/* Define PLL registers for requested video mode */
-static void
-RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONPLLPtr pll, DisplayModePtr mode,
- int flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 feedback_div = 0;
- CARD32 reference_div = 0;
- CARD32 post_divider = 0;
- CARD32 freq = 0;
-
- struct {
- int divider;
- int bitvalue;
- } *post_div, post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- * Reference Manual (Technical Reference
- * Manual P/N RRG-G04100-C Rev. 0.04), page
- * 3-17 (PLL_DIV_[3:0]).
- */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
- { 3, 4 }, /* VCLK_SRC/3 */
- { 16, 5 }, /* VCLK_SRC/16 */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
-
- if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
- save->ppll_ref_div = info->RefDivider;
- save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
- save->htotal_cntl = 0;
- return;
- }
-
- RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- if (post_div->divider == post_divider)
- break;
- }
-
- if (!post_div->divider) {
- save->pll_output_freq = freq;
- post_div = &post_divs[0];
- }
-
- save->dot_clock_freq = freq;
- save->feedback_div = feedback_div;
- save->reference_div = reference_div;
- save->post_div = post_divider;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n",
- (unsigned)save->dot_clock_freq,
- (unsigned)save->pll_output_freq,
- save->feedback_div,
- save->reference_div,
- save->post_div);
-
- save->ppll_ref_div = save->reference_div;
-
-#if defined(__powerpc__)
- /* apparently programming this otherwise causes a hang??? */
- if (info->MacModel == RADEON_MAC_IBOOK)
- save->ppll_div_3 = 0x000600ad;
- else
-#endif
- save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
-
- save->htotal_cntl = mode->HTotal & 0x7;
-
- save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl &
- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
-}
-
-/* Define PLL2 registers for requested video mode */
-static void
-RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONPLLPtr pll, DisplayModePtr mode,
- int flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 feedback_div = 0;
- CARD32 reference_div = 0;
- CARD32 post_divider = 0;
- CARD32 freq = 0;
-
- struct {
- int divider;
- int bitvalue;
- } *post_div, post_divs[] = {
- /* From RAGE 128 VR/RAGE 128 GL Register
- * Reference Manual (Technical Reference
- * Manual P/N RRG-G04100-C Rev. 0.04), page
- * 3-17 (PLL_DIV_[3:0]).
- */
- { 1, 0 }, /* VCLK_SRC */
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
- { 3, 4 }, /* VCLK_SRC/3 */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
- };
-
- if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
- save->p2pll_ref_div = info->RefDivider;
- save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16);
- save->htotal_cntl2 = 0;
- return;
- }
-
- RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- if (post_div->divider == post_divider)
- break;
- }
-
- if (!post_div->divider) {
- save->pll_output_freq_2 = freq;
- post_div = &post_divs[0];
- }
-
- save->dot_clock_freq_2 = freq;
- save->feedback_div_2 = feedback_div;
- save->reference_div_2 = reference_div;
- save->post_div_2 = post_divider;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n",
- (unsigned)save->dot_clock_freq_2,
- (unsigned)save->pll_output_freq_2,
- save->feedback_div_2,
- save->reference_div_2,
- save->post_div_2);
-
- save->p2pll_ref_div = save->reference_div_2;
-
- save->p2pll_div_0 = (save->feedback_div_2 |
- (post_div->bitvalue << 16));
-
- save->htotal_cntl2 = mode->HTotal & 0x7;
-
- save->pixclks_cntl = ((info->SavedReg->pixclks_cntl &
- ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
-}
-
-static void
-radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- /* pixclks_cntl controls tv clock routing */
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);
-}
-
-/* Calculate display buffer watermark to prevent buffer underflow */
-static void
-RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2, DisplayModePtr mode1, DisplayModePtr mode2)
-{
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0;
- float mem_tcas;
- int k1, c;
- CARD32 MemTrcdExtMemCntl[4] = {1, 2, 3, 4};
- CARD32 MemTrpExtMemCntl[4] = {1, 2, 3, 4};
- CARD32 MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
-
- CARD32 MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
- CARD32 MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
- CARD32 MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
-
- float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0};
- float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7};
- float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5};
-
- float mem_bw, peak_disp_bw;
- float min_mem_eff = 0.8;
- float sclk_eff, sclk_delay;
- float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
- float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2;
- float pix_clk, pix_clk2; /* in MHz */
- int cur_size = 16; /* in octawords */
- int critical_point, critical_point2;
- int stop_req, max_stop_req;
- float read_return_rate, time_disp1_drop_priority;
-
- /*
- * Set display0/1 priority up on r3/4xx in the memory controller for
- * high res modes if the user specifies HIGH for displaypriority
- * option.
- */
- if ((info->DispPriority == 2) && IS_R300_VARIANT) {
- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
- if (pRADEONEnt->pCrtc[1]->enabled) {
- mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
- } else {
- mc_init_misc_lat_timer |= 0x0100; /* display 0 only */
- }
- OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
- }
-
-
- /* R420 and RV410 family not supported yet */
- if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return;
-
- /*
- * Determine if there is enough bandwidth for current display mode
- */
- mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1);
-
- pix_clk = mode1->Clock/1000.0;
- if (mode2)
- pix_clk2 = mode2->Clock/1000.0;
- else
- pix_clk2 = 0;
-
- peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes);
- if (pixel_bytes2)
- peak_disp_bw += (pix_clk2 * pixel_bytes2);
-
- if (peak_disp_bw >= mem_bw * min_mem_eff) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "You may not have enough display bandwidth for current mode\n"
- "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
- }
-
- /* CRTC1
- Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
- */
- stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
-
- /* setup Max GRPH_STOP_REQ default value */
- if (IS_RV100_VARIANT)
- max_stop_req = 0x5c;
- else
- max_stop_req = 0x7c;
- if (stop_req > max_stop_req)
- stop_req = max_stop_req;
-
- /* Get values from the EXT_MEM_CNTL register...converting its contents. */
- temp = INREG(RADEON_MEM_TIMING_CNTL);
- if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
- mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2];
- mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0];
- mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4];
- } else { /* RV200 and later */
- mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0];
- mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
- mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
- }
-
- /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
- temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
- data = (temp & (7<<20)) >> 20;
- if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
- mem_tcas = MemTcas [data];
- } else {
- mem_tcas = MemTcas2 [data];
- }
-
- if (IS_R300_VARIANT) {
-
- /* on the R300, Tcas is included in Trbs.
- */
- temp = INREG(RADEON_MEM_CNTL);
- data = (R300_MEM_NUM_CHANNELS_MASK & temp);
- if (data == 1) {
- if (R300_MEM_USE_CD_CH_ONLY & temp) {
- temp = INREG(R300_MC_IND_INDEX);
- temp &= ~R300_MC_IND_ADDR_MASK;
- temp |= R300_MC_READ_CNTL_CD_mcind;
- OUTREG(R300_MC_IND_INDEX, temp);
- temp = INREG(R300_MC_IND_DATA);
- data = (R300_MEM_RBS_POSITION_C_MASK & temp);
- } else {
- temp = INREG(R300_MC_READ_CNTL_AB);
- data = (R300_MEM_RBS_POSITION_A_MASK & temp);
- }
- } else {
- temp = INREG(R300_MC_READ_CNTL_AB);
- data = (R300_MEM_RBS_POSITION_A_MASK & temp);
- }
-
- mem_trbs = MemTrbs[data];
- mem_tcas += mem_trbs;
- }
-
- if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
- /* DDR64 SCLK_EFF = SCLK for analysis */
- sclk_eff = info->sclk;
- } else {
-#ifdef XF86DRI
- if (info->directRenderingEnabled)
- sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0);
- else
-#endif
- sclk_eff = info->sclk;
- }
-
- /* Find the memory controller latency for the display client.
- */
- if (IS_R300_VARIANT) {
- /*not enough for R350 ???*/
- /*
- if (!mode2) sclk_delay = 150;
- else {
- if (info->RamWidth == 256) sclk_delay = 87;
- else sclk_delay = 97;
- }
- */
- sclk_delay = 250;
- } else {
- if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
- info->IsIGP) {
- if (info->IsDDR) sclk_delay = 41;
- else sclk_delay = 33;
- } else {
- if (info->RamWidth == 128) sclk_delay = 57;
- else sclk_delay = 41;
- }
- }
-
- mc_latency_sclk = sclk_delay / sclk_eff;
-
- if (info->IsDDR) {
- if (info->RamWidth == 32) {
- k1 = 40;
- c = 3;
- } else {
- k1 = 20;
- c = 1;
- }
- } else {
- k1 = 40;
- c = 3;
- }
- mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) /
- info->mclk) + (4.0 / sclk_eff);
-
- /*
- HW cursor time assuming worst case of full size colour cursor.
- */
- cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk;
- cur_latency_sclk = cur_size / sclk_eff;
-
- /*
- Find the total latency for the display data.
- */
- disp_latency_overhead = 8.0 / info->sclk;
- mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk;
- mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk;
- disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
-
- /*
- Find the drain rate of the display buffer.
- */
- disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes);
- if (pixel_bytes2)
- disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2);
- else
- disp_drain_rate2 = 0;
-
- /*
- Find the critical point of the display buffer.
- */
- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
-
- /* ???? */
- /*
- temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
- if (critical_point < temp) critical_point = temp;
- */
- if (info->DispPriority == 2) {
- critical_point = 0;
- }
-
- /*
- The critical point should never be above max_stop_req-4. Setting
- GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
- */
- if (max_stop_req - critical_point < 4) critical_point = 0;
-
- if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
- /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
- critical_point = 0x10;
- }
-
- temp = info->SavedReg->grph_buffer_cntl;
- temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
- temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
- temp &= ~(RADEON_GRPH_START_REQ_MASK);
- if ((info->ChipFamily == CHIP_FAMILY_R350) &&
- (stop_req > 0x15)) {
- stop_req -= 0x10;
- }
- temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
-
- temp |= RADEON_GRPH_BUFFER_SIZE;
- temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
- RADEON_GRPH_CRITICAL_AT_SOF |
- RADEON_GRPH_STOP_CNTL);
- /*
- Write the result into the register.
- */
- OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
- (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg->grph_buffer_cntl,
- (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
-
- if (mode2) {
- stop_req = mode2->HDisplay * pixel_bytes2 / 16;
-
- if (stop_req > max_stop_req) stop_req = max_stop_req;
-
- temp = info->SavedReg->grph2_buffer_cntl;
- temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
- temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
- temp &= ~(RADEON_GRPH_START_REQ_MASK);
- if ((info->ChipFamily == CHIP_FAMILY_R350) &&
- (stop_req > 0x15)) {
- stop_req -= 0x10;
- }
- temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
- temp |= RADEON_GRPH_BUFFER_SIZE;
- temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
- RADEON_GRPH_CRITICAL_AT_SOF |
- RADEON_GRPH_STOP_CNTL);
-
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200))
- critical_point2 = 0;
- else {
- read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128));
- time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate);
-
- critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority +
- disp_latency) * disp_drain_rate2 + 0.5);
-
- if (info->DispPriority == 2) {
- critical_point2 = 0;
- }
-
- if (max_stop_req - critical_point2 < 4) critical_point2 = 0;
-
- }
-
- if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) {
- /* some R300 cards have problem with this set to 0 */
- critical_point2 = 0x10;
- }
-
- OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
- (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "GRPH2_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg->grph2_buffer_cntl,
- (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL));
- }
-}
-
-void
-RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- DisplayModePtr mode1, mode2;
- int pixel_bytes2 = 0;
-
- if (info->IsPrimary || info->IsSecondary)
- mode1 = &xf86_config->crtc[0]->mode;
- else
- mode1 = info->CurrentLayout.mode;
- mode2 = NULL;
- pixel_bytes2 = info->CurrentLayout.pixel_bytes;
-
- if (xf86_config->num_crtc == 2) {
- pixel_bytes2 = 0;
- mode2 = NULL;
-
- if (xf86_config->crtc[1]->enabled && xf86_config->crtc[0]->enabled) {
- pixel_bytes2 = info->CurrentLayout.pixel_bytes;
- mode1 = &xf86_config->crtc[0]->mode;
- mode2 = &xf86_config->crtc[1]->mode;
- } else if (xf86_config->crtc[0]->enabled) {
- mode1 = &xf86_config->crtc[0]->mode;
- } else if (xf86_config->crtc[1]->enabled) {
- mode1 = &xf86_config->crtc[1]->mode;
- } else
- return;
- } else {
- if (xf86_config->crtc[0]->enabled)
- mode1 = &xf86_config->crtc[0]->mode;
- else
- return;
- }
-
- RADEONInitDispBandwidth2(pScrn, info, pixel_bytes2, mode1, mode2);
-}
-
-void
-legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
- DisplayModePtr adjusted_mode, int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- Bool tilingOld = info->tilingEnabled;
- int i = 0;
- double dot_clock = 0;
- int pll_flags = RADEON_PLL_LEGACY;
- Bool update_tv_routing = FALSE;
-
-
- if (info->allowColorTiling) {
- info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
-#ifdef XF86DRI
- if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
- RADEONSAREAPrivPtr pSAREAPriv;
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failed changing tiling status\n");
- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
- info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
- }
-#endif
- }
-
- for (i = 0; i < xf86_config->num_output; i++) {
- xf86OutputPtr output = xf86_config->output[i];
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (output->crtc == crtc) {
- if (radeon_output->MonType != MT_CRT)
- pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
- if (radeon_output->MonType == MT_LCD)
- pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV);
- }
- }
-
-
- ErrorF("init memmap\n");
- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
- ErrorF("init common\n");
- RADEONInitCommonRegisters(info->ModeReg, info);
-
- RADEONInitSurfaceCntl(crtc, info->ModeReg);
-
- switch (radeon_crtc->crtc_id) {
- case 0:
- ErrorF("init crtc1\n");
- RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode);
- RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
- dot_clock = adjusted_mode->Clock / 1000.0;
- if (dot_clock) {
- ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
- } else {
- info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
- info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
- info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl;
- }
- break;
- case 1:
- ErrorF("init crtc2\n");
- RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode);
- RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
- dot_clock = adjusted_mode->Clock / 1000.0;
- if (dot_clock) {
- ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
- }
- break;
- }
-
- for (i = 0; i < xf86_config->num_output; i++) {
- xf86OutputPtr output = xf86_config->output[i];
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (output->crtc == crtc) {
- if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- switch (radeon_crtc->crtc_id) {
- case 0:
- RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
- RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
- update_tv_routing = TRUE;
- break;
- case 1:
- RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
- RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
- break;
- }
- }
- }
- }
-
- ErrorF("restore memmap\n");
- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
- ErrorF("restore common\n");
- RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
-
- switch (radeon_crtc->crtc_id) {
- case 0:
- ErrorF("restore crtc1\n");
- RADEONRestoreCrtcRegisters(pScrn, info->ModeReg);
- ErrorF("restore pll1\n");
- RADEONRestorePLLRegisters(pScrn, info->ModeReg);
- break;
- case 1:
- ErrorF("restore crtc2\n");
- RADEONRestoreCrtc2Registers(pScrn, info->ModeReg);
- ErrorF("restore pll2\n");
- RADEONRestorePLL2Registers(pScrn, info->ModeReg);
- break;
- }
-
- /* pixclks_cntl handles tv-out clock routing */
- if (update_tv_routing)
- radeon_update_tv_routing(pScrn, info->ModeReg);
-
- if (info->DispPriority)
- RADEONInitDispBandwidth(pScrn);
-
- if (info->tilingEnabled != tilingOld) {
- /* need to redraw front buffer, I guess this can be considered a hack ? */
- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
- if (pScrn->pScreen)
- xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE);
- RADEONChangeSurfaces(pScrn);
- if (pScrn->pScreen)
- xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE);
- /* xf86SetRootClip would do, but can't access that here */
- }
-
- /* reset ecp_div for Xv */
- info->ecp_div = -1;
-
-}
-
diff --git a/src/legacy_output.c b/src/legacy_output.c
deleted file mode 100644
index 0de13df..0000000
--- a/src/legacy_output.c
+++ /dev/null
@@ -1,1763 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include <stdio.h>
-
-/* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "vgaHW.h"
-#include "xf86Modes.h"
-
-/* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#include "radeon_tv.h"
-#include "radeon_atombios.h"
-
-static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn);
-static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color);
-static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
-static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn);
-
-void
-RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (IS_R300_VARIANT)
- OUTREGP(RADEON_GPIOPAD_A, restore->gpiopad_a, ~1);
-
- OUTREGP(RADEON_DAC_CNTL,
- restore->dac_cntl,
- RADEON_DAC_RANGE_CNTL |
- RADEON_DAC_BLANKING);
-
- OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
-
- if ((info->ChipFamily != CHIP_FAMILY_RADEON) &&
- (info->ChipFamily != CHIP_FAMILY_R200))
- OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
-
- OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
-
- if ((info->ChipFamily == CHIP_FAMILY_R200) ||
- IS_R300_VARIANT) {
- OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
- } else {
- OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
- }
-
- OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl);
-
- /* R200 DAC connected via DVO */
- if (info->ChipFamily == CHIP_FAMILY_R200)
- OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
-}
-
-
-/* Write TMDS registers */
-void
-RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl);
- OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
- OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);
-
- /* old AIW Radeon has some BIOS initialization problem
- * with display buffer underflow, only occurs to DFP
- */
- if (!pRADEONEnt->HasCRTC2)
- OUTREG(RADEON_GRPH_BUFFER_CNTL,
- INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
-
-}
-
-/* Write FP2 registers */
-void
-RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
-
-}
-
-/* Write RMX registers */
-void
-RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch);
- OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch);
- OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl);
- OUTREG(RADEON_FP_HORZ_VERT_ACTIVE, restore->fp_horz_vert_active);
- OUTREG(RADEON_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
- OUTREG(RADEON_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
- OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
- OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
-
-}
-
-/* Write LVDS registers */
-void
-RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->IsMobility) {
- OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
- /*OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl);*/
-
- if (info->ChipFamily == CHIP_FAMILY_RV410) {
- OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
- }
- }
-
-}
-
-void
-RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- save->dac_cntl = INREG(RADEON_DAC_CNTL);
- save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
- save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
- save->disp_tv_out_cntl = INREG(RADEON_DISP_TV_OUT_CNTL);
- save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG);
- save->dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
- save->gpiopad_a = INREG(RADEON_GPIOPAD_A);
-
-}
-
-/* Read flat panel registers */
-void
-RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- save->fp_gen_cntl = INREG(RADEON_FP_GEN_CNTL);
- save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL);
- save->fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
- save->fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
- save->fp_horz_vert_active = INREG(RADEON_FP_HORZ_VERT_ACTIVE);
- save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
- save->lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL);
- save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL);
- save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL);
- save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL);
-
- save->fp_h_sync_strt_wid = INREG(RADEON_FP_H_SYNC_STRT_WID);
- save->fp_v_sync_strt_wid = INREG(RADEON_FP_V_SYNC_STRT_WID);
- save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP);
- save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP);
-
- if (info->ChipFamily == CHIP_FAMILY_RV280) {
- /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
- save->tmds_pll_cntl ^= (1 << 22);
- }
-}
-
-Bool
-RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch)
-{
- if (!xf86I2CReadByte(dvo, addr, ch)) {
- xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR,
- "Unable to read from %s Slave %d.\n",
- dvo->pI2CBus->BusName, dvo->SlaveAddr);
- return FALSE;
- }
- return TRUE;
-}
-
-Bool
-RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch)
-{
- if (!xf86I2CWriteByte(dvo, addr, ch)) {
- xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR,
- "Unable to write to %s Slave %d.\n",
- dvo->pI2CBus->BusName, dvo->SlaveAddr);
- return FALSE;
- }
- return TRUE;
-}
-
-I2CDevPtr
-RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr)
-{
- I2CDevPtr dvo;
-
- dvo = xcalloc(1, sizeof(I2CDevRec));
- if (dvo == NULL)
- return NULL;
-
- dvo->DevName = "RADEON DVO Controller";
- dvo->SlaveAddr = addr;
- dvo->pI2CBus = b;
- dvo->StartTimeout = b->StartTimeout;
- dvo->BitTimeout = b->BitTimeout;
- dvo->AcknTimeout = b->AcknTimeout;
- dvo->ByteTimeout = b->ByteTimeout;
-
- if (xf86I2CDevInit(dvo)) {
- return dvo;
- }
-
- xfree(dvo);
- return NULL;
-}
-
-static void
-RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (!radeon_output->DVOChip)
- return;
-
- OUTREG(radeon_output->dvo_i2c.mask_clk_reg,
- INREG(radeon_output->dvo_i2c.mask_clk_reg) &
- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
-
- if (!RADEONInitExtTMDSInfoFromBIOS(output)) {
- if (radeon_output->DVOChip) {
- switch(info->ext_tmds_chip) {
- case RADEON_SIL_164:
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x30);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x09, 0x00);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0a, 0x90);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0c, 0x89);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x3b);
- break;
-#if 0
- /* needs work see bug 10418 */
- case RADEON_SIL_1178:
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0f, 0x44);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0f, 0x4c);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0e, 0x01);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0a, 0x80);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x09, 0x30);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0c, 0xc9);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x0d, 0x70);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x32);
- RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x33);
- break;
-#endif
- default:
- break;
- }
- }
- }
-}
-
-#if 0
-static RADEONMonitorType
-RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int bConnected = 0;
-
- /* the monitor either wasn't connected or it is a non-DDC CRT.
- * try to probe it
- */
- if(IsCrtDac) {
- unsigned long ulOrigVCLK_ECP_CNTL;
- unsigned long ulOrigDAC_CNTL;
- unsigned long ulOrigDAC_MACRO_CNTL;
- unsigned long ulOrigDAC_EXT_CNTL;
- unsigned long ulOrigCRTC_EXT_CNTL;
- unsigned long ulData;
- unsigned long ulMask;
-
- ulOrigVCLK_ECP_CNTL = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
-
- ulData = ulOrigVCLK_ECP_CNTL;
- ulData &= ~(RADEON_PIXCLK_ALWAYS_ONb
- | RADEON_PIXCLK_DAC_ALWAYS_ONb);
- ulMask = ~(RADEON_PIXCLK_ALWAYS_ONb
- |RADEON_PIXCLK_DAC_ALWAYS_ONb);
- OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask);
-
- ulOrigCRTC_EXT_CNTL = INREG(RADEON_CRTC_EXT_CNTL);
- ulData = ulOrigCRTC_EXT_CNTL;
- ulData |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, ulData);
-
- ulOrigDAC_EXT_CNTL = INREG(RADEON_DAC_EXT_CNTL);
- ulData = ulOrigDAC_EXT_CNTL;
- ulData &= ~RADEON_DAC_FORCE_DATA_MASK;
- ulData |= (RADEON_DAC_FORCE_BLANK_OFF_EN
- |RADEON_DAC_FORCE_DATA_EN
- |RADEON_DAC_FORCE_DATA_SEL_MASK);
- if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280))
- ulData |= (0x01b6 << RADEON_DAC_FORCE_DATA_SHIFT);
- else
- ulData |= (0x01ac << RADEON_DAC_FORCE_DATA_SHIFT);
-
- OUTREG(RADEON_DAC_EXT_CNTL, ulData);
-
- /* turn on power so testing can go through */
- ulOrigDAC_CNTL = INREG(RADEON_DAC_CNTL);
- ulOrigDAC_CNTL &= ~RADEON_DAC_PDWN;
- OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL);
-
- ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL);
- ulOrigDAC_MACRO_CNTL &= ~(RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G |
- RADEON_DAC_PDWN_B);
- OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL);
-
- /* Enable comparators and set DAC range to PS2 (VGA) output level */
- ulData = ulOrigDAC_CNTL;
- ulData |= RADEON_DAC_CMP_EN;
- ulData &= ~RADEON_DAC_RANGE_CNTL_MASK;
- ulData |= 0x2;
- OUTREG(RADEON_DAC_CNTL, ulData);
-
- /* Settle down */
- usleep(10000);
-
- /* Read comparators */
- ulData = INREG(RADEON_DAC_CNTL);
- bConnected = (RADEON_DAC_CMP_OUTPUT & ulData)?1:0;
-
- /* Restore things */
- ulData = ulOrigVCLK_ECP_CNTL;
- ulMask = 0xFFFFFFFFL;
- OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask);
-
- OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL );
- OUTREG(RADEON_DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL );
- OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL);
-
- if (!bConnected) {
- /* Power DAC down if CRT is not connected */
- ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL);
- ulOrigDAC_MACRO_CNTL |= (RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G |
- RADEON_DAC_PDWN_B);
- OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL);
-
- ulData = INREG(RADEON_DAC_CNTL);
- ulData |= RADEON_DAC_PDWN;
- OUTREG(RADEON_DAC_CNTL, ulData);
- }
- } else { /* TV DAC */
-
- /* This doesn't seem to work reliably (maybe worse on some OEM cards),
- for now we always return false. If one wants to connected a
- non-DDC monitor on the DVI port when CRT port is also connected,
- he will need to explicitly tell the driver in the config file
- with Option MonitorLayout.
- */
- bConnected = FALSE;
-
-#if 0
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- unsigned long ulOrigGPIO_MONID;
- unsigned long ulOrigFP2_GEN_CNTL;
- unsigned long ulOrigDISP_OUTPUT_CNTL;
- unsigned long ulOrigCRTC2_GEN_CNTL;
- unsigned long ulOrigDISP_LIN_TRANS_GRPH_A;
- unsigned long ulOrigDISP_LIN_TRANS_GRPH_B;
- unsigned long ulOrigDISP_LIN_TRANS_GRPH_C;
- unsigned long ulOrigDISP_LIN_TRANS_GRPH_D;
- unsigned long ulOrigDISP_LIN_TRANS_GRPH_E;
- unsigned long ulOrigDISP_LIN_TRANS_GRPH_F;
- unsigned long ulOrigCRTC2_H_TOTAL_DISP;
- unsigned long ulOrigCRTC2_V_TOTAL_DISP;
- unsigned long ulOrigCRTC2_H_SYNC_STRT_WID;
- unsigned long ulOrigCRTC2_V_SYNC_STRT_WID;
- unsigned long ulData, i;
-
- ulOrigGPIO_MONID = INREG(RADEON_GPIO_MONID);
- ulOrigFP2_GEN_CNTL = INREG(RADEON_FP2_GEN_CNTL);
- ulOrigDISP_OUTPUT_CNTL = INREG(RADEON_DISP_OUTPUT_CNTL);
- ulOrigCRTC2_GEN_CNTL = INREG(RADEON_CRTC2_GEN_CNTL);
- ulOrigDISP_LIN_TRANS_GRPH_A = INREG(RADEON_DISP_LIN_TRANS_GRPH_A);
- ulOrigDISP_LIN_TRANS_GRPH_B = INREG(RADEON_DISP_LIN_TRANS_GRPH_B);
- ulOrigDISP_LIN_TRANS_GRPH_C = INREG(RADEON_DISP_LIN_TRANS_GRPH_C);
- ulOrigDISP_LIN_TRANS_GRPH_D = INREG(RADEON_DISP_LIN_TRANS_GRPH_D);
- ulOrigDISP_LIN_TRANS_GRPH_E = INREG(RADEON_DISP_LIN_TRANS_GRPH_E);
- ulOrigDISP_LIN_TRANS_GRPH_F = INREG(RADEON_DISP_LIN_TRANS_GRPH_F);
-
- ulOrigCRTC2_H_TOTAL_DISP = INREG(RADEON_CRTC2_H_TOTAL_DISP);
- ulOrigCRTC2_V_TOTAL_DISP = INREG(RADEON_CRTC2_V_TOTAL_DISP);
- ulOrigCRTC2_H_SYNC_STRT_WID = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
- ulOrigCRTC2_V_SYNC_STRT_WID = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
-
- ulData = INREG(RADEON_GPIO_MONID);
- ulData &= ~RADEON_GPIO_A_0;
- OUTREG(RADEON_GPIO_MONID, ulData);
-
- OUTREG(RADEON_FP2_GEN_CNTL, 0x0a000c0c);
-
- OUTREG(RADEON_DISP_OUTPUT_CNTL, 0x00000012);
-
- OUTREG(RADEON_CRTC2_GEN_CNTL, 0x06000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
- OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
- OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
- OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
- OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
-
- for (i = 0; i < 200; i++) {
- ulData = INREG(RADEON_GPIO_MONID);
- bConnected = (ulData & RADEON_GPIO_Y_0)?1:0;
- if (!bConnected) break;
-
- usleep(1000);
- }
-
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, ulOrigDISP_LIN_TRANS_GRPH_A);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, ulOrigDISP_LIN_TRANS_GRPH_B);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, ulOrigDISP_LIN_TRANS_GRPH_C);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, ulOrigDISP_LIN_TRANS_GRPH_D);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, ulOrigDISP_LIN_TRANS_GRPH_E);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, ulOrigDISP_LIN_TRANS_GRPH_F);
- OUTREG(RADEON_CRTC2_H_TOTAL_DISP, ulOrigCRTC2_H_TOTAL_DISP);
- OUTREG(RADEON_CRTC2_V_TOTAL_DISP, ulOrigCRTC2_V_TOTAL_DISP);
- OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, ulOrigCRTC2_H_SYNC_STRT_WID);
- OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, ulOrigCRTC2_V_SYNC_STRT_WID);
- OUTREG(RADEON_CRTC2_GEN_CNTL, ulOrigCRTC2_GEN_CNTL);
- OUTREG(RADEON_DISP_OUTPUT_CNTL, ulOrigDISP_OUTPUT_CNTL);
- OUTREG(RADEON_FP2_GEN_CNTL, ulOrigFP2_GEN_CNTL);
- OUTREG(RADEON_GPIO_MONID, ulOrigGPIO_MONID);
- } else {
- unsigned long ulOrigPIXCLKSDATA;
- unsigned long ulOrigTV_MASTER_CNTL;
- unsigned long ulOrigTV_DAC_CNTL;
- unsigned long ulOrigTV_PRE_DAC_MUX_CNTL;
- unsigned long ulOrigDAC_CNTL2;
- unsigned long ulData;
- unsigned long ulMask;
-
- ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
-
- ulData = ulOrigPIXCLKSDATA;
- ulData &= ~(RADEON_PIX2CLK_ALWAYS_ONb
- | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
- ulMask = ~(RADEON_PIX2CLK_ALWAYS_ONb
- | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask);
-
- ulOrigTV_MASTER_CNTL = INREG(RADEON_TV_MASTER_CNTL);
- ulData = ulOrigTV_MASTER_CNTL;
- ulData &= ~RADEON_TVCLK_ALWAYS_ONb;
- OUTREG(RADEON_TV_MASTER_CNTL, ulData);
-
- ulOrigDAC_CNTL2 = INREG(RADEON_DAC_CNTL2);
- ulData = ulOrigDAC_CNTL2;
- ulData &= ~RADEON_DAC2_DAC2_CLK_SEL;
- OUTREG(RADEON_DAC_CNTL2, ulData);
-
- ulOrigTV_DAC_CNTL = INREG(RADEON_TV_DAC_CNTL);
-
- ulData = 0x00880213;
- OUTREG(RADEON_TV_DAC_CNTL, ulData);
-
- ulOrigTV_PRE_DAC_MUX_CNTL = INREG(RADEON_TV_PRE_DAC_MUX_CNTL);
-
- ulData = (RADEON_Y_RED_EN
- | RADEON_C_GRN_EN
- | RADEON_CMP_BLU_EN
- | RADEON_RED_MX_FORCE_DAC_DATA
- | RADEON_GRN_MX_FORCE_DAC_DATA
- | RADEON_BLU_MX_FORCE_DAC_DATA);
- if (IS_R300_VARIANT)
- ulData |= 0x180 << RADEON_TV_FORCE_DAC_DATA_SHIFT;
- else
- ulData |= 0x1f5 << RADEON_TV_FORCE_DAC_DATA_SHIFT;
- OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulData);
-
- usleep(10000);
-
- ulData = INREG(RADEON_TV_DAC_CNTL);
- bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0;
-
- ulData = ulOrigPIXCLKSDATA;
- ulMask = 0xFFFFFFFFL;
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask);
-
- OUTREG(RADEON_TV_MASTER_CNTL, ulOrigTV_MASTER_CNTL);
- OUTREG(RADEON_DAC_CNTL2, ulOrigDAC_CNTL2);
- OUTREG(RADEON_TV_DAC_CNTL, ulOrigTV_DAC_CNTL);
- OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulOrigTV_PRE_DAC_MUX_CNTL);
- }
-#endif
- return MT_UNKNOWN;
- }
-
- return(bConnected ? MT_CRT : MT_NONE);
-}
-#endif
-
-RADEONMonitorType
-legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONMonitorType found = MT_NONE;
-
- if (OUTPUT_IS_TV) {
- if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
- if (radeon_output->type == OUTPUT_STV)
- found = MT_STV;
- else
- found = MT_CTV;
- } else {
- if (info->InternalTVOut) {
- if (radeon_output->load_detection)
- found = radeon_detect_tv(pScrn);
- else
- found = MT_NONE;
- }
- }
- } else {
- if (radeon_output->DACType == DAC_PRIMARY) {
- if (radeon_output->load_detection)
- found = radeon_detect_primary_dac(pScrn, TRUE);
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (radeon_output->load_detection) {
- if (info->ChipFamily == CHIP_FAMILY_R200)
- found = radeon_detect_ext_dac(pScrn);
- else
- found = radeon_detect_tv_dac(pScrn, TRUE);
- } else
- found = MT_NONE;
- }
- }
-
- return found;
-}
-
-/*
- * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant).
- *
- */
-static void
-RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (IsPrimaryDAC) {
- CARD32 dac_cntl;
- CARD32 dac_macro_cntl = 0;
- dac_cntl = INREG(RADEON_DAC_CNTL);
- dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
- if (IsOn) {
- dac_cntl &= ~RADEON_DAC_PDWN;
- dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
- RADEON_DAC_PDWN_G |
- RADEON_DAC_PDWN_B);
- } else {
- dac_cntl |= RADEON_DAC_PDWN;
- dac_macro_cntl |= (RADEON_DAC_PDWN_R |
- RADEON_DAC_PDWN_G |
- RADEON_DAC_PDWN_B);
- }
- OUTREG(RADEON_DAC_CNTL, dac_cntl);
- OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
- } else {
- CARD32 tv_dac_cntl;
- CARD32 fp2_gen_cntl;
-
- switch(info->ChipFamily)
- {
- case CHIP_FAMILY_R420:
- case CHIP_FAMILY_RV410:
- tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- if (IsOn) {
- tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
- R420_TV_DAC_GDACPD |
- R420_TV_DAC_BDACPD |
- RADEON_TV_DAC_BGSLEEP);
- } else {
- tv_dac_cntl |= (R420_TV_DAC_RDACPD |
- R420_TV_DAC_GDACPD |
- R420_TV_DAC_BDACPD |
- RADEON_TV_DAC_BGSLEEP);
- }
- OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
- break;
- case CHIP_FAMILY_R200:
- fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL);
- if (IsOn) {
- fp2_gen_cntl |= RADEON_FP2_DVO_EN;
- } else {
- fp2_gen_cntl &= ~RADEON_FP2_DVO_EN;
- }
- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
- break;
-
- default:
- tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- if (IsOn) {
- tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
- RADEON_TV_DAC_GDACPD |
- RADEON_TV_DAC_BDACPD |
- RADEON_TV_DAC_BGSLEEP);
- } else {
- tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
- RADEON_TV_DAC_GDACPD |
- RADEON_TV_DAC_BDACPD |
- RADEON_TV_DAC_BGSLEEP);
- }
- OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
- break;
- }
- }
-}
-
-/* This is to be used enable/disable displays dynamically */
-static void
-RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSavePtr save = info->ModeReg;
- unsigned char * RADEONMMIO = info->MMIO;
- unsigned long tmp;
- RADEONOutputPrivatePtr radeon_output;
- int tv_dac_change = 0, o;
- radeon_output = output->driver_private;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
-
- for (o = 0; o < xf86_config->num_output; o++) {
- if (output == xf86_config->output[o]) {
- break;
- }
- }
-
- if (bEnable) {
- ErrorF("enable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- info->output_crt1 |= (1 << o);
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- info->output_crt2 |= (1 << o);
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp |= RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- info->output_dfp1 |= (1 << o);
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- info->output_dfp2 |= (1 << o);
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~RADEON_FP2_BLANK_EN;
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- info->output_lcd1 |= (1 << o);
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
- usleep (radeon_output->PanelPwrDly * 1000);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
- } else if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- info->output_tv1 |= (1 << o);
- tmp = INREG(RADEON_TV_MASTER_CNTL);
- tmp |= RADEON_TV_ON;
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
- radeon_output->tv_on = TRUE;
- }
- } else {
- ErrorF("disable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- info->output_crt1 &= ~(1 << o);
- if (!info->output_crt1) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- }
- } else if (radeon_output->DACType == DAC_TVDAC) {
- info->output_crt2 &= ~(1 << o);
- tv_dac_change = 1;
- if (!info->output_crt2) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- }
- }
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- info->output_dfp1 &= ~(1 << o);
- if (!info->output_dfp1) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- }
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- info->output_dfp2 &= ~(1 << o);
- if (!info->output_dfp2) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
- }
- }
- } else if (radeon_output->MonType == MT_LCD) {
- info->output_lcd1 &= ~(1 << o);
- if (!info->output_lcd1) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
- }
- }
- } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- info->output_tv1 &= ~(1 << o);
- tv_dac_change = 2;
- if (!info->output_tv1) {
- tmp = INREG(RADEON_TV_MASTER_CNTL);
- tmp &= ~RADEON_TV_ON;
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- radeon_output->tv_on = FALSE;
- }
- }
- }
-
- if (tv_dac_change) {
- if (bEnable)
- info->tv_dac_enable_mask |= tv_dac_change;
- else
- info->tv_dac_enable_mask &= ~tv_dac_change;
-
- if (bEnable && info->tv_dac_enable_mask)
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- else if (!bEnable && info->tv_dac_enable_mask == 0)
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
-
- }
-}
-
-void
-legacy_output_dpms(xf86OutputPtr output, int mode)
-{
- switch(mode) {
- case DPMSModeOn:
- RADEONEnableDisplay(output, TRUE);
- break;
- case DPMSModeOff:
- case DPMSModeSuspend:
- case DPMSModeStandby:
- RADEONEnableDisplay(output, FALSE);
- break;
- }
-}
-
-static void
-RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int i;
- CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff;
-
- for (i=0; i<4; i++) {
- if (radeon_output->tmds_pll[i].freq == 0) break;
- if ((CARD32)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) {
- tmp = radeon_output->tmds_pll[i].value ;
- break;
- }
- }
-
- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RV280)) {
- if (tmp & 0xfff00000)
- save->tmds_pll_cntl = tmp;
- else {
- save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000;
- save->tmds_pll_cntl |= tmp;
- }
- } else save->tmds_pll_cntl = tmp;
-
- save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl &
- ~(RADEON_TMDS_TRANSMITTER_PLLRST);
-
- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2)
- save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
- else /* weird, RV chips got this bit reversed? */
- save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
-
- save->fp_gen_cntl = info->SavedReg->fp_gen_cntl |
- (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
- RADEON_FP_CRTC_DONT_SHADOW_HEND );
-
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
-
- if (pScrn->rgbBits == 8)
- save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
- else
- save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
-
-
- if (IsPrimary) {
- if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) {
- save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
- if (radeon_output->Flags & RADEON_USE_RMX)
- save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
- else
- save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
- } else
- save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
- } else {
- if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) {
- save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
- save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
- } else
- save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
- }
-
-}
-
-static void
-RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (pScrn->rgbBits == 8)
- save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl |
- RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
- else
- save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
- ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
-
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON |
- RADEON_FP2_DVO_EN |
- RADEON_FP2_DVO_RATE_SEL_SDR);
-
-
- /* XXX: these may be oem specific */
- if (IS_R300_VARIANT) {
- save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
-#if 0
- if (mode->Clock > 165000)
- save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;
-#endif
- }
-
- if (IsPrimary) {
- if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
- if (radeon_output->Flags & RADEON_USE_RMX)
- save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
- } else {
- save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
- }
- } else {
- if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
- save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
- } else {
- save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
- }
- }
-
-}
-
-static void
-RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl |
- RADEON_LVDS_PLL_EN);
-
- save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
-
- save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON |
- RADEON_LVDS_BLON |
- RADEON_LVDS_EN |
- RADEON_LVDS_RST_FM);
-
- if (IS_R300_VARIANT)
- save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
-
- if (IsPrimary) {
- if (IS_R300_VARIANT) {
- if (radeon_output->Flags & RADEON_USE_RMX)
- save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
- } else
- save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
- } else {
- if (IS_R300_VARIANT) {
- save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
- } else
- save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
- }
-
-}
-
-static void
-RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int xres = mode->HDisplay;
- int yres = mode->VDisplay;
- float Hratio, Vratio;
- int hsync_wid;
- int vsync_wid;
- int hsync_start;
-
-
- save->fp_vert_stretch = info->SavedReg->fp_vert_stretch &
- RADEON_VERT_STRETCH_RESERVED;
- save->fp_horz_stretch = info->SavedReg->fp_horz_stretch &
- (RADEON_HORZ_FP_LOOP_STRETCH |
- RADEON_HORZ_AUTO_RATIO_INC);
-
- save->crtc_more_cntl = 0;
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200)) {
- /* This is to workaround the asic bug for RMX, some versions
- of BIOS dosen't have this register initialized correctly.
- */
- save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
- }
-
-
- save->fp_crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
- | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff)
- << 16));
-
- hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
- if (!hsync_wid) hsync_wid = 1;
- hsync_start = mode->CrtcHSyncStart - 8;
-
- save->fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
- | ((hsync_wid & 0x3f) << 16)
- | ((mode->Flags & V_NHSYNC)
- ? RADEON_CRTC_H_SYNC_POL
- : 0));
-
- save->fp_crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
- | ((mode->CrtcVDisplay - 1) << 16));
-
- vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
- if (!vsync_wid) vsync_wid = 1;
-
- save->fp_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
- | ((vsync_wid & 0x1f) << 16)
- | ((mode->Flags & V_NVSYNC)
- ? RADEON_CRTC_V_SYNC_POL
- : 0));
-
- save->fp_horz_vert_active = 0;
-
- if (radeon_output->MonType != MT_LCD && radeon_output->MonType != MT_DFP)
- return;
-
- if (radeon_output->PanelXRes == 0 || radeon_output->PanelYRes == 0) {
- Hratio = 1.0;
- Vratio = 1.0;
- } else {
- if (xres > radeon_output->PanelXRes) xres = radeon_output->PanelXRes;
- if (yres > radeon_output->PanelYRes) yres = radeon_output->PanelYRes;
-
- Hratio = (float)xres/(float)radeon_output->PanelXRes;
- Vratio = (float)yres/(float)radeon_output->PanelYRes;
- }
-
- if ((Hratio == 1.0) || (!(radeon_output->Flags & RADEON_USE_RMX)) ||
- (radeon_output->rmx_type == RMX_CENTER)) {
- save->fp_horz_stretch |= ((xres/8-1)<<16);
- } else {
- save->fp_horz_stretch |= ((((unsigned long)
- (Hratio * RADEON_HORZ_STRETCH_RATIO_MAX)) &
- RADEON_HORZ_STRETCH_RATIO_MASK) |
- RADEON_HORZ_STRETCH_BLEND |
- RADEON_HORZ_STRETCH_ENABLE |
- ((radeon_output->PanelXRes/8-1)<<16));
- }
-
- if ((Vratio == 1.0) || (!(radeon_output->Flags & RADEON_USE_RMX)) ||
- (radeon_output->rmx_type == RMX_CENTER)) {
- save->fp_vert_stretch |= ((yres-1)<<12);
- } else {
- save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX)) &
- RADEON_VERT_STRETCH_RATIO_MASK) |
- RADEON_VERT_STRETCH_ENABLE |
- RADEON_VERT_STRETCH_BLEND |
- ((radeon_output->PanelYRes-1)<<12));
- }
-
- if ((radeon_output->rmx_type == RMX_CENTER) &&
- (radeon_output->Flags & RADEON_USE_RMX)) {
- int blank_width;
-
- save->crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
- RADEON_CRTC_AUTO_VERT_CENTER_EN);
-
- blank_width = (mode->CrtcHBlankEnd - mode->CrtcHBlankStart) / 8;
- if (blank_width > 110) blank_width = 110;
-
- save->fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
- | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff)
- << 16));
-
- hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8;
- if (!hsync_wid) hsync_wid = 1;
-
- save->fp_h_sync_strt_wid = ((((mode->CrtcHSyncStart - mode->CrtcHBlankStart) / 8) & 0x1fff)
- | ((hsync_wid & 0x3f) << 16)
- | ((mode->Flags & V_NHSYNC)
- ? RADEON_CRTC_H_SYNC_POL
- : 0));
-
- save->fp_crtc_v_total_disp = (((mode->CrtcVBlankEnd - mode->CrtcVBlankStart) & 0xffff)
- | ((mode->CrtcVDisplay - 1) << 16));
-
- vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
- if (!vsync_wid) vsync_wid = 1;
-
- save->fp_v_sync_strt_wid = ((((mode->CrtcVSyncStart - mode->CrtcVBlankStart) & 0xfff)
- | ((vsync_wid & 0x1f) << 16)
- | ((mode->Flags & V_NVSYNC)
- ? RADEON_CRTC_V_SYNC_POL
- : 0)));
-
- save->fp_horz_vert_active = (((radeon_output->PanelYRes) & 0xfff) |
- (((radeon_output->PanelXRes / 8) & 0x1ff) << 16));
-
- }
-}
-
-static void
-RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (IsPrimary) {
- if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg->disp_output_cntl &
- ~RADEON_DISP_DAC_SOURCE_MASK;
- } else {
- save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL);
- }
- } else {
- if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg->disp_output_cntl &
- ~RADEON_DISP_DAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
- } else {
- save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL;
- }
- }
- save->dac_cntl = (RADEON_DAC_MASK_ALL
- | RADEON_DAC_VGA_ADR_EN
- | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN));
-
- save->dac_macro_cntl = info->SavedReg->dac_macro_cntl;
-}
-
-static void
-RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (info->ChipFamily == CHIP_FAMILY_R420 ||
- info->ChipFamily == CHIP_FAMILY_RV410) {
- save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
- ~(RADEON_TV_DAC_STD_MASK |
- RADEON_TV_DAC_BGADJ_MASK |
- R420_TV_DAC_DACADJ_MASK |
- R420_TV_DAC_RDACPD |
- R420_TV_DAC_GDACPD |
- R420_TV_DAC_GDACPD |
- R420_TV_DAC_TVENABLE);
- } else {
- save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
- ~(RADEON_TV_DAC_STD_MASK |
- RADEON_TV_DAC_BGADJ_MASK |
- RADEON_TV_DAC_DACADJ_MASK |
- RADEON_TV_DAC_RDACPD |
- RADEON_TV_DAC_GDACPD |
- RADEON_TV_DAC_GDACPD);
- }
-
- save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
- RADEON_TV_DAC_NHOLD |
- RADEON_TV_DAC_STD_PS2 |
- radeon_output->ps2_tvdac_adj);
-
-}
-
-static void
-RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- /*0x0028023;*/
- RADEONInitTvDacCntl(output, save);
-
- if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg->gpiopad_a | 1;
-
- save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL;
-
- if (IsPrimary) {
- if (IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg->disp_output_cntl &
- ~RADEON_DISP_TVDAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
- } else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
- ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- } else {
- save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL;
- }
- } else {
- if (IS_R300_VARIANT) {
- save->disp_output_cntl = info->SavedReg->disp_output_cntl &
- ~RADEON_DISP_TVDAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
- } else if (info->ChipFamily == CHIP_FAMILY_R200) {
- save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
- ~(R200_FP2_SOURCE_SEL_MASK |
- RADEON_FP2_DVO_RATE_SEL_SDR);
- save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
- } else {
- save->disp_hw_debug = info->SavedReg->disp_hw_debug &
- ~RADEON_CRT2_DISP1_SEL;
- }
- }
-}
-
-static void
-RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output,
- int crtc_num)
-{
- Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (crtc_num == 0)
- RADEONInitRMXRegisters(output, save, mode);
-
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- RADEONInitDACRegisters(output, save, mode, IsPrimary);
- } else {
- RADEONInitDAC2Registers(output, save, mode, IsPrimary);
- }
- } else if (radeon_output->MonType == MT_LCD) {
- RADEONInitLVDSRegisters(output, save, mode, IsPrimary);
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- RADEONInitFPRegisters(output, save, mode, IsPrimary);
- } else {
- RADEONInitFP2Registers(output, save, mode, IsPrimary);
- }
- } else if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- RADEONInitTVRegisters(output, save, mode, IsPrimary);
- }
-}
-
-void
-legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- xf86CrtcPtr crtc = output->crtc;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- RADEONInitOutputRegisters(pScrn, info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id);
-
- if (radeon_crtc->crtc_id == 0)
- RADEONRestoreRMXRegisters(pScrn, info->ModeReg);
-
- switch(radeon_output->MonType) {
- case MT_LCD:
- ErrorF("restore LVDS\n");
- RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
- break;
- case MT_DFP:
- if (radeon_output->TMDSType == TMDS_INT) {
- ErrorF("restore FP\n");
- RADEONRestoreFPRegisters(pScrn, info->ModeReg);
- } else {
- ErrorF("restore FP2\n");
- if (info->IsAtomBios) {
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 fp2_gen_cntl;
-
- atombios_external_tmds_setup(output, mode);
- /* r4xx atom has hard coded crtc mappings in the atom code
- * Fix it up here.
- */
- fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL) & ~R200_FP2_SOURCE_SEL_MASK;
- if (radeon_crtc->crtc_id == 1)
- fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
- else {
- if (radeon_output->Flags & RADEON_USE_RMX)
- fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
- else
- fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
- }
- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
- } else {
- RADEONRestoreDVOChip(pScrn, output);
- RADEONRestoreFP2Registers(pScrn, info->ModeReg);
- }
- }
- break;
- case MT_STV:
- case MT_CTV:
- ErrorF("restore tv\n");
- RADEONRestoreDACRegisters(pScrn, info->ModeReg);
- RADEONRestoreTVRegisters(pScrn, info->ModeReg);
- break;
- default:
- ErrorF("restore dac\n");
- RADEONRestoreDACRegisters(pScrn, info->ModeReg);
- }
-
-}
-
-/* the following functions are based on the load detection code
- * in the beos radeon driver by Thomas Kurschel and the existing
- * load detection code in this driver.
- */
-static RADEONMonitorType
-radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 vclk_ecp_cntl, crtc_ext_cntl;
- CARD32 dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
- RADEONMonitorType found = MT_NONE;
-
- /* save the regs we need */
- vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
- crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
- dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
- dac_cntl = INREG(RADEON_DAC_CNTL);
- dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
-
- tmp = vclk_ecp_cntl &
- ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
-
- tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
-
- tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
- RADEON_DAC_FORCE_DATA_EN;
-
- if (color)
- tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
- else
- tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
-
- if (IS_R300_VARIANT)
- tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
- else
- tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
-
- OUTREG(RADEON_DAC_EXT_CNTL, tmp);
-
- tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
- tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
- OUTREG(RADEON_DAC_CNTL, tmp);
-
- tmp &= ~(RADEON_DAC_PDWN_R |
- RADEON_DAC_PDWN_G |
- RADEON_DAC_PDWN_B);
-
- OUTREG(RADEON_DAC_MACRO_CNTL, tmp);
-
- usleep(2000);
-
- if (INREG(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) {
- found = MT_CRT;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "Found %s CRT connected to primary DAC\n",
- color ? "color" : "bw");
- }
-
- /* restore the regs we used */
- OUTREG(RADEON_DAC_CNTL, dac_cntl);
- OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
- OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
- OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
-
- return found;
-}
-
-static RADEONMonitorType
-radeon_detect_ext_dac(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
- CARD32 disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
- CARD32 disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
- CARD32 tmp, crtc2_h_total_disp, crtc2_v_total_disp;
- CARD32 crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
- RADEONMonitorType found = MT_NONE;
- int connected = 0;
- int i = 0;
-
- /* save the regs we need */
- gpio_monid = INREG(RADEON_GPIO_MONID);
- fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL);
- disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- disp_lin_trans_grph_a = INREG(RADEON_DISP_LIN_TRANS_GRPH_A);
- disp_lin_trans_grph_b = INREG(RADEON_DISP_LIN_TRANS_GRPH_B);
- disp_lin_trans_grph_c = INREG(RADEON_DISP_LIN_TRANS_GRPH_C);
- disp_lin_trans_grph_d = INREG(RADEON_DISP_LIN_TRANS_GRPH_D);
- disp_lin_trans_grph_e = INREG(RADEON_DISP_LIN_TRANS_GRPH_E);
- disp_lin_trans_grph_f = INREG(RADEON_DISP_LIN_TRANS_GRPH_F);
- crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP);
- crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP);
- crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
- crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
-
- tmp = INREG(RADEON_GPIO_MONID);
- tmp &= ~RADEON_GPIO_A_0;
- OUTREG(RADEON_GPIO_MONID, tmp);
-
- OUTREG(RADEON_FP2_GEN_CNTL,
- RADEON_FP2_ON |
- RADEON_FP2_PANEL_FORMAT |
- R200_FP2_SOURCE_SEL_TRANS_UNIT |
- RADEON_FP2_DVO_EN |
- R200_FP2_DVO_RATE_SEL_SDR);
-
- OUTREG(RADEON_DISP_OUTPUT_CNTL,
- RADEON_DISP_DAC_SOURCE_RMX |
- RADEON_DISP_TRANS_MATRIX_GRAPHICS);
-
- OUTREG(RADEON_CRTC2_GEN_CNTL,
- RADEON_CRTC2_EN |
- RADEON_CRTC2_DISP_REQ_EN_B);
-
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
-
- OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
- OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
- OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
- OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
-
- for (i = 0; i < 200; i++) {
- tmp = INREG(RADEON_GPIO_MONID);
- if (tmp & RADEON_GPIO_Y_0)
- connected = 1;
- else
- connected = 0;
-
- if (!connected)
- break;
-
- usleep(1000);
- }
-
- if (connected)
- found = MT_CRT;
-
- /* restore the regs we used */
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
- OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
- OUTREG(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
- OUTREG(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
- OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
- OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
- OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
- OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
- OUTREG(RADEON_GPIO_MONID, gpio_monid);
-
- return found;
-}
-
-static RADEONMonitorType
-radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
- CARD32 disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
- RADEONMonitorType found = MT_NONE;
-
- /* save the regs we need */
- pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- gpiopad_a = IS_R300_VARIANT ? INREG(RADEON_GPIOPAD_A) : 0;
- disp_output_cntl = IS_R300_VARIANT ? INREG(RADEON_DISP_OUTPUT_CNTL) : 0;
- disp_hw_debug = !IS_R300_VARIANT ? INREG(RADEON_DISP_HW_DEBUG) : 0;
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
- dac_cntl2 = INREG(RADEON_DAC_CNTL2);
-
- tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
- | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
-
- if (IS_R300_VARIANT) {
- OUTREGP(RADEON_GPIOPAD_A, 1, ~1 );
- }
-
- tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
- tmp |= RADEON_CRTC2_CRT2_ON |
- (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
-
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
-
- if (IS_R300_VARIANT) {
- tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
- tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
- OUTREG(RADEON_DISP_OUTPUT_CNTL, tmp);
- } else {
- tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
- OUTREG(RADEON_DISP_HW_DEBUG, tmp);
- }
-
- tmp = RADEON_TV_DAC_NBLANK |
- RADEON_TV_DAC_NHOLD |
- RADEON_TV_MONITOR_DETECT_EN |
- RADEON_TV_DAC_STD_PS2;
-
- OUTREG(RADEON_TV_DAC_CNTL, tmp);
-
- tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
- RADEON_DAC2_FORCE_DATA_EN;
-
- if (color)
- tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
- else
- tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
-
- if (IS_R300_VARIANT)
- tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
- else
- tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
-
- OUTREG(RADEON_DAC_EXT_CNTL, tmp);
-
- tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
- OUTREG(RADEON_DAC_CNTL2, tmp);
-
- usleep(10000);
-
- if (IS_R300_VARIANT) {
- if (INREG(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) {
- found = MT_CRT;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "Found %s CRT connected to TV DAC\n",
- color ? "color" : "bw");
- }
- } else {
- if (INREG(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) {
- found = MT_CRT;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "Found %s CRT connected to TV DAC\n",
- color ? "color" : "bw");
- }
- }
-
- /* restore regs we used */
- OUTREG(RADEON_DAC_CNTL2, dac_cntl2);
- OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
- OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
- OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
-
- if (IS_R300_VARIANT) {
- OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
- OUTREGP(RADEON_GPIOPAD_A, gpiopad_a, ~1 );
- } else {
- OUTREG(RADEON_DISP_HW_DEBUG, disp_hw_debug);
- }
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, pixclks_cntl);
-
- return found;
-}
-
-static RADEONMonitorType
-r300_detect_tv(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl;
- CARD32 gpiopad_a, disp_output_cntl;
- RADEONMonitorType found = MT_NONE;
-
- /* save the regs we need */
- gpiopad_a = INREG(RADEON_GPIOPAD_A);
- dac_cntl2 = INREG(RADEON_DAC_CNTL2);
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL);
- tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
-
- OUTREGP(RADEON_GPIOPAD_A, 0, ~1 );
-
- OUTREG(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL );
-
- OUTREG(RADEON_CRTC2_GEN_CNTL,
- RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT );
-
- tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
- tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
- OUTREG(RADEON_DISP_OUTPUT_CNTL, tmp);
-
- OUTREG(RADEON_DAC_EXT_CNTL,
- RADEON_DAC2_FORCE_BLANK_OFF_EN |
- RADEON_DAC2_FORCE_DATA_EN |
- RADEON_DAC_FORCE_DATA_SEL_RGB |
- (0xec << RADEON_DAC_FORCE_DATA_SHIFT ));
-
- OUTREG(RADEON_TV_DAC_CNTL,
- RADEON_TV_DAC_STD_NTSC |
- (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
- (6 << RADEON_TV_DAC_DACADJ_SHIFT ));
-
- INREG(RADEON_TV_DAC_CNTL);
-
- usleep(4000);
-
- OUTREG(RADEON_TV_DAC_CNTL,
- RADEON_TV_DAC_NBLANK |
- RADEON_TV_DAC_NHOLD |
- RADEON_TV_MONITOR_DETECT_EN |
- RADEON_TV_DAC_STD_NTSC |
- (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
- (6 << RADEON_TV_DAC_DACADJ_SHIFT ));
-
- INREG(RADEON_TV_DAC_CNTL);
-
- usleep(6000);
-
- tmp = INREG(RADEON_TV_DAC_CNTL);
- if ( (tmp & RADEON_TV_DAC_GDACDET) != 0 ) {
- found = MT_STV;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "S-Video TV connection detected\n");
- } else if ( (tmp & RADEON_TV_DAC_BDACDET) != 0 ) {
- found = MT_CTV;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "Composite TV connection detected\n" );
- }
-
- OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl );
- OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
- OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
- OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
- OUTREG(RADEON_DAC_CNTL2, dac_cntl2);
- OUTREGP(RADEON_GPIOPAD_A, gpiopad_a, ~1);
-
- return found;
-}
-
-static RADEONMonitorType
-radeon_detect_tv(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp, dac_cntl2, tv_master_cntl;
- CARD32 tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl;
- RADEONMonitorType found = MT_NONE;
-
- if (IS_R300_VARIANT)
- return r300_detect_tv(pScrn);
-
- /* save the regs we need */
- dac_cntl2 = INREG(RADEON_DAC_CNTL2);
- tv_master_cntl = INREG(RADEON_TV_MASTER_CNTL);
- tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- config_cntl = INREG(RADEON_CONFIG_CNTL);
- tv_pre_dac_mux_cntl = INREG(RADEON_TV_PRE_DAC_MUX_CNTL);
-
- tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
- OUTREG(RADEON_DAC_CNTL2, tmp);
-
- tmp = tv_master_cntl | RADEON_TV_ON;
- tmp &= ~(RADEON_TV_ASYNC_RST |
- RADEON_RESTART_PHASE_FIX |
- RADEON_CRT_FIFO_CE_EN |
- RADEON_TV_FIFO_CE_EN |
- RADEON_RE_SYNC_NOW_SEL_MASK);
- tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
-
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
-
- tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
- RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
- (8 << RADEON_TV_DAC_BGADJ_SHIFT);
-
- if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
- tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
- else
- tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
-
- OUTREG(RADEON_TV_DAC_CNTL, tmp);
-
- tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
- RADEON_RED_MX_FORCE_DAC_DATA |
- RADEON_GRN_MX_FORCE_DAC_DATA |
- RADEON_BLU_MX_FORCE_DAC_DATA |
- (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
-
- OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
-
- usleep(3000);
-
- tmp = INREG(RADEON_TV_DAC_CNTL);
- if (tmp & RADEON_TV_DAC_GDACDET) {
- found = MT_STV;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "S-Video TV connection detected\n");
- } else if (tmp & RADEON_TV_DAC_BDACDET) {
- found = MT_CTV;
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "Composite TV connection detected\n" );
- }
-
- OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
- OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
- OUTREG(RADEON_TV_MASTER_CNTL, tv_master_cntl);
- OUTREG(RADEON_DAC_CNTL2, dac_cntl2);
-
- return found;
-}
diff --git a/src/local_xf86Rename.h b/src/local_xf86Rename.h
deleted file mode 100644
index 5102170..0000000
--- a/src/local_xf86Rename.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright © 2006 Keith Packard
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of the copyright holders not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. The copyright holders make no representations
- * about the suitability of this software for any purpose. It is provided "as
- * is" without express or implied warranty.
- *
- * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
- * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
- * OF THIS SOFTWARE.
- */
-
-#define XF86NAME(x) radeon_##x
diff --git a/src/radeon.h b/src/radeon.h
deleted file mode 100644
index aba3c0f..0000000
--- a/src/radeon.h
+++ /dev/null
@@ -1,1187 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- *
- */
-
-#ifndef _RADEON_H_
-#define _RADEON_H_
-
-#include <stdlib.h> /* For abs() */
-#include <unistd.h> /* For usleep() */
-#include <sys/time.h> /* For gettimeofday() */
-
-#include "config.h"
-#include "xf86str.h"
-#include "compiler.h"
-#include "xf86fbman.h"
-
- /* PCI support */
-#include "xf86Pci.h"
-
-#ifdef USE_EXA
-#include "exa.h"
-#endif
-#ifdef USE_XAA
-#include "xaa.h"
-#endif
-
- /* Exa and Cursor Support */
-#include "vbe.h"
-#include "xf86Cursor.h"
-
- /* DDC support */
-#include "xf86DDC.h"
-
- /* Xv support */
-#include "xf86xv.h"
-
-#include "radeon_probe.h"
-#include "radeon_tv.h"
-
- /* DRI support */
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "radeon_dripriv.h"
-#include "dri.h"
-#include "GL/glxint.h"
-#ifdef DAMAGE
-#include "damage.h"
-#include "globals.h"
-#endif
-#endif
-
-#include "xf86Crtc.h"
-#include "X11/Xatom.h"
-
- /* Render support */
-#ifdef RENDER
-#include "picturestr.h"
-#endif
-
-#include "atipcirename.h"
-
-#ifndef MAX
-#define MAX(a,b) ((a)>(b)?(a):(b))
-#endif
-#ifndef MIN
-#define MIN(a,b) ((a)>(b)?(b):(a))
-#endif
-
-#ifndef HAVE_XF86MODEBANDWIDTH
-extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth);
-#define MODE_BANDWIDTH MODE_BAD
-#endif
-
-typedef enum {
- OPTION_NOACCEL,
- OPTION_SW_CURSOR,
- OPTION_DAC_6BIT,
- OPTION_DAC_8BIT,
-#ifdef XF86DRI
- OPTION_BUS_TYPE,
- OPTION_CP_PIO,
- OPTION_USEC_TIMEOUT,
- OPTION_AGP_MODE,
- OPTION_AGP_FW,
- OPTION_GART_SIZE,
- OPTION_GART_SIZE_OLD,
- OPTION_RING_SIZE,
- OPTION_BUFFER_SIZE,
- OPTION_DEPTH_MOVE,
- OPTION_PAGE_FLIP,
- OPTION_NO_BACKBUFFER,
- OPTION_XV_DMA,
- OPTION_FBTEX_PERCENT,
- OPTION_DEPTH_BITS,
- OPTION_PCIAPER_SIZE,
-#ifdef USE_EXA
- OPTION_ACCEL_DFS,
-#endif
-#endif
- OPTION_DDC_MODE,
- OPTION_IGNORE_EDID,
- OPTION_DISP_PRIORITY,
- OPTION_PANEL_SIZE,
- OPTION_MIN_DOTCLOCK,
- OPTION_COLOR_TILING,
-#ifdef XvExtension
- OPTION_VIDEO_KEY,
- OPTION_RAGE_THEATRE_CRYSTAL,
- OPTION_RAGE_THEATRE_TUNER_PORT,
- OPTION_RAGE_THEATRE_COMPOSITE_PORT,
- OPTION_RAGE_THEATRE_SVIDEO_PORT,
- OPTION_TUNER_TYPE,
- OPTION_RAGE_THEATRE_MICROC_PATH,
- OPTION_RAGE_THEATRE_MICROC_TYPE,
- OPTION_SCALER_WIDTH,
-#endif
-#ifdef RENDER
- OPTION_RENDER_ACCEL,
- OPTION_SUBPIXEL_ORDER,
-#endif
- OPTION_SHOWCACHE,
- OPTION_DYNAMIC_CLOCKS,
- OPTION_BIOS_HOTKEYS,
- OPTION_VGA_ACCESS,
- OPTION_REVERSE_DDC,
- OPTION_LVDS_PROBE_PLL,
- OPTION_ACCELMETHOD,
- OPTION_CONNECTORTABLE,
- OPTION_DRI,
- OPTION_DEFAULT_CONNECTOR_TABLE,
-#if defined(__powerpc__)
- OPTION_MAC_MODEL,
-#endif
- OPTION_DEFAULT_TMDS_PLL,
- OPTION_TVDAC_LOAD_DETECT,
- OPTION_FORCE_TVOUT,
- OPTION_TVSTD,
- OPTION_IGNORE_LID_STATUS
-} RADEONOpts;
-
-
-#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
-#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
-
-#define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */
-
-/* Buffer are aligned on 4096 byte boundaries */
-#define RADEON_BUFFER_ALIGN 0x00000fff
-#define RADEON_VBIOS_SIZE 0x00010000
-#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
- * Need to comfirm this is not used
- * for something else.
- */
-
-#define xFixedToFloat(f) (((float) (f)) / 65536)
-
-#define RADEON_LOGLEVEL_DEBUG 4
-
-/* for Xv, outputs */
-#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
-
-/* Other macros */
-#define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
-#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
-#define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate)
-
-typedef struct {
- int revision;
- CARD16 rr1_offset;
- CARD16 rr2_offset;
- CARD16 dyn_clk_offset;
- CARD16 pll_offset;
- CARD16 mem_config_offset;
- CARD16 mem_reset_offset;
- CARD16 short_mem_offset;
- CARD16 rr3_offset;
- CARD16 rr4_offset;
-} RADEONBIOSInitTable;
-
-#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
-#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
-#define RADEON_PLL_USE_REF_DIV (1 << 2)
-#define RADEON_PLL_LEGACY (1 << 3)
-
-typedef struct {
- CARD16 reference_freq;
- CARD16 reference_div;
- CARD32 pll_in_min;
- CARD32 pll_in_max;
- CARD32 pll_out_min;
- CARD32 pll_out_max;
- CARD16 xclk;
-
- CARD32 min_ref_div;
- CARD32 max_ref_div;
- CARD32 min_post_div;
- CARD32 max_post_div;
- CARD32 min_feedback_div;
- CARD32 max_feedback_div;
- CARD32 best_vco;
-} RADEONPLLRec, *RADEONPLLPtr;
-
-typedef struct {
- int bitsPerPixel;
- int depth;
- int displayWidth;
- int displayHeight;
- int pixel_code;
- int pixel_bytes;
- DisplayModePtr mode;
-} RADEONFBLayout;
-
-typedef enum {
- CHIP_FAMILY_UNKNOW,
- CHIP_FAMILY_LEGACY,
- CHIP_FAMILY_RADEON,
- CHIP_FAMILY_RV100,
- CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
- CHIP_FAMILY_RV200,
- CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
- CHIP_FAMILY_R200,
- CHIP_FAMILY_RV250,
- CHIP_FAMILY_RS300, /* RS300/RS350 */
- CHIP_FAMILY_RV280,
- CHIP_FAMILY_R300,
- CHIP_FAMILY_R350,
- CHIP_FAMILY_RV350,
- CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
- CHIP_FAMILY_R420, /* R420/R423/M18 */
- CHIP_FAMILY_RV410, /* RV410, M26 */
- CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
- CHIP_FAMILY_RV515, /* rv515 */
- CHIP_FAMILY_R520, /* r520 */
- CHIP_FAMILY_RV530, /* rv530 */
- CHIP_FAMILY_R580, /* r580 */
- CHIP_FAMILY_RV560, /* rv560 */
- CHIP_FAMILY_RV570, /* rv570 */
- CHIP_FAMILY_RS690,
- CHIP_FAMILY_R600, /* r60 */
- CHIP_FAMILY_R630,
- CHIP_FAMILY_RV610,
- CHIP_FAMILY_RV630,
- CHIP_FAMILY_RV670,
- CHIP_FAMILY_RS740,
- CHIP_FAMILY_LAST
-} RADEONChipFamily;
-
-#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \
- (info->ChipFamily == CHIP_FAMILY_RV200) || \
- (info->ChipFamily == CHIP_FAMILY_RS100) || \
- (info->ChipFamily == CHIP_FAMILY_RS200) || \
- (info->ChipFamily == CHIP_FAMILY_RV250) || \
- (info->ChipFamily == CHIP_FAMILY_RV280) || \
- (info->ChipFamily == CHIP_FAMILY_RS300))
-
-
-#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \
- (info->ChipFamily == CHIP_FAMILY_RV350) || \
- (info->ChipFamily == CHIP_FAMILY_R350) || \
- (info->ChipFamily == CHIP_FAMILY_RV380) || \
- (info->ChipFamily == CHIP_FAMILY_R420) || \
- (info->ChipFamily == CHIP_FAMILY_RV410) || \
- (info->ChipFamily == CHIP_FAMILY_RS400))
-
-#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
-
-/*
- * Errata workarounds
- */
-typedef enum {
- CHIP_ERRATA_R300_CG = 0x00000001,
- CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
- CHIP_ERRATA_PLL_DELAY = 0x00000004
-} RADEONErrata;
-
-typedef enum {
- RADEON_DVOCHIP_NONE,
- RADEON_SIL_164,
- RADEON_SIL_1178
-} RADEONExtTMDSChip;
-
-#if defined(__powerpc__)
-typedef enum {
- RADEON_MAC_NONE,
- RADEON_MAC_IBOOK,
- RADEON_MAC_POWERBOOK_EXTERNAL,
- RADEON_MAC_POWERBOOK_INTERNAL,
- RADEON_MAC_POWERBOOK_VGA,
- RADEON_MAC_MINI_EXTERNAL,
- RADEON_MAC_MINI_INTERNAL,
- RADEON_MAC_IMAC_G5_ISIGHT
-} RADEONMacModel;
-#endif
-
-typedef enum {
- CARD_PCI,
- CARD_AGP,
- CARD_PCIE
-} RADEONCardType;
-
-typedef struct _atomBiosHandle *atomBiosHandlePtr;
-
-typedef struct {
- CARD32 pci_device_id;
- RADEONChipFamily chip_family;
- int mobility;
- int igp;
- int nocrtc2;
- int nointtvout;
- int singledac;
-} RADEONCardInfo;
-
-typedef struct {
- EntityInfoPtr pEnt;
- pciVideoPtr PciInfo;
- PCITAG PciTag;
- int Chipset;
- RADEONChipFamily ChipFamily;
- RADEONErrata ChipErrata;
-
- unsigned long LinearAddr; /* Frame buffer physical address */
- unsigned long MMIOAddr; /* MMIO region physical address */
- unsigned long BIOSAddr; /* BIOS physical address */
- CARD32 fbLocation;
- CARD32 gartLocation;
- CARD32 mc_fb_location;
- CARD32 mc_agp_location;
- CARD32 mc_agp_location_hi;
-
- void *MMIO; /* Map of MMIO region */
- void *FB; /* Map of frame buffer */
- CARD8 *VBIOS; /* Video BIOS pointer */
-
- Bool IsAtomBios; /* New BIOS used in R420 etc. */
- int ROMHeaderStart; /* Start of the ROM Info Table */
- int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */
-
- CARD32 MemCntl;
- CARD32 BusCntl;
- unsigned long MMIOSize; /* MMIO region physical address */
- unsigned long FbMapSize; /* Size of frame buffer, in bytes */
- unsigned long FbSecureSize; /* Size of secured fb area at end of
- framebuffer */
-
- Bool IsMobility; /* Mobile chips for laptops */
- Bool IsIGP; /* IGP chips */
- Bool HasSingleDAC; /* only TVDAC on chip */
- Bool ddc_mode; /* Validate mode by matching exactly
- * the modes supported in DDC data
- */
- Bool R300CGWorkaround;
-
- /* EDID or BIOS values for FPs */
- int RefDivider;
- int FeedbackDivider;
- int PostDivider;
- Bool UseBiosDividers;
- /* EDID data using DDC interface */
- Bool ddc_bios;
- Bool ddc1;
- Bool ddc2;
-
- RADEONPLLRec pll;
-
- int RamWidth;
- float sclk; /* in MHz */
- float mclk; /* in MHz */
- Bool IsDDR;
- int DispPriority;
-
- RADEONSavePtr SavedReg; /* Original (text) mode */
- RADEONSavePtr ModeReg; /* Current mode */
- Bool (*CloseScreen)(int, ScreenPtr);
-
- void (*BlockHandler)(int, pointer, pointer, pointer);
-
- Bool PaletteSavedOnVT; /* Palette saved on last VT switch */
-
-#ifdef USE_EXA
- ExaDriverPtr exa;
- int exaSyncMarker;
- int exaMarkerSynced;
- int engineMode;
-#define EXA_ENGINEMODE_UNKNOWN 0
-#define EXA_ENGINEMODE_2D 1
-#define EXA_ENGINEMODE_3D 2
-#ifdef XF86DRI
- Bool accelDFS;
-#endif
-#endif
-#ifdef USE_XAA
- XAAInfoRecPtr accel;
-#endif
- Bool accelOn;
- xf86CursorInfoPtr cursor;
- Bool allowColorTiling;
- Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
-#ifdef ARGB_CURSOR
- Bool cursor_argb;
-#endif
- int cursor_fg;
- int cursor_bg;
-
-#ifdef USE_XAA
- /*
- * XAAForceTransBlit is used to change the behavior of the XAA
- * SetupForScreenToScreenCopy function, to make it DGA-friendly.
- */
- Bool XAAForceTransBlit;
-#endif
-
- int fifo_slots; /* Free slots in the FIFO (64 max) */
- int pix24bpp; /* Depth of pixmap for 24bpp fb */
- Bool dac6bits; /* Use 6 bit DAC? */
-
- /* Computed values for Radeon */
- int pitch;
- int datatype;
- CARD32 dp_gui_master_cntl;
- CARD32 dp_gui_master_cntl_clip;
- CARD32 trans_color;
-
- /* Saved values for ScreenToScreenCopy */
- int xdir;
- int ydir;
-
-#ifdef USE_XAA
- /* ScanlineScreenToScreenColorExpand support */
- unsigned char *scratch_buffer[1];
- unsigned char *scratch_save;
- int scanline_x;
- int scanline_y;
- int scanline_w;
- int scanline_h;
- int scanline_h_w;
- int scanline_words;
- int scanline_direct;
- int scanline_bpp; /* Only used for ImageWrite */
- int scanline_fg;
- int scanline_bg;
- int scanline_hpass;
- int scanline_x1clip;
- int scanline_x2clip;
-#endif
- /* Saved values for DashedTwoPointLine */
- int dashLen;
- CARD32 dashPattern;
- int dash_fg;
- int dash_bg;
-
- DGAModePtr DGAModes;
- int numDGAModes;
- Bool DGAactive;
- int DGAViewportStatus;
- DGAFunctionRec DGAFuncs;
-
- RADEONFBLayout CurrentLayout;
- CARD32 dst_pitch_offset;
-#ifdef XF86DRI
- Bool noBackBuffer;
- Bool directRenderingEnabled;
- Bool directRenderingInited;
- Bool newMemoryMap;
- drmVersionPtr pLibDRMVersion;
- drmVersionPtr pKernelDRMVersion;
- DRIInfoPtr pDRIInfo;
- int drmFD;
- int numVisualConfigs;
- __GLXvisualConfig *pVisualConfigs;
- RADEONConfigPrivPtr pVisualConfigsPriv;
- Bool (*DRICloseScreen)(int, ScreenPtr);
-
- drm_handle_t fbHandle;
-
- drmSize registerSize;
- drm_handle_t registerHandle;
-
- RADEONCardType cardType; /* Current card is a PCI card */
- drmSize pciSize;
- drm_handle_t pciMemHandle;
- unsigned char *PCI; /* Map */
-
- Bool depthMoves; /* Enable depth moves -- slow! */
- Bool allowPageFlip; /* Enable 3d page flipping */
-#ifdef DAMAGE
- DamagePtr pDamage;
- RegionRec driRegion;
-#endif
- Bool have3DWindows; /* Are there any 3d clients? */
-
- int pciAperSize;
- drmSize gartSize;
- drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */
- unsigned long gartOffset;
- unsigned char *AGP; /* Map */
- int agpMode;
-
- CARD32 pciCommand;
-
- Bool CPRuns; /* CP is running */
- Bool CPInUse; /* CP has been used by X server */
- Bool CPStarted; /* CP has started */
- int CPMode; /* CP mode that server/clients use */
- int CPFifoSize; /* Size of the CP command FIFO */
- int CPusecTimeout; /* CP timeout in usecs */
- Bool needCacheFlush;
-
- /* CP ring buffer data */
- unsigned long ringStart; /* Offset into GART space */
- drm_handle_t ringHandle; /* Handle from drmAddMap */
- drmSize ringMapSize; /* Size of map */
- int ringSize; /* Size of ring (in MB) */
- drmAddress ring; /* Map */
- int ringSizeLog2QW;
-
- unsigned long ringReadOffset; /* Offset into GART space */
- drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */
- drmSize ringReadMapSize; /* Size of map */
- drmAddress ringReadPtr; /* Map */
-
- /* CP vertex/indirect buffer data */
- unsigned long bufStart; /* Offset into GART space */
- drm_handle_t bufHandle; /* Handle from drmAddMap */
- drmSize bufMapSize; /* Size of map */
- int bufSize; /* Size of buffers (in MB) */
- drmAddress buf; /* Map */
- int bufNumBufs; /* Number of buffers */
- drmBufMapPtr buffers; /* Buffer map */
-
- /* CP GART Texture data */
- unsigned long gartTexStart; /* Offset into GART space */
- drm_handle_t gartTexHandle; /* Handle from drmAddMap */
- drmSize gartTexMapSize; /* Size of map */
- int gartTexSize; /* Size of GART tex space (in MB) */
- drmAddress gartTex; /* Map */
- int log2GARTTexGran;
-
- /* CP accleration */
- drmBufPtr indirectBuffer;
- int indirectStart;
-
- /* DRI screen private data */
- int fbX;
- int fbY;
- int backX;
- int backY;
- int depthX;
- int depthY;
-
- int frontOffset;
- int frontPitch;
- int backOffset;
- int backPitch;
- int depthOffset;
- int depthPitch;
- int depthBits;
- int textureOffset;
- int textureSize;
- int log2TexGran;
-
- int pciGartSize;
- CARD32 pciGartOffset;
- void *pciGartBackup;
-#ifdef USE_XAA
- CARD32 frontPitchOffset;
- CARD32 backPitchOffset;
- CARD32 depthPitchOffset;
-
- /* offscreen memory management */
- int backLines;
- FBAreaPtr backArea;
- int depthTexLines;
- FBAreaPtr depthTexArea;
-#endif
-
- /* Saved scissor values */
- CARD32 sc_left;
- CARD32 sc_right;
- CARD32 sc_top;
- CARD32 sc_bottom;
-
- CARD32 re_top_left;
- CARD32 re_width_height;
-
- CARD32 aux_sc_cntl;
-
- int irq;
-
- Bool DMAForXv;
-
-#ifdef PER_CONTEXT_SAREA
- int perctx_sarea_size;
-#endif
-
- /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
- int dma_begin_count;
- char *dma_debug_func;
- int dma_debug_lineno;
-#endif /* XF86DRI */
-
- /* XVideo */
- XF86VideoAdaptorPtr adaptor;
- void (*VideoTimerCallback)(ScrnInfoPtr, Time);
- int videoKey;
- int RageTheatreCrystal;
- int RageTheatreTunerPort;
- int RageTheatreCompositePort;
- int RageTheatreSVideoPort;
- int tunerType;
- char* RageTheatreMicrocPath;
- char* RageTheatreMicrocType;
- Bool MM_TABLE_valid;
- struct {
- CARD8 table_revision;
- CARD8 table_size;
- CARD8 tuner_type;
- CARD8 audio_chip;
- CARD8 product_id;
- CARD8 tuner_voltage_teletext_fm;
- CARD8 i2s_config; /* configuration of the sound chip */
- CARD8 video_decoder_type;
- CARD8 video_decoder_host_config;
- CARD8 input[5];
- } MM_TABLE;
- CARD16 video_decoder_type;
- int overlay_scaler_buffer_width;
- int ecp_div;
-
- /* Render */
- Bool RenderAccel;
- unsigned short texW[2];
- unsigned short texH[2];
-#ifdef USE_XAA
- FBLinearPtr RenderTex;
- void (*RenderCallback)(ScrnInfoPtr);
- Time RenderTimeout;
-#endif
-
- /* general */
- Bool showCache;
- OptionInfoPtr Options;
-
- Bool useEXA;
-#ifdef USE_EXA
- XF86ModReqInfo exaReq;
-#endif
-#ifdef USE_XAA
- XF86ModReqInfo xaaReq;
-#endif
-
- /* X itself has the 3D context */
- Bool XInited3D;
-
- DisplayModePtr currentMode, savedCurrentMode;
-
- /* special handlings for DELL triple-head server */
- Bool IsDellServer;
-
- Bool VGAAccess;
-
- int MaxSurfaceWidth;
- int MaxLines;
-
- CARD32 tv_dac_adj;
- CARD32 tv_dac_enable_mask;
-
- Bool want_vblank_interrupts;
- RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR];
- RADEONBIOSInitTable BiosTable;
-
- /* save crtc state for console restore */
- Bool crtc_on;
- Bool crtc2_on;
-
- Bool InternalTVOut;
- int tvdac_use_count;
-
-#if defined(__powerpc__)
- RADEONMacModel MacModel;
-#endif
- RADEONExtTMDSChip ext_tmds_chip;
-
- atomBiosHandlePtr atomBIOS;
- unsigned long FbFreeStart, FbFreeSize;
- unsigned char* BIOSCopy;
-
- /* output enable masks for outputs shared across connectors */
- int output_crt1;
- int output_crt2;
- int output_dfp1;
- int output_dfp2;
- int output_lcd1;
- int output_tv1;
-
- Rotation rotation;
- void (*PointerMoved)(int, int, int);
- CreateScreenResourcesProcPtr CreateScreenResources;
-
- /* if no devices are connected at server startup */
- Bool first_load_no_devices;
-
- Bool IsSecondary;
- Bool IsPrimary;
-
- Bool r600_shadow_fb;
- void *fb_shadow;
-} RADEONInfoRec, *RADEONInfoPtr;
-
-#define RADEONWaitForFifo(pScrn, entries) \
-do { \
- if (info->fifo_slots < entries) \
- RADEONWaitForFifoFunction(pScrn, entries); \
- info->fifo_slots -= entries; \
-} while (0)
-
-extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
-extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
-extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
-#ifdef XF86DRI
-extern int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value);
-extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
-#endif
-
-extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y,
- Bool clone);
-
-extern void RADEONEngineReset(ScrnInfoPtr pScrn);
-extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
-extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
-
-extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
-extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
-
-extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
-extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
-
-extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
-extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
-
-extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
-
-extern Bool RADEONAccelInit(ScreenPtr pScreen);
-#ifdef USE_EXA
-extern Bool RADEONSetupMemEXA (ScreenPtr pScreen);
-extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
-#ifdef XF86DRI
-extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
-extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type);
-extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
- CARD32 *pitch_offset);
-extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
-extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
- CARD32 src_pitch_offset,
- CARD32 dst_pitch_offset,
- CARD32 datatype, int rop,
- Pixel planemask);
-extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
- int dstY, int w, int h);
-#endif
-#endif
-#ifdef USE_XAA
-extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
-#endif
-extern void RADEONEngineInit(ScrnInfoPtr pScrn);
-extern Bool RADEONCursorInit(ScreenPtr pScreen);
-extern Bool RADEONDGAInit(ScreenPtr pScreen);
-
-extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
-
-extern int RADEONMinBits(int val);
-
-extern void RADEONInitVideo(ScreenPtr pScreen);
-extern void RADEONResetVideo(ScrnInfoPtr pScrn);
-extern void R300CGWorkaround(ScrnInfoPtr pScrn);
-
-extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
-extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
-
-extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
-extern Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn);
-extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn);
-extern Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output);
-
-extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-
-extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr save,
- RADEONInfoPtr info);
-extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
-extern Bool RADEONI2cInit(ScrnInfoPtr pScrn);
-extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
-extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
-extern void RADEONDisableDisplays(ScrnInfoPtr pScrn);
-extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
-extern void RADEONUnblank(ScrnInfoPtr pScrn);
-extern void RADEONUnblank(ScrnInfoPtr pScrn);
-extern void RADEONBlank(ScrnInfoPtr pScrn);
-
-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
-extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
-
-extern void RADEONSetPitch (ScrnInfoPtr pScrn);
-extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
-
-extern DisplayModePtr
-RADEONProbeOutputModes(xf86OutputPtr output);
-
-extern Bool
-RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch);
-extern Bool
-RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch);
-extern Bool
-RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool
-RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
-
-extern RADEONI2CBusRec
-legacy_setup_i2c_bus(int ddc_line);
-extern RADEONI2CBusRec
-atom_setup_i2c_bus(int ddc_line);
-
-extern void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-extern void
-radeon_crtc_show_cursor (xf86CrtcPtr crtc);
-extern void
-radeon_crtc_hide_cursor (xf86CrtcPtr crtc);
-extern void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-extern void
-radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
-extern void
-radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
-extern void
-radeon_crtc_load_lut(xf86CrtcPtr crtc);
-
-extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output);
-extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output);
-extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output);
-extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output);
-extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary);
-
-extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
-
-extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, CARD32 *chosen_dot_clock_freq,
- CARD32 *chosen_feedback_div, CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div, int flags);
-
-#ifdef XF86DRI
-#ifdef USE_XAA
-extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
-#endif
-extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
-extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
-extern void RADEONDRICloseScreen(ScreenPtr pScreen);
-extern void RADEONDRIResume(ScreenPtr pScreen);
-extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
-extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
-extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
-extern void RADEONDRIStop(ScreenPtr pScreen);
-
-extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
-extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
-extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
-extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info);
-extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
-
-extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst,
- CARD32 pitch, int cpp,
- CARD32 *dstPitchOffset, int *x, int *y);
-extern CARD8* RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
- unsigned int w, CARD32 dstPitchOff,
- CARD32 *bufPitch, int x, int *y,
- unsigned int *h, unsigned int *hpass);
-extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn,
- unsigned int bpp,
- CARD8 *dst, CARD8 *src,
- unsigned int hpass,
- unsigned int dstPitch,
- unsigned int srcPitch);
-extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size,
- int swap);
-
-#define RADEONCP_START(pScrn, info) \
-do { \
- int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_START); \
- if (_ret) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "%s: CP start %d\n", __FUNCTION__, _ret); \
- } \
- info->CPStarted = TRUE; \
-} while (0)
-
-#define RADEONCP_RELEASE(pScrn, info) \
-do { \
- if (info->CPInUse) { \
- RADEON_PURGE_CACHE(); \
- RADEON_WAIT_UNTIL_IDLE(); \
- RADEONCPReleaseIndirect(pScrn); \
- info->CPInUse = FALSE; \
- } \
-} while (0)
-
-#define RADEONCP_STOP(pScrn, info) \
-do { \
- int _ret; \
- if (info->CPStarted) { \
- _ret = RADEONCPStop(pScrn, info); \
- if (_ret) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "%s: CP stop %d\n", __FUNCTION__, _ret); \
- } \
- info->CPStarted = FALSE; \
- } \
- RADEONEngineRestore(pScrn); \
- info->CPRuns = FALSE; \
-} while (0)
-
-#define RADEONCP_RESET(pScrn, info) \
-do { \
- if (RADEONCP_USE_RING_BUFFER(info->CPMode)) { \
- int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \
- if (_ret) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "%s: CP reset %d\n", __FUNCTION__, _ret); \
- } \
- } \
-} while (0)
-
-#define RADEONCP_REFRESH(pScrn, info) \
-do { \
- if (!info->CPInUse) { \
- if (info->needCacheFlush) { \
- RADEON_PURGE_CACHE(); \
- RADEON_PURGE_ZCACHE(); \
- info->needCacheFlush = FALSE; \
- } \
- RADEON_WAIT_UNTIL_IDLE(); \
- BEGIN_RING(6); \
- OUT_RING_REG(RADEON_RE_TOP_LEFT, info->re_top_left); \
- OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height); \
- OUT_RING_REG(RADEON_AUX_SC_CNTL, info->aux_sc_cntl); \
- ADVANCE_RING(); \
- info->CPInUse = TRUE; \
- } \
-} while (0)
-
-
-#define CP_PACKET0(reg, n) \
- (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
-#define CP_PACKET1(reg0, reg1) \
- (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
-#define CP_PACKET2() \
- (RADEON_CP_PACKET2)
-#define CP_PACKET3(pkt, n) \
- (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
-
-
-#define RADEON_VERBOSE 0
-
-#define RING_LOCALS CARD32 *__head = NULL; int __expected; int __count = 0
-
-#define BEGIN_RING(n) do { \
- if (RADEON_VERBOSE) { \
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
- "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
- } \
- if (++info->dma_begin_count != 1) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "BEGIN_RING without end at %s:%d\n", \
- info->dma_debug_func, info->dma_debug_lineno); \
- info->dma_begin_count = 1; \
- } \
- info->dma_debug_func = __FILE__; \
- info->dma_debug_lineno = __LINE__; \
- if (!info->indirectBuffer) { \
- info->indirectBuffer = RADEONCPGetBuffer(pScrn); \
- info->indirectStart = 0; \
- } else if (info->indirectBuffer->used + (n) * (int)sizeof(CARD32) > \
- info->indirectBuffer->total) { \
- RADEONCPFlushIndirect(pScrn, 1); \
- } \
- __expected = n; \
- __head = (pointer)((char *)info->indirectBuffer->address + \
- info->indirectBuffer->used); \
- __count = 0; \
-} while (0)
-
-#define ADVANCE_RING() do { \
- if (info->dma_begin_count-- != 1) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "ADVANCE_RING without begin at %s:%d\n", \
- __FILE__, __LINE__); \
- info->dma_begin_count = 0; \
- } \
- if (__count != __expected) { \
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
- "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \
- __count, __expected, __FILE__, __LINE__); \
- } \
- if (RADEON_VERBOSE) { \
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
- "ADVANCE_RING() start: %d used: %d count: %d\n", \
- info->indirectStart, \
- info->indirectBuffer->used, \
- __count * (int)sizeof(CARD32)); \
- } \
- info->indirectBuffer->used += __count * (int)sizeof(CARD32); \
-} while (0)
-
-#define OUT_RING(x) do { \
- if (RADEON_VERBOSE) { \
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
- " OUT_RING(0x%08x)\n", (unsigned int)(x)); \
- } \
- __head[__count++] = (x); \
-} while (0)
-
-#define OUT_RING_REG(reg, val) \
-do { \
- OUT_RING(CP_PACKET0(reg, 0)); \
- OUT_RING(val); \
-} while (0)
-
-#define FLUSH_RING() \
-do { \
- if (RADEON_VERBOSE) \
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
- "FLUSH_RING in %s\n", __FUNCTION__); \
- if (info->indirectBuffer) { \
- RADEONCPFlushIndirect(pScrn, 0); \
- } \
-} while (0)
-
-
-#define RADEON_WAIT_UNTIL_2D_IDLE() \
-do { \
- BEGIN_RING(2); \
- OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
- OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
- RADEON_WAIT_HOST_IDLECLEAN)); \
- ADVANCE_RING(); \
-} while (0)
-
-#define RADEON_WAIT_UNTIL_3D_IDLE() \
-do { \
- BEGIN_RING(2); \
- OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
- OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \
- RADEON_WAIT_HOST_IDLECLEAN)); \
- ADVANCE_RING(); \
-} while (0)
-
-#define RADEON_WAIT_UNTIL_IDLE() \
-do { \
- if (RADEON_VERBOSE) { \
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
- "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \
- } \
- BEGIN_RING(2); \
- OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
- OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
- RADEON_WAIT_3D_IDLECLEAN | \
- RADEON_WAIT_HOST_IDLECLEAN)); \
- ADVANCE_RING(); \
-} while (0)
-
-#define RADEON_PURGE_CACHE() \
-do { \
- BEGIN_RING(2); \
- OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
- OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
- ADVANCE_RING(); \
-} while (0)
-
-#define RADEON_PURGE_ZCACHE() \
-do { \
- OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
- OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
-} while (0)
-
-#endif /* XF86DRI */
-
-static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
-{
-#ifdef USE_EXA
- if (info->useEXA)
- exaMarkSync(pScrn->pScreen);
-#endif
-#ifdef USE_XAA
- if (!info->useEXA)
- SET_SYNC_FLAG(info->accel);
-#endif
-}
-
-static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
-{
-#ifdef USE_EXA
- if (info->useEXA)
- exaWaitSync(pScrn->pScreen);
-#endif
-#ifdef USE_XAA
- if (!info->useEXA && info->accel)
- info->accel->Sync(pScrn);
-#endif
-}
-
-static __inline__ void radeon_init_timeout(struct timeval *endtime,
- unsigned int timeout)
-{
- gettimeofday(endtime, NULL);
- endtime->tv_usec += timeout;
- endtime->tv_sec += endtime->tv_usec / 1000000;
- endtime->tv_usec %= 1000000;
-}
-
-static __inline__ int radeon_timedout(const struct timeval *endtime)
-{
- struct timeval now;
- gettimeofday(&now, NULL);
- return now.tv_sec == endtime->tv_sec ?
- now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec;
-}
-
-#endif /* _RADEON_H_ */
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
deleted file mode 100644
index 8b2f167..0000000
--- a/src/radeon_accel.c
+++ /dev/null
@@ -1,1254 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- *
- * Credits:
- *
- * Thanks to Ani Joshi <ajoshi at shell.unixbox.com> for providing source
- * code to his Radeon driver. Portions of this file are based on the
- * initialization code for that driver.
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- * Notes on unimplemented XAA optimizations:
- *
- * SetClipping: This has been removed as XAA expects 16bit registers
- * for full clipping.
- * TwoPointLine: The Radeon supports this. Not Bresenham.
- * DashedLine with non-power-of-two pattern length: Apparently, there is
- * no way to set the length of the pattern -- it is always
- * assumed to be 8 or 32 (or 1024?).
- * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference
- * Manual where it states that monochrome expansion of frame
- * buffer data is not supported.
- * CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid
- * direct/indirect method. If we had more data registers,
- * then we could do better. If XAA supported a trigger write
- * address, the code would be simpler.
- * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8
- * pattern from frame buffer memory.
- * ImageWrites: Same as CPUToScreenColorExpandFill
- *
- */
-
-#include <errno.h>
-#include <string.h>
- /* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_common.h"
-#include "radeon_sarea.h"
-#endif
-
- /* Line support */
-#include "miline.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-
-
-#ifdef USE_XAA
-static struct {
- int rop;
- int pattern;
-} RADEON_ROP[] = {
- { RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */
- { RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */
- { RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */
- { RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */
- { RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */
- { RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */
- { RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */
- { RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */
- { RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */
- { RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */
- { RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */
- { RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */
- { RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */
- { RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */
- { RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */
- { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */
-};
-#endif
-
-/* The FIFO has 64 slots. This routines waits until at least `entries'
- * of these slots are empty.
- */
-void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int i;
-
- for (;;) {
- for (i = 0; i < RADEON_TIMEOUT; i++) {
- info->fifo_slots =
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
- if (info->fifo_slots >= entries) return;
- }
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "FIFO timed out: %u entries, stat=0x%08x\n",
- (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- (unsigned int)INREG(RADEON_RBBM_STATUS));
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "FIFO timed out, resetting engine...\n");
- RADEONEngineReset(pScrn);
- RADEONEngineRestore(pScrn);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_RESET(pScrn, info);
- RADEONCP_START(pScrn, info);
- }
-#endif
- }
-}
-
-/* Flush all dirty data in the Pixel Cache to memory */
-void RADEONEngineFlush(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int i;
-
- OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT,
- RADEON_RB3D_DC_FLUSH_ALL,
- ~RADEON_RB3D_DC_FLUSH_ALL);
- for (i = 0; i < RADEON_TIMEOUT; i++) {
- if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY))
- break;
- }
- if (i == RADEON_TIMEOUT) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "DC flush timeout: %x\n",
- (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
- }
-}
-
-/* Reset graphics card to known state */
-void RADEONEngineReset(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 clock_cntl_index;
- CARD32 mclk_cntl;
- CARD32 rbbm_soft_reset;
- CARD32 host_path_cntl;
-
- /* The following RBBM_SOFT_RESET sequence can help un-wedge
- * an R300 after the command processor got stuck.
- */
- rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
- RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_HI |
- RADEON_SOFT_RESET_SE |
- RADEON_SOFT_RESET_RE |
- RADEON_SOFT_RESET_PP |
- RADEON_SOFT_RESET_E2 |
- RADEON_SOFT_RESET_RB));
- INREG(RADEON_RBBM_SOFT_RESET);
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32)
- ~(RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_HI |
- RADEON_SOFT_RESET_SE |
- RADEON_SOFT_RESET_RE |
- RADEON_SOFT_RESET_PP |
- RADEON_SOFT_RESET_E2 |
- RADEON_SOFT_RESET_RB)));
- INREG(RADEON_RBBM_SOFT_RESET);
- OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
- INREG(RADEON_RBBM_SOFT_RESET);
-
- RADEONEngineFlush(pScrn);
-
- clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
- RADEONPllErrataAfterIndex(info);
-
-#if 0 /* taken care of by new PM code */
- /* Some ASICs have bugs with dynamic-on feature, which are
- * ASIC-version dependent, so we force all blocks on for now
- */
- if (info->HasCRTC2) {
- CARD32 tmp;
-
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) |
- RADEON_CP_MAX_DYN_STOP_LAT |
- RADEON_SCLK_FORCEON_MASK));
-
- if (info->ChipFamily == CHIP_FAMILY_RV200) {
- tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
- OUTPLL(RADEON_SCLK_MORE_CNTL, tmp | RADEON_SCLK_MORE_FORCEON);
- }
- }
-#endif /* new PM code */
-
- mclk_cntl = INPLL(pScrn, RADEON_MCLK_CNTL);
-
-#if 0 /* handled by new PM code */
- OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
- RADEON_FORCEON_MCLKA |
- RADEON_FORCEON_MCLKB |
- RADEON_FORCEON_YCLKA |
- RADEON_FORCEON_YCLKB |
- RADEON_FORCEON_MC |
- RADEON_FORCEON_AIC));
-#endif /* new PM code */
-
- /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
- * unexpected behaviour on some machines. Here we use
- * RADEON_HOST_PATH_CNTL to reset it.
- */
- host_path_cntl = INREG(RADEON_HOST_PATH_CNTL);
- rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- CARD32 tmp;
-
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
- RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_HI |
- RADEON_SOFT_RESET_E2));
- INREG(RADEON_RBBM_SOFT_RESET);
- OUTREG(RADEON_RBBM_SOFT_RESET, 0);
- tmp = INREG(RADEON_RB3D_DSTCACHE_MODE);
- OUTREG(RADEON_RB3D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
- } else {
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
- RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_SE |
- RADEON_SOFT_RESET_RE |
- RADEON_SOFT_RESET_PP |
- RADEON_SOFT_RESET_E2 |
- RADEON_SOFT_RESET_RB));
- INREG(RADEON_RBBM_SOFT_RESET);
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32)
- ~(RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_SE |
- RADEON_SOFT_RESET_RE |
- RADEON_SOFT_RESET_PP |
- RADEON_SOFT_RESET_E2 |
- RADEON_SOFT_RESET_RB)));
- INREG(RADEON_RBBM_SOFT_RESET);
- }
-
- OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET);
- INREG(RADEON_HOST_PATH_CNTL);
- OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
-
- if (!IS_R300_VARIANT && !IS_AVIVO_VARIANT)
- OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
-
- OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
- RADEONPllErrataAfterIndex(info);
- OUTPLL(pScrn, RADEON_MCLK_CNTL, mclk_cntl);
-}
-
-/* Restore the acceleration hardware to its previous state */
-void RADEONEngineRestore(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "EngineRestore (%d/%d)\n",
- info->CurrentLayout.pixel_code,
- info->CurrentLayout.bitsPerPixel);
-
- /* Setup engine location. This shouldn't be necessary since we
- * set them appropriately before any accel ops, but let's avoid
- * random bogus DMA in case we inadvertently trigger the engine
- * in the wrong place (happened).
- */
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset);
- OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset);
-
- RADEONWaitForFifo(pScrn, 1);
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- OUTREGP(RADEON_DP_DATATYPE,
- RADEON_HOST_BIG_ENDIAN_EN,
- ~RADEON_HOST_BIG_ENDIAN_EN);
-#else
- OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN);
-#endif
-
- /* Restore SURFACE_CNTL */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-
- RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
- | RADEON_DEFAULT_SC_BOTTOM_MAX));
- RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR));
-
- RADEONWaitForFifo(pScrn, 5);
- OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
- OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000);
- OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
- OUTREG(RADEON_DP_SRC_BKGD_CLR, 0x00000000);
- OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff);
-
- RADEONWaitForIdleMMIO(pScrn);
-
- info->XInited3D = FALSE;
-}
-
-/* Initialize the acceleration hardware */
-void RADEONEngineInit(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "EngineInit (%d/%d)\n",
- info->CurrentLayout.pixel_code,
- info->CurrentLayout.bitsPerPixel);
-
- OUTREG(RADEON_RB3D_CNTL, 0);
-
- RADEONEngineReset(pScrn);
-
- switch (info->CurrentLayout.pixel_code) {
- case 8: info->datatype = 2; break;
- case 15: info->datatype = 3; break;
- case 16: info->datatype = 4; break;
- case 24: info->datatype = 5; break;
- case 32: info->datatype = 6; break;
- default:
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Unknown depth/bpp = %d/%d (code = %d)\n",
- info->CurrentLayout.depth,
- info->CurrentLayout.bitsPerPixel,
- info->CurrentLayout.pixel_code);
- }
- info->pitch = ((info->CurrentLayout.displayWidth / 8) *
- (info->CurrentLayout.pixel_bytes == 3 ? 3 : 1));
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Pitch for acceleration = %d\n", info->pitch);
-
- info->dp_gui_master_cntl =
- ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
- | RADEON_GMC_CLR_CMP_CNTL_DIS
- | RADEON_GMC_DST_PITCH_OFFSET_CNTL);
-
-#ifdef XF86DRI
- info->sc_left = 0x00000000;
- info->sc_right = RADEON_DEFAULT_SC_RIGHT_MAX;
- info->sc_top = 0x00000000;
- info->sc_bottom = RADEON_DEFAULT_SC_BOTTOM_MAX;
-
- info->re_top_left = 0x00000000;
- info->re_width_height = ((0x7ff << RADEON_RE_WIDTH_SHIFT) |
- (0x7ff << RADEON_RE_HEIGHT_SHIFT));
-
- info->aux_sc_cntl = 0x00000000;
-#endif
-
- RADEONEngineRestore(pScrn);
-}
-
-
-#define ACCEL_MMIO
-#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
-#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
-#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
-#define FINISH_ACCEL()
-
-#include "radeon_commonfuncs.c"
-#if defined(RENDER) && defined(USE_XAA)
-#include "radeon_render.c"
-#endif
-#include "radeon_accelfuncs.c"
-
-#undef ACCEL_MMIO
-#undef ACCEL_PREAMBLE
-#undef BEGIN_ACCEL
-#undef OUT_ACCEL_REG
-#undef FINISH_ACCEL
-
-#ifdef XF86DRI
-
-#define ACCEL_CP
-#define ACCEL_PREAMBLE() \
- RING_LOCALS; \
- RADEONCP_REFRESH(pScrn, info)
-#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
-#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
-#define FINISH_ACCEL() ADVANCE_RING()
-
-
-#include "radeon_commonfuncs.c"
-#if defined(RENDER) && defined(USE_XAA)
-#include "radeon_render.c"
-#endif
-#include "radeon_accelfuncs.c"
-
-#undef ACCEL_CP
-#undef ACCEL_PREAMBLE
-#undef BEGIN_ACCEL
-#undef OUT_ACCEL_REG
-#undef FINISH_ACCEL
-
-/* Stop the CP */
-int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
-{
- drmRadeonCPStop stop;
- int ret, i;
-
- stop.flush = 1;
- stop.idle = 1;
-
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
-
- if (ret == 0) {
- return 0;
- } else if (errno != EBUSY) {
- return -errno;
- }
-
- stop.flush = 0;
-
- i = 0;
- do {
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
- } while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY);
-
- if (ret == 0) {
- return 0;
- } else if (errno != EBUSY) {
- return -errno;
- }
-
- stop.idle = 0;
-
- if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP,
- &stop, sizeof(drmRadeonCPStop))) {
- return -errno;
- } else {
- return 0;
- }
-}
-
-/* Get an indirect buffer for the CP 2D acceleration commands */
-drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- drmDMAReq dma;
- drmBufPtr buf = NULL;
- int indx = 0;
- int size = 0;
- int i = 0;
- int ret;
-
-#if 0
- /* FIXME: pScrn->pScreen has not been initialized when this is first
- * called from RADEONSelectBuffer via RADEONDRICPInit. We could use
- * the screen index from pScrn, which is initialized, and then get
- * the screen from screenInfo.screens[index], but that is a hack.
- */
- dma.context = DRIGetContext(pScrn->pScreen);
-#else
- /* This is the X server's context */
- dma.context = 0x00000001;
-#endif
-
- dma.send_count = 0;
- dma.send_list = NULL;
- dma.send_sizes = NULL;
- dma.flags = 0;
- dma.request_count = 1;
- dma.request_size = RADEON_BUFFER_SIZE;
- dma.request_list = &indx;
- dma.request_sizes = &size;
- dma.granted_count = 0;
-
- while (1) {
- do {
- ret = drmDMA(info->drmFD, &dma);
- if (ret && ret != -EBUSY) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: CP GetBuffer %d\n", __FUNCTION__, ret);
- }
- } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT));
-
- if (ret == 0) {
- buf = &info->buffers->list[indx];
- buf->used = 0;
- if (RADEON_VERBOSE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " GetBuffer returning %d %p\n",
- buf->idx, buf->address);
- }
- return buf;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "GetBuffer timed out, resetting engine...\n");
- RADEONEngineReset(pScrn);
- RADEONEngineRestore(pScrn);
-
- /* Always restart the engine when doing CP 2D acceleration */
- RADEONCP_RESET(pScrn, info);
- RADEONCP_START(pScrn, info);
- }
-}
-
-/* Flush the indirect buffer to the kernel for submission to the card */
-void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- drmBufPtr buffer = info->indirectBuffer;
- int start = info->indirectStart;
- drmRadeonIndirect indirect;
-
- if (!buffer) return;
- if (start == buffer->used && !discard) return;
-
- if (RADEON_VERBOSE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n",
- buffer->idx);
- }
-
- indirect.idx = buffer->idx;
- indirect.start = start;
- indirect.end = buffer->used;
- indirect.discard = discard;
-
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
- &indirect, sizeof(drmRadeonIndirect));
-
- if (discard) {
- info->indirectBuffer = RADEONCPGetBuffer(pScrn);
- info->indirectStart = 0;
- } else {
- /* Start on a double word boundary */
- info->indirectStart = buffer->used = (buffer->used + 7) & ~7;
- if (RADEON_VERBOSE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, " Starting at %d\n",
- info->indirectStart);
- }
- }
-}
-
-/* Flush and release the indirect buffer */
-void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- drmBufPtr buffer = info->indirectBuffer;
- int start = info->indirectStart;
- drmRadeonIndirect indirect;
-
- info->indirectBuffer = NULL;
- info->indirectStart = 0;
-
- if (!buffer) return;
-
- if (RADEON_VERBOSE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n",
- buffer->idx);
- }
-
- indirect.idx = buffer->idx;
- indirect.start = start;
- indirect.end = buffer->used;
- indirect.discard = 1;
-
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
- &indirect, sizeof(drmRadeonIndirect));
-}
-
-/** \brief Calculate HostDataBlit parameters from pointer and pitch
- *
- * This is a helper for the trivial HostDataBlit users that don't need to worry
- * about tiling etc.
- */
-void
-RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp,
- CARD32 *dstPitchOff, int *x, int *y)
-{
- RADEONInfoPtr info = RADEONPTR( pScrn );
- CARD32 dstOffs = dst - (CARD8*)info->FB + info->fbLocation;
-
- *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10;
- *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch;
- *x = ( ( dstOffs & RADEON_BUFFER_ALIGN ) - ( *y * pitch ) ) / cpp;
-}
-
-/* Set up a hostdata blit to transfer data from system memory to the
- * framebuffer. Returns the address where the data can be written to and sets
- * the dstPitch and hpass variables as required.
- */
-CARD8*
-RADEONHostDataBlit(
- ScrnInfoPtr pScrn,
- unsigned int cpp,
- unsigned int w,
- CARD32 dstPitchOff,
- CARD32 *bufPitch,
- int x,
- int *y,
- unsigned int *h,
- unsigned int *hpass
-){
- RADEONInfoPtr info = RADEONPTR( pScrn );
- CARD32 format, dwords;
- CARD8 *ret;
- RING_LOCALS;
-
- if ( *h == 0 )
- {
- return NULL;
- }
-
- switch ( cpp )
- {
- case 4:
- format = RADEON_GMC_DST_32BPP;
- *bufPitch = 4 * w;
- break;
- case 2:
- format = RADEON_GMC_DST_16BPP;
- *bufPitch = 2 * ((w + 1) & ~1);
- break;
- case 1:
- format = RADEON_GMC_DST_8BPP_CI;
- *bufPitch = (w + 3) & ~3;
- break;
- default:
- xf86DrvMsg( pScrn->scrnIndex, X_ERROR,
- "%s: Unsupported cpp %d!\n", __func__, cpp );
- return NULL;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* Swap doesn't work on R300 and later, it's handled during the
- * copy to ind. buffer pass
- */
- if (info->ChipFamily < CHIP_FAMILY_R300) {
- BEGIN_RING(2);
- if (cpp == 2)
- OUT_RING_REG(RADEON_RBBM_GUICNTL,
- RADEON_HOST_DATA_SWAP_HDW);
- else if (cpp == 1)
- OUT_RING_REG(RADEON_RBBM_GUICNTL,
- RADEON_HOST_DATA_SWAP_32BIT);
- else
- OUT_RING_REG(RADEON_RBBM_GUICNTL,
- RADEON_HOST_DATA_SWAP_NONE);
- ADVANCE_RING();
- }
-#endif
-
- /*RADEON_PURGE_CACHE();
- RADEON_WAIT_UNTIL_IDLE();*/
-
- *hpass = min( *h, ( ( RADEON_BUFFER_SIZE - 10 * 4 ) / *bufPitch ) );
- dwords = *hpass * *bufPitch / 4;
-
- BEGIN_RING( dwords + 10 );
- OUT_RING( CP_PACKET3( RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT, dwords + 10 - 2 ) );
- OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL
- | RADEON_GMC_DST_CLIPPING
- | RADEON_GMC_BRUSH_NONE
- | format
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP3_S
- | RADEON_DP_SRC_SOURCE_HOST_DATA
- | RADEON_GMC_CLR_CMP_CNTL_DIS
- | RADEON_GMC_WR_MSK_DIS );
- OUT_RING( dstPitchOff );
- OUT_RING( (*y << 16) | x );
- OUT_RING( ((*y + *hpass) << 16) | (x + w) );
- OUT_RING( 0xffffffff );
- OUT_RING( 0xffffffff );
- OUT_RING( *y << 16 | x );
- OUT_RING( *hpass << 16 | (*bufPitch / cpp) );
- OUT_RING( dwords );
-
- ret = ( CARD8* )&__head[__count];
-
- __count += dwords;
- ADVANCE_RING();
-
- *y += *hpass;
- *h -= *hpass;
-
- return ret;
-}
-
-void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap)
-{
- switch(swap) {
- case RADEON_HOST_DATA_SWAP_HDW:
- {
- unsigned int *d = (unsigned int *)dst;
- unsigned int *s = (unsigned int *)src;
- unsigned int nwords = size >> 2;
-
- for (; nwords > 0; --nwords, ++d, ++s)
- *d = ((*s & 0xffff) << 16) | ((*s >> 16) & 0xffff);
- return;
- }
- case RADEON_HOST_DATA_SWAP_32BIT:
- {
- unsigned int *d = (unsigned int *)dst;
- unsigned int *s = (unsigned int *)src;
- unsigned int nwords = size >> 2;
-
- for (; nwords > 0; --nwords, ++d, ++s)
-#ifdef __powerpc__
- asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d));
-#else
- *d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00)
- | ((*s & 0xff00) << 8) | ((*s & 0xff) << 24);
-#endif
- return;
- }
- case RADEON_HOST_DATA_SWAP_16BIT:
- {
- unsigned short *d = (unsigned short *)dst;
- unsigned short *s = (unsigned short *)src;
- unsigned int nwords = size >> 1;
-
- for (; nwords > 0; --nwords, ++d, ++s)
-#ifdef __powerpc__
- asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d));
-#else
- *d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00)
- | ((*s & 0xff00) << 8) | ((*s & 0xff) << 24);
-#endif
- return;
- }
- }
- if (src != dst)
- memmove(dst, src, size);
-}
-
-/* Copies a single pass worth of data for a hostdata blit set up by
- * RADEONHostDataBlit().
- */
-void
-RADEONHostDataBlitCopyPass(
- ScrnInfoPtr pScrn,
- unsigned int cpp,
- CARD8 *dst,
- CARD8 *src,
- unsigned int hpass,
- unsigned int dstPitch,
- unsigned int srcPitch
-){
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- RADEONInfoPtr info = RADEONPTR( pScrn );
-#endif
-
- /* RADEONHostDataBlitCopy can return NULL ! */
- if( (dst==NULL) || (src==NULL)) return;
-
- if ( dstPitch == srcPitch )
- {
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- if (info->ChipFamily >= CHIP_FAMILY_R300) {
- switch(cpp) {
- case 1:
- RADEONCopySwap(dst, src, hpass * dstPitch,
- RADEON_HOST_DATA_SWAP_32BIT);
- return;
- case 2:
- RADEONCopySwap(dst, src, hpass * dstPitch,
- RADEON_HOST_DATA_SWAP_HDW);
- return;
- }
- }
-#endif
- memcpy( dst, src, hpass * dstPitch );
- }
- else
- {
- unsigned int minPitch = min( dstPitch, srcPitch );
- while ( hpass-- )
- {
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- if (info->ChipFamily >= CHIP_FAMILY_R300) {
- switch(cpp) {
- case 1:
- RADEONCopySwap(dst, src, minPitch,
- RADEON_HOST_DATA_SWAP_32BIT);
- goto next;
- case 2:
- RADEONCopySwap(dst, src, minPitch,
- RADEON_HOST_DATA_SWAP_HDW);
- goto next;
- }
- }
-#endif
- memcpy( dst, src, minPitch );
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- next:
-#endif
- src += srcPitch;
- dst += dstPitch;
- }
- }
-}
-
-#endif
-
-Bool RADEONAccelInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- return FALSE;
-
-#ifdef USE_EXA
- if (info->useEXA) {
-# ifdef XF86DRI
- if (info->directRenderingEnabled) {
- if (!RADEONDrawInitCP(pScreen))
- return FALSE;
- } else
-# endif /* XF86DRI */
- {
- if (!RADEONDrawInitMMIO(pScreen))
- return FALSE;
- }
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- XAAInfoRecPtr a;
-
- if (!(a = info->accel = XAACreateInfoRec())) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAACreateInfoRec Error\n");
- return FALSE;
- }
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled)
- RADEONAccelInitCP(pScreen, a);
- else
-#endif /* XF86DRI */
- RADEONAccelInitMMIO(pScreen, a);
-
- RADEONEngineInit(pScrn);
-
- if (!XAAInit(pScreen, a)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAAInit Error\n");
- return FALSE;
- }
- }
-#endif /* USE_XAA */
- return TRUE;
-}
-
-void RADEONInit3DEngine(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONSAREAPrivPtr pSAREAPriv;
-
- pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen);
- RADEONInit3DEngineCP(pScrn);
- } else
-#endif
- RADEONInit3DEngineMMIO(pScrn);
-
- info->XInited3D = TRUE;
-}
-
-#ifdef USE_XAA
-#ifdef XF86DRI
-Bool
-RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int cpp = info->CurrentLayout.pixel_bytes;
- int depthCpp = (info->depthBits - 8) / 4;
- int width_bytes = pScrn->displayWidth * cpp;
- int bufferSize;
- int depthSize;
- int l;
- int scanlines;
- int texsizerequest;
- BoxRec MemBox;
- FBAreaPtr fbarea;
-
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
- info->backPitch = pScrn->displayWidth;
-
- /* make sure we use 16 line alignment for tiling (8 might be enough).
- * Might need that for non-XF86DRI too?
- */
- if (info->allowColorTiling) {
- bufferSize = (((pScrn->virtualY + 15) & ~15) * width_bytes
- + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN;
- } else {
- bufferSize = (pScrn->virtualY * width_bytes
- + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN;
- }
-
- /* Due to tiling, the Z buffer pitch must be a multiple of 32 pixels,
- * which is always the case if color tiling is used due to color pitch
- * but not necessarily otherwise, and its height a multiple of 16 lines.
- */
- info->depthPitch = (pScrn->displayWidth + 31) & ~31;
- depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch
- * depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
-
- switch (info->CPMode) {
- case RADEON_DEFAULT_CP_PIO_MODE:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in PIO mode\n");
- break;
- case RADEON_DEFAULT_CP_BM_MODE:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in BM mode\n");
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in UNKNOWN mode\n");
- break;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB GART aperture\n", info->gartSize);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for the ring buffer\n", info->ringSize);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for vertex/indirect buffers\n", info->bufSize);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for GART textures\n", info->gartTexSize);
-
- /* Try for front, back, depth, and three framebuffers worth of
- * pixmap cache. Should be enough for a fullscreen background
- * image plus some leftovers.
- * If the FBTexPercent option was used, try to achieve that percentage instead,
- * but still have at least one pixmap buffer (get problems with xvideo/render
- * otherwise probably), and never reserve more than 3 offscreen buffers as it's
- * probably useless for XAA.
- */
- if (info->textureSize >= 0) {
- texsizerequest = ((int)info->FbMapSize - 2 * bufferSize - depthSize
- - 2 * width_bytes - 16384 - info->FbSecureSize)
- /* first divide, then multiply or we'll get an overflow (been there...) */
- / 100 * info->textureSize;
- }
- else {
- texsizerequest = (int)info->FbMapSize / 2;
- }
- info->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize;
-
- /* If that gives us less than the requested memory, let's
- * be greedy and grab some more. Sorry, I care more about 3D
- * performance than playing nicely, and you'll get around a full
- * framebuffer's worth of pixmap cache anyway.
- */
- if (info->textureSize < texsizerequest) {
- info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize;
- }
- if (info->textureSize < texsizerequest) {
- info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
- }
-
- /* If there's still no space for textures, try without pixmap cache, but
- * never use the reserved space, the space hw cursor and PCIGART table might
- * use.
- */
- if (info->textureSize < 0) {
- info->textureSize = info->FbMapSize - 2 * bufferSize - depthSize
- - 2 * width_bytes - 16384 - info->FbSecureSize;
- }
-
- /* Check to see if there is more room available after the 8192nd
- * scanline for textures
- */
- /* FIXME: what's this good for? condition is pretty much impossible to meet */
- if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize
- > info->textureSize) {
- info->textureSize =
- info->FbMapSize - 8192*width_bytes - bufferSize - depthSize;
- }
-
- /* If backbuffer is disabled, don't allocate memory for it */
- if (info->noBackBuffer) {
- info->textureSize += bufferSize;
- }
-
- /* RADEON_BUFFER_ALIGN is not sufficient for backbuffer!
- At least for pageflip + color tiling, need to make sure it's 16 scanlines aligned,
- otherwise the copy-from-front-to-back will fail (width_bytes * 16 will also guarantee
- it's still 4kb aligned for tiled case). Need to round up offset (might get into cursor
- area otherwise).
- This might cause some space at the end of the video memory to be unused, since it
- can't be used (?) due to that log_tex_granularity thing???
- Could use different copyscreentoscreen function for the pageflip copies
- (which would use different src and dst offsets) to avoid this. */
- if (info->allowColorTiling && !info->noBackBuffer) {
- info->textureSize = info->FbMapSize - ((info->FbMapSize - info->textureSize +
- width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes * 16);
- }
- if (info->textureSize > 0) {
- l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY)
- l = RADEON_LOG_TEX_GRANULARITY;
- /* Round the texture size up to the nearest whole number of
- * texture regions. Again, be greedy about this, don't
- * round down.
- */
- info->log2TexGran = l;
- info->textureSize = (info->textureSize >> l) << l;
- } else {
- info->textureSize = 0;
- }
-
- /* Set a minimum usable local texture heap size. This will fit
- * two 256x256x32bpp textures.
- */
- if (info->textureSize < 512 * 1024) {
- info->textureOffset = 0;
- info->textureSize = 0;
- }
-
- if (info->allowColorTiling && !info->noBackBuffer) {
- info->textureOffset = ((info->FbMapSize - info->textureSize) /
- (width_bytes * 16)) * (width_bytes * 16);
- }
- else {
- /* Reserve space for textures */
- info->textureOffset = ((info->FbMapSize - info->textureSize +
- RADEON_BUFFER_ALIGN) &
- ~(CARD32)RADEON_BUFFER_ALIGN);
- }
-
- /* Reserve space for the shared depth
- * buffer.
- */
- info->depthOffset = ((info->textureOffset - depthSize +
- RADEON_BUFFER_ALIGN) &
- ~(CARD32)RADEON_BUFFER_ALIGN);
-
- /* Reserve space for the shared back buffer */
- if (info->noBackBuffer) {
- info->backOffset = info->depthOffset;
- } else {
- info->backOffset = ((info->depthOffset - bufferSize +
- RADEON_BUFFER_ALIGN) &
- ~(CARD32)RADEON_BUFFER_ALIGN);
- }
-
- info->backY = info->backOffset / width_bytes;
- info->backX = (info->backOffset - (info->backY * width_bytes)) / cpp;
-
- scanlines = (info->FbMapSize-info->FbSecureSize) / width_bytes;
- if (scanlines > 8191)
- scanlines = 8191;
-
- MemBox.x1 = 0;
- MemBox.y1 = 0;
- MemBox.x2 = pScrn->displayWidth;
- MemBox.y2 = scanlines;
-
- if (!xf86InitFBManager(pScreen, &MemBox)) {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Memory manager initialization to "
- "(%d,%d) (%d,%d) failed\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- return FALSE;
- } else {
- int width, height;
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Memory manager initialized to (%d,%d) (%d,%d)\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- /* why oh why can't we just request modes which are guaranteed to be 16 lines
- aligned... sigh */
- if ((fbarea = xf86AllocateOffscreenArea(pScreen,
- pScrn->displayWidth,
- info->allowColorTiling ?
- ((pScrn->virtualY + 15) & ~15)
- - pScrn->virtualY + 2 : 2,
- 0, NULL, NULL,
- NULL))) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved area from (%d,%d) to (%d,%d)\n",
- fbarea->box.x1, fbarea->box.y1,
- fbarea->box.x2, fbarea->box.y2);
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n");
- }
-
- RADEONDRIAllocatePCIGARTTable(pScreen);
-
- if (xf86QueryLargestOffscreenArea(pScreen, &width,
- &height, 0, 0, 0)) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Largest offscreen area available: %d x %d\n",
- width, height);
-
- /* Lines in offscreen area needed for depth buffer and
- * textures
- */
- info->depthTexLines = (scanlines
- - info->depthOffset / width_bytes);
- info->backLines = (scanlines
- - info->backOffset / width_bytes
- - info->depthTexLines);
- info->backArea = NULL;
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Unable to determine largest offscreen area "
- "available\n");
- return FALSE;
- }
- }
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Will use front buffer at offset 0x%x\n",
- info->frontOffset);
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Will use back buffer at offset 0x%x\n",
- info->backOffset);
- xf86DrvMsg(scrnIndex, X_INFO,
- "Will use depth buffer at offset 0x%x\n",
- info->depthOffset);
- if (info->cardType==CARD_PCIE)
- xf86DrvMsg(scrnIndex, X_INFO,
- "Will use %d kb for PCI GART table at offset 0x%x\n",
- info->pciGartSize/1024, (unsigned)info->pciGartOffset);
- xf86DrvMsg(scrnIndex, X_INFO,
- "Will use %d kb for textures at offset 0x%x\n",
- info->textureSize/1024, info->textureOffset);
-
- info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
- ((info->frontOffset + info->fbLocation) >> 10));
-
- info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
- ((info->backOffset + info->fbLocation) >> 10));
-
- info->depthPitchOffset = (((info->depthPitch * depthCpp / 64) << 22) |
- ((info->depthOffset + info->fbLocation) >> 10));
- return TRUE;
-}
-#endif /* XF86DRI */
-
-Bool
-RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- BoxRec MemBox;
- int y2;
-
- int width_bytes = pScrn->displayWidth * info->CurrentLayout.pixel_bytes;
-
- MemBox.x1 = 0;
- MemBox.y1 = 0;
- MemBox.x2 = pScrn->displayWidth;
- y2 = info->FbMapSize / width_bytes;
- if (y2 >= 32768)
- y2 = 32767; /* because MemBox.y2 is signed short */
- MemBox.y2 = y2;
-
- /* The acceleration engine uses 14 bit
- * signed coordinates, so we can't have any
- * drawable caches beyond this region.
- */
- if (MemBox.y2 > 8191)
- MemBox.y2 = 8191;
-
- if (!xf86InitFBManager(pScreen, &MemBox)) {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Memory manager initialization to "
- "(%d,%d) (%d,%d) failed\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- return FALSE;
- } else {
- int width, height;
- FBAreaPtr fbarea;
-
- xf86DrvMsg(scrnIndex, X_INFO,
- "Memory manager initialized to (%d,%d) (%d,%d)\n",
- MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2);
- if ((fbarea = xf86AllocateOffscreenArea(pScreen,
- pScrn->displayWidth,
- info->allowColorTiling ?
- ((pScrn->virtualY + 15) & ~15)
- - pScrn->virtualY + 2 : 2,
- 0, NULL, NULL,
- NULL))) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Reserved area from (%d,%d) to (%d,%d)\n",
- fbarea->box.x1, fbarea->box.y1,
- fbarea->box.x2, fbarea->box.y2);
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n");
- }
- if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
- 0, 0, 0)) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Largest offscreen area available: %d x %d\n",
- width, height);
- }
- return TRUE;
- }
-}
-#endif /* USE_XAA */
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
deleted file mode 100644
index e3b37c1..0000000
--- a/src/radeon_accelfuncs.c
+++ /dev/null
@@ -1,1346 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- * Michel Dänzer <michel at daenzer.net>
- *
- * Credits:
- *
- * Thanks to Ani Joshi <ajoshi at shell.unixbox.com> for providing source
- * code to his Radeon driver. Portions of this file are based on the
- * initialization code for that driver.
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- * Notes on unimplemented XAA optimizations:
- *
- * SetClipping: This has been removed as XAA expects 16bit registers
- * for full clipping.
- * TwoPointLine: The Radeon supports this. Not Bresenham.
- * DashedLine with non-power-of-two pattern length: Apparently, there is
- * no way to set the length of the pattern -- it is always
- * assumed to be 8 or 32 (or 1024?).
- * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference
- * Manual where it states that monochrome expansion of frame
- * buffer data is not supported.
- * CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid
- * direct/indirect method. If we had more data registers,
- * then we could do better. If XAA supported a trigger write
- * address, the code would be simpler.
- * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8
- * pattern from frame buffer memory.
- * ImageWrites: Same as CPUToScreenColorExpandFill
- *
- */
-
-#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
-#error Cannot define both MMIO and CP acceleration!
-#endif
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#ifdef ACCEL_MMIO
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
-#else
-#ifdef ACCEL_CP
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-#else
-#error No accel type defined!
-#endif
-#endif
-
-#ifdef USE_XAA
-
-/* This callback is required for multiheader cards using XAA */
-static void
-FUNC_NAME(RADEONRestoreAccelState)(ScrnInfoPtr pScrn)
-{
- /*RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;*/
-
-#ifdef ACCEL_MMIO
-
-/* OUTREG(RADEON_DEFAULT_OFFSET, info->dst_pitch_offset);*/
- /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */
-
- RADEONWaitForIdleMMIO(pScrn);
-
-#else /* ACCEL_CP */
-
-/* RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_DEFAULT_OFFSET, info->frontPitchOffset);*/
-
- RADEONWaitForIdleMMIO(pScrn);
-
-#if 0
- /* Not working yet */
- RADEONMMIO_TO_CP(pScrn, info);
-#endif
-
- /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */
-#endif
-}
-
-/* Setup for XAA SolidFill */
-static void
-FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn,
- int color,
- int rop,
- unsigned int planemask)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].pattern);
-
- BEGIN_ACCEL(4);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
- | RADEON_DST_Y_TOP_TO_BOTTOM));
-
- FINISH_ACCEL();
-}
-
-/* Subsequent XAA SolidFillRect
- *
- * Tests: xtest CH06/fllrctngl, xterm
- */
-static void
-FUNC_NAME(RADEONSubsequentSolidFillRect)(ScrnInfoPtr pScrn,
- int x, int y,
- int w, int h)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
- OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
-
- FINISH_ACCEL();
-}
-
-/* Setup for XAA solid lines */
-static void
-FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn,
- int color,
- int rop,
- unsigned int planemask)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].pattern);
-
- if (info->ChipFamily >= CHIP_FAMILY_RV200) {
- BEGIN_ACCEL(1);
- OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT,
- 0x55 << RADEON_BRES_CNTL_SHIFT);
- FINISH_ACCEL();
- }
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
-
- FINISH_ACCEL();
-}
-
-/* Subsequent XAA solid horizontal and vertical lines */
-static void
-FUNC_NAME(RADEONSubsequentSolidHorVertLine)(ScrnInfoPtr pScrn,
- int x, int y,
- int len,
- int dir)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int w = 1;
- int h = 1;
- ACCEL_PREAMBLE();
-
- if (dir == DEGREES_0) w = len;
- else h = len;
-
- BEGIN_ACCEL(4);
-
- OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
- | RADEON_DST_Y_TOP_TO_BOTTOM));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
- OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
-
- FINISH_ACCEL();
-}
-
-/* Subsequent XAA solid TwoPointLine line
- *
- * Tests: xtest CH06/drwln, ico, Mark Vojkovich's linetest program
- *
- * [See http://www.xfree86.org/devel/archives/devel/1999-Jun/0102.shtml for
- * Mark Vojkovich's linetest program, posted 2Jun99 to devel at xfree86.org.]
- */
-static void
-FUNC_NAME(RADEONSubsequentSolidTwoPointLine)(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb,
- int flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- /* TODO: Check bounds -- RADEON only has 14 bits */
-
- if (!(flags & OMIT_LAST))
- FUNC_NAME(RADEONSubsequentSolidHorVertLine)(pScrn,
- xb, yb, 1,
- DEGREES_0);
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa);
- OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb);
-
- FINISH_ACCEL();
-}
-
-/* Setup for XAA dashed lines
- *
- * Tests: xtest CH05/stdshs, XFree86/drwln
- *
- * NOTE: Since we can only accelerate lines with power-of-2 patterns of
- * length <= 32
- */
-static void
-FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn,
- int fg,
- int bg,
- int rop,
- unsigned int planemask,
- int length,
- unsigned char *pattern)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 pat = *(CARD32 *)(pointer)pattern;
- ACCEL_PREAMBLE();
-
- /* Save for determining whether or not to draw last pixel */
- info->dashLen = length;
- info->dashPattern = pat;
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-# define PAT_SHIFT(pat, shift) (pat >> shift)
-#else
-# define PAT_SHIFT(pat, shift) (pat << shift)
-#endif
-
- switch (length) {
- case 2: pat |= PAT_SHIFT(pat, 2); /* fall through */
- case 4: pat |= PAT_SHIFT(pat, 4); /* fall through */
- case 8: pat |= PAT_SHIFT(pat, 8); /* fall through */
- case 16: pat |= PAT_SHIFT(pat, 16);
- }
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | (bg == -1
- ? RADEON_GMC_BRUSH_32x1_MONO_FG_LA
- : RADEON_GMC_BRUSH_32x1_MONO_FG_BG)
- | RADEON_ROP[rop].pattern
- | RADEON_GMC_BYTE_LSB_TO_MSB);
- info->dash_fg = fg;
- info->dash_bg = bg;
-
- BEGIN_ACCEL((bg == -1) ? 4 : 5);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
- if (bg != -1)
- OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, bg);
- OUT_ACCEL_REG(RADEON_BRUSH_DATA0, pat);
-
- FINISH_ACCEL();
-}
-
-/* Helper function to draw last point for dashed lines */
-static void
-FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn,
- int x, int y,
- int fg)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 dp_gui_master_cntl = info->dp_gui_master_cntl_clip;
- ACCEL_PREAMBLE();
-
- dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK;
- dp_gui_master_cntl |= RADEON_GMC_BRUSH_SOLID_COLOR;
-
- dp_gui_master_cntl &= ~RADEON_GMC_SRC_DATATYPE_MASK;
- dp_gui_master_cntl |= RADEON_GMC_SRC_DATATYPE_COLOR;
-
- BEGIN_ACCEL(8);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, dp_gui_master_cntl);
- OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
- | RADEON_DST_Y_TOP_TO_BOTTOM));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
- OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (1 << 16) | 1);
-
- /* Restore old values */
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->dash_fg);
-
- FINISH_ACCEL();
-}
-
-/* Subsequent XAA dashed line */
-static void
-FUNC_NAME(RADEONSubsequentDashedTwoPointLine)(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb,
- int flags,
- int phase)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- /* TODO: Check bounds -- RADEON only has 14 bits */
-
- if (!(flags & OMIT_LAST)) {
- int deltax = abs(xa - xb);
- int deltay = abs(ya - yb);
- int shift;
-
- if (deltax > deltay) shift = deltax;
- else shift = deltay;
-
- shift += phase;
- shift %= info->dashLen;
-
- if ((info->dashPattern >> shift) & 1)
- FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->dash_fg);
- else if (info->dash_bg != -1)
- FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->dash_bg);
- }
-
- BEGIN_ACCEL(4);
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa);
- OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT, phase);
- OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb);
-
- FINISH_ACCEL();
-}
-
-/* Set up for transparency
- *
- * Mmmm, Seems as though the transparency compare is opposite to r128.
- * It should only draw when source != trans_color, this is the opposite
- * of that.
- */
-static void
-FUNC_NAME(RADEONSetTransparency)(ScrnInfoPtr pScrn,
- int trans_color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if ((trans_color != -1) || (info->XAAForceTransBlit == TRUE)) {
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_CLR_CMP_CLR_SRC, trans_color);
- OUT_ACCEL_REG(RADEON_CLR_CMP_MASK, RADEON_CLR_CMP_MSK);
- OUT_ACCEL_REG(RADEON_CLR_CMP_CNTL, (RADEON_SRC_CMP_EQ_COLOR
- | RADEON_CLR_CMP_SRC_SOURCE));
-
- FINISH_ACCEL();
- }
-}
-
-/* Setup for XAA screen-to-screen copy
- *
- * Tests: xtest CH06/fllrctngl (also tests transparency)
- */
-static void
-FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn,
- int xdir, int ydir,
- int rop,
- unsigned int planemask,
- int trans_color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- info->xdir = xdir;
- info->ydir = ydir;
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_NONE
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].rop
- | RADEON_DP_SRC_SOURCE_MEMORY
- | RADEON_GMC_SRC_PITCH_OFFSET_CNTL);
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_CNTL,
- ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
- (ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0)));
-
- FINISH_ACCEL();
-
- info->trans_color = trans_color;
- FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color);
-}
-
-/* Subsequent XAA screen-to-screen copy */
-static void
-FUNC_NAME(RADEONSubsequentScreenToScreenCopy)(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb,
- int w, int h)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- if (info->xdir < 0) xa += w - 1, xb += w - 1;
- if (info->ydir < 0) ya += h - 1, yb += h - 1;
-
- BEGIN_ACCEL(5);
-
- OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (yb <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_SRC_Y_X, (ya << 16) | xa);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (yb << 16) | xb);
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
-
- FINISH_ACCEL();
-}
-
-/* Setup for XAA mono 8x8 pattern color expansion. Patterns with
- * transparency use `bg == -1'. This routine is only used if the XAA
- * pixmap cache is turned on.
- *
- * Tests: xtest XFree86/fllrctngl (no other test will test this routine with
- * both transparency and non-transparency)
- */
-static void
-FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn,
- int patternx,
- int patterny,
- int fg,
- int bg,
- int rop,
- unsigned int planemask)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char pattern[8];
-#endif
- ACCEL_PREAMBLE();
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* Take care of endianness */
- pattern[0] = (patternx & 0x000000ff);
- pattern[1] = (patternx & 0x0000ff00) >> 8;
- pattern[2] = (patternx & 0x00ff0000) >> 16;
- pattern[3] = (patternx & 0xff000000) >> 24;
- pattern[4] = (patterny & 0x000000ff);
- pattern[5] = (patterny & 0x0000ff00) >> 8;
- pattern[6] = (patterny & 0x00ff0000) >> 16;
- pattern[7] = (patterny & 0xff000000) >> 24;
-#endif
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | (bg == -1
- ? RADEON_GMC_BRUSH_8X8_MONO_FG_LA
- : RADEON_GMC_BRUSH_8X8_MONO_FG_BG)
- | RADEON_ROP[rop].pattern
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- | RADEON_GMC_BYTE_MSB_TO_LSB
-#endif
- );
-
- BEGIN_ACCEL((bg == -1) ? 5 : 6);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
- if (bg != -1)
- OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, bg);
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- OUT_ACCEL_REG(RADEON_BRUSH_DATA0, patternx);
- OUT_ACCEL_REG(RADEON_BRUSH_DATA1, patterny);
-#else
- OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(CARD32 *)(pointer)&pattern[0]);
- OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(CARD32 *)(pointer)&pattern[4]);
-#endif
-
- FINISH_ACCEL();
-}
-
-/* Subsequent XAA 8x8 pattern color expansion. Because they are used in
- * the setup function, `patternx' and `patterny' are not used here.
- */
-static void
-FUNC_NAME(RADEONSubsequentMono8x8PatternFillRect)(ScrnInfoPtr pScrn,
- int patternx,
- int patterny,
- int x, int y,
- int w, int h)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(4);
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (patterny << 8) | patternx);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
-
- FINISH_ACCEL();
-}
-
-#if 0
-/* Setup for XAA color 8x8 pattern fill
- *
- * Tests: xtest XFree86/fllrctngl (with Mono8x8PatternFill off)
- */
-static void
-FUNC_NAME(RADEONSetupForColor8x8PatternFill)(ScrnInfoPtr pScrn,
- int patx, int paty,
- int rop,
- unsigned int planemask,
- int trans_color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_BRUSH_8x8_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].pattern
- | RADEON_DP_SRC_SOURCE_MEMORY);
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_SRC_Y_X, (paty << 16) | patx);
-
- FINISH_ACCEL();
-
- info->trans_color = trans_color;
- FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color);
-}
-
-/* Subsequent XAA 8x8 pattern color expansion */
-static void
-FUNC_NAME(RADEONSubsequentColor8x8PatternFillRect)(ScrnInfoPtr pScrn,
- int patx, int paty,
- int x, int y,
- int w, int h)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(4);
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (paty << 16) | patx);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
-
- FINISH_ACCEL();
-}
-#endif
-
-#ifdef ACCEL_CP
-#define CP_BUFSIZE (info->indirectBuffer->total/4-10)
-
-/* Helper function to write out a HOSTDATA_BLT packet into the indirect
- * buffer and set the XAA scratch buffer address appropriately.
- */
-static void
-RADEONCPScanlinePacket(ScrnInfoPtr pScrn, int bufno)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int chunk_words = info->scanline_hpass * info->scanline_words;
- ACCEL_PREAMBLE();
-
- if (RADEON_VERBOSE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "CPScanline Packet h=%d hpass=%d chunkwords=%d\n",
- info->scanline_h, info->scanline_hpass, chunk_words);
- }
- BEGIN_RING(chunk_words+10);
-
- OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT,chunk_words+10-2));
- OUT_RING(info->dp_gui_master_cntl_clip);
- OUT_RING(info->dst_pitch_offset |
- ((info->tilingEnabled && (info->scanline_y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_RING((info->scanline_y << 16) |
- (info->scanline_x1clip & 0xffff));
- OUT_RING(((info->scanline_y+info->scanline_hpass) << 16) |
- (info->scanline_x2clip & 0xffff));
- OUT_RING(info->scanline_fg);
- OUT_RING(info->scanline_bg);
- OUT_RING((info->scanline_y << 16) |
- (info->scanline_x & 0xffff));
- OUT_RING((info->scanline_hpass << 16) |
- (info->scanline_w & 0xffff));
- OUT_RING(chunk_words);
-
- info->scratch_buffer[bufno] = (unsigned char *)&__head[__count];
- __count += chunk_words;
-
- /* The ring can only be advanced after the __head and __count have
- been adjusted above */
- FINISH_ACCEL();
-
- info->scanline_y += info->scanline_hpass;
- info->scanline_h -= info->scanline_hpass;
-}
-#endif
-
-/* Setup for XAA indirect CPU-to-screen color expansion (indirect).
- * Because of how the scratch buffer is initialized, this is really a
- * mainstore-to-screen color expansion. Transparency is supported when
- * `bg == -1'.
- */
-static void
-FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr pScrn,
- int fg,
- int bg,
- int rop,
- unsigned int
- planemask)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- info->scanline_bpp = 0;
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_DST_CLIPPING
- | RADEON_GMC_BRUSH_NONE
- | (bg == -1
- ? RADEON_GMC_SRC_DATATYPE_MONO_FG_LA
- : RADEON_GMC_SRC_DATATYPE_MONO_FG_BG)
- | RADEON_ROP[rop].rop
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- | RADEON_GMC_BYTE_LSB_TO_MSB
-#else
- | RADEON_GMC_BYTE_MSB_TO_LSB
-#endif
- | RADEON_DP_SRC_SOURCE_HOST_DATA);
-
-#ifdef ACCEL_MMIO
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- BEGIN_ACCEL(4);
-#else
- BEGIN_ACCEL(5);
-
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
-#endif
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_SRC_FRGD_CLR, fg);
- OUT_ACCEL_REG(RADEON_DP_SRC_BKGD_CLR, bg);
-
-#else /* ACCEL_CP */
-
- info->scanline_fg = fg;
- info->scanline_bg = bg;
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- BEGIN_ACCEL(1);
-#else
- if (info->ChipFamily < CHIP_FAMILY_R300) {
- BEGIN_ACCEL(2);
-
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT);
- } else
- BEGIN_ACCEL(1);
-#endif
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
-
-#endif
-
- FINISH_ACCEL();
-}
-
-/* Subsequent XAA indirect CPU-to-screen color expansion. This is only
- * called once for each rectangle.
- */
-static void
-FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr
- pScrn,
- int x, int y,
- int w, int h,
- int skipleft)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#ifdef ACCEL_MMIO
- ACCEL_PREAMBLE();
-
- info->scanline_h = h;
- info->scanline_words = (w + 31) >> 5;
-
-#ifdef __alpha__
- /* Always use indirect for Alpha */
- if (0)
-#else
- if ((info->scanline_words * h) <= 9)
-#endif
- {
- /* Turn on direct for less than 9 dword colour expansion */
- info->scratch_buffer[0] =
- (unsigned char *)(ADDRREG(RADEON_HOST_DATA_LAST)
- - (info->scanline_words - 1));
- info->scanline_direct = 1;
- } else {
- /* Use indirect for anything else */
- info->scratch_buffer[0] = info->scratch_save;
- info->scanline_direct = 0;
- }
-
- BEGIN_ACCEL(5 + (info->scanline_direct ?
- (info->scanline_words * h) : 0));
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft)
- & 0xffff));
- OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | (x & 0xffff));
- /* Have to pad the width here and use clipping engine */
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
-
- FINISH_ACCEL();
-
-#else /* ACCEL_CP */
-
- info->scanline_x = x;
- info->scanline_y = y;
- /* Have to pad the width here and use clipping engine */
- info->scanline_w = (w + 31) & ~31;
- info->scanline_h = h;
-
- info->scanline_x1clip = x + skipleft;
- info->scanline_x2clip = x + w;
-
- info->scanline_words = info->scanline_w / 32;
- info->scanline_hpass = min(h,(CP_BUFSIZE/info->scanline_words));
-
- RADEONCPScanlinePacket(pScrn, 0);
-
-#endif
-}
-
-/* Subsequent XAA indirect CPU-to-screen color expansion and indirect
- * image write. This is called once for each scanline.
- */
-static void
-FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn,
- int bufno)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#ifdef ACCEL_MMIO
- CARD32 *p = (pointer)info->scratch_buffer[bufno];
- int i;
- int left = info->scanline_words;
- volatile CARD32 *d;
- ACCEL_PREAMBLE();
-
- if (info->scanline_direct) return;
-
- --info->scanline_h;
-
- while (left) {
- write_mem_barrier();
- if (left <= 8) {
- /* Last scanline - finish write to DATA_LAST */
- if (info->scanline_h == 0) {
- BEGIN_ACCEL(left);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(RADEON_HOST_DATA_LAST) - (left - 1); left; --left)
- *d++ = *p++;
- return;
- } else {
- BEGIN_ACCEL(left);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(RADEON_HOST_DATA7) - (left - 1); left; --left)
- *d++ = *p++;
- }
- } else {
- BEGIN_ACCEL(8);
- /* Unrolling doesn't improve performance */
- for (d = ADDRREG(RADEON_HOST_DATA0), i = 0; i < 8; i++)
- *d++ = *p++;
- left -= 8;
- }
- }
-
- FINISH_ACCEL();
-
-#else /* ACCEL_CP */
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- if (info->ChipFamily >= CHIP_FAMILY_R300) {
- if (info->scanline_bpp == 16) {
- RADEONCopySwap(info->scratch_buffer[bufno],
- info->scratch_buffer[bufno],
- info->scanline_words << 2,
- RADEON_HOST_DATA_SWAP_HDW);
- } else if (info->scanline_bpp < 15) {
- RADEONCopySwap(info->scratch_buffer[bufno],
- info->scratch_buffer[bufno],
- info->scanline_words << 2,
- RADEON_HOST_DATA_SWAP_32BIT);
- }
- }
-#endif
-
- if (--info->scanline_hpass) {
- info->scratch_buffer[bufno] += 4 * info->scanline_words;
- } else if (info->scanline_h) {
- info->scanline_hpass =
- min(info->scanline_h,(CP_BUFSIZE/info->scanline_words));
- RADEONCPScanlinePacket(pScrn, bufno);
- }
-
-#endif
-}
-
-/* Setup for XAA indirect image write */
-static void
-FUNC_NAME(RADEONSetupForScanlineImageWrite)(ScrnInfoPtr pScrn,
- int rop,
- unsigned int planemask,
- int trans_color,
- int bpp,
- int depth)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- info->scanline_bpp = bpp;
-
- /* Save for later clipping */
- info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl
- | RADEON_GMC_DST_CLIPPING
- | RADEON_GMC_BRUSH_NONE
- | RADEON_GMC_SRC_DATATYPE_COLOR
- | RADEON_ROP[rop].rop
- | RADEON_GMC_BYTE_MSB_TO_LSB
- | RADEON_DP_SRC_SOURCE_HOST_DATA);
-
-#ifdef ACCEL_MMIO
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- BEGIN_ACCEL(2);
-#else
- BEGIN_ACCEL(3);
-
- if (bpp == 16)
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_16BIT);
- else if (bpp == 32)
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT);
- else
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
-#endif
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
-
-#else /* ACCEL_CP */
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- BEGIN_ACCEL(1);
-#else
- if (info->ChipFamily < CHIP_FAMILY_R300) {
- BEGIN_ACCEL(2);
-
- if (bpp == 16)
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_HDW);
- else
- OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
- } else
- BEGIN_ACCEL(1);
-#endif
-#endif
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
-
- FINISH_ACCEL();
-
- info->trans_color = trans_color;
- FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color);
-}
-
-/* Subsequent XAA indirect image write. This is only called once for
- * each rectangle.
- */
-static void
-FUNC_NAME(RADEONSubsequentScanlineImageWriteRect)(ScrnInfoPtr pScrn,
- int x, int y,
- int w, int h,
- int skipleft)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef ACCEL_MMIO
-
- int shift = 0; /* 32bpp */
- ACCEL_PREAMBLE();
-
- if (pScrn->bitsPerPixel == 8) shift = 3;
- else if (pScrn->bitsPerPixel == 16) shift = 1;
-
- info->scanline_h = h;
- info->scanline_words = (w * info->scanline_bpp + 31) >> 5;
-
-#ifdef __alpha__
- /* Always use indirect for Alpha */
- if (0)
-#else
- if ((info->scanline_words * h) <= 9)
-#endif
- {
- /* Turn on direct for less than 9 dword colour expansion */
- info->scratch_buffer[0]
- = (unsigned char *)(ADDRREG(RADEON_HOST_DATA_LAST)
- - (info->scanline_words - 1));
- info->scanline_direct = 1;
- } else {
- /* Use indirect for anything else */
- info->scratch_buffer[0] = info->scratch_save;
- info->scanline_direct = 0;
- }
-
- BEGIN_ACCEL(5 + (info->scanline_direct ?
- (info->scanline_words * h) : 0));
-
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset |
- ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0));
- OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft)
- & 0xffff));
- OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | (x & 0xffff));
- /* Have to pad the width here and use clipping engine */
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | ((w + shift) &
- ~shift));
-
- FINISH_ACCEL();
-
-#else /* ACCEL_CP */
-
- int pad = 0; /* 32bpp */
-
- if (pScrn->bitsPerPixel == 8) pad = 3;
- else if (pScrn->bitsPerPixel == 16) pad = 1;
-
- info->scanline_x = x;
- info->scanline_y = y;
- /* Have to pad the width here and use clipping engine */
- info->scanline_w = (w + pad) & ~pad;
- info->scanline_h = h;
-
- info->scanline_x1clip = x + skipleft;
- info->scanline_x2clip = x + w;
-
- info->scanline_words = (w * info->scanline_bpp + 31) / 32;
- info->scanline_hpass = min(h,(CP_BUFSIZE/info->scanline_words));
-
- RADEONCPScanlinePacket(pScrn, 0);
-
-#endif
-}
-
-/* Set up the clipping rectangle */
-static void
-FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned long tmp1 = 0;
- unsigned long tmp2 = 0;
- ACCEL_PREAMBLE();
-
- if (xa < 0) {
- tmp1 = (-xa) & 0x3fff;
- tmp1 |= RADEON_SC_SIGN_MASK_LO;
- } else {
- tmp1 = xa;
- }
-
- if (ya < 0) {
- tmp1 |= (((-ya) & 0x3fff) << 16);
- tmp1 |= RADEON_SC_SIGN_MASK_HI;
- } else {
- tmp1 |= (ya << 16);
- }
-
- xb++; yb++;
-
- if (xb < 0) {
- tmp2 = (-xb) & 0x3fff;
- tmp2 |= RADEON_SC_SIGN_MASK_LO;
- } else {
- tmp2 = xb;
- }
-
- if (yb < 0) {
- tmp2 |= (((-yb) & 0x3fff) << 16);
- tmp2 |= RADEON_SC_SIGN_MASK_HI;
- } else {
- tmp2 |= (yb << 16);
- }
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl_clip
- | RADEON_GMC_DST_CLIPPING));
- OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, tmp1);
- OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, tmp2);
-
- FINISH_ACCEL();
-
- FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color);
-}
-
-/* Disable the clipping rectangle */
-static void
-FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->dp_gui_master_cntl_clip);
- OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, 0);
- OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX |
- RADEON_DEFAULT_SC_BOTTOM_MAX));
-
- FINISH_ACCEL();
-
- FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color);
-}
-
-void
-FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- a->Flags = (PIXMAP_CACHE
- | OFFSCREEN_PIXMAPS
- | LINEAR_FRAMEBUFFER);
-
- /* Sync */
- a->Sync = FUNC_NAME(RADEONWaitForIdle);
-
- /* Solid Filled Rectangle */
- a->PolyFillRectSolidFlags = 0;
- a->SetupForSolidFill
- = FUNC_NAME(RADEONSetupForSolidFill);
- a->SubsequentSolidFillRect
- = FUNC_NAME(RADEONSubsequentSolidFillRect);
-
- /* Screen-to-screen Copy */
- a->ScreenToScreenCopyFlags = 0;
- a->SetupForScreenToScreenCopy
- = FUNC_NAME(RADEONSetupForScreenToScreenCopy);
- a->SubsequentScreenToScreenCopy
- = FUNC_NAME(RADEONSubsequentScreenToScreenCopy);
-
- /* Mono 8x8 Pattern Fill (Color Expand) */
- a->SetupForMono8x8PatternFill
- = FUNC_NAME(RADEONSetupForMono8x8PatternFill);
- a->SubsequentMono8x8PatternFillRect
- = FUNC_NAME(RADEONSubsequentMono8x8PatternFillRect);
- a->Mono8x8PatternFillFlags = (HARDWARE_PATTERN_PROGRAMMED_BITS
- | HARDWARE_PATTERN_PROGRAMMED_ORIGIN
- | HARDWARE_PATTERN_SCREEN_ORIGIN);
-
-#if X_BYTE_ORDER == X_LITTLE_ENDIAN
- if (info->ChipFamily >= CHIP_FAMILY_RV200)
- a->Mono8x8PatternFillFlags |= BIT_ORDER_IN_BYTE_MSBFIRST;
- else
- a->Mono8x8PatternFillFlags |= BIT_ORDER_IN_BYTE_LSBFIRST;
-#else
- a->Mono8x8PatternFillFlags |= BIT_ORDER_IN_BYTE_LSBFIRST;
-#endif
-
- /* Indirect CPU-To-Screen Color Expand */
-
- /* RADEON gets upset, when using HOST provided data without a source
- rop. To show run 'xtest's drwarc. */
- a->ScanlineCPUToScreenColorExpandFillFlags
- = (LEFT_EDGE_CLIPPING
- | ROP_NEEDS_SOURCE
- | LEFT_EDGE_CLIPPING_NEGATIVE_X);
- a->NumScanlineColorExpandBuffers = 1;
- a->ScanlineColorExpandBuffers = info->scratch_buffer;
- if (!info->scratch_save)
- info->scratch_save
- = xalloc(((pScrn->virtualX+31)/32*4)
- + (pScrn->virtualX * info->CurrentLayout.pixel_bytes));
- info->scratch_buffer[0] = info->scratch_save;
- a->SetupForScanlineCPUToScreenColorExpandFill
- = FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill);
- a->SubsequentScanlineCPUToScreenColorExpandFill
- = FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill);
- a->SubsequentColorExpandScanline
- = FUNC_NAME(RADEONSubsequentScanline);
-
- /* Solid Lines */
- a->SetupForSolidLine
- = FUNC_NAME(RADEONSetupForSolidLine);
- a->SubsequentSolidHorVertLine
- = FUNC_NAME(RADEONSubsequentSolidHorVertLine);
-
- if (info->xaaReq.minorversion >= 1) {
-
- /* RADEON only supports 14 bits for lines and clipping and only
- * draws lines that are completely on-screen correctly. This will
- * cause display corruption problem in the cases when out-of-range
- * commands are issued, like when dimming screen during GNOME logout
- * in dual-head setup. Solid and dashed lines are therefore limited
- * to the virtual screen.
- */
-
- a->SolidLineFlags = LINE_LIMIT_COORDS;
- a->SolidLineLimits.x1 = 0;
- a->SolidLineLimits.y1 = 0;
- a->SolidLineLimits.x2 = pScrn->virtualX-1;
- a->SolidLineLimits.y2 = pScrn->virtualY-1;
-
- /* Call miSetZeroLineBias() to have mi/mfb/fb routines match
- hardware accel two point lines */
- miSetZeroLineBias(pScreen, (OCTANT5 | OCTANT6 | OCTANT7 | OCTANT8));
-
-#ifdef ACCEL_CP
- /* RV280s lock up with this using the CP for reasons to be determined.
- * See https://bugs.freedesktop.org/show_bug.cgi?id=5986 .
- */
- if (info->ChipFamily != CHIP_FAMILY_RV280)
-#endif
- a->SubsequentSolidTwoPointLine
- = FUNC_NAME(RADEONSubsequentSolidTwoPointLine);
-
- /* Disabled on RV200 and newer because it does not pass XTest */
- if (info->ChipFamily < CHIP_FAMILY_RV200) {
- a->SetupForDashedLine
- = FUNC_NAME(RADEONSetupForDashedLine);
- a->SubsequentDashedTwoPointLine
- = FUNC_NAME(RADEONSubsequentDashedTwoPointLine);
- a->DashPatternMaxLength = 32;
- /* ROP3 doesn't seem to work properly for dashedline with GXinvert */
- a->DashedLineFlags = (LINE_PATTERN_LSBFIRST_LSBJUSTIFIED
- | LINE_PATTERN_POWER_OF_2_ONLY
- | LINE_LIMIT_COORDS
- | ROP_NEEDS_SOURCE);
- a->DashedLineLimits.x1 = 0;
- a->DashedLineLimits.y1 = 0;
- a->DashedLineLimits.x2 = pScrn->virtualX-1;
- a->DashedLineLimits.y2 = pScrn->virtualY-1;
- }
-
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "libxaa too old, can't accelerate TwoPoint lines\n");
- }
-
- /* Clipping, note that without this, all line accelerations will
- * not be called
- */
- a->SetClippingRectangle
- = FUNC_NAME(RADEONSetClippingRectangle);
- a->DisableClipping
- = FUNC_NAME(RADEONDisableClipping);
- a->ClippingFlags
- = (HARDWARE_CLIP_SOLID_LINE
- | HARDWARE_CLIP_DASHED_LINE
- /* | HARDWARE_CLIP_SOLID_FILL -- seems very slow with this on */
- | HARDWARE_CLIP_MONO_8x8_FILL
- | HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY);
-
- if (xf86IsEntityShared(info->pEnt->index)) {
- /* If there are more than one devices sharing this entity, we
- * have to assign this call back, otherwise the XAA will be
- * disabled
- */
- if (xf86GetNumEntityInstances(info->pEnt->index) > 1)
- a->RestoreAccelState = FUNC_NAME(RADEONRestoreAccelState);
- }
-
- /* ImageWrite */
- a->NumScanlineImageWriteBuffers = 1;
- a->ScanlineImageWriteBuffers = info->scratch_buffer;
- a->SetupForScanlineImageWrite
- = FUNC_NAME(RADEONSetupForScanlineImageWrite);
- a->SubsequentScanlineImageWriteRect
- = FUNC_NAME(RADEONSubsequentScanlineImageWriteRect);
- a->SubsequentImageWriteScanline = FUNC_NAME(RADEONSubsequentScanline);
- a->ScanlineImageWriteFlags = (CPU_TRANSFER_PAD_DWORD
-#ifdef ACCEL_MMIO
- /* Performance tests show that we shouldn't use GXcopy
- * for uploads as a memcpy is faster
- */
- | NO_GXCOPY
-#endif
- /* RADEON gets upset, when using HOST provided data
- * without a source rop. To show run 'xtest's ptimg
- */
- | ROP_NEEDS_SOURCE
- | SCANLINE_PAD_DWORD
- | LEFT_EDGE_CLIPPING
- | LEFT_EDGE_CLIPPING_NEGATIVE_X);
-
-#if 0
- /* Color 8x8 Pattern Fill */
- a->SetupForColor8x8PatternFill
- = FUNC_NAME(RADEONSetupForColor8x8PatternFill);
- a->SubsequentColor8x8PatternFillRect
- = FUNC_NAME(RADEONSubsequentColor8x8PatternFillRect);
- a->Color8x8PatternFillFlags = (HARDWARE_PATTERN_PROGRAMMED_ORIGIN
- | HARDWARE_PATTERN_SCREEN_ORIGIN
- | BIT_ORDER_IN_BYTE_LSBFIRST);
-#endif
-
-#ifdef RENDER
- if (info->RenderAccel && info->xaaReq.minorversion >= 2) {
-
- a->CPUToScreenAlphaTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY;
- a->CPUToScreenAlphaTextureFormats = RADEONTextureFormats;
- a->CPUToScreenAlphaTextureDstFormats = RADEONDstFormats;
- a->CPUToScreenTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY;
- a->CPUToScreenTextureFormats = RADEONTextureFormats;
- a->CPUToScreenTextureDstFormats = RADEONDstFormats;
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "unsupported on Radeon 9500/9700 and newer.\n");
- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_R200)) {
- a->SetupForCPUToScreenAlphaTexture2 =
- FUNC_NAME(R200SetupForCPUToScreenAlphaTexture);
- a->SubsequentCPUToScreenAlphaTexture =
- FUNC_NAME(R200SubsequentCPUToScreenTexture);
-
- a->SetupForCPUToScreenTexture2 =
- FUNC_NAME(R200SetupForCPUToScreenTexture);
- a->SubsequentCPUToScreenTexture =
- FUNC_NAME(R200SubsequentCPUToScreenTexture);
- } else {
- a->SetupForCPUToScreenAlphaTexture2 =
- FUNC_NAME(R100SetupForCPUToScreenAlphaTexture);
- a->SubsequentCPUToScreenAlphaTexture =
- FUNC_NAME(R100SubsequentCPUToScreenTexture);
-
- a->SetupForCPUToScreenTexture2 =
- FUNC_NAME(R100SetupForCPUToScreenTexture);
- a->SubsequentCPUToScreenTexture =
- FUNC_NAME(R100SubsequentCPUToScreenTexture);
- }
- } else if (info->RenderAccel) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration currently "
- "requires XAA v1.2 or newer.\n");
- }
-
- if (!a->SetupForCPUToScreenAlphaTexture2 && !a->SetupForCPUToScreenTexture2)
- info->RenderAccel = FALSE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration %s\n",
- info->RenderAccel ? "enabled" : "disabled");
-#endif /* RENDER */
-}
-
-#endif /* USE_XAA */
-
-#undef FUNC_NAME
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
deleted file mode 100644
index 88c220b..0000000
--- a/src/radeon_atombios.c
+++ /dev/null
@@ -1,2884 +0,0 @@
-/*
- * Copyright 2007 Egbert Eich <eich at novell.com>
- * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
- * Copyright 2007 Matthias Hopf <mhopf at novell.com>
- * Copyright 2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-# include "config.h"
-#endif
-#include "xf86.h"
-#include "xf86_OSproc.h"
-
-#include "radeon.h"
-#include "radeon_atombios.h"
-#include "radeon_atomwrapper.h"
-#include "radeon_probe.h"
-#include "radeon_macros.h"
-
-#include "xorg-server.h"
-
-/* only for testing now */
-#include "xf86DDC.h"
-
-typedef AtomBiosResult (*AtomBiosRequestFunc)(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data);
-typedef struct rhdConnectorInfo *rhdConnectorInfoPtr;
-
-static AtomBiosResult rhdAtomInit(atomBiosHandlePtr unused1,
- AtomBiosRequestID unused2, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomTearDown(atomBiosHandlePtr handle,
- AtomBiosRequestID unused1, AtomBiosArgPtr unused2);
-static AtomBiosResult rhdAtomVramInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomAllocateFbScratch(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomLvdsGetTimings(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomCVGetTimings(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-static AtomBiosResult rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-/*static AtomBiosResult rhdAtomConnectorInfo(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data);*/
-# ifdef ATOM_BIOS_PARSER
-static AtomBiosResult rhdAtomExec(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data);
-# endif
-static AtomBiosResult
-rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data);
-
-
-enum msgDataFormat {
- MSG_FORMAT_NONE,
- MSG_FORMAT_HEX,
- MSG_FORMAT_DEC
-};
-
-struct atomBIOSRequests {
- AtomBiosRequestID id;
- AtomBiosRequestFunc request;
- char *message;
- enum msgDataFormat message_format;
-} AtomBiosRequestList [] = {
- {ATOMBIOS_INIT, rhdAtomInit,
- "AtomBIOS Init", MSG_FORMAT_NONE},
- {ATOMBIOS_TEARDOWN, rhdAtomTearDown,
- "AtomBIOS Teardown", MSG_FORMAT_NONE},
-# ifdef ATOM_BIOS_PARSER
- {ATOMBIOS_EXEC, rhdAtomExec,
- "AtomBIOS Exec", MSG_FORMAT_NONE},
-#endif
- {ATOMBIOS_ALLOCATE_FB_SCRATCH, rhdAtomAllocateFbScratch,
- "AtomBIOS Set FB Space", MSG_FORMAT_NONE},
- /*{ATOMBIOS_GET_CONNECTORS, rhdAtomConnectorInfo,
- "AtomBIOS Get Connectors", MSG_FORMAT_NONE},*/
- {ATOMBIOS_GET_PANEL_MODE, rhdAtomLvdsGetTimings,
- "AtomBIOS Get Panel Mode", MSG_FORMAT_NONE},
- {ATOMBIOS_GET_PANEL_EDID, rhdAtomLvdsGetTimings,
- "AtomBIOS Get Panel EDID", MSG_FORMAT_NONE},
- {GET_DEFAULT_ENGINE_CLOCK, rhdAtomFirmwareInfoQuery,
- "Default Engine Clock", MSG_FORMAT_DEC},
- {GET_DEFAULT_MEMORY_CLOCK, rhdAtomFirmwareInfoQuery,
- "Default Memory Clock", MSG_FORMAT_DEC},
- {GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery,
- "Maximum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC},
- {GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery,
- "Minimum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC},
- {GET_MAX_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery,
- "Maximum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC},
- {GET_MIN_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery,
- "Minimum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC},
- {GET_MAX_PIXEL_CLK, rhdAtomFirmwareInfoQuery,
- "Maximum Pixel Clock", MSG_FORMAT_DEC},
- {GET_REF_CLOCK, rhdAtomFirmwareInfoQuery,
- "Reference Clock", MSG_FORMAT_DEC},
- {GET_FW_FB_START, rhdAtomVramInfoQuery,
- "Start of VRAM area used by Firmware", MSG_FORMAT_HEX},
- {GET_FW_FB_SIZE, rhdAtomVramInfoQuery,
- "Framebuffer space used by Firmware (kb)", MSG_FORMAT_DEC},
- {ATOM_TMDS_FREQUENCY, rhdAtomTmdsInfoQuery,
- "TMDS Frequency", MSG_FORMAT_DEC},
- {ATOM_TMDS_PLL_CHARGE_PUMP, rhdAtomTmdsInfoQuery,
- "TMDS PLL ChargePump", MSG_FORMAT_DEC},
- {ATOM_TMDS_PLL_DUTY_CYCLE, rhdAtomTmdsInfoQuery,
- "TMDS PLL DutyCycle", MSG_FORMAT_DEC},
- {ATOM_TMDS_PLL_VCO_GAIN, rhdAtomTmdsInfoQuery,
- "TMDS PLL VCO Gain", MSG_FORMAT_DEC},
- {ATOM_TMDS_PLL_VOLTAGE_SWING, rhdAtomTmdsInfoQuery,
- "TMDS PLL VoltageSwing", MSG_FORMAT_DEC},
- {ATOM_LVDS_SUPPORTED_REFRESH_RATE, rhdAtomLvdsInfoQuery,
- "LVDS Supported Refresh Rate", MSG_FORMAT_DEC},
- {ATOM_LVDS_OFF_DELAY, rhdAtomLvdsInfoQuery,
- "LVDS Off Delay", MSG_FORMAT_DEC},
- {ATOM_LVDS_SEQ_DIG_ONTO_DE, rhdAtomLvdsInfoQuery,
- "LVDS SEQ Dig onto DE", MSG_FORMAT_DEC},
- {ATOM_LVDS_SEQ_DE_TO_BL, rhdAtomLvdsInfoQuery,
- "LVDS SEQ DE to BL", MSG_FORMAT_DEC},
- {ATOM_LVDS_DITHER, rhdAtomLvdsInfoQuery,
- "LVDS Ditherc", MSG_FORMAT_HEX},
- {ATOM_LVDS_DUALLINK, rhdAtomLvdsInfoQuery,
- "LVDS Duallink", MSG_FORMAT_HEX},
- {ATOM_LVDS_GREYLVL, rhdAtomLvdsInfoQuery,
- "LVDS Grey Level", MSG_FORMAT_HEX},
- {ATOM_LVDS_FPDI, rhdAtomLvdsInfoQuery,
- "LVDS FPDI", MSG_FORMAT_HEX},
- {ATOM_LVDS_24BIT, rhdAtomLvdsInfoQuery,
- "LVDS 24Bit", MSG_FORMAT_HEX},
- {ATOM_GPIO_I2C_CLK_MASK, rhdAtomGPIOI2CInfoQuery,
- "GPIO_I2C_Clk_Mask", MSG_FORMAT_HEX},
- {ATOM_DAC1_BG_ADJ, rhdAtomCompassionateDataQuery,
- "DAC1 BG Adjustment", MSG_FORMAT_HEX},
- {ATOM_DAC1_DAC_ADJ, rhdAtomCompassionateDataQuery,
- "DAC1 DAC Adjustment", MSG_FORMAT_HEX},
- {ATOM_DAC1_FORCE, rhdAtomCompassionateDataQuery,
- "DAC1 Force Data", MSG_FORMAT_HEX},
- {ATOM_DAC2_CRTC2_BG_ADJ, rhdAtomCompassionateDataQuery,
- "DAC2_CRTC2 BG Adjustment", MSG_FORMAT_HEX},
- {ATOM_DAC2_CRTC2_DAC_ADJ, rhdAtomCompassionateDataQuery,
- "DAC2_CRTC2 DAC Adjustment", MSG_FORMAT_HEX},
- {ATOM_DAC2_CRTC2_FORCE, rhdAtomCompassionateDataQuery,
- "DAC2_CRTC2 Force", MSG_FORMAT_HEX},
- {ATOM_DAC2_CRTC2_MUX_REG_IND,rhdAtomCompassionateDataQuery,
- "DAC2_CRTC2 Mux Register Index", MSG_FORMAT_HEX},
- {ATOM_DAC2_CRTC2_MUX_REG_INFO,rhdAtomCompassionateDataQuery,
- "DAC2_CRTC2 Mux Register Info", MSG_FORMAT_HEX},
- {ATOMBIOS_GET_CV_MODES, rhdAtomCVGetTimings,
- "AtomBIOS Get CV Mode", MSG_FORMAT_NONE},
- {FUNC_END, NULL,
- NULL, MSG_FORMAT_NONE}
-};
-
-enum {
- legacyBIOSLocation = 0xC0000,
- legacyBIOSMax = 0x10000
-};
-
-#define DEBUGP(x) {x;}
-#define LOG_DEBUG 7
-
-# ifdef ATOM_BIOS_PARSER
-
-# define LOG_CAIL LOG_DEBUG + 1
-
-#if 0
-
-static void
-RHDDebug(int scrnIndex, const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_DEBUG, format, ap);
- va_end(ap);
-}
-
-static void
-RHDDebugCont(const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- xf86VDrvMsgVerb(-1, X_NONE, LOG_DEBUG, format, ap);
- va_end(ap);
-}
-
-#endif
-
-static void
-CailDebug(int scrnIndex, const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_CAIL, format, ap);
- va_end(ap);
-}
-# define CAILFUNC(ptr) \
- CailDebug(((atomBiosHandlePtr)(ptr))->scrnIndex, "CAIL: %s\n", __func__)
-
-# endif
-
-static int
-rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr)
-{
- if (hdr->usStructureSize == 0xaa55)
- return FALSE;
-
- return TRUE;
-}
-
-static int
-rhdAtomAnalyzeRomHdr(unsigned char *rombase,
- ATOM_ROM_HEADER *hdr,
- unsigned int *data_offset,
- unsigned int *command_offset)
-{
- if (!rhdAtomAnalyzeCommonHdr(&hdr->sHeader)) {
- return FALSE;
- }
- xf86DrvMsg(-1,X_NONE,"\tSubsystemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n",
- hdr->usSubsystemVendorID,hdr->usSubsystemID);
- xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress);
- xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset);
- xf86DrvMsgVerb(-1,X_NONE,3,"\tBIOS Bootup Message: %s\n",
- rombase + hdr->usBIOS_BootupMessageOffset);
-
- *data_offset = hdr->usMasterDataTableOffset;
- *command_offset = hdr->usMasterCommandTableOffset;
-
- return TRUE;
-}
-
-static int
-rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset,
- void *ptr,unsigned short *size)
-{
- ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *)
- (base + offset);
-
- if (!*size || !rhdAtomAnalyzeCommonHdr(table)) {
- if (*size) *size -= 2;
- *(void **)ptr = NULL;
- return FALSE;
- }
- *size -= 2;
- *(void **)ptr = (void *)(table);
- return TRUE;
-}
-
-Bool
-rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr,
- CARD8 *contentRev,
- CARD8 *formatRev,
- unsigned short *size)
-{
- if (!hdr)
- return FALSE;
-
- if (contentRev) *contentRev = hdr->ucTableContentRevision;
- if (formatRev) *formatRev = hdr->ucTableFormatRevision;
- if (size) *size = (short)hdr->usStructureSize
- - sizeof(ATOM_COMMON_TABLE_HEADER);
- return TRUE;
-}
-
-static Bool
-rhdAtomAnalyzeMasterDataTable(unsigned char *base,
- ATOM_MASTER_DATA_TABLE *table,
- atomDataTablesPtr data)
-{
- ATOM_MASTER_LIST_OF_DATA_TABLES *data_table =
- &table->ListOfDataTables;
- unsigned short size;
-
- if (!rhdAtomAnalyzeCommonHdr(&table->sHeader))
- return FALSE;
- if (!rhdAtomGetTableRevisionAndSize(&table->sHeader,NULL,NULL,
- &size))
- return FALSE;
-# define SET_DATA_TABLE(x) {\
- rhdAtomAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \
- }
-
-# define SET_DATA_TABLE_VERS(x) {\
- rhdAtomAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \
- }
-
- SET_DATA_TABLE(UtilityPipeLine);
- SET_DATA_TABLE(MultimediaCapabilityInfo);
- SET_DATA_TABLE(MultimediaConfigInfo);
- SET_DATA_TABLE(StandardVESA_Timing);
- SET_DATA_TABLE_VERS(FirmwareInfo);
- SET_DATA_TABLE(DAC_Info);
- SET_DATA_TABLE_VERS(LVDS_Info);
- SET_DATA_TABLE(TMDS_Info);
- SET_DATA_TABLE(AnalogTV_Info);
- SET_DATA_TABLE_VERS(SupportedDevicesInfo);
- SET_DATA_TABLE(GPIO_I2C_Info);
- SET_DATA_TABLE(VRAM_UsageByFirmware);
- SET_DATA_TABLE(GPIO_Pin_LUT);
- SET_DATA_TABLE(VESA_ToInternalModeLUT);
- SET_DATA_TABLE_VERS(ComponentVideoInfo);
- SET_DATA_TABLE(PowerPlayInfo);
- SET_DATA_TABLE(CompassionateData);
- SET_DATA_TABLE(SaveRestoreInfo);
- SET_DATA_TABLE(PPLL_SS_Info);
- SET_DATA_TABLE(OemInfo);
- SET_DATA_TABLE(XTMDS_Info);
- SET_DATA_TABLE(MclkSS_Info);
- SET_DATA_TABLE(Object_Header);
- SET_DATA_TABLE(IndirectIOAccess);
- SET_DATA_TABLE(MC_InitParameter);
- SET_DATA_TABLE(ASIC_VDDC_Info);
- SET_DATA_TABLE(ASIC_InternalSS_Info);
- SET_DATA_TABLE(TV_VideoMode);
- SET_DATA_TABLE_VERS(VRAM_Info);
- SET_DATA_TABLE(MemoryTrainingInfo);
- SET_DATA_TABLE_VERS(IntegratedSystemInfo);
- SET_DATA_TABLE(ASIC_ProfilingInfo);
- SET_DATA_TABLE(VoltageObjectInfo);
- SET_DATA_TABLE(PowerSourceInfo);
-# undef SET_DATA_TABLE
-
- return TRUE;
-}
-
-static Bool
-rhdAtomGetDataTable(int scrnIndex,
- unsigned char *base,
- atomDataTables *atomDataPtr,
- unsigned int *cmd_offset,
- unsigned int BIOSImageSize)
-{
- unsigned int data_offset;
- unsigned int atom_romhdr_off = *(unsigned short*)
- (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
- ATOM_ROM_HEADER *atom_rom_hdr =
- (ATOM_ROM_HEADER *)(base + atom_romhdr_off);
-
- //RHDFUNCI(scrnIndex);
-
- if (atom_romhdr_off + sizeof(ATOM_ROM_HEADER) > BIOSImageSize) {
- xf86DrvMsg(scrnIndex,X_ERROR,
- "%s: AtomROM header extends beyond BIOS image\n",__func__);
- return FALSE;
- }
-
- if (memcmp("ATOM",&atom_rom_hdr->uaFirmWareSignature,4)) {
- xf86DrvMsg(scrnIndex,X_ERROR,"%s: No AtomBios signature found\n",
- __func__);
- return FALSE;
- }
- xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n");
- if (!rhdAtomAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) {
- xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n");
- return FALSE;
- }
-
- if (data_offset + sizeof (ATOM_MASTER_DATA_TABLE) > BIOSImageSize) {
- xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom data table outside of BIOS\n",
- __func__);
- }
-
- if (*cmd_offset + sizeof (ATOM_MASTER_COMMAND_TABLE) > BIOSImageSize) {
- xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom command table outside of BIOS\n",
- __func__);
- }
-
- if (!rhdAtomAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *)
- (base + data_offset),
- atomDataPtr)) {
- xf86DrvMsg(scrnIndex, X_ERROR, "%s: ROM Master Table invalid\n",
- __func__);
- return FALSE;
- }
- return TRUE;
-}
-
-static Bool
-rhdAtomGetFbBaseAndSize(atomBiosHandlePtr handle, unsigned int *base,
- unsigned int *size)
-{
- AtomBiosArgRec data;
- if (RHDAtomBiosFunc(handle->scrnIndex, handle, GET_FW_FB_SIZE, &data)
- == ATOM_SUCCESS) {
- if (data.val == 0) {
- xf86DrvMsg(handle->scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM "
- "scratch space size invalid\n", __func__);
- return FALSE;
- }
- if (size)
- *size = (int)data.val;
- } else
- return FALSE;
- if (RHDAtomBiosFunc(handle->scrnIndex, handle, GET_FW_FB_START, &data)
- == ATOM_SUCCESS) {
- if (data.val == 0)
- return FALSE;
- if (base)
- *base = (int)data.val;
- }
- return TRUE;
-}
-
-/*
- * Uses videoRam form ScrnInfoRec.
- */
-static AtomBiosResult
-rhdAtomAllocateFbScratch(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data)
-{
- unsigned int fb_base = 0;
- unsigned int fb_size = 0;
- unsigned int start = data->fb.start;
- unsigned int size = data->fb.size;
- handle->scratchBase = NULL;
- handle->fbBase = 0;
-
- if (rhdAtomGetFbBaseAndSize(handle, &fb_base, &fb_size)) {
- xf86DrvMsg(handle->scrnIndex, X_INFO, "AtomBIOS requests %ikB"
- " of VRAM scratch space\n",fb_size);
- fb_size *= 1024; /* convert to bytes */
- xf86DrvMsg(handle->scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n",
- fb_base);
- } else {
- fb_size = 20 * 1024;
- xf86DrvMsg(handle->scrnIndex, X_INFO, " default to: %i\n",fb_size);
- }
- if (fb_base && fb_size && size) {
- /* 4k align */
- fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0);
- if ((fb_base + fb_size) > (start + size)) {
- xf86DrvMsg(handle->scrnIndex, X_WARNING,
- "%s: FW FB scratch area %i (size: %i)"
- " extends beyond available framebuffer size %i\n",
- __func__, fb_base, fb_size, size);
- } else if ((fb_base + fb_size) < (start + size)) {
- xf86DrvMsg(handle->scrnIndex, X_WARNING,
- "%s: FW FB scratch area not located "
- "at the end of VRAM. Scratch End: "
- "0x%x VRAM End: 0x%x\n", __func__,
- (unsigned int)(fb_base + fb_size),
- size);
- } else if (fb_base < start) {
- xf86DrvMsg(handle->scrnIndex, X_WARNING,
- "%s: FW FB scratch area extends below "
- "the base of the free VRAM: 0x%x Base: 0x%x\n",
- __func__, (unsigned int)(fb_base), start);
- } else {
- size -= fb_size;
- handle->fbBase = fb_base;
- return ATOM_SUCCESS;
- }
- }
-
- if (!handle->fbBase) {
- xf86DrvMsg(handle->scrnIndex, X_INFO,
- "Cannot get VRAM scratch space. "
- "Allocating in main memory instead\n");
- handle->scratchBase = xcalloc(fb_size,1);
- return ATOM_SUCCESS;
- }
- return ATOM_FAILED;
-}
-
-# ifdef ATOM_BIOS_PARSER
-static Bool
-rhdAtomASICInit(atomBiosHandlePtr handle)
-{
- ASIC_INIT_PS_ALLOCATION asicInit;
- AtomBiosArgRec data;
-
- RHDAtomBiosFunc(handle->scrnIndex, handle,
- GET_DEFAULT_ENGINE_CLOCK,
- &data);
- asicInit.sASICInitClocks.ulDefaultEngineClock = data.val / 10;/*in 10 Khz*/
- RHDAtomBiosFunc(handle->scrnIndex, handle,
- GET_DEFAULT_MEMORY_CLOCK,
- &data);
- asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val / 10;/*in 10 Khz*/
- data.exec.dataSpace = NULL;
- data.exec.index = 0x0;
- data.exec.pspace = &asicInit;
- xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling ASIC Init\n");
- if (RHDAtomBiosFunc(handle->scrnIndex, handle,
- ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Successful\n");
- return TRUE;
- }
- xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Failed\n");
- return FALSE;
-}
-
-Bool
-rhdAtomSetScaler(atomBiosHandlePtr handle, unsigned char scalerID, int setting)
-{
- ENABLE_SCALER_PARAMETERS scaler;
- AtomBiosArgRec data;
-
- scaler.ucScaler = scalerID;
- scaler.ucEnable = setting;
- data.exec.dataSpace = NULL;
- data.exec.index = 0x21;
- data.exec.pspace = &scaler;
- xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling EnableScaler\n");
- if (RHDAtomBiosFunc(handle->scrnIndex, handle,
- ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- xf86DrvMsg(handle->scrnIndex, X_INFO, "EnableScaler Successful\n");
- return TRUE;
- }
- xf86DrvMsg(handle->scrnIndex, X_INFO, "EableScaler Failed\n");
- return FALSE;
-}
-
-# endif
-
-static AtomBiosResult
-rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
- AtomBiosArgPtr data)
-{
- int scrnIndex = data->val;
- RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]);
- unsigned char *ptr;
- atomDataTablesPtr atomDataPtr;
- unsigned int cmd_offset;
- atomBiosHandlePtr handle = NULL;
- unsigned int BIOSImageSize = 0;
- data->atomhandle = NULL;
-
- //RHDFUNCI(scrnIndex);
-
- /*if (info->BIOSCopy) {
- xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from INT10\n");
- ptr = info->BIOSCopy;
- info->BIOSCopy = NULL;
-
- BIOSImageSize = ptr[2] * 512;
- if (BIOSImageSize > legacyBIOSMax) {
- xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n");
- return ATOM_FAILED;
- }
- } else*/ {
- /*if (!xf86IsEntityPrimary(info->entityIndex)) {
- if (!(BIOSImageSize = RHDReadPCIBios(info, &ptr)))
- return ATOM_FAILED;
- } else*/ {
- int read_len;
- unsigned char tmp[32];
- xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from legacy VBIOS location\n");
- if (xf86ReadBIOS(legacyBIOSLocation, 0, tmp, 32) < 0) {
- xf86DrvMsg(scrnIndex,X_ERROR,
- "Cannot obtain POSTed BIOS header\n");
- return ATOM_FAILED;
- }
- BIOSImageSize = tmp[2] * 512;
- if (BIOSImageSize > legacyBIOSMax) {
- xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n");
- return ATOM_FAILED;
- }
- if (!(ptr = xcalloc(1,BIOSImageSize))) {
- xf86DrvMsg(scrnIndex,X_ERROR,
- "Cannot allocate %i bytes of memory "
- "for BIOS image\n",BIOSImageSize);
- return ATOM_FAILED;
- }
- if ((read_len = xf86ReadBIOS(legacyBIOSLocation, 0, ptr, BIOSImageSize)
- < 0)) {
- xf86DrvMsg(scrnIndex,X_ERROR,"Cannot read POSTed BIOS\n");
- goto error;
- }
- }
- }
-
- if (!(atomDataPtr = xcalloc(1, sizeof(atomDataTables)))) {
- xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for "
- "ATOM BIOS data tabes\n");
- goto error;
- }
- if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr, &cmd_offset, BIOSImageSize))
- goto error1;
- if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) {
- xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n");
- goto error1;
- }
- handle->BIOSBase = ptr;
- handle->atomDataPtr = atomDataPtr;
- handle->cmd_offset = cmd_offset;
- handle->scrnIndex = scrnIndex;
-#if XSERVER_LIBPCIACCESS
- handle->device = info->PciInfo;
-#else
- handle->PciTag = info->PciTag;
-#endif
- handle->BIOSImageSize = BIOSImageSize;
-
-# if ATOM_BIOS_PARSER
- /* Try to find out if BIOS has been posted (either by system or int10 */
- if (!rhdAtomGetFbBaseAndSize(handle, NULL, NULL)) {
- /* run AsicInit */
- if (!rhdAtomASICInit(handle))
- xf86DrvMsg(scrnIndex, X_WARNING,
- "%s: AsicInit failed. Won't be able to obtain in VRAM "
- "FB scratch space\n",__func__);
- }
-# endif
-
- data->atomhandle = handle;
- return ATOM_SUCCESS;
-
- error1:
- xfree(atomDataPtr);
- error:
- xfree(ptr);
- return ATOM_FAILED;
-}
-
-static AtomBiosResult
-rhdAtomTearDown(atomBiosHandlePtr handle,
- AtomBiosRequestID unused1, AtomBiosArgPtr unused2)
-{
- //RHDFUNC(handle);
-
- xfree(handle->BIOSBase);
- xfree(handle->atomDataPtr);
- if (handle->scratchBase) xfree(handle->scratchBase);
- xfree(handle);
- return ATOM_SUCCESS;
-}
-
-static AtomBiosResult
-rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func,
- AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD32 *val = &data->val;
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- switch (func) {
- case GET_FW_FB_START:
- *val = atomDataPtr->VRAM_UsageByFirmware
- ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
- break;
- case GET_FW_FB_SIZE:
- *val = atomDataPtr->VRAM_UsageByFirmware
- ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- return ATOM_SUCCESS;
-}
-
-static AtomBiosResult
-rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD32 *val = &data->val;
- int idx = *val;
-
- atomDataPtr = handle->atomDataPtr;
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->TMDS_Info),
- NULL,NULL,NULL)) {
- return ATOM_FAILED;
- }
-
- //RHDFUNC(handle);
-
- switch (func) {
- case ATOM_TMDS_FREQUENCY:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency;
- break;
- case ATOM_TMDS_PLL_CHARGE_PUMP:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_ChargePump;
- break;
- case ATOM_TMDS_PLL_DUTY_CYCLE:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_DutyCycle;
- break;
- case ATOM_TMDS_PLL_VCO_GAIN:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VCO_Gain;
- break;
- case ATOM_TMDS_PLL_VOLTAGE_SWING:
- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VoltageSwing;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- return ATOM_SUCCESS;
-}
-
-static DisplayModePtr
-rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd)
-{
- DisplayModePtr mode;
-#define NAME_LEN 16
- char name[NAME_LEN];
-
- //RHDFUNC(handle);
-
- if (!dtd->usHActive || !dtd->usVActive)
- return NULL;
-
- if (!(mode = (DisplayModePtr)xcalloc(1,sizeof(DisplayModeRec))))
- return NULL;
-
- mode->CrtcHDisplay = mode->HDisplay = dtd->usHActive;
- mode->CrtcVDisplay = mode->VDisplay = dtd->usVActive;
- mode->CrtcHBlankStart = dtd->usHActive + dtd->ucHBorder;
- mode->CrtcHBlankEnd = mode->CrtcHBlankStart + dtd->usHBlanking_Time;
- mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd + dtd->ucHBorder;
- mode->CrtcVBlankStart = dtd->usVActive + dtd->ucVBorder;
- mode->CrtcVBlankEnd = mode->CrtcVBlankStart + dtd->usVBlanking_Time;
- mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd + dtd->ucVBorder;
- mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + dtd->usHSyncOffset;
- mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + dtd->usHSyncWidth;
- mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + dtd->usVSyncOffset;
- mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + dtd->usVSyncWidth;
-
- mode->SynthClock = mode->Clock = dtd->usPixClk * 10;
-
- mode->HSync = ((float) mode->Clock) / ((float)mode->HTotal);
- mode->VRefresh = (1000.0 * ((float) mode->Clock))
- / ((float)(((float)mode->HTotal) * ((float)mode->VTotal)));
-
- if (dtd->susModeMiscInfo.sbfAccess.CompositeSync)
- mode->Flags |= V_CSYNC;
- if (dtd->susModeMiscInfo.sbfAccess.Interlace)
- mode->Flags |= V_INTERLACE;
- if (dtd->susModeMiscInfo.sbfAccess.DoubleClock)
- mode->Flags |= V_DBLSCAN;
- if (dtd->susModeMiscInfo.sbfAccess.VSyncPolarity)
- mode->Flags |= V_NVSYNC;
- if (dtd->susModeMiscInfo.sbfAccess.HSyncPolarity)
- mode->Flags |= V_NHSYNC;
-
- snprintf(name, NAME_LEN, "%dx%d",
- mode->HDisplay, mode->VDisplay);
- mode->name = xstrdup(name);
-
- ErrorF("DTD Modeline: %s "
- "%2.d %i (%i) %i %i (%i) %i %i (%i) %i %i (%i) %i flags: 0x%x\n",
- mode->name, mode->Clock,
- mode->HDisplay, mode->CrtcHBlankStart, mode->HSyncStart, mode->CrtcHSyncEnd,
- mode->CrtcHBlankEnd, mode->HTotal,
- mode->VDisplay, mode->CrtcVBlankStart, mode->VSyncStart, mode->VSyncEnd,
- mode->CrtcVBlankEnd, mode->VTotal, mode->Flags);
-
- return mode;
-}
-
-static unsigned char*
-rhdAtomLvdsDDC(atomBiosHandlePtr handle, CARD32 offset, unsigned char *record)
-{
- unsigned char *EDIDBlock;
-
- //RHDFUNC(handle);
-
- while (*record != ATOM_RECORD_END_TYPE) {
-
- switch (*record) {
- case LCD_MODE_PATCH_RECORD_MODE_TYPE:
- offset += sizeof(ATOM_PATCH_RECORD_MODE);
- if (offset > handle->BIOSImageSize) break;
- record += sizeof(ATOM_PATCH_RECORD_MODE);
- break;
-
- case LCD_RTS_RECORD_TYPE:
- offset += sizeof(ATOM_LCD_RTS_RECORD);
- if (offset > handle->BIOSImageSize) break;
- record += sizeof(ATOM_LCD_RTS_RECORD);
- break;
-
- case LCD_CAP_RECORD_TYPE:
- offset += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
- if (offset > handle->BIOSImageSize) break;
- record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
- break;
-
- case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
- offset += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
- /* check if the structure still fully lives in the BIOS image */
- if (offset > handle->BIOSImageSize) break;
- offset += ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength
- - sizeof(UCHAR);
- if (offset > handle->BIOSImageSize) break;
- /* dup string as we free it later */
- if (!(EDIDBlock = (unsigned char *)xalloc(
- ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength)))
- return NULL;
- memcpy(EDIDBlock,&((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDString,
- ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength);
-
- /* for testing */
- {
- xf86MonPtr mon = xf86InterpretEDID(handle->scrnIndex,EDIDBlock);
- xf86PrintEDID(mon);
- xfree(mon);
- }
- return EDIDBlock;
-
- case LCD_PANEL_RESOLUTION_RECORD_TYPE:
- offset += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
- if (offset > handle->BIOSImageSize) break;
- record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
- break;
-
- default:
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: unknown record type: %x\n",__func__,*record);
- return NULL;
- }
- }
-
- return NULL;
-}
-
-static AtomBiosResult
-rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func,
- AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- DisplayModePtr last = NULL;
- DisplayModePtr new = NULL;
- DisplayModePtr first = NULL;
- int i;
-
- data->modes = NULL;
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->ComponentVideoInfo.base),
- &frev,&crev,NULL)) {
- return ATOM_FAILED;
- }
-
- switch (frev) {
-
- case 1:
- switch (func) {
- case ATOMBIOS_GET_CV_MODES:
- for (i = 0; i < MAX_SUPPORTED_CV_STANDARDS; i++) {
- new = rhdAtomDTDTimings(handle,
- &atomDataPtr->ComponentVideoInfo
- .ComponentVideoInfo->aModeTimings[i]);
-
- if (!new)
- continue;
-
- new->type |= M_T_DRIVER;
- new->next = NULL;
- new->prev = last;
-
- if (last) last->next = new;
- last = new;
- if (!first) first = new;
- }
- if (last) {
- last->next = NULL; //first;
- first->prev = NULL; //last;
- data->modes = first;
- }
- if (data->modes)
- return ATOM_SUCCESS;
- default:
- return ATOM_FAILED;
- }
- case 2:
- switch (func) {
- case ATOMBIOS_GET_CV_MODES:
- for (i = 0; i < MAX_SUPPORTED_CV_STANDARDS; i++) {
- new = rhdAtomDTDTimings(handle,
- &atomDataPtr->ComponentVideoInfo
- .ComponentVideoInfo_v21->aModeTimings[i]);
-
- if (!new)
- continue;
-
- new->type |= M_T_DRIVER;
- new->next = NULL;
- new->prev = last;
-
- if (last) last->next = new;
- last = new;
- if (!first) first = new;
-
- }
- if (last) {
- last->next = NULL; //first;
- first->prev = NULL; //last;
- data->modes = first;
- }
- if (data->modes)
- return ATOM_SUCCESS;
- return ATOM_FAILED;
-
- default:
- return ATOM_FAILED;
- }
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
-/*NOTREACHED*/
-}
-
-static AtomBiosResult
-rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func,
- AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- unsigned long offset;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base),
- &frev,&crev,NULL)) {
- return ATOM_FAILED;
- }
-
- switch (crev) {
-
- case 1:
- switch (func) {
- case ATOMBIOS_GET_PANEL_MODE:
- data->modes = rhdAtomDTDTimings(handle,
- &atomDataPtr->LVDS_Info
- .LVDS_Info->sLCDTiming);
- if (data->modes)
- return ATOM_SUCCESS;
- default:
- return ATOM_FAILED;
- }
- case 2:
- switch (func) {
- case ATOMBIOS_GET_PANEL_MODE:
- data->modes = rhdAtomDTDTimings(handle,
- &atomDataPtr->LVDS_Info
- .LVDS_Info_v12->sLCDTiming);
- if (data->modes)
- return ATOM_SUCCESS;
- return ATOM_FAILED;
-
- case ATOMBIOS_GET_PANEL_EDID:
- offset = (unsigned long)&atomDataPtr->LVDS_Info.base
- - (unsigned long)handle->BIOSBase
- + atomDataPtr->LVDS_Info
- .LVDS_Info_v12->usExtInfoTableOffset;
-
- data->EDIDBlock
- = rhdAtomLvdsDDC(handle, offset,
- (unsigned char *)
- &atomDataPtr->LVDS_Info.base
- + atomDataPtr->LVDS_Info
- .LVDS_Info_v12->usExtInfoTableOffset);
- if (data->EDIDBlock)
- return ATOM_SUCCESS;
- default:
- return ATOM_FAILED;
- }
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
-/*NOTREACHED*/
-}
-
-static AtomBiosResult
-rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- CARD32 *val = &data->val;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base),
- &frev,&crev,NULL)) {
- return ATOM_FAILED;
- }
-
- switch (crev) {
- case 1:
- switch (func) {
- case ATOM_LVDS_SUPPORTED_REFRESH_RATE:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->usSupportedRefreshRate;
- break;
- case ATOM_LVDS_OFF_DELAY:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->usOffDelayInMs;
- break;
- case ATOM_LVDS_SEQ_DIG_ONTO_DE:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucPowerSequenceDigOntoDEin10Ms * 10;
- break;
- case ATOM_LVDS_SEQ_DE_TO_BL:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucPowerSequenceDEtoBLOnin10Ms * 10;
- break;
- case ATOM_LVDS_DITHER:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucLVDS_Misc & 0x40;
- break;
- case ATOM_LVDS_DUALLINK:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucLVDS_Misc & 0x01;
- break;
- case ATOM_LVDS_24BIT:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucLVDS_Misc & 0x02;
- break;
- case ATOM_LVDS_GREYLVL:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucLVDS_Misc & 0x0C;
- break;
- case ATOM_LVDS_FPDI:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info->ucLVDS_Misc * 0x10;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- break;
- case 2:
- switch (func) {
- case ATOM_LVDS_SUPPORTED_REFRESH_RATE:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->usSupportedRefreshRate;
- break;
- case ATOM_LVDS_OFF_DELAY:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->usOffDelayInMs;
- break;
- case ATOM_LVDS_SEQ_DIG_ONTO_DE:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucPowerSequenceDigOntoDEin10Ms * 10;
- break;
- case ATOM_LVDS_SEQ_DE_TO_BL:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucPowerSequenceDEtoBLOnin10Ms * 10;
- break;
- case ATOM_LVDS_DITHER:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucLVDS_Misc & 0x40;
- break;
- case ATOM_LVDS_DUALLINK:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucLVDS_Misc & 0x01;
- break;
- case ATOM_LVDS_24BIT:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucLVDS_Misc & 0x02;
- break;
- case ATOM_LVDS_GREYLVL:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucLVDS_Misc & 0x0C;
- break;
- case ATOM_LVDS_FPDI:
- *val = atomDataPtr->LVDS_Info
- .LVDS_Info_v12->ucLVDS_Misc * 0x10;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
-
- return ATOM_SUCCESS;
-}
-
-static AtomBiosResult
-rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- CARD32 *val = &data->val;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->CompassionateData),
- &frev,&crev,NULL)) {
- return ATOM_FAILED;
- }
-
- switch (func) {
- case ATOM_DAC1_BG_ADJ:
- *val = atomDataPtr->CompassionateData->
- ucDAC1_BG_Adjustment;
- break;
- case ATOM_DAC1_DAC_ADJ:
- *val = atomDataPtr->CompassionateData->
- ucDAC1_DAC_Adjustment;
- break;
- case ATOM_DAC1_FORCE:
- *val = atomDataPtr->CompassionateData->
- usDAC1_FORCE_Data;
- break;
- case ATOM_DAC2_CRTC2_BG_ADJ:
- *val = atomDataPtr->CompassionateData->
- ucDAC2_CRT2_BG_Adjustment;
- break;
- case ATOM_DAC2_CRTC2_DAC_ADJ:
- *val = atomDataPtr->CompassionateData->
- ucDAC2_CRT2_DAC_Adjustment;
- break;
- case ATOM_DAC2_CRTC2_FORCE:
- *val = atomDataPtr->CompassionateData->
- usDAC2_CRT2_FORCE_Data;
- break;
- case ATOM_DAC2_CRTC2_MUX_REG_IND:
- *val = atomDataPtr->CompassionateData->
- usDAC2_CRT2_MUX_RegisterIndex;
- break;
- case ATOM_DAC2_CRTC2_MUX_REG_INFO:
- *val = atomDataPtr->CompassionateData->
- ucDAC2_CRT2_MUX_RegisterInfo;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- return ATOM_SUCCESS;
-}
-
-static AtomBiosResult
-rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- CARD32 *val = &data->val;
- unsigned short size;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->GPIO_I2C_Info),
- &frev,&crev,&size)) {
- return ATOM_FAILED;
- }
-
- switch (func) {
- case ATOM_GPIO_I2C_CLK_MASK:
- if ((sizeof(ATOM_COMMON_TABLE_HEADER)
- + (*val * sizeof(ATOM_GPIO_I2C_ASSIGMENT))) > size) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: GPIO_I2C Device "
- "num %lu exeeds table size %u\n",__func__,
- (unsigned long)val,
- size);
- return ATOM_FAILED;
- }
-
- *val = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val]
- .usClkMaskRegisterIndex;
- break;
-
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- return ATOM_SUCCESS;
-}
-
-static AtomBiosResult
-rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle,
- AtomBiosRequestID func, AtomBiosArgPtr data)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- CARD32 *val = &data->val;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base),
- &crev,&frev,NULL)) {
- return ATOM_FAILED;
- }
-
- switch (crev) {
- case 1:
- switch (func) {
- case GET_DEFAULT_ENGINE_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->ulDefaultEngineClock * 10;
- break;
- case GET_DEFAULT_MEMORY_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->ulDefaultMemoryClock * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->ulMaxPixelClockPLL_Output * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMinPixelClockPLL_Output * 10;
- case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMaxPixelClockPLL_Input * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMinPixelClockPLL_Input * 10;
- break;
- case GET_MAX_PIXEL_CLK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usMaxPixelClock * 10;
- break;
- case GET_REF_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo->usReferenceClock * 10;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- case 2:
- switch (func) {
- case GET_DEFAULT_ENGINE_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->ulDefaultEngineClock * 10;
- break;
- case GET_DEFAULT_MEMORY_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->ulDefaultMemoryClock * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input * 10;
- break;
- case GET_MAX_PIXEL_CLK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usMaxPixelClock * 10;
- break;
- case GET_REF_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_2->usReferenceClock * 10;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- break;
- case 3:
- switch (func) {
- case GET_DEFAULT_ENGINE_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->ulDefaultEngineClock * 10;
- break;
- case GET_DEFAULT_MEMORY_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->ulDefaultMemoryClock * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input * 10;
- break;
- case GET_MAX_PIXEL_CLK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usMaxPixelClock * 10;
- break;
- case GET_REF_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_3->usReferenceClock * 10;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- break;
- case 4:
- switch (func) {
- case GET_DEFAULT_ENGINE_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->ulDefaultEngineClock * 10;
- break;
- case GET_DEFAULT_MEMORY_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->ulDefaultMemoryClock * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_INPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input * 10;
- break;
- case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output * 10;
- break;
- case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output * 10;
- break;
- case GET_MAX_PIXEL_CLK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usMaxPixelClock * 10;
- break;
- case GET_REF_CLOCK:
- *val = atomDataPtr->FirmwareInfo
- .FirmwareInfo_V_1_4->usReferenceClock * 10;
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- break;
- default:
- return ATOM_NOT_IMPLEMENTED;
- }
- return ATOM_SUCCESS;
-}
-
-const int object_connector_convert[] =
- { CONNECTOR_NONE,
- CONNECTOR_DVI_I,
- CONNECTOR_DVI_I,
- CONNECTOR_DVI_D,
- CONNECTOR_DVI_D,
- CONNECTOR_VGA,
- CONNECTOR_CTV,
- CONNECTOR_STV,
- CONNECTOR_NONE,
- CONNECTOR_DIN,
- CONNECTOR_SCART,
- CONNECTOR_HDMI_TYPE_A,
- CONNECTOR_HDMI_TYPE_B,
- CONNECTOR_HDMI_TYPE_B,
- CONNECTOR_LVDS,
- CONNECTOR_DIN,
- CONNECTOR_NONE,
- CONNECTOR_NONE,
- CONNECTOR_NONE,
- CONNECTOR_NONE,
- };
-
-static void
-rhdAtomParseI2CRecord(atomBiosHandlePtr handle,
- ATOM_I2C_RECORD *Record, int *ddc_line)
-{
- ErrorF(" %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n",
- __func__,
- Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID",
- Record->sucI2cId.bfI2C_LineMux,
- Record->sucI2cId.bfHW_EngineID,
- Record->ucI2CAddr);
-
- if (!*(unsigned char *)&(Record->sucI2cId))
- *ddc_line = 0;
- else {
- if (Record->ucI2CAddr != 0)
- return;
-
- if (Record->sucI2cId.bfHW_Capable) {
- switch(Record->sucI2cId.bfI2C_LineMux) {
- case 0: *ddc_line = 0x7e40; break;
- case 1: *ddc_line = 0x7e50; break;
- case 2: *ddc_line = 0x7e30; break;
- default: break;
- }
- return;
- } else {
- /* add GPIO pin parsing */
- }
- }
-}
-
-static RADEONI2CBusRec
-RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- atomDataTablesPtr atomDataPtr;
- ATOM_GPIO_I2C_ASSIGMENT gpio;
- RADEONI2CBusRec i2c;
- CARD8 crev, frev;
-
- memset(&i2c, 0, sizeof(RADEONI2CBusRec));
- i2c.valid = FALSE;
-
- atomDataPtr = info->atomBIOS->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->GPIO_I2C_Info->sHeader),
- &crev,&frev,NULL)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n");
- return i2c;
- }
-
- gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id];
- i2c.mask_clk_reg = gpio.usClkMaskRegisterIndex * 4;
- i2c.mask_data_reg = gpio.usDataMaskRegisterIndex * 4;
- i2c.put_clk_reg = gpio.usClkEnRegisterIndex * 4;
- i2c.put_data_reg = gpio.usDataEnRegisterIndex * 4;
- i2c.get_clk_reg = gpio.usClkY_RegisterIndex * 4;
- i2c.get_data_reg = gpio.usDataY_RegisterIndex * 4;
- i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
- i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
- i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
- i2c.put_data_mask = (1 << gpio.ucDataEnShift);
- i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
- i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
- i2c.valid = TRUE;
-
-#if 0
- ErrorF("mask_clk_reg: 0x%x\n", gpio.usClkMaskRegisterIndex * 4);
- ErrorF("mask_data_reg: 0x%x\n", gpio.usDataMaskRegisterIndex * 4);
- ErrorF("put_clk_reg: 0x%x\n", gpio.usClkEnRegisterIndex * 4);
- ErrorF("put_data_reg: 0x%x\n", gpio.usDataEnRegisterIndex * 4);
- ErrorF("get_clk_reg: 0x%x\n", gpio.usClkY_RegisterIndex * 4);
- ErrorF("get_data_reg: 0x%x\n", gpio.usDataY_RegisterIndex * 4);
- ErrorF("other_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4);
- ErrorF("other_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4);
- ErrorF("mask_clk_mask: %d\n", gpio.ucClkMaskShift);
- ErrorF("mask_data_mask: %d\n", gpio.ucDataMaskShift);
- ErrorF("put_clk_mask: %d\n", gpio.ucClkEnShift);
- ErrorF("put_data_mask: %d\n", gpio.ucDataEnShift);
- ErrorF("get_clk_mask: %d\n", gpio.ucClkY_Shift);
- ErrorF("get_data_mask: %d\n", gpio.ucDataY_Shift);
- ErrorF("other_clk_mask: %d\n", gpio.ucClkA_Shift);
- ErrorF("other_data_mask: %d\n", gpio.ucDataA_Shift);
-#endif
-
- return i2c;
-}
-
-Bool
-RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- CARD8 crev, frev;
- unsigned short size;
- atomDataTablesPtr atomDataPtr;
- ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
- int i, j, ddc_line = 0;
-
- atomDataPtr = info->atomBIOS->atomDataPtr;
- if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size))
- return FALSE;
-
- if (crev < 2)
- return FALSE;
-
- con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
- ((char *)&atomDataPtr->Object_Header->sHeader +
- atomDataPtr->Object_Header->usConnectorObjectTableOffset);
-
- for (i = 0; i < con_obj->ucNumberOfObjects; i++) {
- ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable;
- ATOM_COMMON_RECORD_HEADER *Record;
- CARD8 obj_id, num, obj_type;
- int record_base;
-
- obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
- num = (con_obj->asObjects[i].usObjectID & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
- obj_type = (con_obj->asObjects[i].usObjectID & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
- if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR)
- continue;
-
- SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
- ((char *)&atomDataPtr->Object_Header->sHeader
- + con_obj->asObjects[i].usSrcDstTableOffset);
-
- ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc);
- info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id];
- info->BiosConnector[i].valid = TRUE;
- info->BiosConnector[i].devices = 0;
-
- for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
- CARD8 sobj_id;
-
- sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
- ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id);
-
- switch(sobj_id) {
- case ENCODER_OBJECT_ID_INTERNAL_LVDS:
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX);
- break;
- case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX);
- info->BiosConnector[i].TMDSType = TMDS_INT;
- break;
- case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX);
- info->BiosConnector[i].TMDSType = TMDS_EXT;
- break;
- case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP3_INDEX);
- info->BiosConnector[i].TMDSType = TMDS_LVTMA;
- break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT1_INDEX);
- info->BiosConnector[i].DACType = DAC_PRIMARY;
- break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC2:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN ||
- info->BiosConnector[i].ConnectorType == CONNECTOR_STV ||
- info->BiosConnector[i].ConnectorType == CONNECTOR_CTV)
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX);
- else
- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX);
- info->BiosConnector[i].DACType = DAC_TVDAC;
- break;
- }
- }
-
- Record = (ATOM_COMMON_RECORD_HEADER *)
- ((char *)&atomDataPtr->Object_Header->sHeader
- + con_obj->asObjects[i].usRecordOffset);
-
- record_base = con_obj->asObjects[i].usRecordOffset;
-
- while (Record->ucRecordType > 0
- && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) {
-
- ErrorF("record type %d\n", Record->ucRecordType);
- switch (Record->ucRecordType) {
- case ATOM_I2C_RECORD_TYPE:
- rhdAtomParseI2CRecord(info->atomBIOS,
- (ATOM_I2C_RECORD *)Record,
- &ddc_line);
- info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line);
- break;
- case ATOM_HPD_INT_RECORD_TYPE:
- break;
- case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
- break;
- }
-
- Record = (ATOM_COMMON_RECORD_HEADER*)
- ((char *)Record + Record->ucRecordSize);
- }
- }
- return TRUE;
-}
-
-Bool
-RADEONGetATOMTVInfo(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- ATOM_ANALOG_TV_INFO *tv_info;
-
- tv_info = info->atomBIOS->atomDataPtr->AnalogTV_Info;
-
- if (!tv_info)
- return FALSE;
-
- switch(tv_info->ucTV_BootUpDefaultStandard) {
- case NTSC_SUPPORT:
- radeon_output->default_tvStd = TV_STD_NTSC;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n");
- break;
- case NTSCJ_SUPPORT:
- radeon_output->default_tvStd = TV_STD_NTSC_J;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n");
- break;
- case PAL_SUPPORT:
- radeon_output->default_tvStd = TV_STD_PAL;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n");
- break;
- case PALM_SUPPORT:
- radeon_output->default_tvStd = TV_STD_PAL_M;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n");
- break;
- case PAL60_SUPPORT:
- radeon_output->default_tvStd = TV_STD_PAL_60;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n");
- break;
- }
-
- radeon_output->tvStd = radeon_output->default_tvStd;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: ");
- radeon_output->SupportedTVStds = radeon_output->default_tvStd;
- if (tv_info->ucTV_SupportedStandard & NTSC_SUPPORT) {
- ErrorF("NTSC ");
- radeon_output->SupportedTVStds |= TV_STD_NTSC;
- }
- if (tv_info->ucTV_SupportedStandard & NTSCJ_SUPPORT) {
- ErrorF("NTSC-J ");
- radeon_output->SupportedTVStds |= TV_STD_NTSC_J;
- }
- if (tv_info->ucTV_SupportedStandard & PAL_SUPPORT) {
- ErrorF("PAL ");
- radeon_output->SupportedTVStds |= TV_STD_PAL;
- }
- if (tv_info->ucTV_SupportedStandard & PALM_SUPPORT) {
- ErrorF("PAL-M ");
- radeon_output->SupportedTVStds |= TV_STD_PAL_M;
- }
- if (tv_info->ucTV_SupportedStandard & PAL60_SUPPORT) {
- ErrorF("PAL-60 ");
- radeon_output->SupportedTVStds |= TV_STD_PAL_60;
- }
- ErrorF("\n");
-
- if (tv_info->ucExt_TV_ASIC_ID) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown external TV ASIC\n");
- return FALSE;
- }
-
- return TRUE;
-}
-
-Bool
-RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, int32_t *pixel_clock)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ATOM_ANALOG_TV_INFO *tv_info;
-
- tv_info = info->atomBIOS->atomDataPtr->AnalogTV_Info;
-
- if (index > MAX_SUPPORTED_TV_TIMING)
- return FALSE;
-
- crtc_timing->usH_Total = tv_info->aModeTimings[index].usCRTC_H_Total;
- crtc_timing->usH_Disp = tv_info->aModeTimings[index].usCRTC_H_Disp;
- crtc_timing->usH_SyncStart = tv_info->aModeTimings[index].usCRTC_H_SyncStart;
- crtc_timing->usH_SyncWidth = tv_info->aModeTimings[index].usCRTC_H_SyncWidth;
-
- crtc_timing->usV_Total = tv_info->aModeTimings[index].usCRTC_V_Total;
- crtc_timing->usV_Disp = tv_info->aModeTimings[index].usCRTC_V_Disp;
- crtc_timing->usV_SyncStart = tv_info->aModeTimings[index].usCRTC_V_SyncStart;
- crtc_timing->usV_SyncWidth = tv_info->aModeTimings[index].usCRTC_V_SyncWidth;
-
- crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
-
- crtc_timing->ucOverscanRight = tv_info->aModeTimings[index].usCRTC_OverscanRight;
- crtc_timing->ucOverscanLeft = tv_info->aModeTimings[index].usCRTC_OverscanLeft;
- crtc_timing->ucOverscanBottom = tv_info->aModeTimings[index].usCRTC_OverscanBottom;
- crtc_timing->ucOverscanTop = tv_info->aModeTimings[index].usCRTC_OverscanTop;
- *pixel_clock = tv_info->aModeTimings[index].usPixelClock * 10;
-
- return TRUE;
-}
-
-Bool
-RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- int i, j;
-
- atomDataPtr = info->atomBIOS->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
- &crev,&frev,NULL)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n");
- return FALSE;
- }
-
- for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
- ATOM_CONNECTOR_INFO_I2C ci
- = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[i];
-
- if (!(atomDataPtr->SupportedDevicesInfo
- .SupportedDevicesInfo->usDeviceSupport & (1 << i))) {
- info->BiosConnector[i].valid = FALSE;
- continue;
- }
-
-#if 1
- if (i == ATOM_DEVICE_CV_INDEX) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n");
- info->BiosConnector[i].valid = FALSE;
- continue;
- }
-#endif
-
- info->BiosConnector[i].valid = TRUE;
- info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
- if (info->IsIGP && (i == ATOM_DEVICE_DFP2_INDEX))
- info->BiosConnector[i].devices = (1 << ATOM_DEVICE_DFP3_INDEX);
- else if (info->IsIGP && (i == ATOM_DEVICE_DFP3_INDEX))
- info->BiosConnector[i].devices = (1 << ATOM_DEVICE_DFP2_INDEX);
- else
- info->BiosConnector[i].devices = (1 << i);
- info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
- info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
-
- /* don't assign a gpio for tv */
- if ((i == ATOM_DEVICE_TV1_INDEX) ||
- (i == ATOM_DEVICE_TV2_INDEX) ||
- (i == ATOM_DEVICE_CV_INDEX))
- info->BiosConnector[i].ddc_i2c.valid = FALSE;
- else if ((i == ATOM_DEVICE_DFP3_INDEX) && info->IsIGP) {
- /* DDIA port uses non-standard gpio entry */
- if (info->BiosConnector[ATOM_DEVICE_DFP2_INDEX].valid)
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 2);
- else
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- } else
- info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
-
- if (i == ATOM_DEVICE_DFP1_INDEX)
- info->BiosConnector[i].TMDSType = TMDS_INT;
- else if (i == ATOM_DEVICE_DFP2_INDEX) {
- if (info->IsIGP)
- info->BiosConnector[i].TMDSType = TMDS_LVTMA;
- else
- info->BiosConnector[i].TMDSType = TMDS_EXT;
- } else if (i == ATOM_DEVICE_DFP3_INDEX) {
- if (info->IsIGP)
- info->BiosConnector[i].TMDSType = TMDS_DDIA;
- else
- info->BiosConnector[i].TMDSType = TMDS_LVTMA;
- } else
- info->BiosConnector[i].TMDSType = TMDS_NONE;
-
- /* Always set the connector type to VGA for CRT1/CRT2. if they are
- * shared with a DVI port, we'll pick up the DVI connector below when we
- * merge the outputs
- */
- if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) &&
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I ||
- info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D ||
- info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
- info->BiosConnector[i].ConnectorType = CONNECTOR_VGA;
- }
-
- if (crev > 1) {
- ATOM_CONNECTOR_INC_SRC_BITMAP isb
- = atomDataPtr->SupportedDevicesInfo
- .SupportedDevicesInfo_HD->asIntSrcInfo[i];
-
- switch (isb.ucIntSrcBitmap) {
- case 0x4:
- info->BiosConnector[i].hpd_mask = 0x00000001;
- break;
- case 0xa:
- info->BiosConnector[i].hpd_mask = 0x00000100;
- break;
- default:
- info->BiosConnector[i].hpd_mask = 0;
- break;
- }
- } else {
- info->BiosConnector[i].hpd_mask = 0;
- }
- }
-
- /* CRTs/DFPs may share a port */
- for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
- if (info->BiosConnector[i].valid) {
- for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
- if (info->BiosConnector[j].valid && (i != j) ) {
- if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) {
- if (((i == ATOM_DEVICE_DFP1_INDEX) ||
- (i == ATOM_DEVICE_DFP2_INDEX) ||
- (i == ATOM_DEVICE_DFP3_INDEX)) &&
- ((j == ATOM_DEVICE_CRT1_INDEX) || (j == ATOM_DEVICE_CRT2_INDEX))) {
- info->BiosConnector[i].DACType = info->BiosConnector[j].DACType;
- info->BiosConnector[i].devices |= info->BiosConnector[j].devices;
- info->BiosConnector[j].valid = FALSE;
- } else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
- (j == ATOM_DEVICE_DFP2_INDEX) ||
- (j == ATOM_DEVICE_DFP3_INDEX)) &&
- ((i == ATOM_DEVICE_CRT1_INDEX) || (i == ATOM_DEVICE_CRT2_INDEX))) {
- info->BiosConnector[j].DACType = info->BiosConnector[i].DACType;
- info->BiosConnector[j].devices |= info->BiosConnector[i].devices;
- info->BiosConnector[i].valid = FALSE;
- }
- /* other possible combos? */
- }
- }
- }
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n");
- for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
- if (info->BiosConnector[i].valid) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d, hpd_mask-0x%x\n",
- i, (unsigned int)info->BiosConnector[i].ddc_i2c.mask_clk_reg, info->BiosConnector[i].DACType,
- info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType,
- info->BiosConnector[i].hpd_mask);
- }
- }
-
- return TRUE;
-}
-
-#if 0
-#define RHD_CONNECTORS_MAX 4
-#define MAX_OUTPUTS_PER_CONNECTOR 2
-
-#define Limit(n,max,name) ((n >= max) ? ( \
- xf86DrvMsg(handle->scrnIndex,X_ERROR,"%s: %s %i exceeds maximum %i\n", \
- __func__,name,n,max), TRUE) : FALSE)
-
-static const struct _rhd_connector_objs
-{
- char *name;
- RADEONConnectorTypeATOM con;
-} rhd_connector_objs[] = {
- { "NONE", CONNECTOR_NONE_ATOM },
- { "SINGLE_LINK_DVI_I", CONNECTOR_DVI_I_ATOM },
- { "DUAL_LINK_DVI_I", CONNECTOR_DVI_I_ATOM },
- { "SINGLE_LINK_DVI_D", CONNECTOR_DVI_D_ATOM },
- { "DUAL_LINK_DVI_D", CONNECTOR_DVI_D_ATOM },
- { "VGA", CONNECTOR_VGA_ATOM },
- { "COMPOSITE", CONNECTOR_CTV_ATOM },
- { "SVIDEO", CONNECTOR_STV_ATOM },
- { "D_CONNECTOR", CONNECTOR_NONE_ATOM },
- { "9PIN_DIN", CONNECTOR_NONE_ATOM },
- { "SCART", CONNECTOR_SCART_ATOM },
- { "HDMI_TYPE_A", CONNECTOR_HDMI_TYPE_A_ATOM },
- { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM },
- { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM },
- { "LVDS", CONNECTOR_LVDS_ATOM },
- { "7PIN_DIN", CONNECTOR_STV_ATOM },
- { "PCIE_CONNECTOR", CONNECTOR_NONE_ATOM },
- { "CROSSFIRE", CONNECTOR_NONE_ATOM },
- { "HARDCODE_DVI", CONNECTOR_NONE_ATOM },
- { "DISPLAYPORT", CONNECTOR_DISPLAY_PORT_ATOM }
-};
-static const int n_rhd_connector_objs = sizeof (rhd_connector_objs) / sizeof(struct _rhd_connector_objs);
-
-static const struct _rhd_encoders
-{
- char *name;
- RADEONOutputTypeATOM ot;
-} rhd_encoders[] = {
- { "NONE", OUTPUT_NONE_ATOM },
- { "INTERNAL_LVDS", OUTPUT_LVDS_ATOM },
- { "INTERNAL_TMDS1", OUTPUT_TMDSA_ATOM },
- { "INTERNAL_TMDS2", OUTPUT_TMDSB_ATOM },
- { "INTERNAL_DAC1", OUTPUT_DACA_ATOM },
- { "INTERNAL_DAC2", OUTPUT_DACB_ATOM },
- { "INTERNAL_SDVOA", OUTPUT_NONE_ATOM },
- { "INTERNAL_SDVOB", OUTPUT_NONE_ATOM },
- { "SI170B", OUTPUT_NONE_ATOM },
- { "CH7303", OUTPUT_NONE_ATOM },
- { "CH7301", OUTPUT_NONE_ATOM },
- { "INTERNAL_DVO1", OUTPUT_NONE_ATOM },
- { "EXTERNAL_SDVOA", OUTPUT_NONE_ATOM },
- { "EXTERNAL_SDVOB", OUTPUT_NONE_ATOM },
- { "TITFP513", OUTPUT_NONE_ATOM },
- { "INTERNAL_LVTM1", OUTPUT_LVTMA_ATOM },
- { "VT1623", OUTPUT_NONE_ATOM },
- { "HDMI_SI1930", OUTPUT_NONE_ATOM },
- { "HDMI_INTERNAL", OUTPUT_NONE_ATOM },
- { "INTERNAL_KLDSCP_TMDS1", OUTPUT_TMDSA_ATOM },
- { "INTERNAL_KLSCP_DVO1", OUTPUT_NONE_ATOM },
- { "INTERNAL_KLDSCP_DAC1", OUTPUT_DACA_ATOM },
- { "INTERNAL_KLDSCP_DAC2", OUTPUT_DACB_ATOM },
- { "SI178", OUTPUT_NONE_ATOM },
- { "MVPU_FPGA", OUTPUT_NONE_ATOM },
- { "INTERNAL_DDI", OUTPUT_NONE_ATOM },
- { "VT1625", OUTPUT_NONE_ATOM },
- { "HDMI_SI1932", OUTPUT_NONE_ATOM },
- { "AN9801", OUTPUT_NONE_ATOM },
- { "DP501", OUTPUT_NONE_ATOM },
-};
-static const int n_rhd_encoders = sizeof (rhd_encoders) / sizeof(struct _rhd_encoders);
-
-static const struct _rhd_connectors
-{
- char *name;
- RADEONConnectorTypeATOM con;
- Bool dual;
-} rhd_connectors[] = {
- {"NONE", CONNECTOR_NONE_ATOM, FALSE },
- {"VGA", CONNECTOR_VGA_ATOM, FALSE },
- {"DVI-I", CONNECTOR_DVI_I_ATOM, TRUE },
- {"DVI-D", CONNECTOR_DVI_D_ATOM, FALSE },
- {"DVI-A", CONNECTOR_DVI_A_ATOM, FALSE },
- {"SVIDEO", CONNECTOR_STV_ATOM, FALSE },
- {"COMPOSITE", CONNECTOR_CTV_ATOM, FALSE },
- {"PANEL", CONNECTOR_LVDS_ATOM, FALSE },
- {"DIGITAL_LINK", CONNECTOR_DIGITAL_ATOM, FALSE },
- {"SCART", CONNECTOR_SCART_ATOM, FALSE },
- {"HDMI Type A", CONNECTOR_HDMI_TYPE_A_ATOM, FALSE },
- {"HDMI Type B", CONNECTOR_HDMI_TYPE_B_ATOM, FALSE },
- {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE },
- {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE },
- {"DVI+DIN", CONNECTOR_NONE_ATOM, FALSE }
-};
-static const int n_rhd_connectors = sizeof(rhd_connectors) / sizeof(struct _rhd_connectors);
-
-static const struct _rhd_devices
-{
- char *name;
- RADEONOutputTypeATOM ot;
-} rhd_devices[] = {
- {" CRT1", OUTPUT_NONE_ATOM },
- {" LCD1", OUTPUT_LVTMA_ATOM },
- {" TV1", OUTPUT_NONE_ATOM },
- {" DFP1", OUTPUT_TMDSA_ATOM },
- {" CRT2", OUTPUT_NONE_ATOM },
- {" LCD2", OUTPUT_LVTMA_ATOM },
- {" TV2", OUTPUT_NONE_ATOM },
- {" DFP2", OUTPUT_LVTMA_ATOM },
- {" CV", OUTPUT_NONE_ATOM },
- {" DFP3", OUTPUT_LVTMA_ATOM }
-};
-static const int n_rhd_devices = sizeof(rhd_devices) / sizeof(struct _rhd_devices);
-
-static const rhdDDC hwddc[] = { RHD_DDC_0, RHD_DDC_1, RHD_DDC_2, RHD_DDC_3 };
-static const int n_hwddc = sizeof(hwddc) / sizeof(rhdDDC);
-
-static const rhdOutputType acc_dac[] = { OUTPUT_NONE_ATOM,
- OUTPUT_DACA_ATOM,
- OUTPUT_DACB_ATOM,
- OUTPUT_DAC_EXTERNAL_ATOM };
-static const int n_acc_dac = sizeof(acc_dac) / sizeof (rhdOutputType);
-
-/*
- *
- */
-static Bool
-rhdAtomInterpretObjectID(atomBiosHandlePtr handle,
- CARD16 id, CARD8 *obj_type, CARD8 *obj_id,
- CARD8 *num, char **name)
-{
- *obj_id = (id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
- *num = (id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
- *obj_type = (id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
-
- *name = NULL;
-
- switch (*obj_type) {
- case GRAPH_OBJECT_TYPE_CONNECTOR:
- if (!Limit(*obj_id, n_rhd_connector_objs, "obj_id"))
- *name = rhd_connector_objs[*obj_id].name;
- break;
- case GRAPH_OBJECT_TYPE_ENCODER:
- if (!Limit(*obj_id, n_rhd_encoders, "obj_id"))
- *name = rhd_encoders[*obj_id].name;
- break;
- default:
- break;
- }
- return TRUE;
-}
-
-/*
- *
- */
-static void
-rhdAtomDDCFromI2CRecord(atomBiosHandlePtr handle,
- ATOM_I2C_RECORD *Record, rhdDDC *DDC)
-{
- RHDDebug(handle->scrnIndex,
- " %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n",
- __func__,
- Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID",
- Record->sucI2cId.bfI2C_LineMux,
- Record->sucI2cId.bfHW_EngineID,
- Record->ucI2CAddr);
-
- if (!*(unsigned char *)&(Record->sucI2cId))
- *DDC = RHD_DDC_NONE;
- else {
-
- if (Record->ucI2CAddr != 0)
- return;
-
- if (Record->sucI2cId.bfHW_Capable) {
-
- *DDC = (rhdDDC)Record->sucI2cId.bfI2C_LineMux;
- if (*DDC >= RHD_DDC_MAX)
- *DDC = RHD_DDC_NONE;
-
- } else {
- *DDC = RHD_DDC_GPIO;
- /* add GPIO pin parsing */
- }
- }
-}
-
-/*
- *
- */
-static void
-rhdAtomParseGPIOLutForHPD(atomBiosHandlePtr handle,
- CARD8 pinID, rhdHPD *HPD)
-{
- atomDataTablesPtr atomDataPtr;
- ATOM_GPIO_PIN_LUT *gpio_pin_lut;
- unsigned short size;
- int i = 0;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- *HPD = RHD_HPD_NONE;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &atomDataPtr->GPIO_Pin_LUT->sHeader, NULL, NULL, &size)) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: No valid GPIO pin LUT in AtomBIOS\n",__func__);
- return;
- }
- gpio_pin_lut = atomDataPtr->GPIO_Pin_LUT;
-
- while (1) {
- if (gpio_pin_lut->asGPIO_Pin[i].ucGPIO_ID == pinID) {
-
- if ((sizeof(ATOM_COMMON_TABLE_HEADER)
- + (i * sizeof(ATOM_GPIO_PIN_ASSIGNMENT))) > size)
- return;
-
- RHDDebug(handle->scrnIndex,
- " %s: GPIO PinID: %i Index: %x Shift: %i\n",
- __func__,
- pinID,
- gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex,
- gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift);
-
- /* grr... map backwards: register indices -> line numbers */
- if (gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex
- == (DC_GPIO_HPD_A >> 2)) {
- switch (gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift) {
- case 0:
- *HPD = RHD_HPD_0;
- return;
- case 8:
- *HPD = RHD_HPD_1;
- return;
- case 16:
- *HPD = RHD_HPD_2;
- return;
- }
- }
- }
- i++;
- }
-}
-
-/*
- *
- */
-static void
-rhdAtomHPDFromRecord(atomBiosHandlePtr handle,
- ATOM_HPD_INT_RECORD *Record, rhdHPD *HPD)
-{
- RHDDebug(handle->scrnIndex,
- " %s: HPD Record: GPIO ID: %x Plugged_PinState: %x\n",
- __func__,
- Record->ucHPDIntGPIOID,
- Record->ucPluggged_PinState);
- rhdAtomParseGPIOLutForHPD(handle, Record->ucHPDIntGPIOID, HPD);
-}
-
-/*
- *
- */
-static char *
-rhdAtomDeviceTagsFromRecord(atomBiosHandlePtr handle,
- ATOM_CONNECTOR_DEVICE_TAG_RECORD *Record)
-{
- int i, j, k;
- char *devices;
-
- //RHDFUNC(handle);
-
- RHDDebug(handle->scrnIndex," NumberOfDevice: %i\n",
- Record->ucNumberOfDevice);
-
- if (!Record->ucNumberOfDevice) return NULL;
-
- devices = (char *)xcalloc(Record->ucNumberOfDevice * 4 + 1,1);
-
- for (i = 0; i < Record->ucNumberOfDevice; i++) {
- k = 0;
- j = Record->asDeviceTag[i].usDeviceID;
-
- while (!(j & 0x1)) { j >>= 1; k++; };
-
- if (!Limit(k,n_rhd_devices,"usDeviceID"))
- strcat(devices, rhd_devices[k].name);
- }
-
- RHDDebug(handle->scrnIndex," Devices:%s\n",devices);
-
- return devices;
-}
-
-/*
- *
- */
-static AtomBiosResult
-rhdAtomConnectorInfoFromObjectHeader(atomBiosHandlePtr handle,
- rhdConnectorInfoPtr *ptr)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
- rhdConnectorInfoPtr cp;
- unsigned long object_header_end;
- int ncon = 0;
- int i,j;
- unsigned short object_header_size;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &atomDataPtr->Object_Header->sHeader,
- &crev,&frev,&object_header_size)) {
- return ATOM_NOT_IMPLEMENTED;
- }
-
- if (crev < 2) /* don't bother with anything below rev 2 */
- return ATOM_NOT_IMPLEMENTED;
-
- if (!(cp = (rhdConnectorInfoPtr)xcalloc(sizeof(struct rhdConnectorInfo),
- RHD_CONNECTORS_MAX)))
- return ATOM_FAILED;
-
- object_header_end =
- atomDataPtr->Object_Header->usConnectorObjectTableOffset
- + object_header_size;
-
- RHDDebug(handle->scrnIndex,"ObjectTable - size: %u, BIOS - size: %u "
- "TableOffset: %u object_header_end: %u\n",
- object_header_size, handle->BIOSImageSize,
- atomDataPtr->Object_Header->usConnectorObjectTableOffset,
- object_header_end);
-
- if ((object_header_size > handle->BIOSImageSize)
- || (atomDataPtr->Object_Header->usConnectorObjectTableOffset
- > handle->BIOSImageSize)
- || object_header_end > handle->BIOSImageSize) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: Object table information is bogus\n",__func__);
- return ATOM_FAILED;
- }
-
- if (((unsigned long)&atomDataPtr->Object_Header->sHeader
- + object_header_end) > ((unsigned long)handle->BIOSBase
- + handle->BIOSImageSize)) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: Object table extends beyond BIOS Image\n",__func__);
- return ATOM_FAILED;
- }
-
- con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
- ((char *)&atomDataPtr->Object_Header->sHeader +
- atomDataPtr->Object_Header->usConnectorObjectTableOffset);
-
- for (i = 0; i < con_obj->ucNumberOfObjects; i++) {
- ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable;
- ATOM_COMMON_RECORD_HEADER *Record;
- int record_base;
- CARD8 obj_type, obj_id, num;
- char *name;
- int nout = 0;
-
- rhdAtomInterpretObjectID(handle, con_obj->asObjects[i].usObjectID,
- &obj_type, &obj_id, &num, &name);
-
- RHDDebug(handle->scrnIndex, "Object: ID: %x name: %s type: %x id: %x\n",
- con_obj->asObjects[i].usObjectID, name ? name : "",
- obj_type, obj_id);
-
-
- if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR)
- continue;
-
- SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
- ((char *)&atomDataPtr->Object_Header->sHeader
- + con_obj->asObjects[i].usSrcDstTableOffset);
-
- if (con_obj->asObjects[i].usSrcDstTableOffset
- + (SrcDstTable->ucNumberOfSrc
- * sizeof(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT))
- > handle->BIOSImageSize) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: SrcDstTable[%i] extends "
- "beyond Object_Header table\n",__func__,i);
- continue;
- }
-
- cp[ncon].Type = rhd_connector_objs[obj_id].con;
- cp[ncon].Name = RhdAppendString(cp[ncon].Name,name);
-
- for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
- CARD8 stype, sobj_id, snum;
- char *sname;
-
- rhdAtomInterpretObjectID(handle, SrcDstTable->usSrcObjectID[j],
- &stype, &sobj_id, &snum, &sname);
-
- RHDDebug(handle->scrnIndex, " * SrcObject: ID: %x name: %s\n",
- SrcDstTable->usSrcObjectID[j], sname);
-
- cp[ncon].Output[nout] = rhd_encoders[sobj_id].ot;
- if (++nout >= MAX_OUTPUTS_PER_CONNECTOR)
- break;
- }
-
- Record = (ATOM_COMMON_RECORD_HEADER *)
- ((char *)&atomDataPtr->Object_Header->sHeader
- + con_obj->asObjects[i].usRecordOffset);
-
- record_base = con_obj->asObjects[i].usRecordOffset;
-
- while (Record->ucRecordType > 0
- && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) {
- char *taglist;
-
- if ((record_base += Record->ucRecordSize)
- > object_header_size) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: Object Records extend beyond Object Table\n",
- __func__);
- break;
- }
-
- RHDDebug(handle->scrnIndex, " - Record Type: %x\n",
- Record->ucRecordType);
-
- switch (Record->ucRecordType) {
-
- case ATOM_I2C_RECORD_TYPE:
- rhdAtomDDCFromI2CRecord(handle,
- (ATOM_I2C_RECORD *)Record,
- &cp[ncon].DDC);
- break;
-
- case ATOM_HPD_INT_RECORD_TYPE:
- rhdAtomHPDFromRecord(handle,
- (ATOM_HPD_INT_RECORD *)Record,
- &cp[ncon].HPD);
- break;
-
- case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
- taglist = rhdAtomDeviceTagsFromRecord(handle,
- (ATOM_CONNECTOR_DEVICE_TAG_RECORD *)Record);
- if (taglist) {
- cp[ncon].Name = RhdAppendString(cp[ncon].Name,taglist);
- xfree(taglist);
- }
- break;
-
- default:
- break;
- }
-
- Record = (ATOM_COMMON_RECORD_HEADER*)
- ((char *)Record + Record->ucRecordSize);
-
- }
-
- if ((++ncon) == RHD_CONNECTORS_MAX)
- break;
- }
- *ptr = cp;
-
- RhdPrintConnectorInfo(handle->scrnIndex, cp);
-
- return ATOM_SUCCESS;
-}
-
-/*
- *
- */
-static AtomBiosResult
-rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
- rhdConnectorInfoPtr *ptr)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- rhdConnectorInfoPtr cp;
- struct {
- rhdOutputType ot;
- rhdConnectorType con;
- rhdDDC ddc;
- rhdHPD hpd;
- Bool dual;
- char *name;
- char *outputName;
- } devices[ATOM_MAX_SUPPORTED_DEVICE];
- int ncon = 0;
- int n;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
- &crev,&frev,NULL)) {
- return ATOM_NOT_IMPLEMENTED;
- }
-
- if (!(cp = (rhdConnectorInfoPtr)xcalloc(RHD_CONNECTORS_MAX,
- sizeof(struct rhdConnectorInfo))))
- return ATOM_FAILED;
-
- for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
- ATOM_CONNECTOR_INFO_I2C ci
- = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[n];
-
- devices[n].ot = OUTPUT_NONE_ATOM;
-
- if (!(atomDataPtr->SupportedDevicesInfo
- .SupportedDevicesInfo->usDeviceSupport & (1 << n)))
- continue;
-
- if (Limit(ci.sucConnectorInfo.sbfAccess.bfConnectorType,
- n_rhd_connectors, "bfConnectorType"))
- continue;
-
- devices[n].con
- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].con;
- if (devices[n].con == RHD_CONNECTOR_NONE)
- continue;
-
- devices[n].dual
- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].dual;
- devices[n].name
- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].name;
-
- RHDDebug(handle->scrnIndex,"AtomBIOS Connector[%i]: %s Device:%s ",n,
- rhd_connectors[ci.sucConnectorInfo
- .sbfAccess.bfConnectorType].name,
- rhd_devices[n].name);
-
- devices[n].outputName = rhd_devices[n].name;
-
- if (!Limit(ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC,
- n_acc_dac, "bfAssociatedDAC")) {
- if ((devices[n].ot
- = acc_dac[ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC])
- == OUTPUT_NONE_ATOM) {
- devices[n].ot = rhd_devices[n].ot;
- }
- } else
- devices[n].ot = OUTPUT_NONE_ATOM;
-
- RHDDebugCont("Output: %x ",devices[n].ot);
-
- if (ci.sucI2cId.sbfAccess.bfHW_Capable) {
-
- RHDDebugCont("HW DDC %i ",
- ci.sucI2cId.sbfAccess.bfI2C_LineMux);
-
- if (Limit(ci.sucI2cId.sbfAccess.bfI2C_LineMux,
- n_hwddc, "bfI2C_LineMux"))
- devices[n].ddc = RHD_DDC_NONE;
- else
- devices[n].ddc = hwddc[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
-
- } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) {
-
- RHDDebugCont("GPIO DDC ");
- devices[n].ddc = RHD_DDC_GPIO;
-
- /* add support for GPIO line */
- } else {
-
- RHDDebugCont("NO DDC ");
- devices[n].ddc = RHD_DDC_NONE;
-
- }
-
- if (crev > 1) {
- ATOM_CONNECTOR_INC_SRC_BITMAP isb
- = atomDataPtr->SupportedDevicesInfo
- .SupportedDevicesInfo_HD->asIntSrcInfo[n];
-
- switch (isb.ucIntSrcBitmap) {
- case 0x4:
- RHDDebugCont("HPD 0\n");
- devices[n].hpd = RHD_HPD_0;
- break;
- case 0xa:
- RHDDebugCont("HPD 1\n");
- devices[n].hpd = RHD_HPD_1;
- break;
- default:
- RHDDebugCont("NO HPD\n");
- devices[n].hpd = RHD_HPD_NONE;
- break;
- }
- } else {
- RHDDebugCont("NO HPD\n");
- devices[n].hpd = RHD_HPD_NONE;
- }
- }
- /* sort devices for connectors */
- for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
- int i;
-
- if (devices[n].ot == OUTPUT_NONE_ATOM)
- continue;
- if (devices[n].con == CONNECTOR_NONE_ATOM)
- continue;
-
- cp[ncon].DDC = devices[n].ddc;
- cp[ncon].HPD = devices[n].hpd;
- cp[ncon].Output[0] = devices[n].ot;
- cp[ncon].Output[1] = OUTPUT_NONE_ATOM;
- cp[ncon].Type = devices[n].con;
- cp[ncon].Name = xf86strdup(devices[n].name);
- cp[ncon].Name = RhdAppendString(cp[ncon].Name, devices[n].outputName);
-
- if (devices[n].dual) {
- if (devices[n].ddc == RHD_DDC_NONE)
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "No DDC channel for device %s found."
- " Cannot find matching device.\n",devices[n].name);
- else {
- for (i = n + 1; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
-
- if (!devices[i].dual)
- continue;
-
- if (devices[n].ddc != devices[i].ddc)
- continue;
-
- if (((devices[n].ot == OUTPUT_DACA_ATOM
- || devices[n].ot == OUTPUT_DACB_ATOM)
- && (devices[i].ot == OUTPUT_LVTMA_ATOM
- || devices[i].ot == OUTPUT_TMDSA_ATOM))
- || ((devices[i].ot == OUTPUT_DACA_ATOM
- || devices[i].ot == OUTPUT_DACB_ATOM)
- && (devices[n].ot == OUTPUT_LVTMA_ATOM
- || devices[n].ot == OUTPUT_TMDSA_ATOM))) {
-
- cp[ncon].Output[1] = devices[i].ot;
-
- if (cp[ncon].HPD == RHD_HPD_NONE)
- cp[ncon].HPD = devices[i].hpd;
-
- cp[ncon].Name = RhdAppendString(cp[ncon].Name,
- devices[i].outputName);
- devices[i].ot = OUTPUT_NONE_ATOM; /* zero the device */
- }
- }
- }
- }
-
- if ((++ncon) == RHD_CONNECTORS_MAX)
- break;
- }
- *ptr = cp;
-
- RhdPrintConnectorInfo(handle->scrnIndex, cp);
-
- return ATOM_SUCCESS;
-}
-
-/*
- *
- */
-static AtomBiosResult
-rhdAtomConnectorInfo(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data)
-{
- data->connectorInfo = NULL;
-
- if (rhdAtomConnectorInfoFromObjectHeader(handle,&data->connectorInfo)
- == ATOM_SUCCESS)
- return ATOM_SUCCESS;
- else
- return rhdAtomConnectorInfoFromSupportedDevices(handle,
- &data->connectorInfo);
-}
-#endif
-
-# ifdef ATOM_BIOS_PARSER
-static AtomBiosResult
-rhdAtomExec (atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data)
-{
- RADEONInfoPtr info = RADEONPTR (xf86Screens[handle->scrnIndex]);
- Bool ret = FALSE;
- char *msg;
- int idx = data->exec.index;
- void *pspace = data->exec.pspace;
- pointer *dataSpace = data->exec.dataSpace;
-
- //RHDFUNCI(handle->scrnIndex);
-
- if (dataSpace) {
- if (!handle->fbBase && !handle->scratchBase)
- return ATOM_FAILED;
- if (handle->fbBase) {
- if (!info->FB) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: "
- "Cannot exec AtomBIOS: framebuffer not mapped\n",
- __func__);
- return ATOM_FAILED;
- }
- *dataSpace = (CARD8*)info->FB + handle->fbBase;
- } else
- *dataSpace = (CARD8*)handle->scratchBase;
- }
- ret = ParseTableWrapper(pspace, idx, handle,
- handle->BIOSBase,
- &msg);
- if (!ret)
- xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s\n",msg);
- else
- xf86DrvMsgVerb(handle->scrnIndex, X_INFO, 5, "%s\n",msg);
-
- return (ret) ? ATOM_SUCCESS : ATOM_FAILED;
-}
-# endif
-
-AtomBiosResult
-RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle,
- AtomBiosRequestID id, AtomBiosArgPtr data)
-{
- AtomBiosResult ret = ATOM_FAILED;
- int i;
- char *msg = NULL;
- enum msgDataFormat msg_f = MSG_FORMAT_NONE;
- AtomBiosRequestFunc req_func = NULL;
-
- //RHDFUNCI(scrnIndex);
-
- for (i = 0; AtomBiosRequestList[i].id != FUNC_END; i++) {
- if (id == AtomBiosRequestList[i].id) {
- req_func = AtomBiosRequestList[i].request;
- msg = AtomBiosRequestList[i].message;
- msg_f = AtomBiosRequestList[i].message_format;
- break;
- }
- }
-
- if (req_func == NULL) {
- xf86DrvMsg(scrnIndex, X_ERROR, "Unknown AtomBIOS request: %i\n",id);
- return ATOM_NOT_IMPLEMENTED;
- }
- /* Hack for now */
- if (id == ATOMBIOS_INIT)
- data->val = scrnIndex;
-
- if (id == ATOMBIOS_INIT || handle)
- ret = req_func(handle, id, data);
-
- if (ret == ATOM_SUCCESS) {
-
- switch (msg_f) {
- case MSG_FORMAT_DEC:
- xf86DrvMsg(scrnIndex,X_INFO,"%s: %li\n", msg,
- (unsigned long) data->val);
- break;
- case MSG_FORMAT_HEX:
- xf86DrvMsg(scrnIndex,X_INFO,"%s: 0x%lx\n",msg ,
- (unsigned long) data->val);
- break;
- case MSG_FORMAT_NONE:
- xf86DrvMsgVerb(scrnIndex, 7, X_INFO,
- "Call to %s succeeded\n", msg);
- break;
- }
-
- } else {
-
- char *result = (ret == ATOM_FAILED) ? "failed"
- : "not implemented";
- switch (msg_f) {
- case MSG_FORMAT_DEC:
- case MSG_FORMAT_HEX:
- xf86DrvMsgVerb(scrnIndex, 1, X_WARNING,
- "Call to %s %s\n", msg, result);
- break;
- case MSG_FORMAT_NONE:
- xf86DrvMsg(scrnIndex,X_INFO,"Query for %s: %s\n", msg, result);
- break;
- }
- }
- return ret;
-}
-
-# ifdef ATOM_BIOS_PARSER
-VOID*
-CailAllocateMemory(VOID *CAIL,UINT16 size)
-{
- CAILFUNC(CAIL);
-
- return malloc(size);
-}
-
-VOID
-CailReleaseMemory(VOID *CAIL, VOID *addr)
-{
- CAILFUNC(CAIL);
-
- free(addr);
-}
-
-VOID
-CailDelayMicroSeconds(VOID *CAIL, UINT32 delay)
-{
- CAILFUNC(CAIL);
-
- usleep(delay);
-
- DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));
-}
-
-UINT32
-CailReadATIRegister(VOID* CAIL, UINT32 idx)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- UINT32 ret;
- CAILFUNC(CAIL);
-
- ret = INREG(idx << 2);
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret));
- return ret;
-}
-
-VOID
-CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CAILFUNC(CAIL);
-
- OUTREG(idx << 2,data);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));
-}
-
-UINT32
-CailReadFBData(VOID* CAIL, UINT32 idx)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- UINT32 ret;
-
- CAILFUNC(CAIL);
-
- if (((atomBiosHandlePtr)CAIL)->fbBase) {
- CARD8 *FBBase = (CARD8*)info->FB;
- ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx));
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));
- } else if (((atomBiosHandlePtr)CAIL)->scratchBase) {
- ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx);
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));
- } else {
- xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR,
- "%s: no fbbase set\n",__func__);
- return 0;
- }
- return ret;
-}
-
-VOID
-CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data)
-{
- CAILFUNC(CAIL);
-
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));
- if (((atomBiosHandlePtr)CAIL)->fbBase) {
- CARD8 *FBBase = (CARD8*)
- RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB;
- *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data;
- } else if (((atomBiosHandlePtr)CAIL)->scratchBase) {
- *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data;
- } else
- xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR,
- "%s: no fbbase set\n",__func__);
-}
-
-ULONG
-CailReadMC(VOID *CAIL, ULONG Address)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- ULONG ret;
-
- CAILFUNC(CAIL);
-
- ret = INMC(pScrn, Address);
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));
- return ret;
-}
-
-VOID
-CailWriteMC(VOID *CAIL, ULONG Address, ULONG data)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
-
- CAILFUNC(CAIL);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));
- OUTMC(pScrn, Address, data);
-}
-
-#ifdef XSERVER_LIBPCIACCESS
-
-VOID
-CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size)
-{
- pci_device_cfg_read(RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->PciInfo,
- ret,idx << 2 , size >> 3, NULL);
-}
-
-VOID
-CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size)
-{
- pci_device_cfg_write(RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->PciInfo,
- src, idx << 2, size >> 3, NULL);
-}
-
-#else
-
-VOID
-CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size)
-{
- PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag;
-
- CAILFUNC(CAIL);
-
- switch (size) {
- case 8:
- *(CARD8*)ret = pciReadByte(tag,idx << 2);
- break;
- case 16:
- *(CARD16*)ret = pciReadWord(tag,idx << 2);
- break;
- case 32:
- *(CARD32*)ret = pciReadLong(tag,idx << 2);
- break;
- default:
- xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,
- X_ERROR,"%s: Unsupported size: %i\n",
- __func__,(int)size);
- return;
- break;
- }
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret));
-
-}
-
-VOID
-CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size)
-{
- PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag;
-
- CAILFUNC(CAIL);
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));
- switch (size) {
- case 8:
- pciWriteByte(tag,idx << 2,*(CARD8*)src);
- break;
- case 16:
- pciWriteWord(tag,idx << 2,*(CARD16*)src);
- break;
- case 32:
- pciWriteLong(tag,idx << 2,*(CARD32*)src);
- break;
- default:
- xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR,
- "%s: Unsupported size: %i\n",__func__,(int)size);
- break;
- }
-}
-#endif
-
-ULONG
-CailReadPLL(VOID *CAIL, ULONG Address)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- ULONG ret;
-
- CAILFUNC(CAIL);
-
- ret = RADEONINPLL(pScrn, Address);
- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));
- return ret;
-}
-
-VOID
-CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data)
-{
- ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
- CAILFUNC(CAIL);
-
- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data));
- RADEONOUTPLL(pScrn, Address, Data);
-}
-
-void
-atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor)
-{
- ATOM_MASTER_COMMAND_TABLE *cmd_table = (void *)(atomBIOS->BIOSBase + atomBIOS->cmd_offset);
- ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start;
- ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr;
-
- //unsigned short *ptr;
- unsigned short offset;
-
- table_start = &cmd_table->ListOfCommandTables;
-
- offset = *(((unsigned short *)table_start) + index);
-
- table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset);
-
- *major = table_hdr->CommonHeader.ucTableFormatRevision;
- *minor = table_hdr->CommonHeader.ucTableContentRevision;
-}
-
-
-#endif /* ATOM_BIOS */
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
deleted file mode 100644
index 9cb279e..0000000
--- a/src/radeon_atombios.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * Copyright 2007 Egbert Eich <eich at novell.com>
- * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
- * Copyright 2007 Matthias Hopf <mhopf at novell.com>
- * Copyright 2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef RHD_ATOMBIOS_H_
-# define RHD_ATOMBIOS_H_
-
-//#include "radeon.h"
-
-# ifdef ATOM_BIOS
-
-typedef enum _AtomBiosRequestID {
- ATOMBIOS_INIT,
- ATOMBIOS_TEARDOWN,
-# ifdef ATOM_BIOS_PARSER
- ATOMBIOS_EXEC,
-#endif
- ATOMBIOS_ALLOCATE_FB_SCRATCH,
- ATOMBIOS_GET_CONNECTORS,
- ATOMBIOS_GET_PANEL_MODE,
- ATOMBIOS_GET_PANEL_EDID,
- GET_DEFAULT_ENGINE_CLOCK,
- GET_DEFAULT_MEMORY_CLOCK,
- GET_MAX_PIXEL_CLOCK_PLL_OUTPUT,
- GET_MIN_PIXEL_CLOCK_PLL_OUTPUT,
- GET_MAX_PIXEL_CLOCK_PLL_INPUT,
- GET_MIN_PIXEL_CLOCK_PLL_INPUT,
- GET_MAX_PIXEL_CLK,
- GET_REF_CLOCK,
- GET_FW_FB_START,
- GET_FW_FB_SIZE,
- ATOM_TMDS_FREQUENCY,
- ATOM_TMDS_PLL_CHARGE_PUMP,
- ATOM_TMDS_PLL_DUTY_CYCLE,
- ATOM_TMDS_PLL_VCO_GAIN,
- ATOM_TMDS_PLL_VOLTAGE_SWING,
- ATOM_LVDS_SUPPORTED_REFRESH_RATE,
- ATOM_LVDS_OFF_DELAY,
- ATOM_LVDS_SEQ_DIG_ONTO_DE,
- ATOM_LVDS_SEQ_DE_TO_BL,
- ATOM_LVDS_DITHER,
- ATOM_LVDS_DUALLINK,
- ATOM_LVDS_24BIT,
- ATOM_LVDS_GREYLVL,
- ATOM_LVDS_FPDI,
- ATOM_GPIO_QUERIES,
- ATOM_GPIO_I2C_CLK_MASK,
- ATOM_DAC1_BG_ADJ,
- ATOM_DAC1_DAC_ADJ,
- ATOM_DAC1_FORCE,
- ATOM_DAC2_CRTC2_BG_ADJ,
- ATOM_DAC2_CRTC2_DAC_ADJ,
- ATOM_DAC2_CRTC2_FORCE,
- ATOM_DAC2_CRTC2_MUX_REG_IND,
- ATOM_DAC2_CRTC2_MUX_REG_INFO,
- ATOMBIOS_GET_CV_MODES,
- FUNC_END
-} AtomBiosRequestID;
-
-typedef enum _AtomBiosResult {
- ATOM_SUCCESS,
- ATOM_FAILED,
- ATOM_NOT_IMPLEMENTED
-} AtomBiosResult;
-
-typedef struct AtomExec {
- int index;
- pointer pspace;
- pointer *dataSpace;
-} AtomExecRec, *AtomExecPtr;
-
-typedef struct AtomFb {
- unsigned int start;
- unsigned int size;
-} AtomFbRec, *AtomFbPtr;
-
-typedef union AtomBiosArg
-{
- CARD32 val;
- struct rhdConnectorInfo *connectorInfo;
- unsigned char* EDIDBlock;
- atomBiosHandlePtr atomhandle;
- DisplayModePtr modes;
- AtomExecRec exec;
- AtomFbRec fb;
-} AtomBiosArgRec, *AtomBiosArgPtr;
-
-extern AtomBiosResult
-RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle,
- AtomBiosRequestID id, AtomBiosArgPtr data);
-
-extern Bool
-RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn);
-extern Bool
-RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn);
-
-extern Bool
-RADEONGetATOMTVInfo(xf86OutputPtr output);
-
-extern int
-atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
-
-extern void
-atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor);
-
-# include "xf86int10.h"
-# ifdef ATOM_BIOS_PARSER
-# define INT8 INT8
-# define INT16 INT16
-# define INT32 INT32
-# include "CD_Common_Types.h"
-# else
-# ifndef ULONG
-typedef unsigned int ULONG;
-# define ULONG ULONG
-# endif
-# ifndef UCHAR
-typedef unsigned char UCHAR;
-# define UCHAR UCHAR
-# endif
-# ifndef USHORT
-typedef unsigned short USHORT;
-# define USHORT USHORT
-# endif
-# endif
-
-# include "atombios.h"
-# include "ObjectID.h"
-
-
-/*
- * This works around a bug in atombios.h where
- * ATOM_MAX_SUPPORTED_DEVICE_INFO is specified incorrectly.
- */
-
-#define ATOM_MAX_SUPPORTED_DEVICE_INFO_HD (ATOM_DEVICE_RESERVEDF_INDEX+1)
-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_HD
-{
- ATOM_COMMON_TABLE_HEADER sHeader;
- USHORT usDeviceSupport;
- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD];
- ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD];
-} ATOM_SUPPORTED_DEVICES_INFO_HD;
-
-typedef struct _atomDataTables
-{
- unsigned char *UtilityPipeLine;
- ATOM_MULTIMEDIA_CAPABILITY_INFO *MultimediaCapabilityInfo;
- ATOM_MULTIMEDIA_CONFIG_INFO *MultimediaConfigInfo;
- ATOM_STANDARD_VESA_TIMING *StandardVESA_Timing;
- union {
- void *base;
- ATOM_FIRMWARE_INFO *FirmwareInfo;
- ATOM_FIRMWARE_INFO_V1_2 *FirmwareInfo_V_1_2;
- ATOM_FIRMWARE_INFO_V1_3 *FirmwareInfo_V_1_3;
- ATOM_FIRMWARE_INFO_V1_4 *FirmwareInfo_V_1_4;
- } FirmwareInfo;
- ATOM_DAC_INFO *DAC_Info;
- union {
- void *base;
- ATOM_LVDS_INFO *LVDS_Info;
- ATOM_LVDS_INFO_V12 *LVDS_Info_v12;
- } LVDS_Info;
- ATOM_TMDS_INFO *TMDS_Info;
- ATOM_ANALOG_TV_INFO *AnalogTV_Info;
- union {
- void *base;
- ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo;
- ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2;
- ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1;
- ATOM_SUPPORTED_DEVICES_INFO_HD *SupportedDevicesInfo_HD;
- } SupportedDevicesInfo;
- ATOM_GPIO_I2C_INFO *GPIO_I2C_Info;
- ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware;
- ATOM_GPIO_PIN_LUT *GPIO_Pin_LUT;
- ATOM_VESA_TO_INTENAL_MODE_LUT *VESA_ToInternalModeLUT;
- union {
- void *base;
- ATOM_COMPONENT_VIDEO_INFO *ComponentVideoInfo;
- ATOM_COMPONENT_VIDEO_INFO_V21 *ComponentVideoInfo_v21;
- } ComponentVideoInfo;
-/**/unsigned char *PowerPlayInfo;
- COMPASSIONATE_DATA *CompassionateData;
- ATOM_DISPLAY_DEVICE_PRIORITY_INFO *SaveRestoreInfo;
-/**/unsigned char *PPLL_SS_Info;
- ATOM_OEM_INFO *OemInfo;
- ATOM_XTMDS_INFO *XTMDS_Info;
- ATOM_ASIC_MVDD_INFO *MclkSS_Info;
- ATOM_OBJECT_HEADER *Object_Header;
- INDIRECT_IO_ACCESS *IndirectIOAccess;
- ATOM_MC_INIT_PARAM_TABLE *MC_InitParameter;
-/**/unsigned char *ASIC_VDDC_Info;
- ATOM_ASIC_INTERNAL_SS_INFO *ASIC_InternalSS_Info;
-/**/unsigned char *TV_VideoMode;
- union {
- void *base;
- ATOM_VRAM_INFO_V2 *VRAM_Info_v2;
- ATOM_VRAM_INFO_V3 *VRAM_Info_v3;
- } VRAM_Info;
- ATOM_MEMORY_TRAINING_INFO *MemoryTrainingInfo;
- union {
- void *base;
- ATOM_INTEGRATED_SYSTEM_INFO *IntegratedSystemInfo;
- ATOM_INTEGRATED_SYSTEM_INFO_V2 *IntegratedSystemInfo_v2;
- } IntegratedSystemInfo;
- ATOM_ASIC_PROFILING_INFO *ASIC_ProfilingInfo;
- ATOM_VOLTAGE_OBJECT_INFO *VoltageObjectInfo;
- ATOM_POWER_SOURCE_INFO *PowerSourceInfo;
-} atomDataTables, *atomDataTablesPtr;
-
-typedef struct _atomBiosHandle {
- int scrnIndex;
- unsigned char *BIOSBase;
- atomDataTablesPtr atomDataPtr;
- unsigned int cmd_offset;
- pointer *scratchBase;
- CARD32 fbBase;
-#if XSERVER_LIBPCIACCESS
- struct pci_device *device;
-#else
- PCITAG PciTag;
-#endif
- unsigned int BIOSImageSize;
-} atomBiosHandleRec;
-
-# endif
-
-extern Bool
-RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, int32_t *pixel_clock);
-
-#endif /* RHD_ATOMBIOS_H_ */
diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c
deleted file mode 100644
index 259366c..0000000
--- a/src/radeon_atomwrapper.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
- * Copyright 2007 Matthias Hopf <mhopf at novell.com>
- * Copyright 2007 Egbert Eich <eich at novell.com>
- * Copyright 2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-# include "config.h"
-#endif
-
-//#include "radeon_atomwrapper.h"
-
-#define INT32 INT32
-#include "CD_Common_Types.h"
-#include "CD_Definitions.h"
-
-
-int
-ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase,
- char **msg_return)
-{
- DEVICE_DATA deviceData;
- int ret = 0;
-
- /* FILL OUT PARAMETER SPACE */
- deviceData.pParameterSpace = (UINT32*) pspace;
- deviceData.CAIL = handle;
- deviceData.pBIOS_Image = BIOSBase;
- deviceData.format = TABLE_FORMAT_BIOS;
-
- switch (ParseTable(&deviceData, index)) { /* IndexInMasterTable */
- case CD_SUCCESS:
- ret = 1;
- *msg_return = "ParseTable said: CD_SUCCESS";
- break;
- case CD_CALL_TABLE:
- ret = 1;
- *msg_return = "ParseTable said: CD_CALL_TABLE";
- break;
- case CD_COMPLETED:
- ret = 1;
- *msg_return = "ParseTable said: CD_COMPLETED";
- break;
- case CD_GENERAL_ERROR:
- ret = 0;
- *msg_return = " ParseTable said: CD_GENERAL_ERROR";
- break;
- case CD_INVALID_OPCODE:
- ret = 0;
- *msg_return = " ParseTable said: CD_INVALID_OPCODE";
- break;
- case CD_NOT_IMPLEMENTED:
- ret = 0;
- *msg_return = " ParseTable said: CD_NOT_IMPLEMENTED";
- break;
- case CD_EXEC_TABLE_NOT_FOUND:
- ret = 0;
- *msg_return = " ParseTable said: CD_EXEC_TABLE_NOT_FOUND";
- break;
- case CD_EXEC_PARAMETER_ERROR:
- ret = 0;
- *msg_return = " ParseTable said: CD_EXEC_PARAMETER_ERROR";
- break;
- case CD_EXEC_PARSER_ERROR:
- ret = 0;
- *msg_return = " ParseTable said: CD_EXEC_PARSER_ERROR";
- break;
- case CD_INVALID_DESTINATION_TYPE:
- ret = 0;
- *msg_return = " ParseTable said: CD_INVALID_DESTINATION_TYPE";
- break;
- case CD_UNEXPECTED_BEHAVIOR:
- ret = 0;
- *msg_return = " ParseTable said: CD_UNEXPECTED_BEHAVIOR";
- break;
- case CD_INVALID_SWITCH_OPERAND_SIZE:
- ret = 0;
- *msg_return = " ParseTable said: CD_INVALID_SWITCH_OPERAND_SIZE\n";
- break;
- }
- return ret;
-}
diff --git a/src/radeon_atomwrapper.h b/src/radeon_atomwrapper.h
deleted file mode 100644
index 1e7cc77..0000000
--- a/src/radeon_atomwrapper.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2007 Luc Verhaegen <lverhaegen at novell.com>
- * Copyright 2007 Matthias Hopf <mhopf at novell.com>
- * Copyright 2007 Egbert Eich <eich at novell.com>
- * Copyright 2007 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef RHD_ATOMWRAPPER_H_
-# define RHD_ATOMWRAPPER_H_
-
-extern int ParseTableWrapper(void *pspace, int index, void *CAIL,
- void *BIOSBase, char **msg_return);
-
-#endif /* RHD_ATOMWRAPPER_H_ */
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
deleted file mode 100644
index 8e6bd8d..0000000
--- a/src/radeon_bios.c
+++ /dev/null
@@ -1,1469 +0,0 @@
-/*
- * Copyright 2004 ATI Technologies Inc., Markham, Ontario
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
-#include "xf86.h"
-#include "xf86_OSproc.h"
-
-#include "xf86PciInfo.h"
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_atombios.h"
-#include "vbe.h"
-
-typedef enum
-{
- DDC_NONE_DETECTED,
- DDC_MONID,
- DDC_DVI,
- DDC_VGA,
- DDC_CRT2,
- DDC_LCD,
- DDC_GPIO,
-} RADEONLegacyDDCType;
-
-typedef enum
-{
- CONNECTOR_NONE_LEGACY,
- CONNECTOR_PROPRIETARY_LEGACY,
- CONNECTOR_CRT_LEGACY,
- CONNECTOR_DVI_I_LEGACY,
- CONNECTOR_DVI_D_LEGACY,
- CONNECTOR_CTV_LEGACY,
- CONNECTOR_STV_LEGACY,
- CONNECTOR_UNSUPPORTED_LEGACY
-} RADEONLegacyConnectorType;
-
-
-/* Read the Video BIOS block and the FP registers (if applicable). */
-Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int tmp;
- unsigned short dptr;
-
-#ifdef XSERVER_LIBPCIACCESS
- //info->VBIOS = xalloc(info->PciInfo->rom_size);
- info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
-#else
- info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
-#endif
- if (!info->VBIOS) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Cannot allocate space for hold Video BIOS!\n");
- return FALSE;
- } else {
- if (pInt10) {
- info->BIOSAddr = pInt10->BIOSseg << 4;
- (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr),
- RADEON_VBIOS_SIZE);
- } else {
-#ifdef XSERVER_LIBPCIACCESS
- if (pci_device_read_rom(info->PciInfo, info->VBIOS)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Failed to read PCI ROM!\n");
- }
-#else
- xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE);
- if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Video BIOS not detected in PCI space!\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Attempting to read Video BIOS from "
- "legacy ISA space!\n");
- info->BIOSAddr = 0x000c0000;
- xf86ReadDomainMemory(info->PciTag, info->BIOSAddr,
- RADEON_VBIOS_SIZE, info->VBIOS);
- }
-#endif
- }
- }
-
- if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Unrecognized BIOS signature, BIOS data will not be used\n");
- xfree (info->VBIOS);
- info->VBIOS = NULL;
- return FALSE;
- }
-
- /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */
- dptr = RADEON_BIOS16(0x18);
- /* If PCI data signature is wrong assume x86 video BIOS anyway */
- if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "ROM PCI data signature incorrect, ignoring\n");
- }
- else if (info->VBIOS[dptr + 0x14] != 0x0) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Not an x86 BIOS ROM image, BIOS data will not be used\n");
- xfree (info->VBIOS);
- info->VBIOS = NULL;
- return FALSE;
- }
-
- if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48);
-
- if(!info->ROMHeaderStart) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Invalid ROM pointer, BIOS data will not be used\n");
- xfree (info->VBIOS);
- info->VBIOS = NULL;
- return FALSE;
- }
-
- tmp = info->ROMHeaderStart + 4;
- if ((RADEON_BIOS8(tmp) == 'A' &&
- RADEON_BIOS8(tmp+1) == 'T' &&
- RADEON_BIOS8(tmp+2) == 'O' &&
- RADEON_BIOS8(tmp+3) == 'M') ||
- (RADEON_BIOS8(tmp) == 'M' &&
- RADEON_BIOS8(tmp+1) == 'O' &&
- RADEON_BIOS8(tmp+2) == 'T' &&
- RADEON_BIOS8(tmp+3) == 'A'))
- info->IsAtomBios = TRUE;
- else
- info->IsAtomBios = FALSE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n",
- info->IsAtomBios ? "ATOM":"Legacy");
-
- if (info->IsAtomBios) {
-#if 1
- AtomBiosArgRec atomBiosArg;
-
- if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg)
- == ATOM_SUCCESS) {
- info->atomBIOS = atomBiosArg.atomhandle;
- }
-
- atomBiosArg.fb.start = info->FbFreeStart;
- atomBiosArg.fb.size = info->FbFreeSize;
- if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH,
- &atomBiosArg) == ATOM_SUCCESS) {
-
- info->FbFreeStart = atomBiosArg.fb.start;
- info->FbFreeSize = atomBiosArg.fb.size;
- }
-
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK,
- &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK,
- &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MAX_PIXEL_CLK, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_REF_CLOCK, &atomBiosArg);
-
-#endif
- info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
- }
-
- return TRUE;
-}
-
-static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
-
- if (!info->VBIOS) return FALSE;
-
- if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn))
- return TRUE;
-
- if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn))
- return TRUE;
-
- return FALSE;
-}
-
-static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- int offset, i, entry, tmp, tmp0, tmp1;
- RADEONLegacyDDCType DDCType;
- RADEONLegacyConnectorType ConnectorType;
-
- if (!info->VBIOS) return FALSE;
-
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x50);
- if (offset) {
- for (i = 0; i < 4; i++) {
- entry = offset + 2 + i*2;
-
- if (!RADEON_BIOS16(entry)) {
- break;
- }
- info->BiosConnector[i].valid = TRUE;
- tmp = RADEON_BIOS16(entry);
- info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf;
- ConnectorType = (tmp >> 12) & 0xf;
- switch (ConnectorType) {
- case CONNECTOR_PROPRIETARY_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_LVDS;
- break;
- case CONNECTOR_CRT_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_VGA;
- break;
- case CONNECTOR_DVI_I_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I;
- break;
- case CONNECTOR_DVI_D_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D;
- break;
- case CONNECTOR_CTV_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_CTV;
- break;
- case CONNECTOR_STV_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_STV;
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType);
- info->BiosConnector[i].valid = FALSE;
- break;
- }
-
- info->BiosConnector[i].ddc_i2c.valid = FALSE;
-
- DDCType = (tmp >> 8) & 0xf;
- switch (DDCType) {
- case DDC_MONID:
- info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- break;
- case DDC_DVI:
- info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- break;
- case DDC_VGA:
- info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- break;
- case DDC_CRT2:
- info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType);
- break;
- }
-
- if (tmp & 0x1)
- info->BiosConnector[i].DACType = DAC_TVDAC;
- else
- info->BiosConnector[i].DACType = DAC_PRIMARY;
-
- /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
- if (info->IsIGP)
- info->BiosConnector[i].DACType = DAC_TVDAC;
-
- if ((tmp >> 4) & 0x1)
- info->BiosConnector[i].TMDSType = TMDS_EXT;
- else
- info->BiosConnector[i].TMDSType = TMDS_INT;
-
- /* most XPRESS chips seem to specify DDC_CRT2 for their
- * VGA DDC port, however DDC never seems to work on that
- * port. Some have reported success on DDC_MONID, so
- * lets see what happens with that.
- */
- if (info->ChipFamily == CHIP_FAMILY_RS400 &&
- info->BiosConnector[i].ConnectorType == CONNECTOR_VGA &&
- info->BiosConnector[i].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
- info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- }
-
- /* XPRESS desktop chips seem to have a proprietary connector listed for
- * DVI-D, try and do the right thing here.
- */
- if ((!info->IsMobility) &&
- (info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Proprietary connector found, assuming DVI-D\n");
- info->BiosConnector[i].DACType = DAC_NONE;
- info->BiosConnector[i].TMDSType = TMDS_EXT;
- info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D;
- }
- }
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n");
-
- /* old radeons and r128 didn't use connector tables you just check
- * for LVDS, DVI, TV, etc. tables
- */
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34);
- if (offset) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Found DFP table, assuming DVI connector\n");
- info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[0].DACType = DAC_PRIMARY;
- info->BiosConnector[0].TMDSType = TMDS_INT;
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- } else
- return FALSE;
- }
-
- /* check LVDS table */
- if (info->IsMobility) {
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40);
- if (offset) {
- info->BiosConnector[4].valid = TRUE;
- info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[4].DACType = DAC_NONE;
- info->BiosConnector[4].TMDSType = TMDS_NONE;
- info->BiosConnector[4].ddc_i2c.valid = FALSE;
-
- tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42);
- if (tmp) {
- tmp0 = RADEON_BIOS16(tmp + 0x15);
- if (tmp0) {
- tmp1 = RADEON_BIOS8(tmp0+2) & 0x07;
- if (tmp1) {
- DDCType = tmp1;
- switch (DDCType) {
- case DDC_MONID:
- info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- break;
- case DDC_DVI:
- info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- break;
- case DDC_VGA:
- info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- break;
- case DDC_CRT2:
- info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- break;
- case DDC_LCD:
- info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
- info->BiosConnector[4].ddc_i2c.mask_clk_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.mask_data_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
- info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
- info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07);
- break;
- case DDC_GPIO:
- info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
- info->BiosConnector[4].ddc_i2c.mask_clk_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.mask_data_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
- info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
- info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07);
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType);
- break;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n");
- }
- }
- } else {
- info->BiosConnector[4].ddc_i2c.valid = FALSE;
- }
- }
- }
-
- /* check TV table */
- if (info->InternalTVOut) {
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32);
- if (offset) {
- if (RADEON_BIOS8(offset + 6) == 'T') {
- info->BiosConnector[5].valid = TRUE;
- /* assume s-video for now */
- info->BiosConnector[5].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[5].DACType = DAC_TVDAC;
- info->BiosConnector[5].TMDSType = TMDS_NONE;
- info->BiosConnector[5].ddc_i2c.valid = FALSE;
- }
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n");
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].valid) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d\n",
- i, (unsigned int)info->BiosConnector[i].ddc_i2c.mask_clk_reg, info->BiosConnector[i].DACType,
- info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType);
- }
- }
-
- return TRUE;
-}
-
-Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
-
- if(!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios)
- return RADEONGetATOMConnectorInfoFromBIOS(pScrn);
- else
- return RADEONGetLegacyConnectorInfoFromBIOS(pScrn);
-}
-
-Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) {
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int offset, refclk, stds;
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- return RADEONGetATOMTVInfo(output);
- } else {
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32);
- if (offset) {
- if (RADEON_BIOS8(offset + 6) == 'T') {
- switch (RADEON_BIOS8(offset + 7) & 0xf) {
- case 1:
- radeon_output->default_tvStd = TV_STD_NTSC;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n");
- break;
- case 2:
- radeon_output->default_tvStd = TV_STD_PAL;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n");
- break;
- case 3:
- radeon_output->default_tvStd = TV_STD_PAL_M;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n");
- break;
- case 4:
- radeon_output->default_tvStd = TV_STD_PAL_60;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n");
- break;
- case 5:
- radeon_output->default_tvStd = TV_STD_NTSC_J;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n");
- break;
- case 6:
- radeon_output->default_tvStd = TV_STD_SCART_PAL;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n");
- break;
- default:
- radeon_output->default_tvStd = TV_STD_NTSC;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n");
- break;
- }
- radeon_output->tvStd = radeon_output->default_tvStd;
-
- refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3;
- if (refclk == 0)
- radeon_output->TVRefClk = 29.498928713; /* MHz */
- else if (refclk == 1)
- radeon_output->TVRefClk = 28.636360000;
- else if (refclk == 2)
- radeon_output->TVRefClk = 14.318180000;
- else if (refclk == 3)
- radeon_output->TVRefClk = 27.000000000;
-
- radeon_output->SupportedTVStds = radeon_output->default_tvStd;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: ");
- stds = RADEON_BIOS8(offset + 10) & 0x1f;
- if (stds & TV_STD_NTSC) {
- radeon_output->SupportedTVStds |= TV_STD_NTSC;
- ErrorF("NTSC ");
- }
- if (stds & TV_STD_PAL) {
- radeon_output->SupportedTVStds |= TV_STD_PAL;
- ErrorF("PAL ");
- }
- if (stds & TV_STD_PAL_M) {
- radeon_output->SupportedTVStds |= TV_STD_PAL_M;
- ErrorF("PAL-M ");
- }
- if (stds & TV_STD_PAL_60) {
- radeon_output->SupportedTVStds |= TV_STD_PAL_60;
- ErrorF("PAL-60 ");
- }
- if (stds & TV_STD_NTSC_J) {
- radeon_output->SupportedTVStds |= TV_STD_NTSC_J;
- ErrorF("NTSC-J ");
- }
- if (stds & TV_STD_SCART_PAL) {
- radeon_output->SupportedTVStds |= TV_STD_SCART_PAL;
- ErrorF("SCART-PAL");
- }
- ErrorF("\n");
-
- return TRUE;
- }
- }
- }
- return FALSE;
-}
-
-/* Read PLL parameters from BIOS block. Default to typical values if there
- is no BIOS. */
-Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- RADEONPLLPtr pll = &info->pll;
- CARD16 pll_info_block;
-
- if (!info->VBIOS) {
- return FALSE;
- } else {
- if (info->IsAtomBios) {
- pll_info_block = RADEON_BIOS16 (info->MasterDataStart + 12);
-
- pll->reference_freq = RADEON_BIOS16 (pll_info_block + 82);
- pll->reference_div = 0; /* Need to derive from existing setting
- or use a new algorithm to calculate
- from min_input and max_input
- */
- pll->pll_out_min = RADEON_BIOS16 (pll_info_block + 78);
- pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 32);
-
- if (pll->pll_out_min == 0) {
- if (IS_AVIVO_VARIANT)
- pll->pll_out_min = 64800;
- else
- pll->pll_out_min = 20000;
- }
-
- pll->pll_in_min = RADEON_BIOS16 (pll_info_block + 74);
- pll->pll_in_max = RADEON_BIOS16 (pll_info_block + 76);
-
- pll->xclk = RADEON_BIOS16 (pll_info_block + 72);
-
- info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0;
- info->mclk = RADEON_BIOS32(pll_info_block + 12) / 100.0;
- } else {
- int rev;
-
- pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30);
-
- rev = RADEON_BIOS8(pll_info_block);
-
- pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e);
- pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10);
- pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12);
- pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16);
-
- if (rev > 9) {
- pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36);
- pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a);
- } else {
- pll->pll_in_min = 40;
- pll->pll_in_max = 500;
- }
-
- pll->xclk = RADEON_BIOS16(pll_info_block + 0x08);
-
- info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0;
- info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0;
- }
-
- if (info->sclk == 0) info->sclk = 200;
- if (info->mclk == 0) info->mclk = 200;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_out_pll: %u, "
- "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, "
- "sclk: %f, mclk: %f\n",
- pll->reference_freq, (unsigned)pll->pll_out_min,
- (unsigned)pll->pll_out_max, (unsigned)pll->pll_in_min,
- (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk);
-
- return TRUE;
-}
-
-Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int offset, rev, bg, dac;
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- /* not implemented yet */
- return FALSE;
- } else {
- /* first check TV table */
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32);
- if (offset) {
- rev = RADEON_BIOS8(offset + 0x3);
- if (rev > 1) {
- bg = RADEON_BIOS8(offset + 0xc) & 0xf;
- dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf;
- radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
-
- bg = RADEON_BIOS8(offset + 0xd) & 0xf;
- dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf;
- radeon_output->pal_tvdac_adj = (bg << 16) | (dac << 20);
-
- bg = RADEON_BIOS8(offset + 0xe) & 0xf;
- dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf;
- radeon_output->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
-
- return TRUE;
- }
- }
- /* then check CRT table */
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x60);
- if (offset) {
- rev = RADEON_BIOS8(offset) & 0x3;
- if (rev < 2) {
- bg = RADEON_BIOS8(offset + 0x3) & 0xf;
- dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf;
- radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
- radeon_output->pal_tvdac_adj = radeon_output->ps2_tvdac_adj;
- radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj;
-
- return TRUE;
- }
- }
- }
-
- return FALSE;
-}
-
-Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- unsigned long tmp, i;
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- if((tmp = RADEON_BIOS16 (info->MasterDataStart + 16))) {
-
- radeon_output->PanelXRes = RADEON_BIOS16(tmp+6);
- radeon_output->PanelYRes = RADEON_BIOS16(tmp+10);
- radeon_output->DotClock = RADEON_BIOS16(tmp+4)*10;
- radeon_output->HBlank = RADEON_BIOS16(tmp+8);
- radeon_output->HOverPlus = RADEON_BIOS16(tmp+14);
- radeon_output->HSyncWidth = RADEON_BIOS16(tmp+16);
- radeon_output->VBlank = RADEON_BIOS16(tmp+12);
- radeon_output->VOverPlus = RADEON_BIOS16(tmp+18);
- radeon_output->VSyncWidth = RADEON_BIOS16(tmp+20);
- radeon_output->PanelPwrDly = RADEON_BIOS16(tmp+40);
-
- if (radeon_output->PanelPwrDly > 2000 || radeon_output->PanelPwrDly < 0)
- radeon_output->PanelPwrDly = 2000;
-
- radeon_output->Flags = 0;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No LVDS Info Table found in BIOS!\n");
- return FALSE;
- }
- } else {
-
- tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40);
-
- if (!tmp) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No Panel Info Table found in BIOS!\n");
- return FALSE;
- } else {
- char stmp[30];
- int tmp0;
-
- for (i = 0; i < 24; i++)
- stmp[i] = RADEON_BIOS8(tmp+i+1);
- stmp[24] = 0;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Panel ID string: %s\n", stmp);
-
- radeon_output->PanelXRes = RADEON_BIOS16(tmp+25);
- radeon_output->PanelYRes = RADEON_BIOS16(tmp+27);
- xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes);
-
- radeon_output->PanelPwrDly = RADEON_BIOS16(tmp+44);
- if (radeon_output->PanelPwrDly > 2000 || radeon_output->PanelPwrDly < 0)
- radeon_output->PanelPwrDly = 2000;
-
- /* some panels only work well with certain divider combinations.
- */
- info->RefDivider = RADEON_BIOS16(tmp+46);
- info->PostDivider = RADEON_BIOS8(tmp+48);
- info->FeedbackDivider = RADEON_BIOS16(tmp+49);
- if ((info->RefDivider != 0) &&
- (info->FeedbackDivider > 3)) {
- info->UseBiosDividers = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "BIOS provided dividers will be used.\n");
- }
-
- /* We don't use a while loop here just in case we have a corrupted BIOS image.
- The max number of table entries is 23 at present, but may grow in future.
- To ensure it works with future revisions we loop it to 32.
- */
- for (i = 0; i < 32; i++) {
- tmp0 = RADEON_BIOS16(tmp+64+i*2);
- if (tmp0 == 0) break;
- if ((RADEON_BIOS16(tmp0) == radeon_output->PanelXRes) &&
- (RADEON_BIOS16(tmp0+2) == radeon_output->PanelYRes)) {
- radeon_output->HBlank = (RADEON_BIOS16(tmp0+17) -
- RADEON_BIOS16(tmp0+19)) * 8;
- radeon_output->HOverPlus = (RADEON_BIOS16(tmp0+21) -
- RADEON_BIOS16(tmp0+19) - 1) * 8;
- radeon_output->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8;
- radeon_output->VBlank = (RADEON_BIOS16(tmp0+24) -
- RADEON_BIOS16(tmp0+26));
- radeon_output->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) -
- RADEON_BIOS16(tmp0+26));
- radeon_output->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11);
- radeon_output->DotClock = RADEON_BIOS16(tmp0+9) * 10;
- radeon_output->Flags = 0;
- }
- }
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "LVDS Info:\n"
- "XRes: %d, YRes: %d, DotClock: %d\n"
- "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n"
- "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes, radeon_output->DotClock,
- radeon_output->HBlank, radeon_output->HOverPlus, radeon_output->HSyncWidth,
- radeon_output->VBlank, radeon_output->VOverPlus, radeon_output->VSyncWidth);
-
- return TRUE;
-}
-
-Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- unsigned long tmp;
- char EDID[256];
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- /* Not yet */
- return FALSE;
- } else {
- if (!(tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c))) {
- return FALSE;
- }
-
- memcpy(EDID, (char*)(info->VBIOS + tmp), 256);
-
- radeon_output->DotClock = (*(CARD16*)(EDID+54)) * 10;
- radeon_output->PanelXRes = (*(CARD8*)(EDID+56)) + ((*(CARD8*)(EDID+58))>>4)*256;
- radeon_output->HBlank = (*(CARD8*)(EDID+57)) + ((*(CARD8*)(EDID+58)) & 0xf)*256;
- radeon_output->HOverPlus = (*(CARD8*)(EDID+62)) + ((*(CARD8*)(EDID+65)>>6)*256);
- radeon_output->HSyncWidth = (*(CARD8*)(EDID+63)) + (((*(CARD8*)(EDID+65)>>4) & 3)*256);
- radeon_output->PanelYRes = (*(CARD8*)(EDID+59)) + ((*(CARD8*)(EDID+61))>>4)*256;
- radeon_output->VBlank = ((*(CARD8*)(EDID+60)) + ((*(CARD8*)(EDID+61)) & 0xf)*256);
- radeon_output->VOverPlus = (((*(CARD8*)(EDID+64))>>4) + (((*(CARD8*)(EDID+65)>>2) & 3)*16));
- radeon_output->VSyncWidth = (((*(CARD8*)(EDID+64)) & 0xf) + ((*(CARD8*)(EDID+65)) & 3)*256);
- radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(CARD8*)(EDID+71);*/
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n");
- }
- return TRUE;
-}
-
-Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- CARD32 tmp, maxfreq;
- int i, n;
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) {
-
- maxfreq = RADEON_BIOS16(tmp+4);
-
- for (i=0; i<4; i++) {
- radeon_output->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6);
- /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */
- radeon_output->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) |
- ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) |
- ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) |
- ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16));
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "TMDS PLL from BIOS: %u %x\n",
- (unsigned)radeon_output->tmds_pll[i].freq,
- (unsigned)radeon_output->tmds_pll[i].value);
-
- if (maxfreq == radeon_output->tmds_pll[i].freq) {
- radeon_output->tmds_pll[i].freq = 0xffffffff;
- break;
- }
- }
- return TRUE;
- }
- } else {
-
- tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34);
- if (tmp) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "DFP table revision: %d\n", RADEON_BIOS8(tmp));
- if (RADEON_BIOS8(tmp) == 3) {
- n = RADEON_BIOS8(tmp + 5) + 1;
- if (n > 4) n = 4;
- for (i=0; i<n; i++) {
- radeon_output->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08);
- radeon_output->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10);
- }
- return TRUE;
- } else if (RADEON_BIOS8(tmp) == 4) {
- int stride = 0;
- n = RADEON_BIOS8(tmp + 5) + 1;
- if (n > 4) n = 4;
- for (i=0; i<n; i++) {
- radeon_output->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08);
- radeon_output->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10);
- if (i == 0) stride += 10;
- else stride += 6;
- }
- return TRUE;
- }
- }
- }
- return FALSE;
-}
-
-Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int offset, table_start, max_freq, gpio_reg, flags;
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- return FALSE;
- } else {
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58);
- if (offset) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "External TMDS Table revision: %d\n",
- RADEON_BIOS8(offset));
- table_start = offset+4;
- max_freq = RADEON_BIOS16(table_start);
- radeon_output->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2);
- radeon_output->dvo_i2c.valid = FALSE;
- gpio_reg = RADEON_BIOS8(table_start+3);
- if (gpio_reg == 1)
- radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- else if (gpio_reg == 2)
- radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- else if (gpio_reg == 3)
- radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- else if (gpio_reg == 4)
- radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- else if (gpio_reg == 5)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "unsupported MM gpio_reg\n");
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Unknown gpio reg: %d\n", gpio_reg);
- return FALSE;
- }
- flags = RADEON_BIOS8(table_start+5);
- radeon_output->dvo_duallink = flags & 0x01;
- if (radeon_output->dvo_duallink) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Duallink TMDS detected\n");
- }
- return TRUE;
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No External TMDS Table found\n");
-
- return FALSE;
-}
-
-Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int offset, index, id;
- CARD32 val, reg, andmask, ormask;
-
- if (!info->VBIOS) return FALSE;
-
- if (info->IsAtomBios) {
- return FALSE;
- } else {
- offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58);
- if (offset) {
- index = offset+10;
- id = RADEON_BIOS16(index);
- while (id != 0xffff) {
- index += 2;
- switch(id >> 13) {
- case 0:
- reg = id & 0x1fff;
- val = RADEON_BIOS32(index);
- index += 4;
- ErrorF("WRITE INDEXED: 0x%x 0x%x\n",
- (unsigned)reg, (unsigned)val);
- /*OUTREG(reg, val);*/
- break;
- case 2:
- reg = id & 0x1fff;
- andmask = RADEON_BIOS32(index);
- index += 4;
- ormask = RADEON_BIOS32(index);
- index += 4;
- val = INREG(reg);
- val = (val & andmask) | ormask;
- ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n",
- (unsigned)reg, (unsigned)andmask, (unsigned)ormask);
- /*OUTREG(reg, val);*/
- break;
- case 4:
- val = RADEON_BIOS16(index);
- index += 2;
- ErrorF("delay: %u\n", (unsigned)val);
- usleep(val);
- break;
- case 5:
- reg = id & 0x1fff;
- andmask = RADEON_BIOS32(index);
- index += 4;
- ormask = RADEON_BIOS32(index);
- index += 4;
- ErrorF("MASK PLL: 0x%x 0x%x 0x%x\n",
- (unsigned)reg, (unsigned)andmask, (unsigned)ormask);
- /*val = INPLL(pScrn, reg);
- val = (val & andmask) | ormask;
- OUTPLL(pScrn, reg, val);*/
- break;
- case 6:
- reg = id & 0x1fff;
- val = RADEON_BIOS8(index);
- index += 1;
- ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg,
- (unsigned)val);
- RADEONDVOWriteByte(radeon_output->DVOChip, reg, val);
- break;
- default:
- ErrorF("unknown id %d\n", id>>13);
- return FALSE;
- };
- id = RADEON_BIOS16(index);
- }
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-/* support for init from bios tables
- *
- * Based heavily on the netbsd radeonfb driver
- * Written by Garrett D'Amore
- * Copyright (c) 2006 Itronix Inc.
- *
- */
-
-/* bios table defines */
-
-#define RADEON_TABLE_ENTRY_FLAG_MASK 0xe000
-#define RADEON_TABLE_ENTRY_INDEX_MASK 0x1fff
-#define RADEON_TABLE_ENTRY_COMMAND_MASK 0x00ff
-
-#define RADEON_TABLE_FLAG_WRITE_INDEXED 0x0000
-#define RADEON_TABLE_FLAG_WRITE_DIRECT 0x2000
-#define RADEON_TABLE_FLAG_MASK_INDEXED 0x4000
-#define RADEON_TABLE_FLAG_MASK_DIRECT 0x6000
-#define RADEON_TABLE_FLAG_DELAY 0x8000
-#define RADEON_TABLE_FLAG_SCOMMAND 0xa000
-
-#define RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK 0x03
-#define RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE 0x08
-
-#define RADEON_PLL_FLAG_MASK 0xc0
-#define RADEON_PLL_INDEX_MASK 0x3f
-
-#define RADEON_PLL_FLAG_WRITE 0x00
-#define RADEON_PLL_FLAG_MASK_BYTE 0x40
-#define RADEON_PLL_FLAG_WAIT 0x80
-
-#define RADEON_PLL_WAIT_150MKS 1
-#define RADEON_PLL_WAIT_5MS 2
-#define RADEON_PLL_WAIT_MC_BUSY_MASK 3
-#define RADEON_PLL_WAIT_DLL_READY_MASK 4
-#define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5
-
-static CARD16
-RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, CARD16 offset)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- CARD8 revision = RADEON_BIOS8(offset - 1);
-
- if (revision > 0x10) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Bad revision %d for BIOS table\n", revision);
- return 0;
- }
-
- if (offset < 0x60) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Bad offset 0x%x for BIOS Table\n", offset);
- return 0;
- }
-
- return offset;
-}
-
-Bool
-RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- CARD8 val;
-
- if (!info->VBIOS) {
- return FALSE;
- } else {
- if (info->IsAtomBios) {
- return FALSE;
- } else {
- info->BiosTable.revision = RADEON_BIOS8(info->ROMHeaderStart + 4);
- info->BiosTable.rr1_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x0c);
- if (info->BiosTable.rr1_offset) {
- info->BiosTable.rr1_offset =
- RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr1_offset);
- }
- if (info->BiosTable.revision > 0x09)
- return TRUE;
- info->BiosTable.rr2_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x4e);
- if (info->BiosTable.rr2_offset) {
- info->BiosTable.rr2_offset =
- RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr2_offset);
- }
- info->BiosTable.dyn_clk_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x52);
- if (info->BiosTable.dyn_clk_offset) {
- info->BiosTable.dyn_clk_offset =
- RADEONValidateBIOSOffset(pScrn, info->BiosTable.dyn_clk_offset);
- }
- info->BiosTable.pll_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x46);
- if (info->BiosTable.pll_offset) {
- info->BiosTable.pll_offset =
- RADEONValidateBIOSOffset(pScrn, info->BiosTable.pll_offset);
- }
- info->BiosTable.mem_config_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x48);
- if (info->BiosTable.mem_config_offset) {
- info->BiosTable.mem_config_offset =
- RADEONValidateBIOSOffset(pScrn, info->BiosTable.mem_config_offset);
- }
- if (info->BiosTable.mem_config_offset) {
- info->BiosTable.mem_reset_offset = info->BiosTable.mem_config_offset;
- if (info->BiosTable.mem_reset_offset) {
- while (RADEON_BIOS8(info->BiosTable.mem_reset_offset))
- info->BiosTable.mem_reset_offset++;
- info->BiosTable.mem_reset_offset++;
- info->BiosTable.mem_reset_offset += 2;
- }
- }
- if (info->BiosTable.mem_config_offset) {
- info->BiosTable.short_mem_offset = info->BiosTable.mem_config_offset;
- if ((info->BiosTable.short_mem_offset != 0) &&
- (RADEON_BIOS8(info->BiosTable.short_mem_offset - 2) <= 64))
- info->BiosTable.short_mem_offset +=
- RADEON_BIOS8(info->BiosTable.short_mem_offset - 3);
- }
- if (info->BiosTable.rr2_offset) {
- info->BiosTable.rr3_offset = info->BiosTable.rr2_offset;
- if (info->BiosTable.rr3_offset) {
- while ((val = RADEON_BIOS8(info->BiosTable.rr3_offset + 1)) != 0) {
- if (val & 0x40)
- info->BiosTable.rr3_offset += 10;
- else if (val & 0x80)
- info->BiosTable.rr3_offset += 4;
- else
- info->BiosTable.rr3_offset += 6;
- }
- info->BiosTable.rr3_offset += 2;
- }
- }
-
- if (info->BiosTable.rr3_offset) {
- info->BiosTable.rr4_offset = info->BiosTable.rr3_offset;
- if (info->BiosTable.rr4_offset) {
- while ((val = RADEON_BIOS8(info->BiosTable.rr4_offset + 1)) != 0) {
- if (val & 0x40)
- info->BiosTable.rr4_offset += 10;
- else if (val & 0x80)
- info->BiosTable.rr4_offset += 4;
- else
- info->BiosTable.rr4_offset += 6;
- }
- info->BiosTable.rr4_offset += 2;
- }
- }
-
- if (info->BiosTable.rr3_offset + 1 == info->BiosTable.pll_offset) {
- info->BiosTable.rr3_offset = 0;
- info->BiosTable.rr4_offset = 0;
- }
-
- return TRUE;
-
- }
- }
-}
-
-static void
-RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD16 offset = table_offset;
- CARD16 value, flag, index, count;
- CARD32 andmask, ormask, val, channel_complete_mask;
- CARD8 command;
-
- if (offset == 0)
- return;
-
- while ((value = RADEON_BIOS16(offset)) != 0) {
- flag = value & RADEON_TABLE_ENTRY_FLAG_MASK;
- index = value & RADEON_TABLE_ENTRY_INDEX_MASK;
- command = value & RADEON_TABLE_ENTRY_COMMAND_MASK;
-
- offset += 2;
-
- switch (flag) {
- case RADEON_TABLE_FLAG_WRITE_INDEXED:
- val = RADEON_BIOS32(offset);
- ErrorF("WRITE INDEXED: 0x%x 0x%x\n",
- index, (unsigned)val);
- OUTREG(RADEON_MM_INDEX, index);
- OUTREG(RADEON_MM_DATA, val);
- offset += 4;
- break;
-
- case RADEON_TABLE_FLAG_WRITE_DIRECT:
- val = RADEON_BIOS32(offset);
- ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val);
- OUTREG(index, val);
- offset += 4;
- break;
-
- case RADEON_TABLE_FLAG_MASK_INDEXED:
- andmask = RADEON_BIOS32(offset);
- offset += 4;
- ormask = RADEON_BIOS32(offset);
- offset += 4;
- ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n",
- index, (unsigned)andmask, (unsigned)ormask);
- OUTREG(RADEON_MM_INDEX, index);
- val = INREG(RADEON_MM_DATA);
- val = (val & andmask) | ormask;
- OUTREG(RADEON_MM_DATA, val);
- break;
-
- case RADEON_TABLE_FLAG_MASK_DIRECT:
- andmask = RADEON_BIOS32(offset);
- offset += 4;
- ormask = RADEON_BIOS32(offset);
- offset += 4;
- ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n",
- index, (unsigned)andmask, (unsigned)ormask);
- val = INREG(index);
- val = (val & andmask) | ormask;
- OUTREG(index, val);
- break;
-
- case RADEON_TABLE_FLAG_DELAY:
- count = RADEON_BIOS16(offset);
- ErrorF("delay: %d\n", count);
- usleep(count);
- offset += 2;
- break;
-
- case RADEON_TABLE_FLAG_SCOMMAND:
- ErrorF("SCOMMAND 0x%x\n", command);
- switch (command) {
- case RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK:
- count = RADEON_BIOS16(offset);
- ErrorF("SCOMMAND_WAIT_MC_BUSY_MASK %d\n", count);
- while (count--) {
- if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) &
- RADEON_MC_BUSY))
- break;
- }
- break;
-
- case RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE:
- count = RADEON_BIOS16(offset);
- ErrorF("SCOMMAND_WAIT_MEM_PWRUP_COMPLETE %d\n", count);
- /* may need to take into account how many memory channels
- * each card has
- */
- if (IS_R300_VARIANT)
- channel_complete_mask = R300_MEM_PWRUP_COMPLETE;
- else
- channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE;
- while (count--) {
- /* XXX: may need indexed access */
- if ((INREG(RADEON_MEM_STR_CNTL) &
- channel_complete_mask) ==
- channel_complete_mask)
- break;
- }
- break;
-
- }
- offset += 2;
- break;
- }
- }
-}
-
-static void
-RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD16 offset = table_offset;
- CARD16 count;
- CARD32 ormask, val, channel_complete_mask;
- CARD8 index;
-
- if (offset == 0)
- return;
-
- while ((index = RADEON_BIOS8(offset)) != 0xff) {
- offset++;
- if (index == 0x0f) {
- count = 20000;
- ErrorF("MEM_WAIT_MEM_PWRUP_COMPLETE %d\n", count);
- /* may need to take into account how many memory channels
- * each card has
- */
- if (IS_R300_VARIANT)
- channel_complete_mask = R300_MEM_PWRUP_COMPLETE;
- else
- channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE;
- while (count--) {
- /* XXX: may need indexed access */
- if ((INREG(RADEON_MEM_STR_CNTL) &
- channel_complete_mask) ==
- channel_complete_mask)
- break;
- }
- } else {
- ormask = RADEON_BIOS16(offset);
- offset += 2;
-
- ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n",
- RADEON_SDRAM_MODE_MASK, (unsigned)ormask);
-
- /* can this use direct access? */
- OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG);
- val = INREG(RADEON_MM_DATA);
- val = (val & RADEON_SDRAM_MODE_MASK) | ormask;
- OUTREG(RADEON_MM_DATA, val);
-
- ormask = (CARD32)index << 24;
-
- ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n",
- RADEON_B3MEM_RESET_MASK, (unsigned)ormask);
-
- /* can this use direct access? */
- OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG);
- val = INREG(RADEON_MM_DATA);
- val = (val & RADEON_B3MEM_RESET_MASK) | ormask;
- OUTREG(RADEON_MM_DATA, val);
- }
- }
-}
-
-static void
-RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- CARD16 offset = table_offset;
- CARD8 index, shift;
- CARD32 andmask, ormask, val, clk_pwrmgt_cntl;
- CARD16 count;
-
- if (offset == 0)
- return;
-
- while ((index = RADEON_BIOS8(offset)) != 0) {
- offset++;
-
- switch (index & RADEON_PLL_FLAG_MASK) {
- case RADEON_PLL_FLAG_WAIT:
- switch (index & RADEON_PLL_INDEX_MASK) {
- case RADEON_PLL_WAIT_150MKS:
- ErrorF("delay: 150 us\n");
- usleep(150);
- break;
- case RADEON_PLL_WAIT_5MS:
- ErrorF("delay: 5 ms\n");
- usleep(5000);
- break;
-
- case RADEON_PLL_WAIT_MC_BUSY_MASK:
- count = 1000;
- ErrorF("PLL_WAIT_MC_BUSY_MASK %d\n", count);
- while (count--) {
- if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) &
- RADEON_MC_BUSY))
- break;
- }
- break;
-
- case RADEON_PLL_WAIT_DLL_READY_MASK:
- count = 1000;
- ErrorF("PLL_WAIT_DLL_READY_MASK %d\n", count);
- while (count--) {
- if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) &
- RADEON_DLL_READY)
- break;
- }
- break;
-
- case RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24:
- ErrorF("PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24\n");
- clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL);
- if (clk_pwrmgt_cntl & RADEON_CG_NO1_DEBUG_0) {
- val = INPLL(pScrn, RADEON_MCLK_CNTL);
- /* is this right? */
- val = (val & 0xFFFF0000) | 0x1111; /* seems like we should clear these... */
- OUTPLL(pScrn, RADEON_MCLK_CNTL, val);
- usleep(10000);
- OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL,
- clk_pwrmgt_cntl & ~RADEON_CG_NO1_DEBUG_0);
- usleep(10000);
- }
- break;
- }
- break;
-
- case RADEON_PLL_FLAG_MASK_BYTE:
- shift = RADEON_BIOS8(offset) * 8;
- offset++;
-
- andmask =
- (((CARD32)RADEON_BIOS8(offset)) << shift) |
- ~((CARD32)0xff << shift);
- offset++;
-
- ormask = ((CARD32)RADEON_BIOS8(offset)) << shift;
- offset++;
-
- ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n",
- index, shift, (unsigned)andmask, (unsigned)ormask);
- val = INPLL(pScrn, index);
- val = (val & andmask) | ormask;
- OUTPLL(pScrn, index, val);
- break;
-
- case RADEON_PLL_FLAG_WRITE:
- val = RADEON_BIOS32(offset);
- ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val);
- OUTPLL(pScrn, index, val);
- offset += 4;
- break;
- }
- }
-}
-
-Bool
-RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
-
- if (!info->VBIOS) {
- return FALSE;
- } else {
- if (info->IsAtomBios) {
- return FALSE;
- } else {
- if (info->BiosTable.rr1_offset) {
- ErrorF("rr1 restore, 0x%x\n", info->BiosTable.rr1_offset);
- RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr1_offset);
- }
- if (info->BiosTable.revision < 0x09) {
- if (info->BiosTable.pll_offset) {
- ErrorF("pll restore, 0x%x\n", info->BiosTable.pll_offset);
- RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.pll_offset);
- }
- if (info->BiosTable.rr2_offset) {
- ErrorF("rr2 restore, 0x%x\n", info->BiosTable.rr2_offset);
- RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr2_offset);
- }
- if (info->BiosTable.rr4_offset) {
- ErrorF("rr4 restore, 0x%x\n", info->BiosTable.rr4_offset);
- RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr4_offset);
- }
- if (info->BiosTable.mem_reset_offset) {
- ErrorF("mem reset restore, 0x%x\n", info->BiosTable.mem_reset_offset);
- RADEONRestoreBIOSMemBlock(pScrn, info->BiosTable.mem_reset_offset);
- }
- if (info->BiosTable.rr3_offset) {
- ErrorF("rr3 restore, 0x%x\n", info->BiosTable.rr3_offset);
- RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr3_offset);
- }
- if (info->BiosTable.dyn_clk_offset) {
- ErrorF("dyn_clk restore, 0x%x\n", info->BiosTable.dyn_clk_offset);
- RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.dyn_clk_offset);
- }
- }
- }
- }
- return TRUE;
-}
diff --git a/src/radeon_common.h b/src/radeon_common.h
deleted file mode 100644
index 467addf..0000000
--- a/src/radeon_common.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/* radeon_common.h -- common header definitions for Radeon 2D/3D/DRM suite
- *
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Author:
- * Gareth Hughes <gareth at valinux.com>
- * Kevin E. Martin <martin at valinux.com>
- * Keith Whitwell <keith at tungstengraphics.com>
- *
- * Converted to common header format:
- * Jens Owen <jens at tungstengraphics.com>
- *
- */
-
-#ifndef _RADEON_COMMON_H_
-#define _RADEON_COMMON_H_
-
-#include <inttypes.h>
-#include "xf86drm.h"
-
-/* WARNING: If you change any of these defines, make sure to change
- * the kernel include file as well (radeon_drm.h)
- */
-
-/* Driver specific DRM command indices
- * NOTE: these are not OS specific, but they are driver specific
- */
-#define DRM_RADEON_CP_INIT 0x00
-#define DRM_RADEON_CP_START 0x01
-#define DRM_RADEON_CP_STOP 0x02
-#define DRM_RADEON_CP_RESET 0x03
-#define DRM_RADEON_CP_IDLE 0x04
-#define DRM_RADEON_RESET 0x05
-#define DRM_RADEON_FULLSCREEN 0x06
-#define DRM_RADEON_SWAP 0x07
-#define DRM_RADEON_CLEAR 0x08
-#define DRM_RADEON_VERTEX 0x09
-#define DRM_RADEON_INDICES 0x0a
-#define DRM_RADEON_STIPPLE 0x0c
-#define DRM_RADEON_INDIRECT 0x0d
-#define DRM_RADEON_TEXTURE 0x0e
-#define DRM_RADEON_VERTEX2 0x0f
-#define DRM_RADEON_CMDBUF 0x10
-#define DRM_RADEON_GETPARAM 0x11
-#define DRM_RADEON_FLIP 0x12
-#define DRM_RADEON_ALLOC 0x13
-#define DRM_RADEON_FREE 0x14
-#define DRM_RADEON_INIT_HEAP 0x15
-#define DRM_RADEON_IRQ_EMIT 0x16
-#define DRM_RADEON_IRQ_WAIT 0x17
-#define DRM_RADEON_CP_RESUME 0x18
-#define DRM_RADEON_SETPARAM 0x19
-#define DRM_RADEON_SURF_ALLOC 0x1a
-#define DRM_RADEON_SURF_FREE 0x1b
-#define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39
-
-
-#define RADEON_FRONT 0x1
-#define RADEON_BACK 0x2
-#define RADEON_DEPTH 0x4
-#define RADEON_STENCIL 0x8
-
-#define RADEON_CLEAR_X1 0
-#define RADEON_CLEAR_Y1 1
-#define RADEON_CLEAR_X2 2
-#define RADEON_CLEAR_Y2 3
-#define RADEON_CLEAR_DEPTH 4
-
-
-typedef struct {
- enum {
- DRM_RADEON_INIT_CP = 0x01,
- DRM_RADEON_CLEANUP_CP = 0x02,
- DRM_RADEON_INIT_R200_CP = 0x03,
- DRM_RADEON_INIT_R300_CP = 0x04
- } func;
- unsigned long sarea_priv_offset;
- int is_pci;
- int cp_mode;
- int gart_size;
- int ring_size;
- int usec_timeout;
-
- unsigned int fb_bpp;
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_bpp;
- unsigned int depth_offset, depth_pitch;
-
- unsigned long fb_offset;
- unsigned long mmio_offset;
- unsigned long ring_offset;
- unsigned long ring_rptr_offset;
- unsigned long buffers_offset;
- unsigned long gart_textures_offset;
-} drmRadeonInit;
-
-typedef struct {
- int flush;
- int idle;
-} drmRadeonCPStop;
-
-typedef struct {
- int idx;
- int start;
- int end;
- int discard;
-} drmRadeonIndirect;
-
-typedef union drmRadeonClearR {
- float f[5];
- unsigned int ui[5];
-} drmRadeonClearRect;
-
-typedef struct drmRadeonClearT {
- unsigned int flags;
- unsigned int clear_color;
- unsigned int clear_depth;
- unsigned int color_mask;
- unsigned int depth_mask; /* misnamed field: should be stencil */
- drmRadeonClearRect *depth_boxes;
-} drmRadeonClearType;
-
-typedef struct drmRadeonFullscreenT {
- enum {
- RADEON_INIT_FULLSCREEN = 0x01,
- RADEON_CLEANUP_FULLSCREEN = 0x02
- } func;
-} drmRadeonFullscreenType;
-
-typedef struct {
- unsigned int *mask;
-} drmRadeonStipple;
-
-typedef struct {
- unsigned int x;
- unsigned int y;
- unsigned int width;
- unsigned int height;
- const void *data;
-} drmRadeonTexImage;
-
-typedef struct {
- unsigned int offset;
- int pitch;
- int format;
- int width; /* Texture image coordinates */
- int height;
- drmRadeonTexImage *image;
-} drmRadeonTexture;
-
-
-#define RADEON_MAX_TEXTURE_UNITS 3
-
-/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
- */
-typedef struct {
- struct {
- unsigned int pp_misc; /* 0x1c14 */
- unsigned int pp_fog_color;
- unsigned int re_solid_color;
- unsigned int rb3d_blendcntl;
- unsigned int rb3d_depthoffset;
- unsigned int rb3d_depthpitch;
- unsigned int rb3d_zstencilcntl;
- unsigned int pp_cntl; /* 0x1c38 */
- unsigned int rb3d_cntl;
- unsigned int rb3d_coloroffset;
- unsigned int re_width_height;
- unsigned int rb3d_colorpitch;
- } context;
- struct {
- unsigned int se_cntl;
- } setup1;
- struct {
- unsigned int se_coord_fmt; /* 0x1c50 */
- } vertex;
- struct {
- unsigned int re_line_pattern; /* 0x1cd0 */
- unsigned int re_line_state;
- unsigned int se_line_width; /* 0x1db8 */
- } line;
- struct {
- unsigned int pp_lum_matrix; /* 0x1d00 */
- unsigned int pp_rot_matrix_0; /* 0x1d58 */
- unsigned int pp_rot_matrix_1;
- } bumpmap;
- struct {
- unsigned int rb3d_stencilrefmask; /* 0x1d7c */
- unsigned int rb3d_ropcntl;
- unsigned int rb3d_planemask;
- } mask;
- struct {
- unsigned int se_vport_xscale; /* 0x1d98 */
- unsigned int se_vport_xoffset;
- unsigned int se_vport_yscale;
- unsigned int se_vport_yoffset;
- unsigned int se_vport_zscale;
- unsigned int se_vport_zoffset;
- } viewport;
- struct {
- unsigned int se_cntl_status; /* 0x2140 */
- } setup2;
- struct {
- unsigned int re_top_left; /*ignored*/ /* 0x26c0 */
- unsigned int re_misc;
- } misc;
- struct {
- unsigned int pp_txfilter;
- unsigned int pp_txformat;
- unsigned int pp_txoffset;
- unsigned int pp_txcblend;
- unsigned int pp_txablend;
- unsigned int pp_tfactor;
- unsigned int pp_border_color;
- } texture[RADEON_MAX_TEXTURE_UNITS];
- struct {
- unsigned int se_zbias_factor;
- unsigned int se_zbias_constant;
- } zbias;
- unsigned int dirty;
-} drmRadeonState;
-
-/* 1.1 vertex ioctl. Used in compatibility modes.
- */
-typedef struct {
- int prim;
- int idx; /* Index of vertex buffer */
- int count; /* Number of vertices in buffer */
- int discard; /* Client finished with buffer? */
-} drmRadeonVertex;
-
-typedef struct {
- unsigned int start;
- unsigned int finish;
- unsigned int prim:8;
- unsigned int stateidx:8;
- unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
- unsigned int vc_format;
-} drmRadeonPrim;
-
-typedef struct {
- int idx; /* Index of vertex buffer */
- int discard; /* Client finished with buffer? */
- int nr_states;
- drmRadeonState *state;
- int nr_prims;
- drmRadeonPrim *prim;
-} drmRadeonVertex2;
-
-#define RADEON_MAX_STATES 16
-#define RADEON_MAX_PRIMS 64
-
-/* Command buffer. Replace with true dma stream?
- */
-typedef struct {
- int bufsz;
- char *buf;
- int nbox;
- drm_clip_rect_t *boxes;
-} drmRadeonCmdBuffer;
-
-/* New style per-packet identifiers for use in cmd_buffer ioctl with
- * the RADEON_EMIT_PACKET command. Comments relate new packets to old
- * state bits and the packet size:
- */
-#define RADEON_EMIT_PP_MISC 0 /* context/7 */
-#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
-#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
-#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
-#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
-#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
-#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
-#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
-#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
-#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
-#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
-#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
-#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
-#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
-#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
-#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
-#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
-#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
-#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
-#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
-#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
-#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
-#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
-#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
-#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
-#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
-#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/6 */
-#define R200_EMIT_TFACTOR_0 30 /* tf/6 */
-#define R200_EMIT_VTX_FMT_0 31 /* vtx/4 */
-#define R200_EMIT_VAP_CTL 32 /* vap/1 */
-#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
-#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
-#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
-#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
-#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
-#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
-#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
-#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
-#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
-#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
-#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
-#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
-#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
-#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
-#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
-#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
-#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
-#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
-#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
-#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
-#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
-#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
-#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
-#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
-#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
-#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
-#define R200_EMIT_PP_CUBIC_FACES_0 61
-#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
-#define R200_EMIT_PP_CUBIC_FACES_1 63
-#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
-#define R200_EMIT_PP_CUBIC_FACES_2 65
-#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
-#define R200_EMIT_PP_CUBIC_FACES_3 67
-#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
-#define R200_EMIT_PP_CUBIC_FACES_4 69
-#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
-#define R200_EMIT_PP_CUBIC_FACES_5 71
-#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
-#define RADEON_EMIT_PP_TEX_SIZE_0 73
-#define RADEON_EMIT_PP_TEX_SIZE_1 74
-#define RADEON_EMIT_PP_TEX_SIZE_2 75
-#define R200_EMIT_RB3D_BLENDCOLOR 76
-#define RADEON_MAX_STATE_PACKETS 77
-
-
-/* Commands understood by cmd_buffer ioctl. More can be added but
- * obviously these can't be removed or changed:
- */
-#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
-#define RADEON_CMD_SCALARS 2 /* emit scalar data */
-#define RADEON_CMD_VECTORS 3 /* emit vector data */
-#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
-#define RADEON_CMD_PACKET3 5 /* emit hw packet */
-#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
-#define RADEON_CMD_SCALARS2 7 /* R200 stopgap */
-#define RADEON_CMD_WAIT 8 /* synchronization */
-
-typedef union {
- int i;
- struct {
- unsigned char cmd_type, pad0, pad1, pad2;
- } header;
- struct {
- unsigned char cmd_type, packet_id, pad0, pad1;
- } packet;
- struct {
- unsigned char cmd_type, offset, stride, count;
- } scalars;
- struct {
- unsigned char cmd_type, offset, stride, count;
- } vectors;
- struct {
- unsigned char cmd_type, buf_idx, pad0, pad1;
- } dma;
- struct {
- unsigned char cmd_type, flags, pad0, pad1;
- } wait;
-} drmRadeonCmdHeader;
-
-
-#define RADEON_WAIT_2D 0x1
-#define RADEON_WAIT_3D 0x2
-
-
-/* 1.3: An ioctl to get parameters that aren't available to the 3d
- * client any other way.
- */
-#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
-#define RADEON_PARAM_LAST_FRAME 2
-#define RADEON_PARAM_LAST_DISPATCH 3
-#define RADEON_PARAM_LAST_CLEAR 4
-/* Added with DRM version 1.6. */
-#define RADEON_PARAM_IRQ_NR 5
-#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
-/* Added with DRM version 1.8. */
-#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
-#define RADEON_PARAM_STATUS_HANDLE 8
-#define RADEON_PARAM_SAREA_HANDLE 9
-#define RADEON_PARAM_GART_TEX_HANDLE 10
-#define RADEON_PARAM_SCRATCH_OFFSET 11
-#define RADEON_PARAM_CARD_TYPE 12
-#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
-
-typedef struct drm_radeon_getparam {
- int param;
- int *value;
-} drmRadeonGetParam;
-
-
-#define RADEON_MEM_REGION_GART 1
-#define RADEON_MEM_REGION_FB 2
-
-typedef struct drm_radeon_mem_alloc {
- int region;
- int alignment;
- int size;
- int *region_offset; /* offset from start of fb or GART */
-} drmRadeonMemAlloc;
-
-typedef struct drm_radeon_mem_free {
- int region;
- int region_offset;
-} drmRadeonMemFree;
-
-typedef struct drm_radeon_mem_init_heap {
- int region;
- int size;
- int start;
-} drmRadeonMemInitHeap;
-
-/* 1.6: Userspace can request & wait on irq's:
- */
-typedef struct drm_radeon_irq_emit {
- int *irq_seq;
-} drmRadeonIrqEmit;
-
-typedef struct drm_radeon_irq_wait {
- int irq_seq;
-} drmRadeonIrqWait;
-
-
-/* 1.10: Clients tell the DRM where they think the framebuffer is located in
- * the card's address space, via a new generic ioctl to set parameters
- */
-
-typedef struct drm_radeon_set_param {
- unsigned int param;
- int64_t value;
-} drmRadeonSetParam;
-
-#define RADEON_SETPARAM_FB_LOCATION 1
-#define RADEON_SETPARAM_SWITCH_TILING 2
-#define RADEON_SETPARAM_PCIGART_LOCATION 3
-#define RADEON_SETPARAM_NEW_MEMMAP 4
-#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
-#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
-/* 1.14: Clients can allocate/free a surface
- */
-typedef struct drm_radeon_surface_alloc {
- unsigned int address;
- unsigned int size;
- unsigned int flags;
-} drmRadeonSurfaceAlloc;
-
-typedef struct drm_radeon_surface_free {
- unsigned int address;
-} drmRadeonSurfaceFree;
-
-#define DRM_RADEON_VBLANK_CRTC1 1
-#define DRM_RADEON_VBLANK_CRTC2 2
-
-#endif
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
deleted file mode 100644
index 0250aef..0000000
--- a/src/radeon_commonfuncs.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "ati_pciids_gen.h"
-
-#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
-#error Cannot define both MMIO and CP acceleration!
-#endif
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#ifdef ACCEL_MMIO
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
-#else
-#ifdef ACCEL_CP
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-#else
-#error No accel type defined!
-#endif
-#endif
-
-static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 gb_tile_config;
- ACCEL_PREAMBLE();
-
- info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
- FINISH_ACCEL();
-
- gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
-
- if ((info->Chipset == PCI_CHIP_RV410_5E4C) ||
- (info->Chipset == PCI_CHIP_RV410_5E4F)) {
- /* RV410 SE chips */
- gb_tile_config |= R300_PIPE_COUNT_RV350;
- } else if ((info->ChipFamily == CHIP_FAMILY_RV350) ||
- (info->ChipFamily == CHIP_FAMILY_RV380) ||
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
- /* RV3xx, RS4xx chips */
- gb_tile_config |= R300_PIPE_COUNT_RV350;
- } else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- (info->ChipFamily == CHIP_FAMILY_R350)) {
- /* R3xx chips */
- gb_tile_config |= R300_PIPE_COUNT_R300;
- } else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
- (info->ChipFamily == CHIP_FAMILY_RS690)) {
- /* RV4xx, RS6xx chips */
- gb_tile_config |= R300_PIPE_COUNT_R420_3P;
- } else {
- /* R4xx, R5xx chips */
- gb_tile_config |= R300_PIPE_COUNT_R420;
- }
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
- OUT_ACCEL_REG(R300_GB_SELECT, 0);
- OUT_ACCEL_REG(R300_GB_ENABLE, 0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
- (8 << R300_MS_Y0_SHIFT) |
- (8 << R300_MS_X1_SHIFT) |
- (8 << R300_MS_Y1_SHIFT) |
- (8 << R300_MS_X2_SHIFT) |
- (8 << R300_MS_Y2_SHIFT) |
- (8 << R300_MSBD0_Y_SHIFT) |
- (7 << R300_MSBD0_X_SHIFT)));
- OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
- (8 << R300_MS_Y3_SHIFT) |
- (8 << R300_MS_X4_SHIFT) |
- (8 << R300_MS_Y4_SHIFT) |
- (8 << R300_MS_X5_SHIFT) |
- (8 << R300_MS_Y5_SHIFT) |
- (8 << R300_MSBD1_SHIFT)));
- FINISH_ACCEL();
-
- BEGIN_ACCEL(4);
- OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
- OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
- R300_COLOR_ROUND_NEAREST));
- OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
- R300_ALPHA0_SHADING_GOURAUD |
- R300_RGB1_SHADING_GOURAUD |
- R300_ALPHA1_SHADING_GOURAUD |
- R300_RGB2_SHADING_GOURAUD |
- R300_ALPHA2_SHADING_GOURAUD |
- R300_RGB3_SHADING_GOURAUD |
- R300_ALPHA3_SHADING_GOURAUD));
- OUT_ACCEL_REG(R300_GA_OFFSET, 0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0);
- OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
- OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
- OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
- OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(R300_US_W_FMT, 0);
- OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- OUT_ACCEL_REG(R300_US_OUT_FMT_0, (R300_OUT_FMT_C4_10 |
- R300_OUT_FMT_C0_SEL_BLUE |
- R300_OUT_FMT_C1_SEL_GREEN |
- R300_OUT_FMT_C2_SEL_RED |
- R300_OUT_FMT_C3_SEL_ALPHA));
- FINISH_ACCEL();
-
-
- BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0);
- OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0);
- OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(12);
- OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0);
- OUT_ACCEL_REG(R300_RB3D_ZTOP, 0);
- OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0);
-
- OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0);
- OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
- R300_GREEN_MASK_EN |
- R300_RED_MASK_EN |
- R300_ALPHA_MASK_EN));
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(R300_RB3D_CCTL, 0);
- OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- FINISH_ACCEL();
-
- BEGIN_ACCEL(7);
- OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
- OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
- (0 << R300_SCISSOR_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
- (8191 << R300_SCISSOR_Y_SHIFT)));
-
- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) {
- /* clip has offset 1440 */
- OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
- (1088 << R300_CLIP_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2048) << R300_CLIP_X_SHIFT) |
- ((1080 + 2048) << R300_CLIP_Y_SHIFT)));
- } else {
- OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
- (0 << R300_CLIP_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
- (4080 << R300_CLIP_Y_SHIFT)));
- }
- OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
- OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
- FINISH_ACCEL();
- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_R200)) {
-
- BEGIN_ACCEL(7);
- if (info->ChipFamily == CHIP_FAMILY_RS300) {
- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
- } else {
- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
- }
- OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
- OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
- OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
- OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
- OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
- OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
- R200_VAP_VF_MAX_VTX_NUM);
- FINISH_ACCEL();
- } else {
- BEGIN_ACCEL(2);
- if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
- (info->ChipFamily == CHIP_FAMILY_RV200))
- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
- else
- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
- OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
- RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
- RADEON_VTX_ST0_NONPARAMETRIC |
- RADEON_VTX_ST1_NONPARAMETRIC |
- RADEON_TEX1_W_ROUTING_USE_W0);
- FINISH_ACCEL();
- }
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
- OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
- OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
- OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
- OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
- RADEON_BFACE_SOLID |
- RADEON_FFACE_SOLID |
- RADEON_VTX_PIX_CENTER_OGL |
- RADEON_ROUND_MODE_ROUND |
- RADEON_ROUND_PREC_4TH_PIX));
- FINISH_ACCEL();
-}
-
-
-/* MMIO:
- *
- * Wait for the graphics engine to be completely idle: the FIFO has
- * drained, the Pixel Cache is flushed, and the engine is idle. This is
- * a standard "sync" function that will make the hardware "quiescent".
- *
- * CP:
- *
- * Wait until the CP is completely idle: the FIFO has drained and the CP
- * is idle.
- */
-void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int i = 0;
-
-#ifdef ACCEL_CP
- /* Make sure the CP is idle first */
- if (info->CPStarted) {
- int ret;
-
- FLUSH_RING();
-
- for (;;) {
- do {
- ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE);
- if (ret && ret != -EBUSY) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: CP idle %d\n", __FUNCTION__, ret);
- }
- } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT));
-
- if (ret == 0) return;
-
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Idle timed out, resetting engine...\n");
- RADEONEngineReset(pScrn);
- RADEONEngineRestore(pScrn);
-
- /* Always restart the engine when doing CP 2D acceleration */
- RADEONCP_RESET(pScrn, info);
- RADEONCP_START(pScrn, info);
- }
- }
-#endif
-
-#if 0
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "WaitForIdle (entering): %d entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
-#endif
-
- /* Wait for the engine to go idle */
- RADEONWaitForFifoFunction(pScrn, 64);
-
- for (;;) {
- for (i = 0; i < RADEON_TIMEOUT; i++) {
- if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) {
- RADEONEngineFlush(pScrn);
- return;
- }
- }
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Idle timed out: %u entries, stat=0x%08x\n",
- (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- (unsigned int)INREG(RADEON_RBBM_STATUS));
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Idle timed out, resetting engine...\n");
- RADEONEngineReset(pScrn);
- RADEONEngineRestore(pScrn);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_RESET(pScrn, info);
- RADEONCP_START(pScrn, info);
- }
-#endif
- }
-}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
deleted file mode 100644
index 3524b75..0000000
--- a/src/radeon_crtc.c
+++ /dev/null
@@ -1,721 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include <stdio.h>
-
-/* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "vgaHW.h"
-#include "xf86Modes.h"
-
-/* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
-#include "sarea.h"
-#endif
-
-extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode,
- int x, int y);
-extern void legacy_crtc_mode_set(xf86CrtcPtr crtc,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode,
- int x, int y);
-extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
-extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
-
-static void
-radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
-{
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0];
-
- if (IS_AVIVO_VARIANT) {
- atombios_crtc_dpms(crtc, mode);
- } else {
-
- /* need to restore crtc1 before crtc0 or we may get a blank screen
- * in some cases
- */
- if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) {
- if (crtc0->enabled)
- legacy_crtc_dpms(crtc0, DPMSModeOff);
- }
-
- legacy_crtc_dpms(crtc, mode);
-
- if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) {
- if (crtc0->enabled)
- legacy_crtc_dpms(crtc0, mode);
- }
- }
-}
-
-static Bool
-radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- return TRUE;
-}
-
-static void
-radeon_crtc_mode_prepare(xf86CrtcPtr crtc)
-{
- radeon_crtc_dpms(crtc, DPMSModeOff);
-}
-
-static CARD32 RADEONDiv(CARD64 n, CARD32 d)
-{
- return (n + (d / 2)) / d;
-}
-
-void
-RADEONComputePLL(RADEONPLLPtr pll,
- unsigned long freq,
- CARD32 *chosen_dot_clock_freq,
- CARD32 *chosen_feedback_div,
- CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div,
- int flags)
-{
- CARD32 min_ref_div = pll->min_ref_div;
- CARD32 max_ref_div = pll->max_ref_div;
- CARD32 best_vco = pll->best_vco;
- CARD32 best_post_div = 1;
- CARD32 best_ref_div = 1;
- CARD32 best_feedback_div = 1;
- CARD32 best_freq = 1;
- CARD32 best_error = 0xffffffff;
- CARD32 best_vco_diff = 1;
- CARD32 post_div;
-
- freq = freq * 1000;
-
- ErrorF("freq: %lu\n", freq);
-
- if (flags & RADEON_PLL_USE_REF_DIV)
- min_ref_div = max_ref_div = pll->reference_div;
-
- for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
- CARD32 ref_div;
- CARD32 vco = (freq / 10000) * post_div;
-
- if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
- continue;
-
- /* legacy radeons only have a few post_divs */
- if (flags & RADEON_PLL_LEGACY) {
- if ((post_div == 5) ||
- (post_div == 7) ||
- (post_div == 9) ||
- (post_div == 10) ||
- (post_div == 11))
- continue;
- }
-
- if (vco < pll->pll_out_min || vco > pll->pll_out_max)
- continue;
-
- for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
- CARD32 feedback_div, current_freq, error, vco_diff;
- CARD32 pll_in = pll->reference_freq / ref_div;
-
- if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
- continue;
-
- feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div,
- pll->reference_freq * 10000);
-
- if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
- continue;
-
- current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div,
- ref_div * post_div);
-
- error = abs(current_freq - freq);
- vco_diff = abs(vco - best_vco);
-
- if ((best_vco == 0 && error < best_error) ||
- (ref_div == pll->reference_div) ||
- (best_vco != 0 &&
- (error < best_error - 100 ||
- (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
- best_post_div = post_div;
- best_ref_div = ref_div;
- best_feedback_div = feedback_div;
- best_freq = current_freq;
- best_error = error;
- best_vco_diff = vco_diff;
- }
- }
- if (best_freq == freq)
- break;
- }
-
- ErrorF("best_freq: %u\n", (unsigned int)best_freq);
- ErrorF("best_feedback_div: %u\n", (unsigned int)best_feedback_div);
- ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div);
- ErrorF("best_post_div: %u\n", (unsigned int)best_post_div);
-
- *chosen_dot_clock_freq = best_freq / 10000;
- *chosen_feedback_div = best_feedback_div;
- *chosen_reference_div = best_ref_div;
- *chosen_post_div = best_post_div;
-
-}
-
-static void
-radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
- DisplayModePtr adjusted_mode, int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (IS_AVIVO_VARIANT) {
- atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
- } else {
- legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
- }
-}
-
-static void
-radeon_crtc_mode_commit(xf86CrtcPtr crtc)
-{
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- xf86CrtcPtr other;
- if (radeon_crtc->crtc_id == 1)
- other = pRADEONEnt->pCrtc[0];
- else
- other = pRADEONEnt->pCrtc[1];
- if (other->enabled)
- radeon_crtc_dpms(other, DPMSModeOn);
- }
-
- radeon_crtc_dpms(crtc, DPMSModeOn);
-}
-
-void
-radeon_crtc_load_lut(xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int i;
-
- if (!crtc->enabled)
- return;
-
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
-
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
-
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff);
- OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff);
- }
-
- PAL_SELECT(radeon_crtc->crtc_id);
-
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_DC_LUT_RW_MODE, 0);
- OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
- }
-
- for (i = 0; i < 256; i++) {
- OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]);
- }
-
-}
-
-
-static void
-radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green,
- CARD16 *blue, int size)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- ScrnInfoPtr pScrn = crtc->scrn;
- int i, j;
-
- if (pScrn->depth == 16) {
- for (i = 0; i < 64; i++) {
- if (i <= 31) {
- for (j = 0; j < 8; j++) {
- radeon_crtc->lut_r[i * 8 + j] = red[i] >> 8;
- radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 8;
- }
- }
-
- for (j = 0; j < 4; j++) {
- radeon_crtc->lut_g[i * 4 + j] = green[i] >> 8;
- }
- }
- } else {
- for (i = 0; i < 256; i++) {
- radeon_crtc->lut_r[i] = red[i] >> 8;
- radeon_crtc->lut_g[i] = green[i] >> 8;
- radeon_crtc->lut_b[i] = blue[i] >> 8;
- }
- }
-
- radeon_crtc_load_lut(crtc);
-}
-
-static Bool
-radeon_crtc_lock(xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) {
- DRILock(pScrn->pScreen, 0);
- if (info->accelOn)
- RADEON_SYNC(info, pScrn);
- return TRUE;
- }
-#endif
- if (info->accelOn)
- RADEON_SYNC(info, pScrn);
-
- return FALSE;
-
-}
-
-static void
-radeon_crtc_unlock(xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
-#endif
-
- if (info->accelOn)
- RADEON_SYNC(info, pScrn);
-}
-
-#ifdef USE_XAA
-/**
- * Allocates memory from the XF86 linear allocator, but also purges
- * memory if possible to cause the allocation to succeed.
- */
-static FBLinearPtr
-radeon_xf86AllocateOffscreenLinear(ScreenPtr pScreen, int length,
- int granularity,
- MoveLinearCallbackProcPtr moveCB,
- RemoveLinearCallbackProcPtr removeCB,
- pointer privData)
-{
- FBLinearPtr linear;
- int max_size;
-
- linear = xf86AllocateOffscreenLinear(pScreen, length, granularity, moveCB,
- removeCB, privData);
- if (linear != NULL)
- return linear;
-
- /* The above allocation didn't succeed, so purge unlocked stuff and try
- * again.
- */
- xf86QueryLargestOffscreenLinear(pScreen, &max_size, granularity,
- PRIORITY_EXTREME);
-
- if (max_size < length)
- return NULL;
-
- xf86PurgeUnlockedOffscreenAreas(pScreen);
-
- linear = xf86AllocateOffscreenLinear(pScreen, length, granularity, moveCB,
- removeCB, privData);
-
- return linear;
-}
-#endif
-
-/**
- * Allocates memory for a locked-in-framebuffer shadow of the given
- * width and height for this CRTC's rotated shadow framebuffer.
- */
-
-static void *
-radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
- ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- unsigned long rotate_pitch;
- unsigned long rotate_offset;
- int align = 4096, size;
- int cpp = pScrn->bitsPerPixel / 8;
-
- rotate_pitch = pScrn->displayWidth * cpp;
- size = rotate_pitch * height;
-
-#ifdef USE_EXA
- /* We could get close to what we want here by just creating a pixmap like
- * normal, but we have to lock it down in framebuffer, and there is no
- * setter for offscreen area locking in EXA currently. So, we just
- * allocate offscreen memory and fake up a pixmap header for it.
- */
- if (info->useEXA) {
- assert(radeon_crtc->rotate_mem_exa == NULL);
-
- radeon_crtc->rotate_mem_exa = exaOffscreenAlloc(pScreen, size, align,
- TRUE, NULL, NULL);
- if (radeon_crtc->rotate_mem_exa == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't allocate shadow memory for rotated CRTC\n");
- return NULL;
- }
- rotate_offset = radeon_crtc->rotate_mem_exa->offset;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- /* The XFree86 linear allocator operates in units of screen pixels,
- * sadly.
- */
- size = (size + cpp - 1) / cpp;
- align = (align + cpp - 1) / cpp;
-
- assert(radeon_crtc->rotate_mem_xaa == NULL);
-
- radeon_crtc->rotate_mem_xaa =
- radeon_xf86AllocateOffscreenLinear(pScreen, size, align,
- NULL, NULL, NULL);
- if (radeon_crtc->rotate_mem_xaa == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't allocate shadow memory for rotated CRTC\n");
- return NULL;
- }
-#ifdef XF86DRI
- rotate_offset = info->frontOffset +
- radeon_crtc->rotate_mem_xaa->offset * cpp;
-#endif
- }
-#endif /* USE_XAA */
-
- return info->FB + rotate_offset;
-}
-
-/**
- * Creates a pixmap for this CRTC's rotated shadow framebuffer.
- */
-static PixmapPtr
-radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- unsigned long rotate_pitch;
- PixmapPtr rotate_pixmap;
- int cpp = pScrn->bitsPerPixel / 8;
-
- if (!data)
- data = radeon_crtc_shadow_allocate(crtc, width, height);
-
- rotate_pitch = pScrn->displayWidth * cpp;
-
- rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
- width, height,
- pScrn->depth,
- pScrn->bitsPerPixel,
- rotate_pitch,
- data);
-
- if (rotate_pixmap == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Couldn't allocate shadow pixmap for rotated CRTC\n");
- }
-
- return rotate_pixmap;
-}
-
-static void
-radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- if (rotate_pixmap)
- FreeScratchPixmapHeader(rotate_pixmap);
-
- if (data) {
-#ifdef USE_EXA
- if (info->useEXA && radeon_crtc->rotate_mem_exa != NULL) {
- exaOffscreenFree(pScrn->pScreen, radeon_crtc->rotate_mem_exa);
- radeon_crtc->rotate_mem_exa = NULL;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- xf86FreeOffscreenLinear(radeon_crtc->rotate_mem_xaa);
- radeon_crtc->rotate_mem_xaa = NULL;
- }
-#endif /* USE_XAA */
- }
-}
-
-static const xf86CrtcFuncsRec radeon_crtc_funcs = {
- .dpms = radeon_crtc_dpms,
- .save = NULL, /* XXX */
- .restore = NULL, /* XXX */
- .mode_fixup = radeon_crtc_mode_fixup,
- .prepare = radeon_crtc_mode_prepare,
- .mode_set = radeon_crtc_mode_set,
- .commit = radeon_crtc_mode_commit,
- .gamma_set = radeon_crtc_gamma_set,
- .lock = radeon_crtc_lock,
- .unlock = radeon_crtc_unlock,
- .shadow_create = radeon_crtc_shadow_create,
- .shadow_allocate = radeon_crtc_shadow_allocate,
- .shadow_destroy = radeon_crtc_shadow_destroy,
- .set_cursor_colors = radeon_crtc_set_cursor_colors,
- .set_cursor_position = radeon_crtc_set_cursor_position,
- .show_cursor = radeon_crtc_show_cursor,
- .hide_cursor = radeon_crtc_hide_cursor,
- .load_cursor_argb = radeon_crtc_load_cursor_argb,
- .destroy = NULL, /* XXX */
-};
-
-Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
-{
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-
- if (mask & 1) {
- if (pRADEONEnt->Controller[0])
- return TRUE;
-
- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[0])
- return FALSE;
-
- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[0])
- return FALSE;
-
- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0];
- pRADEONEnt->Controller[0]->crtc_id = 0;
- pRADEONEnt->Controller[0]->crtc_offset = 0;
- }
-
- if (mask & 2) {
- if (!pRADEONEnt->HasCRTC2)
- return TRUE;
-
- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs);
- if (!pRADEONEnt->pCrtc[1])
- return FALSE;
-
- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1);
- if (!pRADEONEnt->Controller[1])
- {
- xfree(pRADEONEnt->Controller[0]);
- return FALSE;
- }
-
- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1];
- pRADEONEnt->Controller[1]->crtc_id = 1;
- pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
- }
-
- return TRUE;
-}
-
-/**
- * In the current world order, there are lists of modes per output, which may
- * or may not include the mode that was asked to be set by XFree86's mode
- * selection. Find the closest one, in the following preference order:
- *
- * - Equality
- * - Closer in size to the requested mode, but no larger
- * - Closer in refresh rate to the requested mode.
- */
-DisplayModePtr
-RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- DisplayModePtr pBest = NULL, pScan = NULL;
- int i;
-
- /* Assume that there's only one output connected to the given CRTC. */
- for (i = 0; i < xf86_config->num_output; i++)
- {
- xf86OutputPtr output = xf86_config->output[i];
- if (output->crtc == crtc && output->probed_modes != NULL)
- {
- pScan = output->probed_modes;
- break;
- }
- }
-
- /* If the pipe doesn't have any detected modes, just let the system try to
- * spam the desired mode in.
- */
- if (pScan == NULL) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No crtc mode list for crtc %d,"
- "continuing with desired mode\n", radeon_crtc->crtc_id);
- return pMode;
- }
-
- for (; pScan != NULL; pScan = pScan->next) {
- assert(pScan->VRefresh != 0.0);
-
- /* If there's an exact match, we're done. */
- if (xf86ModesEqual(pScan, pMode)) {
- pBest = pMode;
- break;
- }
-
- /* Reject if it's larger than the desired mode. */
- if (pScan->HDisplay > pMode->HDisplay ||
- pScan->VDisplay > pMode->VDisplay)
- {
- continue;
- }
-
- if (pBest == NULL) {
- pBest = pScan;
- continue;
- }
-
- /* Find if it's closer to the right size than the current best
- * option.
- */
- if ((pScan->HDisplay > pBest->HDisplay &&
- pScan->VDisplay >= pBest->VDisplay) ||
- (pScan->HDisplay >= pBest->HDisplay &&
- pScan->VDisplay > pBest->VDisplay))
- {
- pBest = pScan;
- continue;
- }
-
- /* Find if it's still closer to the right refresh than the current
- * best resolution.
- */
- if (pScan->HDisplay == pBest->HDisplay &&
- pScan->VDisplay == pBest->VDisplay &&
- (fabs(pScan->VRefresh - pMode->VRefresh) <
- fabs(pBest->VRefresh - pMode->VRefresh))) {
- pBest = pScan;
- }
- }
-
- if (pBest == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No suitable mode found to program for the pipe.\n"
- " continuing with desired mode %dx%d@%.1f\n",
- pMode->HDisplay, pMode->VDisplay, pMode->VRefresh);
- } else if (!xf86ModesEqual(pBest, pMode)) {
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- int crtc = radeon_crtc->crtc_id;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Choosing pipe %d's mode %dx%d@%.1f instead of xf86 "
- "mode %dx%d@%.1f\n", crtc,
- pBest->HDisplay, pBest->VDisplay, pBest->VRefresh,
- pMode->HDisplay, pMode->VDisplay, pMode->VRefresh);
- pMode = pBest;
- }
- return pMode;
-}
-
-void
-RADEONBlank(ScrnInfoPtr pScrn)
-{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- xf86OutputPtr output;
- xf86CrtcPtr crtc;
- int o, c;
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- crtc = xf86_config->crtc[c];
- for (o = 0; o < xf86_config->num_output; o++) {
- output = xf86_config->output[o];
- if (output->crtc != crtc)
- continue;
-
- output->funcs->dpms(output, DPMSModeOff);
- }
- crtc->funcs->dpms(crtc, DPMSModeOff);
- }
-}
-
-void
-RADEONUnblank(ScrnInfoPtr pScrn)
-{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- xf86OutputPtr output;
- xf86CrtcPtr crtc;
- int o, c;
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- crtc = xf86_config->crtc[c];
- if(!crtc->enabled)
- continue;
- crtc->funcs->dpms(crtc, DPMSModeOn);
- for (o = 0; o < xf86_config->num_output; o++) {
- output = xf86_config->output[o];
- if (output->crtc != crtc)
- continue;
-
- output->funcs->dpms(output, DPMSModeOn);
- }
- }
-}
-
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
deleted file mode 100644
index 0f7e668..0000000
--- a/src/radeon_cursor.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#define RADEONCTRACE(x)
-/*#define RADEONCTRACE(x) RADEONTRACE(x) */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
-
- /* Driver data structures */
-#include "radeon.h"
-#include "radeon_version.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-
-#define CURSOR_WIDTH 64
-#define CURSOR_HEIGHT 64
-
-/*
- * The cursor bits are always 32bpp. On MSBFirst buses,
- * configure byte swapping to swap 32 bit units when writing
- * the cursor image. Byte swapping must always be returned
- * to its previous value before returning.
- */
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-
-#define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO;
-#define CURSOR_SWAPPING_START() \
- do { \
- OUTREG(RADEON_SURFACE_CNTL, \
- (info->ModeReg->surface_cntl | \
- RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
- ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \
- } while (0)
-#define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \
- info->ModeReg->surface_cntl))
-
-#else
-
-#define CURSOR_SWAPPING_DECL_MMIO
-#define CURSOR_SWAPPING_START()
-#define CURSOR_SWAPPING_END()
-
-#endif
-
-static void
-avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
-{
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(crtc->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 0);
-
- if (enable) {
- OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
- info->fbLocation + radeon_crtc->cursor_offset);
- OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
- ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1));
- OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
- AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
- }
-}
-
-void
-radeon_crtc_show_cursor (xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- int crtc_id = radeon_crtc->crtc_id;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
- INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
- | AVIVO_D1CURSOR_EN);
- avivo_setup_cursor(crtc, TRUE);
- } else {
- switch (crtc_id) {
- case 0:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
- break;
- case 1:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
- break;
- default:
- return;
- }
-
- OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
- ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
- }
-}
-
-void
-radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- int crtc_id = radeon_crtc->crtc_id;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_D1CUR_CONTROL+ radeon_crtc->crtc_offset,
- INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
- & ~(AVIVO_D1CURSOR_EN));
- avivo_setup_cursor(crtc, FALSE);
- } else {
- switch(crtc_id) {
- case 0:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
- break;
- case 1:
- OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
- break;
- default:
- return;
- }
-
- OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
- }
-}
-
-void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- int crtc_id = radeon_crtc->crtc_id;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int xorigin = 0, yorigin = 0;
- int stride = 256;
- DisplayModePtr mode = &crtc->mode;
-
- if (x < 0) xorigin = -x+1;
- if (y < 0) yorigin = -y+1;
- if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1;
- if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
-
- if (mode->Flags & V_INTERLACE)
- y /= 2;
- else if (mode->Flags & V_DBLSCAN)
- y *= 2;
-
- if (IS_AVIVO_VARIANT) {
- /* avivo cursor spans the full fb width */
- x += crtc->x;
- y += crtc->y;
- OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y));
- OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
- } else {
- if (crtc_id == 0) {
- OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
- OUTREG(RADEON_CUR_OFFSET,
- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
- } else if (crtc_id == 1) {
- OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
- | (xorigin << 16)
- | yorigin));
- OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
- | ((xorigin ? 0 : x) << 16)
- | (yorigin ? 0 : y)));
- RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
- OUTREG(RADEON_CUR2_OFFSET,
- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
- }
- }
-}
-
-void
-radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset);
- int pixel, i;
- CURSOR_SWAPPING_DECL_MMIO
-
- RADEONCTRACE(("RADEONSetCursorColors\n"));
-
-#ifdef ARGB_CURSOR
- /* Don't recolour cursors set with SetCursorARGB. */
- if (info->cursor_argb)
- return;
-#endif
-
- fg |= 0xff000000;
- bg |= 0xff000000;
-
- /* Don't recolour the image if we don't have to. */
- if (fg == info->cursor_fg && bg == info->cursor_bg)
- return;
-
- CURSOR_SWAPPING_START();
-
- /* Note: We assume that the pixels are either fully opaque or fully
- * transparent, so we won't premultiply them, and we can just
- * check for non-zero pixel values; those are either fg or bg
- */
- for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
- if ((pixel = *pixels))
- *pixels = (pixel == info->cursor_fg) ? fg : bg;
-
- CURSOR_SWAPPING_END();
- info->cursor_fg = fg;
- info->cursor_bg = bg;
-}
-
-#ifdef ARGB_CURSOR
-
-void
-radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
-{
- ScrnInfoPtr pScrn = crtc->scrn;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CURSOR_SWAPPING_DECL_MMIO
- CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset);
-
- RADEONCTRACE(("RADEONLoadCursorARGB\n"));
-
- info->cursor_argb = TRUE;
-
- CURSOR_SWAPPING_START();
-
- memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4);
-
- CURSOR_SWAPPING_END ();
-}
-
-#endif
-
-
-/* Initialize hardware cursor support. */
-Bool RADEONCursorInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int width;
- int width_bytes;
- int height;
- int size_bytes;
- CARD32 cursor_offset = 0;
- int c;
-
- size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
- width = pScrn->displayWidth;
- width_bytes = width * (pScrn->bitsPerPixel / 8);
- height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes;
-
-#ifdef USE_XAA
- if (!info->useEXA) {
- int align = IS_AVIVO_VARIANT ? 4096 : 256;
- FBAreaPtr fbarea;
-
- fbarea = xf86AllocateOffscreenArea(pScreen, width, height,
- align, NULL, NULL, NULL);
-
- if (!fbarea) {
- cursor_offset = 0;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Hardware cursor disabled"
- " due to insufficient offscreen memory\n");
- return FALSE;
- } else {
- cursor_offset = RADEON_ALIGN((fbarea->box.x1 +
- fbarea->box.y1 * width) *
- info->CurrentLayout.pixel_bytes,
- align);
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- radeon_crtc->cursor_offset = cursor_offset + (c * size_bytes);
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor %d (scanline %u)\n", c,
- (unsigned)(radeon_crtc->cursor_offset / pScrn->displayWidth
- / info->CurrentLayout.pixel_bytes));
- }
-
- }
- }
-#endif
-
- return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
- (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* this is a lie --
- * HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
- * actually inverts the bit order, so
- * this switches to LSBFIRST
- */
- HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
-#endif
- HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
- HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
- HARDWARE_CURSOR_ARGB));
-}
diff --git a/src/radeon_dga.c b/src/radeon_dga.c
deleted file mode 100644
index ab5d278..0000000
--- a/src/radeon_dga.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- *
- * Credits:
- *
- * Thanks to Ove KÃ¥ven <ovek at transgaming.com> for writing the Rage 128
- * DGA support. Portions of this file are based on the initialization
- * code for that driver.
- *
- */
-
-#include <string.h>
-
- /* Driver data structures */
-#include "radeon.h"
-#include "radeon_probe.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-
- /* DGA support */
-#include "dgaproc.h"
-
-
-static Bool RADEON_OpenFramebuffer(ScrnInfoPtr, char **, unsigned char **,
- int *, int *, int *);
-static Bool RADEON_SetMode(ScrnInfoPtr, DGAModePtr);
-static int RADEON_GetViewport(ScrnInfoPtr);
-static void RADEON_SetViewport(ScrnInfoPtr, int, int, int);
-#ifdef USE_XAA
-static void RADEON_FillRect(ScrnInfoPtr, int, int, int, int, unsigned long);
-static void RADEON_BlitRect(ScrnInfoPtr, int, int, int, int, int, int);
-static void RADEON_BlitTransRect(ScrnInfoPtr, int, int, int, int, int, int,
- unsigned long);
-#endif
-
-static DGAModePtr RADEONSetupDGAMode(ScrnInfoPtr pScrn,
- DGAModePtr modes,
- int *num,
- int bitsPerPixel,
- int depth,
- Bool pixmap,
- int secondPitch,
- unsigned long red,
- unsigned long green,
- unsigned long blue,
- short visualClass)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- DGAModePtr newmodes = NULL;
- DGAModePtr currentMode;
- DisplayModePtr pMode;
- DisplayModePtr firstMode;
- unsigned int size;
- int pitch;
- int Bpp = bitsPerPixel >> 3;
-
-SECOND_PASS:
-
- pMode = firstMode = pScrn->modes;
-
- while (1) {
- pitch = pScrn->displayWidth;
- size = pitch * Bpp * pMode->VDisplay;
-
- if ((!secondPitch || (pitch != secondPitch)) &&
- (size <= info->FbMapSize)) {
-
- if (secondPitch)
- pitch = secondPitch;
-
- if (!(newmodes = xrealloc(modes, (*num + 1) * sizeof(DGAModeRec))))
- break;
-
- modes = newmodes;
- currentMode = modes + *num;
-
- currentMode->mode = pMode;
- currentMode->flags = DGA_CONCURRENT_ACCESS;
-
- if (pixmap)
- currentMode->flags |= DGA_PIXMAP_AVAILABLE;
-
-#ifdef USE_EXA
- if (info->useEXA) {
- /* We need to fill in RADEON_FillRect and RADEON_BlitRect and
- * connect them in RADEONDGAInit before turning these on.
- */
- /*if (info->exa.accel.PrepareSolid && info->exa.accel.Solid)
- currentMode->flags |= DGA_FILL_RECT;
- if (info->exa.accel.PrepareCopy && info->exa.accel.Copy)
- currentMode->flags |= DGA_BLIT_RECT | DGA_BLIT_RECT_TRANS;*/
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA && info->accel) {
- if (info->accel->SetupForSolidFill &&
- info->accel->SubsequentSolidFillRect)
- currentMode->flags |= DGA_FILL_RECT;
- if (info->accel->SetupForScreenToScreenCopy &&
- info->accel->SubsequentScreenToScreenCopy)
- currentMode->flags |= DGA_BLIT_RECT | DGA_BLIT_RECT_TRANS;
- if (currentMode->flags &
- (DGA_PIXMAP_AVAILABLE | DGA_FILL_RECT |
- DGA_BLIT_RECT | DGA_BLIT_RECT_TRANS))
- currentMode->flags &= ~DGA_CONCURRENT_ACCESS;
- }
-#endif /* USE_XAA */
-
- if (pMode->Flags & V_DBLSCAN)
- currentMode->flags |= DGA_DOUBLESCAN;
- if (pMode->Flags & V_INTERLACE)
- currentMode->flags |= DGA_INTERLACED;
-
- currentMode->byteOrder = pScrn->imageByteOrder;
- currentMode->depth = depth;
- currentMode->bitsPerPixel = bitsPerPixel;
- currentMode->red_mask = red;
- currentMode->green_mask = green;
- currentMode->blue_mask = blue;
- currentMode->visualClass = visualClass;
- currentMode->viewportWidth = pMode->HDisplay;
- currentMode->viewportHeight = pMode->VDisplay;
- currentMode->xViewportStep = 8;
- currentMode->yViewportStep = 1;
- currentMode->viewportFlags = DGA_FLIP_RETRACE;
- currentMode->offset = 0;
- currentMode->address = (unsigned char*)info->LinearAddr;
- currentMode->bytesPerScanline = pitch * Bpp;
- currentMode->imageWidth = pitch;
- currentMode->imageHeight = (info->FbMapSize
- / currentMode->bytesPerScanline);
- currentMode->pixmapWidth = currentMode->imageWidth;
- currentMode->pixmapHeight = currentMode->imageHeight;
- currentMode->maxViewportX = (currentMode->imageWidth
- - currentMode->viewportWidth);
- /* this might need to get clamped to some maximum */
- currentMode->maxViewportY = (currentMode->imageHeight
- - currentMode->viewportHeight);
- (*num)++;
- }
-
- pMode = pMode->next;
- if (pMode == firstMode)
- break;
- }
-
- if (secondPitch) {
- secondPitch = 0;
- goto SECOND_PASS;
- }
-
- return modes;
-}
-
-Bool RADEONDGAInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- DGAModePtr modes = NULL;
- int num = 0;
-
- /* 8 */
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 8, 8,
- (pScrn->bitsPerPixel == 8),
- ((pScrn->bitsPerPixel != 8)
- ? 0 : pScrn->displayWidth),
- 0, 0, 0, PseudoColor);
-
- /* 15 */
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 16, 15,
- (pScrn->bitsPerPixel == 16),
- ((pScrn->depth != 15)
- ? 0 : pScrn->displayWidth),
- 0x7c00, 0x03e0, 0x001f, TrueColor);
-
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 16, 15,
- (pScrn->bitsPerPixel == 16),
- ((pScrn->depth != 15)
- ? 0 : pScrn->displayWidth),
- 0x7c00, 0x03e0, 0x001f, DirectColor);
-
- /* 16 */
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 16, 16,
- (pScrn->bitsPerPixel == 16),
- ((pScrn->depth != 16)
- ? 0 : pScrn->displayWidth),
- 0xf800, 0x07e0, 0x001f, TrueColor);
-
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 16, 16,
- (pScrn->bitsPerPixel == 16),
- ((pScrn->depth != 16)
- ? 0 : pScrn->displayWidth),
- 0xf800, 0x07e0, 0x001f, DirectColor);
-
- /* 32 */
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 32, 24,
- (pScrn->bitsPerPixel == 32),
- ((pScrn->bitsPerPixel != 32)
- ? 0 : pScrn->displayWidth),
- 0xff0000, 0x00ff00, 0x0000ff, TrueColor);
-
- modes = RADEONSetupDGAMode(pScrn, modes, &num, 32, 24,
- (pScrn->bitsPerPixel == 32),
- ((pScrn->bitsPerPixel != 32)
- ? 0 : pScrn->displayWidth),
- 0xff0000, 0x00ff00, 0x0000ff, DirectColor);
-
- info->numDGAModes = num;
- info->DGAModes = modes;
-
- info->DGAFuncs.OpenFramebuffer = RADEON_OpenFramebuffer;
- info->DGAFuncs.CloseFramebuffer = NULL;
- info->DGAFuncs.SetMode = RADEON_SetMode;
- info->DGAFuncs.SetViewport = RADEON_SetViewport;
- info->DGAFuncs.GetViewport = RADEON_GetViewport;
-
- info->DGAFuncs.Sync = NULL;
- info->DGAFuncs.FillRect = NULL;
- info->DGAFuncs.BlitRect = NULL;
- info->DGAFuncs.BlitTransRect = NULL;
-
-#ifdef USE_EXA
- /*info->DGAFuncs.Sync = info->exa.accel->Sync;*/
- if (info->useEXA) {
- /*if (info->exa.accel.PrepareSolid && info->exa.accel.Solid) {
- info->DGAFuncs.FillRect = RADEON_FillRect;
- }
- if (info->exa.accel.PrepareCopy && info->exa.accel.Copy) {
- info->DGAFuncs.BlitRect = RADEON_BlitRect;
- }*/
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA && info->accel) {
- info->DGAFuncs.Sync = info->accel->Sync;
- if (info->accel->SetupForSolidFill &&
- info->accel->SubsequentSolidFillRect)
- info->DGAFuncs.FillRect = RADEON_FillRect;
- if (info->accel->SetupForScreenToScreenCopy &&
- info->accel->SubsequentScreenToScreenCopy) {
- info->DGAFuncs.BlitRect = RADEON_BlitRect;
- info->DGAFuncs.BlitTransRect = RADEON_BlitTransRect;
- }
- }
-#endif /* USE_XAA */
-
- return DGAInit(pScreen, &info->DGAFuncs, modes, num);
-}
-
-static Bool RADEON_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode)
-{
- static RADEONFBLayout SavedLayouts[MAXSCREENS];
- int indx = pScrn->pScreen->myNum;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (!pMode) { /* restore the original mode */
- /* put the ScreenParameters back */
- if (info->DGAactive)
- memcpy(&info->CurrentLayout, &SavedLayouts[indx],
- sizeof(RADEONFBLayout));
-
- pScrn->currentMode = info->CurrentLayout.mode;
-
- RADEONSwitchMode(indx, pScrn->currentMode, 0);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_STOP(pScrn, info);
- }
-#endif
- if (info->accelOn)
- RADEONEngineInit(pScrn);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_START(pScrn, info);
- }
-#endif
- RADEONAdjustFrame(indx, 0, 0, 0);
- info->DGAactive = FALSE;
- } else {
- if (!info->DGAactive) { /* save the old parameters */
- memcpy(&SavedLayouts[indx], &info->CurrentLayout,
- sizeof(RADEONFBLayout));
- info->DGAactive = TRUE;
- }
-
- info->CurrentLayout.bitsPerPixel = pMode->bitsPerPixel;
- info->CurrentLayout.depth = pMode->depth;
- info->CurrentLayout.displayWidth = (pMode->bytesPerScanline /
- (pMode->bitsPerPixel >> 3));
- info->CurrentLayout.pixel_bytes = pMode->bitsPerPixel / 8;
- info->CurrentLayout.pixel_code = (pMode->bitsPerPixel != 16
- ? pMode->bitsPerPixel
- : pMode->depth);
- /* RADEONModeInit() will set the mode field */
-
- RADEONSwitchMode(indx, pMode->mode, 0);
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_STOP(pScrn, info);
- }
-#endif
- if (info->accelOn)
- RADEONEngineInit(pScrn);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_START(pScrn, info);
- }
-#endif
- }
-
- return TRUE;
-}
-
-static int RADEON_GetViewport(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- return info->DGAViewportStatus;
-}
-
-static void RADEON_SetViewport(ScrnInfoPtr pScrn, int x, int y, int flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- RADEONAdjustFrame(pScrn->pScreen->myNum, x, y, flags);
- info->DGAViewportStatus = 0; /* FIXME */
-}
-
-
-#ifdef USE_XAA
-
-static void RADEON_FillRect(ScrnInfoPtr pScrn,
- int x, int y, int w, int h,
- unsigned long color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef USE_EXA
- /* XXX */
- if (info->useEXA) {
- /*
- info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (CARD32)(~0));
- info->exa.accel.Solid(pScrn, x, y, x+w, y+h);
- info->exa.accel.DoneSolid();
- */
- RADEON_MARK_SYNC(info, pScrn);
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (CARD32)(~0));
- (*info->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h);
- if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
- RADEON_MARK_SYNC(info, pScrn);
- }
-#endif /* USE_XAA */
-
-}
-
-static void RADEON_BlitRect(ScrnInfoPtr pScrn,
- int srcx, int srcy, int w, int h,
- int dstx, int dsty)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1;
- int ydir = (srcy < dsty) ? -1 : 1;
-
- #ifdef USE_EXA
- /* XXX */
- if (info->useEXA) {
- /*
- info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (CARD32)(~0));
- info->exa.accel.Copy(pScrn, srcx, srcy, dstx, dsty, w, h);
- info->exa.accel.DoneCopy();
- */
- RADEON_MARK_SYNC(info, pScrn);
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir,
- GXcopy, (CARD32)(~0), -1);
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy,
- dstx, dsty, w, h);
- if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
- RADEON_MARK_SYNC(info, pScrn);
- }
-#endif /* USE_XAA */
-}
-
-static void RADEON_BlitTransRect(ScrnInfoPtr pScrn,
- int srcx, int srcy, int w, int h,
- int dstx, int dsty, unsigned long color)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1;
- int ydir = (srcy < dsty) ? -1 : 1;
-
- info->XAAForceTransBlit = TRUE;
- (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir,
- GXcopy, (CARD32)(~0), color);
-
- info->XAAForceTransBlit = FALSE;
-
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy,
- dstx, dsty, w, h);
-
- if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel)
- RADEON_MARK_SYNC(info, pScrn);
-}
-
-#endif /* USE_XAA */
-
-static Bool RADEON_OpenFramebuffer(ScrnInfoPtr pScrn,
- char **name,
- unsigned char **mem,
- int *size, int *offset, int *flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- *name = NULL; /* no special device */
- *mem = (unsigned char*)info->LinearAddr;
- *size = info->FbMapSize;
- *offset = 0;
- *flags = 0; /* DGA_NEED_ROOT; -- don't need root, just /dev/mem access */
-
- return TRUE;
-}
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
deleted file mode 100644
index ac8d03c..0000000
--- a/src/radeon_dri.c
+++ /dev/null
@@ -1,2216 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Gareth Hughes <gareth at valinux.com>
- *
- */
-
-#include <string.h>
-#include <stdio.h>
-
- /* Driver data structures */
-#include "radeon.h"
-#include "radeon_video.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_dri.h"
-#include "radeon_version.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-#include "xf86PciInfo.h"
-#include "windowstr.h"
-
- /* GLX/DRI/DRM definitions */
-#define _XF86DRI_SERVER_
-#include "GL/glxtokens.h"
-#include "sarea.h"
-#include "radeon_sarea.h"
-
-static size_t radeon_drm_page_size;
-
-
-static void RADEONDRITransitionTo2d(ScreenPtr pScreen);
-static void RADEONDRITransitionTo3d(ScreenPtr pScreen);
-static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen);
-static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen);
-
-#ifdef DAMAGE
-static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg);
-
-#if (DRIINFO_MAJOR_VERSION > 5 || \
- (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1))
-static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num);
-#endif
-#endif
-
-/* Initialize the visual configs that are supported by the hardware.
- * These are combined with the visual configs that the indirect
- * rendering core supports, and the intersection is exported to the
- * client.
- */
-static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int numConfigs = 0;
- __GLXvisualConfig *pConfigs = 0;
- RADEONConfigPrivPtr pRADEONConfigs = 0;
- RADEONConfigPrivPtr *pRADEONConfigPtrs = 0;
- int i, accum, stencil, db, use_db;
-
- use_db = !info->noBackBuffer ? 1 : 0;
-
- switch (info->CurrentLayout.pixel_code) {
- case 8: /* 8bpp mode is not support */
- case 15: /* FIXME */
- case 24: /* FIXME */
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] RADEONInitVisualConfigs failed "
- "(depth %d not supported). "
- "Disabling DRI.\n", info->CurrentLayout.pixel_code);
- return FALSE;
-
-#define RADEON_USE_ACCUM 1
-#define RADEON_USE_STENCIL 1
-
- case 16:
- numConfigs = 1;
- if (RADEON_USE_ACCUM) numConfigs *= 2;
- if (RADEON_USE_STENCIL) numConfigs *= 2;
- if (use_db) numConfigs *= 2;
-
- if (!(pConfigs
- = (__GLXvisualConfig *)xcalloc(sizeof(__GLXvisualConfig),
- numConfigs))) {
- return FALSE;
- }
- if (!(pRADEONConfigs
- = (RADEONConfigPrivPtr)xcalloc(sizeof(RADEONConfigPrivRec),
- numConfigs))) {
- xfree(pConfigs);
- return FALSE;
- }
- if (!(pRADEONConfigPtrs
- = (RADEONConfigPrivPtr *)xcalloc(sizeof(RADEONConfigPrivPtr),
- numConfigs))) {
- xfree(pConfigs);
- xfree(pRADEONConfigs);
- return FALSE;
- }
-
- i = 0;
- for (db = use_db; db >= 0; db--) {
- for (accum = 0; accum <= RADEON_USE_ACCUM; accum++) {
- for (stencil = 0; stencil <= RADEON_USE_STENCIL; stencil++) {
- pRADEONConfigPtrs[i] = &pRADEONConfigs[i];
-
- pConfigs[i].vid = (VisualID)(-1);
- pConfigs[i].class = -1;
- pConfigs[i].rgba = TRUE;
- pConfigs[i].redSize = 5;
- pConfigs[i].greenSize = 6;
- pConfigs[i].blueSize = 5;
- pConfigs[i].alphaSize = 0;
- pConfigs[i].redMask = 0x0000F800;
- pConfigs[i].greenMask = 0x000007E0;
- pConfigs[i].blueMask = 0x0000001F;
- pConfigs[i].alphaMask = 0x00000000;
- if (accum) { /* Simulated in software */
- pConfigs[i].accumRedSize = 16;
- pConfigs[i].accumGreenSize = 16;
- pConfigs[i].accumBlueSize = 16;
- pConfigs[i].accumAlphaSize = 0;
- } else {
- pConfigs[i].accumRedSize = 0;
- pConfigs[i].accumGreenSize = 0;
- pConfigs[i].accumBlueSize = 0;
- pConfigs[i].accumAlphaSize = 0;
- }
- if (db)
- pConfigs[i].doubleBuffer = TRUE;
- else
- pConfigs[i].doubleBuffer = FALSE;
- pConfigs[i].stereo = FALSE;
- pConfigs[i].bufferSize = 16;
- pConfigs[i].depthSize = info->depthBits;
- if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil)
- : stencil) {
- pConfigs[i].stencilSize = 8;
- } else {
- pConfigs[i].stencilSize = 0;
- }
- pConfigs[i].auxBuffers = 0;
- pConfigs[i].level = 0;
- if (accum ||
- (pConfigs[i].stencilSize && pConfigs[i].depthSize == 16)) {
- pConfigs[i].visualRating = GLX_SLOW_CONFIG;
- } else {
- pConfigs[i].visualRating = GLX_NONE;
- }
- pConfigs[i].transparentPixel = GLX_NONE;
- pConfigs[i].transparentRed = 0;
- pConfigs[i].transparentGreen = 0;
- pConfigs[i].transparentBlue = 0;
- pConfigs[i].transparentAlpha = 0;
- pConfigs[i].transparentIndex = 0;
- i++;
- }
- }
- }
- break;
-
- case 32:
- numConfigs = 1;
- if (RADEON_USE_ACCUM) numConfigs *= 2;
- if (RADEON_USE_STENCIL) numConfigs *= 2;
- if (use_db) numConfigs *= 2;
-
- if (!(pConfigs
- = (__GLXvisualConfig *)xcalloc(sizeof(__GLXvisualConfig),
- numConfigs))) {
- return FALSE;
- }
- if (!(pRADEONConfigs
- = (RADEONConfigPrivPtr)xcalloc(sizeof(RADEONConfigPrivRec),
- numConfigs))) {
- xfree(pConfigs);
- return FALSE;
- }
- if (!(pRADEONConfigPtrs
- = (RADEONConfigPrivPtr *)xcalloc(sizeof(RADEONConfigPrivPtr),
- numConfigs))) {
- xfree(pConfigs);
- xfree(pRADEONConfigs);
- return FALSE;
- }
-
- i = 0;
- for (db = use_db; db >= 0; db--) {
- for (accum = 0; accum <= RADEON_USE_ACCUM; accum++) {
- for (stencil = 0; stencil <= RADEON_USE_STENCIL; stencil++) {
- pRADEONConfigPtrs[i] = &pRADEONConfigs[i];
-
- pConfigs[i].vid = (VisualID)(-1);
- pConfigs[i].class = -1;
- pConfigs[i].rgba = TRUE;
- pConfigs[i].redSize = 8;
- pConfigs[i].greenSize = 8;
- pConfigs[i].blueSize = 8;
- pConfigs[i].alphaSize = 8;
- pConfigs[i].redMask = 0x00FF0000;
- pConfigs[i].greenMask = 0x0000FF00;
- pConfigs[i].blueMask = 0x000000FF;
- pConfigs[i].alphaMask = 0xFF000000;
- if (accum) { /* Simulated in software */
- pConfigs[i].accumRedSize = 16;
- pConfigs[i].accumGreenSize = 16;
- pConfigs[i].accumBlueSize = 16;
- pConfigs[i].accumAlphaSize = 16;
- } else {
- pConfigs[i].accumRedSize = 0;
- pConfigs[i].accumGreenSize = 0;
- pConfigs[i].accumBlueSize = 0;
- pConfigs[i].accumAlphaSize = 0;
- }
- if (db)
- pConfigs[i].doubleBuffer = TRUE;
- else
- pConfigs[i].doubleBuffer = FALSE;
- pConfigs[i].stereo = FALSE;
- pConfigs[i].bufferSize = 32;
- pConfigs[i].depthSize = info->depthBits;
- if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil)
- : stencil) {
- pConfigs[i].stencilSize = 8;
- } else {
- pConfigs[i].stencilSize = 0;
- }
- pConfigs[i].auxBuffers = 0;
- pConfigs[i].level = 0;
- if (accum ||
- (pConfigs[i].stencilSize && pConfigs[i].depthSize == 16)) {
- pConfigs[i].visualRating = GLX_SLOW_CONFIG;
- } else {
- pConfigs[i].visualRating = GLX_NONE;
- }
- pConfigs[i].transparentPixel = GLX_NONE;
- pConfigs[i].transparentRed = 0;
- pConfigs[i].transparentGreen = 0;
- pConfigs[i].transparentBlue = 0;
- pConfigs[i].transparentAlpha = 0;
- pConfigs[i].transparentIndex = 0;
- i++;
- }
- }
- }
- break;
- }
-
- info->numVisualConfigs = numConfigs;
- info->pVisualConfigs = pConfigs;
- info->pVisualConfigsPriv = pRADEONConfigs;
- GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pRADEONConfigPtrs);
- return TRUE;
-}
-
-/* Create the Radeon-specific context information */
-static Bool RADEONCreateContext(ScreenPtr pScreen, VisualPtr visual,
- drm_context_t hwContext, void *pVisualConfigPriv,
- DRIContextType contextStore)
-{
-#ifdef PER_CONTEXT_SAREA
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONDRIContextPtr ctx_info;
-
- ctx_info = (RADEONDRIContextPtr)contextStore;
- if (!ctx_info) return FALSE;
-
- if (drmAddMap(info->drmFD, 0,
- info->perctx_sarea_size,
- DRM_SHM,
- DRM_REMOVABLE,
- &ctx_info->sarea_handle) < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[dri] could not create private sarea for ctx id (%d)\n",
- (int)hwContext);
- return FALSE;
- }
-
- if (drmAddContextPrivateMapping(info->drmFD, hwContext,
- ctx_info->sarea_handle) < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[dri] could not associate private sarea to ctx id (%d)\n",
- (int)hwContext);
- drmRmMap(info->drmFD, ctx_info->sarea_handle);
- return FALSE;
- }
-
- ctx_info->ctx_id = hwContext;
-#endif
- return TRUE;
-}
-
-/* Destroy the Radeon-specific context information */
-static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
- DRIContextType contextStore)
-{
-#ifdef PER_CONTEXT_SAREA
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONDRIContextPtr ctx_info;
-
- ctx_info = (RADEONDRIContextPtr)contextStore;
- if (!ctx_info) return;
-
- if (drmRmMap(info->drmFD, ctx_info->sarea_handle) < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[dri] could not remove private sarea for ctx id (%d)\n",
- (int)hwContext);
- }
-#endif
-}
-
-/* Called when the X server is woken up to allow the last client's
- * context to be saved and the X server's context to be loaded. This is
- * not necessary for the Radeon since the client detects when it's
- * context is not currently loaded and then load's it itself. Since the
- * registers to start and stop the CP are privileged, only the X server
- * can start/stop the engine.
- */
-static void RADEONEnterServer(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSAREAPrivPtr pSAREAPriv;
-
-
- RADEON_MARK_SYNC(info, pScrn);
-
- pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen)) {
- info->XInited3D = FALSE;
- info->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
- }
-
-#ifdef DAMAGE
- if (!info->pDamage && info->allowPageFlip) {
- PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
- info->pDamage = DamageCreate(NULL, NULL, DamageReportNone, TRUE,
- pScreen, pPix);
-
- if (info->pDamage == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No screen damage record, page flipping disabled\n");
- info->allowPageFlip = 0;
- } else {
- DamageRegister(&pPix->drawable, info->pDamage);
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Damage tracking initialized for page flipping\n");
- }
- }
-#endif
-}
-
-/* Called when the X server goes to sleep to allow the X server's
- * context to be saved and the last client's context to be loaded. This
- * is not necessary for the Radeon since the client detects when it's
- * context is not currently loaded and then load's it itself. Since the
- * registers to start and stop the CP are privileged, only the X server
- * can start/stop the engine.
- */
-static void RADEONLeaveServer(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RING_LOCALS;
-
-#ifdef DAMAGE
- if (info->pDamage) {
- RegionPtr pDamageReg = DamageRegion(info->pDamage);
- int nrects = pDamageReg ? REGION_NUM_RECTS(pDamageReg) : 0;
-
- if (nrects) {
- RADEONDRIRefreshArea(pScrn, pDamageReg);
- }
- }
-#endif
-
- /* The CP is always running, but if we've generated any CP commands
- * we must flush them to the kernel module now.
- */
- RADEONCP_RELEASE(pScrn, info);
-
-#ifdef USE_EXA
- info->engineMode = EXA_ENGINEMODE_UNKNOWN;
-#endif
-}
-
-/* Contexts can be swapped by the X server if necessary. This callback
- * is currently only used to perform any functions necessary when
- * entering or leaving the X server, and in the future might not be
- * necessary.
- */
-static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
- DRIContextType oldContextType,
- void *oldContext,
- DRIContextType newContextType,
- void *newContext)
-{
- if ((syncType==DRI_3D_SYNC) && (oldContextType==DRI_2D_CONTEXT) &&
- (newContextType==DRI_2D_CONTEXT)) { /* Entering from Wakeup */
- RADEONEnterServer(pScreen);
- }
-
- if ((syncType==DRI_2D_SYNC) && (oldContextType==DRI_NO_CONTEXT) &&
- (newContextType==DRI_2D_CONTEXT)) { /* Exiting from Block Handler */
- RADEONLeaveServer(pScreen);
- }
-}
-
-#ifdef USE_XAA
-
-/* The Radeon has depth tiling on all the time. Rely on surface regs to
- * translate the addresses (only works if allowColorTiling is true).
- */
-
-/* 16-bit depth buffer functions */
-#define WRITE_DEPTH16(_x, _y, d) \
- *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d)
-
-#define READ_DEPTH16(d, _x, _y) \
- (d) = *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch))
-
-/* 32-bit depth buffer (stencil and depth simultaneously) functions */
-#define WRITE_DEPTHSTENCIL32(_x, _y, d) \
- *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d)
-
-#define READ_DEPTHSTENCIL32(d, _x, _y) \
- (d) = *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch))
-
-/* Screen to screen copy of data in the depth buffer */
-static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn,
- int xa, int ya,
- int xb, int yb,
- int w, int h)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *buf = info->FB + info->depthOffset;
- int xstart, xend, xdir;
- int ystart, yend, ydir;
- int x, y, d;
-
- if (xa < xb) xdir = -1, xstart = w-1, xend = 0;
- else xdir = 1, xstart = 0, xend = w-1;
-
- if (ya < yb) ydir = -1, ystart = h-1, yend = 0;
- else ydir = 1, ystart = 0, yend = h-1;
-
- switch (pScrn->bitsPerPixel) {
- case 16:
- for (x = xstart; x != xend; x += xdir) {
- for (y = ystart; y != yend; y += ydir) {
- READ_DEPTH16(d, xa+x, ya+y);
- WRITE_DEPTH16(xb+x, yb+y, d);
- }
- }
- break;
-
- case 32:
- for (x = xstart; x != xend; x += xdir) {
- for (y = ystart; y != yend; y += ydir) {
- READ_DEPTHSTENCIL32(d, xa+x, ya+y);
- WRITE_DEPTHSTENCIL32(xb+x, yb+y, d);
- }
- }
- break;
-
- default:
- break;
- }
-}
-
-#endif /* USE_XAA */
-
-/* Initialize the state of the back and depth buffers */
-static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx)
-{
- /* NOOP. There's no need for the 2d driver to be clearing buffers
- * for the 3d client. It knows how to do that on its own.
- */
-}
-
-/* Copy the back and depth buffers when the X server moves a window.
- *
- * This routine is a modified form of XAADoBitBlt with the calls to
- * ScreenToScreenBitBlt built in. My routine has the prgnSrc as source
- * instead of destination. My origin is upside down so the ydir cases
- * are reversed.
- */
-static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
- RegionPtr prgnSrc, CARD32 indx)
-{
-#ifdef USE_XAA
- ScreenPtr pScreen = pParent->drawable.pScreen;
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- BoxPtr pboxTmp, pboxNext, pboxBase;
- DDXPointPtr pptTmp;
- int xdir, ydir;
-
- int screenwidth = pScrn->virtualX;
- int screenheight = pScrn->virtualY;
-
- BoxPtr pbox = REGION_RECTS(prgnSrc);
- int nbox = REGION_NUM_RECTS(prgnSrc);
-
- BoxPtr pboxNew1 = NULL;
- BoxPtr pboxNew2 = NULL;
- DDXPointPtr pptNew1 = NULL;
- DDXPointPtr pptNew2 = NULL;
- DDXPointPtr pptSrc = &ptOldOrg;
-
- int dx = pParent->drawable.x - ptOldOrg.x;
- int dy = pParent->drawable.y - ptOldOrg.y;
-
- /* XXX: Fix in EXA case. */
- if (info->useEXA)
- return;
-
- /* If the copy will overlap in Y, reverse the order */
- if (dy > 0) {
- ydir = -1;
-
- if (nbox > 1) {
- /* Keep ordering in each band, reverse order of bands */
- pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
- if (!pboxNew1) return;
-
- pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
- if (!pptNew1) {
- xfree(pboxNew1);
- return;
- }
-
- pboxBase = pboxNext = pbox+nbox-1;
-
- while (pboxBase >= pbox) {
- while ((pboxNext >= pbox) && (pboxBase->y1 == pboxNext->y1))
- pboxNext--;
-
- pboxTmp = pboxNext+1;
- pptTmp = pptSrc + (pboxTmp - pbox);
-
- while (pboxTmp <= pboxBase) {
- *pboxNew1++ = *pboxTmp++;
- *pptNew1++ = *pptTmp++;
- }
-
- pboxBase = pboxNext;
- }
-
- pboxNew1 -= nbox;
- pbox = pboxNew1;
- pptNew1 -= nbox;
- pptSrc = pptNew1;
- }
- } else {
- /* No changes required */
- ydir = 1;
- }
-
- /* If the regions will overlap in X, reverse the order */
- if (dx > 0) {
- xdir = -1;
-
- if (nbox > 1) {
- /* reverse order of rects in each band */
- pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
- pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
-
- if (!pboxNew2 || !pptNew2) {
- xfree(pptNew2);
- xfree(pboxNew2);
- xfree(pptNew1);
- xfree(pboxNew1);
- return;
- }
-
- pboxBase = pboxNext = pbox;
-
- while (pboxBase < pbox+nbox) {
- while ((pboxNext < pbox+nbox)
- && (pboxNext->y1 == pboxBase->y1))
- pboxNext++;
-
- pboxTmp = pboxNext;
- pptTmp = pptSrc + (pboxTmp - pbox);
-
- while (pboxTmp != pboxBase) {
- *pboxNew2++ = *--pboxTmp;
- *pptNew2++ = *--pptTmp;
- }
-
- pboxBase = pboxNext;
- }
-
- pboxNew2 -= nbox;
- pbox = pboxNew2;
- pptNew2 -= nbox;
- pptSrc = pptNew2;
- }
- } else {
- /* No changes are needed */
- xdir = 1;
- }
-
- /* pretty much a hack. */
- info->dst_pitch_offset = info->backPitchOffset;
- if (info->tilingEnabled)
- info->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
-
- (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy,
- (CARD32)(-1), -1);
-
- for (; nbox-- ; pbox++) {
- int xa = pbox->x1;
- int ya = pbox->y1;
- int destx = xa + dx;
- int desty = ya + dy;
- int w = pbox->x2 - xa + 1;
- int h = pbox->y2 - ya + 1;
-
- if (destx < 0) xa -= destx, w += destx, destx = 0;
- if (desty < 0) ya -= desty, h += desty, desty = 0;
- if (destx + w > screenwidth) w = screenwidth - destx;
- if (desty + h > screenheight) h = screenheight - desty;
-
- if (w <= 0) continue;
- if (h <= 0) continue;
-
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn,
- xa, ya,
- destx, desty,
- w, h);
-
- if (info->depthMoves) {
- RADEONScreenToScreenCopyDepth(pScrn,
- xa, ya,
- destx, desty,
- w, h);
- }
- }
-
- info->dst_pitch_offset = info->frontPitchOffset;;
-
- xfree(pptNew2);
- xfree(pboxNew2);
- xfree(pptNew1);
- xfree(pboxNew1);
-
- info->accel->NeedToSync = TRUE;
-#endif /* USE_XAA */
-}
-
-static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
-{
- int s, l;
-
- info->gartOffset = 0;
-
- /* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
- info->ringSizeLog2QW = RADEONMinBits(info->ringSize*1024*1024/8)-1;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- /* Reserve the rest for GART textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
-}
-
-/* Set AGP transfer mode according to requests and constraints */
-static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */
- unsigned int vendor = drmAgpVendorId(info->drmFD);
- unsigned int device = drmAgpDeviceId(info->drmFD);
- /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
- pcie-agp rialto bridge chip - use the one from bridge which must match */
- CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
- Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
- unsigned int defaultMode;
- MessageType from;
-
- if (is_v3) {
- defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
- } else {
- if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
- else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
- else defaultMode = 1;
- }
-
- from = X_DEFAULT;
-
- if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) {
- if ((info->agpMode < (is_v3 ? 4 : 1)) ||
- (info->agpMode > (is_v3 ? 8 : 4)) ||
- (info->agpMode & (info->agpMode - 1))) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "Illegal AGP Mode: %d (valid values: %s), leaving at "
- "%dx\n", info->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
- defaultMode);
- info->agpMode = defaultMode;
- } else
- from = X_CONFIG;
- } else
- info->agpMode = defaultMode;
-
- xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->agpMode);
-
- mode &= ~RADEON_AGP_MODE_MASK;
- if (is_v3) {
- /* only set one mode bit for AGPv3 */
- switch (info->agpMode) {
- case 8: mode |= RADEON_AGPv3_8X_MODE; break;
- case 4: default: mode |= RADEON_AGPv3_4X_MODE;
- }
- /*TODO: need to take care of other bits valid for v3 mode
- * currently these bits are not used in all tested cards.
- */
- } else {
- switch (info->agpMode) {
- case 4: mode |= RADEON_AGP_4X_MODE;
- case 2: mode |= RADEON_AGP_2X_MODE;
- case 1: default: mode |= RADEON_AGP_1X_MODE;
- }
- }
-
- /* AGP Fast Writes.
- * TODO: take into account that certain agp modes don't support fast
- * writes at all */
- mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
- if (xf86ReturnOptValBool(info->Options, OPTION_AGP_FW, FALSE)) {
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "WARNING: Using the AGPFastWrite option is not recommended.\n");
- xf86Msg(X_NONE, "\tThis option does not provide much of a noticable speed"
- " boost, while it\n\twill probably hard lock your machine."
- " All bets are off!\n");
-
- /* Black list some host/AGP bridges. */
- if ((vendor == PCI_VENDOR_AMD) && (device == PCI_CHIP_AMD761))
- xf86DrvMsg(pScreen->myNum, X_PROBED, "Ignoring AGPFastWrite option "
- "for the AMD 761 northbridge.\n");
- else {
- xf86DrvMsg(pScreen->myNum, X_CONFIG, "Enabling AGP Fast Writes.\n");
- mode |= RADEON_AGP_FW_MODE;
- }
- } /* Don't mention this otherwise, so that people don't get funny ideas */
-
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
- mode, vendor, device,
- PCI_DEV_VENDOR_ID(info->PciInfo),
- PCI_DEV_DEVICE_ID(info->PciInfo));
-
- if (drmAgpEnable(info->drmFD, mode) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
- drmAgpRelease(info->drmFD);
- return FALSE;
- }
-
- /* Workaround for some hardware bugs */
- if (info->ChipFamily < CHIP_FAMILY_R200)
- OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
-
- /* Modify the mode if the default mode
- * is not appropriate for this
- * particular combination of graphics
- * card and AGP chipset.
- */
-
- return TRUE;
-}
-
-/* Initialize Radeon's AGP registers */
-static void RADEONSetAgpBase(RADEONInfoPtr info)
-{
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD));
-}
-
-/* Initialize the AGP state. Request memory for use in AGP space, and
- * initialize the Radeon registers to point to that memory.
- */
-static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- int ret;
-
- if (drmAgpAcquire(info->drmFD) < 0) {
- xf86DrvMsg(pScreen->myNum, X_WARNING, "[agp] AGP not available\n");
- return FALSE;
- }
-
- if (!RADEONSetAgpMode(info, pScreen))
- return FALSE;
-
- RADEONDRIInitGARTValues(info);
-
- if ((ret = drmAgpAlloc(info->drmFD, info->gartSize*1024*1024, 0, NULL,
- &info->agpMemHandle)) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Out of memory (%d)\n", ret);
- drmAgpRelease(info->drmFD);
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, info->agpMemHandle);
-
- if (drmAgpBind(info->drmFD,
- info->agpMemHandle, info->gartOffset) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not bind\n");
- drmAgpFree(info->drmFD, info->agpMemHandle);
- drmAgpRelease(info->drmFD);
- return FALSE;
- }
-
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add ring mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring handle = 0x%08x\n", info->ringHandle);
-
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
-
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add ring read ptr mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
-
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not map ring read ptr\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
-
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_AGP, 0, &info->bufHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add vertex/indirect buffers mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
-
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not map vertex/indirect buffers\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
-
- if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_AGP, 0, &info->gartTexHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not add GART texture map mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
-
- if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize,
- &info->gartTex) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] Could not map GART texture map\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] GART Texture map mapped at 0x%08lx\n",
- (unsigned long)info->gartTex);
-
- RADEONSetAgpBase(info);
-
- return TRUE;
-}
-
-/* Initialize the PCI GART state. Request memory for use in PCI space,
- * and initialize the Radeon registers to point to that memory.
- */
-static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- int ret;
- int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
-
- ret = drmScatterGatherAlloc(info->drmFD, info->gartSize*1024*1024,
- &info->pciMemHandle);
- if (ret < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Out of memory (%d)\n", ret);
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, info->pciMemHandle);
-
- RADEONDRIInitGARTValues(info);
-
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add ring mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring handle = 0x%08x\n", info->ringHandle);
-
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ring);
-
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add ring read ptr mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
-
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not map ring read ptr\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Ring read ptr contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ringReadPtr);
-
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add vertex/indirect buffers mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
-
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not map vertex/indirect buffers\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] Vertex/indirect buffers contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->buf);
-
- if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not add GART texture map mapping\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
-
- if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize,
- &info->gartTex) < 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] Could not map GART texture map\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] GART Texture map mapped at 0x%08lx\n",
- (unsigned long)info->gartTex);
-
- return TRUE;
-}
-
-/* Add a map for the MMIO registers that will be accessed by any
- * DRI-based clients.
- */
-static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- /* Map registers */
- info->registerSize = info->MMIOSize;
- if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize,
- DRM_REGISTERS, DRM_READ_ONLY, &info->registerHandle) < 0) {
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] register handle = 0x%08x\n", info->registerHandle);
-
- return TRUE;
-}
-
-/* Initialize the kernel data structures */
-static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- int cpp = info->CurrentLayout.pixel_bytes;
- drmRadeonInit drmInfo;
-
- memset(&drmInfo, 0, sizeof(drmRadeonInit));
- if ( info->ChipFamily >= CHIP_FAMILY_R300 )
- drmInfo.func = DRM_RADEON_INIT_R300_CP;
- else
- if ( info->ChipFamily >= CHIP_FAMILY_R200 )
- drmInfo.func = DRM_RADEON_INIT_R200_CP;
- else
- drmInfo.func = DRM_RADEON_INIT_CP;
-
- drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
- drmInfo.is_pci = (info->cardType!=CARD_AGP);
- drmInfo.cp_mode = info->CPMode;
- drmInfo.gart_size = info->gartSize*1024*1024;
- drmInfo.ring_size = info->ringSize*1024*1024;
- drmInfo.usec_timeout = info->CPusecTimeout;
-
- drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
- drmInfo.depth_bpp = (info->depthBits - 8) * 2;
-
- drmInfo.front_offset = info->frontOffset;
- drmInfo.front_pitch = info->frontPitch * cpp;
- drmInfo.back_offset = info->backOffset;
- drmInfo.back_pitch = info->backPitch * cpp;
- drmInfo.depth_offset = info->depthOffset;
- drmInfo.depth_pitch = info->depthPitch * drmInfo.depth_bpp / 8;
-
- drmInfo.fb_offset = info->fbHandle;
- drmInfo.mmio_offset = info->registerHandle;
- drmInfo.ring_offset = info->ringHandle;
- drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
- drmInfo.buffers_offset = info->bufHandle;
- drmInfo.gart_textures_offset= info->gartTexHandle;
-
- if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT,
- &drmInfo, sizeof(drmRadeonInit)) < 0)
- return FALSE;
-
- /* DRM_RADEON_CP_INIT does an engine reset, which resets some engine
- * registers back to their default values, so we need to restore
- * those engine register here.
- */
- RADEONEngineRestore(pScrn);
-
- return TRUE;
-}
-
-static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- drmRadeonMemInitHeap drmHeap;
-
- /* Start up the simple memory manager for GART space */
- drmHeap.region = RADEON_MEM_REGION_GART;
- drmHeap.start = 0;
- drmHeap.size = info->gartTexMapSize;
-
- if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP,
- &drmHeap, sizeof(drmHeap))) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[drm] Failed to initialize GART heap manager\n");
- } else {
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] Initialized kernel GART heap manager, %d\n",
- info->gartTexMapSize);
- }
-}
-
-/* Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- */
-static Bool RADEONDRIBufInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- /* Initialize vertex buffers */
- info->bufNumBufs = drmAddBufs(info->drmFD,
- info->bufMapSize / RADEON_BUFFER_SIZE,
- RADEON_BUFFER_SIZE,
- (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
- info->bufStart);
-
- if (info->bufNumBufs <= 0) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[drm] Could not create vertex/indirect buffers list\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] Added %d %d byte vertex/indirect buffers\n",
- info->bufNumBufs, RADEON_BUFFER_SIZE);
-
- if (!(info->buffers = drmMapBufs(info->drmFD))) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[drm] Failed to map vertex/indirect buffers list\n");
- return FALSE;
- }
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] Mapped %d vertex/indirect buffers\n",
- info->buffers->count);
-
- return TRUE;
-}
-
-static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-
- if (!info->irq) {
- info->irq = drmGetInterruptFromBusID(
- info->drmFD,
- PCI_CFG_BUS(info->PciInfo),
- PCI_CFG_DEV(info->PciInfo),
- PCI_CFG_FUNC(info->PciInfo));
-
- if ((drmCtlInstHandler(info->drmFD, info->irq)) != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[drm] failure adding irq handler, "
- "there is a device already using that irq\n"
- "[drm] falling back to irq-free operation\n");
- info->irq = 0;
- } else {
- unsigned char *RADEONMMIO = info->MMIO;
- info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
- }
- }
-
- if (info->irq)
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[drm] dma control initialized, using IRQ %d\n",
- info->irq);
-}
-
-
-/* Initialize the CP state, and start the CP (if used by the X server) */
-static void RADEONDRICPInit(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- /* Turn on bus mastering */
- info->BusCntl &= ~RADEON_BUS_MASTER_DIS;
-
- /* Make sure the CP is on for the X server */
- RADEONCP_START(pScrn, info);
-#ifdef USE_XAA
- if (!info->useEXA)
- info->dst_pitch_offset = info->frontPitchOffset;
-#endif
-}
-
-
-/* Get the DRM version and do some basic useability checks of DRI */
-Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int major, minor, patch, fd;
- int req_minor, req_patch;
- char *busId;
-
- /* Check that the GLX, DRI, and DRM modules have been loaded by testing
- * for known symbols in each module.
- */
- if (!xf86LoaderCheckSymbol("GlxSetVisualConfigs")) return FALSE;
- if (!xf86LoaderCheckSymbol("drmAvailable")) return FALSE;
- if (!xf86LoaderCheckSymbol("DRIQueryVersion")) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed (libdri.a too old)\n"
- "[dri] Disabling DRI.\n");
- return FALSE;
- }
-
- /* Check the DRI version */
- DRIQueryVersion(&major, &minor, &patch);
- if (major != DRIINFO_MAJOR_VERSION || minor < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed because of a version "
- "mismatch.\n"
- "[dri] libdri version is %d.%d.%d but version %d.%d.x is "
- "needed.\n"
- "[dri] Disabling DRI.\n",
- major, minor, patch,
- DRIINFO_MAJOR_VERSION, 0);
- return FALSE;
- }
-
- /* Check the lib version */
- if (xf86LoaderCheckSymbol("drmGetLibVersion"))
- info->pLibDRMVersion = drmGetLibVersion(info->drmFD);
- if (info->pLibDRMVersion == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed because libDRM is really "
- "way to old to even get a version number out of it.\n"
- "[dri] Disabling DRI.\n");
- return FALSE;
- }
- if (info->pLibDRMVersion->version_major != 1 ||
- info->pLibDRMVersion->version_minor < 2) {
- /* incompatible drm library version */
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed because of a "
- "version mismatch.\n"
- "[dri] libdrm.a module version is %d.%d.%d but "
- "version 1.2.x is needed.\n"
- "[dri] Disabling DRI.\n",
- info->pLibDRMVersion->version_major,
- info->pLibDRMVersion->version_minor,
- info->pLibDRMVersion->version_patchlevel);
- drmFreeVersion(info->pLibDRMVersion);
- info->pLibDRMVersion = NULL;
- return FALSE;
- }
-
- /* Create a bus Id */
- if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
- busId = DRICreatePCIBusID(info->PciInfo);
- } else {
- busId = xalloc(64);
- sprintf(busId,
- "PCI:%d:%d:%d",
- PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
- }
-
- /* Low level DRM open */
- fd = drmOpen(RADEON_DRIVER_NAME, busId);
- xfree(busId);
- if (fd < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed to open the DRM\n"
- "[dri] Disabling DRI.\n");
- return FALSE;
- }
-
- /* Get DRM version & close DRM */
- info->pKernelDRMVersion = drmGetVersion(fd);
- drmClose(fd);
- if (info->pKernelDRMVersion == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed to get the DRM version\n"
- "[dri] Disabling DRI.\n");
- return FALSE;
- }
-
- /* Now check if we qualify */
- if (info->ChipFamily >= CHIP_FAMILY_R300) {
- req_minor = 17;
- req_patch = 0;
- } else if (info->IsIGP) {
- req_minor = 10;
- req_patch = 0;
- } else { /* Many problems have been reported with 1.7 in the 2.4 kernel */
- req_minor = 8;
- req_patch = 0;
- }
-
- /* We don't, bummer ! */
- if (info->pKernelDRMVersion->version_major != 1 ||
- info->pKernelDRMVersion->version_minor < req_minor ||
- (info->pKernelDRMVersion->version_minor == req_minor &&
- info->pKernelDRMVersion->version_patchlevel < req_patch)) {
- /* Incompatible drm version */
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[dri] RADEONDRIGetVersion failed because of a version "
- "mismatch.\n"
- "[dri] radeon.o kernel module version is %d.%d.%d "
- "but version 1.%d.%d or newer is needed.\n"
- "[dri] Disabling DRI.\n",
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel,
- req_minor,
- req_patch);
- drmFreeVersion(info->pKernelDRMVersion);
- info->pKernelDRMVersion = NULL;
- return FALSE;
- }
-
- return TRUE;
-}
-
-Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int value = 0;
-
- if (!info->want_vblank_interrupts)
- on = FALSE;
-
- if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor >= 28) {
- if (on) {
- if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled)
- value = DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2;
- else
- value = DRM_RADEON_VBLANK_CRTC1;
- }
-
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_VBLANK_CRTC, value)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RADEON Vblank Crtc Setup Failed %d\n", value);
- return FALSE;
- }
- }
- return TRUE;
-}
-
-
-/* Initialize the screen-specific data structures for the DRI and the
- * Radeon. This is the main entry point to the device-specific
- * initialization code. It calls device-independent DRI functions to
- * create the DRI data structures and initialize the DRI state.
- */
-Bool RADEONDRIScreenInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- DRIInfoPtr pDRIInfo;
- RADEONDRIPtr pRADEONDRI;
-
- info->DRICloseScreen = NULL;
-
- switch (info->CurrentLayout.pixel_code) {
- case 8:
- case 15:
- case 24:
- /* These modes are not supported (yet). */
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] RADEONInitVisualConfigs failed "
- "(depth %d not supported). "
- "Disabling DRI.\n", info->CurrentLayout.pixel_code);
- return FALSE;
-
- /* Only 16 and 32 color depths are supports currently. */
- case 16:
- case 32:
- break;
- }
-
- radeon_drm_page_size = getpagesize();
-
- /* Create the DRI data structure, and fill it in before calling the
- * DRIScreenInit().
- */
- if (!(pDRIInfo = DRICreateInfoRec())) return FALSE;
-
- info->pDRIInfo = pDRIInfo;
- pDRIInfo->drmDriverName = RADEON_DRIVER_NAME;
-
- if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) {
- pDRIInfo->clientDriverName = R300_DRIVER_NAME;
- } else
- if ( info->ChipFamily >= CHIP_FAMILY_R200 )
- pDRIInfo->clientDriverName = R200_DRIVER_NAME;
- else
- pDRIInfo->clientDriverName = RADEON_DRIVER_NAME;
-
- if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
- pDRIInfo->busIdString = DRICreatePCIBusID(info->PciInfo);
- } else {
- pDRIInfo->busIdString = xalloc(64);
- sprintf(pDRIInfo->busIdString,
- "PCI:%d:%d:%d",
- PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
- }
- pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ?
- RADEON_VERSION_MAJOR_TILED : RADEON_VERSION_MAJOR;
- pDRIInfo->ddxDriverMinorVersion = RADEON_VERSION_MINOR;
- pDRIInfo->ddxDriverPatchVersion = RADEON_VERSION_PATCH;
- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->frontOffset;
- pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize;
- pDRIInfo->frameBufferStride = (pScrn->displayWidth *
- info->CurrentLayout.pixel_bytes);
- pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES;
- pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES
- < RADEON_MAX_DRAWABLES
- ? SAREA_MAX_DRAWABLES
- : RADEON_MAX_DRAWABLES);
- /* kill DRIAdjustFrame. We adjust sarea frame info ourselves to work
- correctly with pageflip + mergedfb/color tiling */
- pDRIInfo->wrap.AdjustFrame = NULL;
-
-#ifdef PER_CONTEXT_SAREA
- /* This is only here for testing per-context SAREAs. When used, the
- magic number below would be properly defined in a header file. */
- info->perctx_sarea_size = 64 * 1024;
-#endif
-
-#ifdef NOT_DONE
- /* FIXME: Need to extend DRI protocol to pass this size back to
- * client for SAREA mapping that includes a device private record
- */
- pDRIInfo->SAREASize = ((sizeof(XF86DRISAREARec) + 0xfff)
- & 0x1000); /* round to page */
- /* + shared memory device private rec */
-#else
- /* For now the mapping works by using a fixed size defined
- * in the SAREA header
- */
- if (sizeof(XF86DRISAREARec)+sizeof(RADEONSAREAPriv) > SAREA_MAX) {
- ErrorF("Data does not fit in SAREA\n");
- return FALSE;
- }
- pDRIInfo->SAREASize = SAREA_MAX;
-#endif
-
- if (!(pRADEONDRI = (RADEONDRIPtr)xcalloc(sizeof(RADEONDRIRec),1))) {
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
- return FALSE;
- }
- pDRIInfo->devPrivate = pRADEONDRI;
- pDRIInfo->devPrivateSize = sizeof(RADEONDRIRec);
- pDRIInfo->contextSize = sizeof(RADEONDRIContextRec);
-
- pDRIInfo->CreateContext = RADEONCreateContext;
- pDRIInfo->DestroyContext = RADEONDestroyContext;
- pDRIInfo->SwapContext = RADEONDRISwapContext;
- pDRIInfo->InitBuffers = RADEONDRIInitBuffers;
- pDRIInfo->MoveBuffers = RADEONDRIMoveBuffers;
- pDRIInfo->bufferRequests = DRI_ALL_WINDOWS;
- pDRIInfo->TransitionTo2d = RADEONDRITransitionTo2d;
- pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d;
- pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d;
- pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d;
-#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \
- (DRIINFO_MAJOR_VERSION == 5 && \
- DRIINFO_MINOR_VERSION >= 1))
- pDRIInfo->ClipNotify = RADEONDRIClipNotify;
-#endif
-
- pDRIInfo->createDummyCtx = TRUE;
- pDRIInfo->createDummyCtxPriv = FALSE;
-
-#ifdef USE_EXA
- if (info->useEXA) {
-#if DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3
- int major, minor, patch;
-
- DRIQueryVersion(&major, &minor, &patch);
-
- if (minor >= 3)
-#endif
-#if DRIINFO_MAJOR_VERSION > 5 || \
- (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3)
- pDRIInfo->texOffsetStart = RADEONTexOffsetStart;
-#endif
- }
-#endif
-
- if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[dri] DRIScreenInit failed. Disabling DRI.\n");
- xfree(pDRIInfo->devPrivate);
- pDRIInfo->devPrivate = NULL;
- DRIDestroyInfoRec(pDRIInfo);
- pDRIInfo = NULL;
- return FALSE;
- }
- /* Initialize AGP */
- if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[agp] AGP failed to initialize. Disabling the DRI.\n" );
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] You may want to make sure the agpgart kernel "
- "module\nis loaded before the radeon kernel module.\n");
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize PCI */
- if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
- "[pci] PCI failed to initialize. Disabling the DRI.\n" );
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* DRIScreenInit doesn't add all the
- * common mappings. Add additional
- * mappings here.
- */
- if (!RADEONDRIMapInit(info, pScreen)) {
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* DRIScreenInit adds the frame buffer
- map, but we need it as well */
- {
- void *scratch_ptr;
- int scratch_int;
-
- DRIGetDeviceInfo(pScreen, &info->fbHandle,
- &scratch_int, &scratch_int,
- &scratch_int, &scratch_int,
- &scratch_ptr);
- }
-
- /* FIXME: When are these mappings unmapped? */
-
- if (!RADEONInitVisualConfigs(pScreen)) {
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n");
-
- return TRUE;
-}
-
-static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- RADEONDRICloseScreen(pScreen);
-
- pScreen->CloseScreen = info->DRICloseScreen;
- return (*pScreen->CloseScreen)(scrnIndex, pScreen);
-}
-
-/* Finish initializing the device-dependent DRI state, and call
- * DRIFinishScreenInit() to complete the device-independent DRI
- * initialization.
- */
-Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSAREAPrivPtr pSAREAPriv;
- RADEONDRIPtr pRADEONDRI;
-
- info->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
- /* info->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
-
- /* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit
- * because *DRIKernelInit requires that the hardware lock is held by
- * the X server, and the first time the hardware lock is grabbed is
- * in DRIFinishScreenInit.
- */
- if (!DRIFinishScreenInit(pScreen)) {
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize the kernel data structures */
- if (!RADEONDRIKernelInit(info, pScreen)) {
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize the vertex buffers list */
- if (!RADEONDRIBufInit(info, pScreen)) {
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
- /* Initialize IRQ */
- RADEONDRIIrqInit(info, pScreen);
-
- /* Initialize kernel GART memory manager */
- RADEONDRIGartHeapInit(info, pScreen);
-
- /* Initialize and start the CP if required */
- RADEONDRICPInit(pScrn);
-
- /* Initialize the SAREA private data structure */
- pSAREAPriv = (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
- memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
- pRADEONDRI = (RADEONDRIPtr)info->pDRIInfo->devPrivate;
-
- pRADEONDRI->deviceID = info->Chipset;
- pRADEONDRI->width = pScrn->virtualX;
- pRADEONDRI->height = pScrn->virtualY;
- pRADEONDRI->depth = pScrn->depth;
- pRADEONDRI->bpp = pScrn->bitsPerPixel;
-
- pRADEONDRI->IsPCI = (info->cardType!=CARD_AGP);
- pRADEONDRI->AGPMode = info->agpMode;
-
- pRADEONDRI->frontOffset = info->frontOffset;
- pRADEONDRI->frontPitch = info->frontPitch;
- pRADEONDRI->backOffset = info->backOffset;
- pRADEONDRI->backPitch = info->backPitch;
- pRADEONDRI->depthOffset = info->depthOffset;
- pRADEONDRI->depthPitch = info->depthPitch;
- pRADEONDRI->textureOffset = info->textureOffset;
- pRADEONDRI->textureSize = info->textureSize;
- pRADEONDRI->log2TexGran = info->log2TexGran;
-
- pRADEONDRI->registerHandle = info->registerHandle;
- pRADEONDRI->registerSize = info->registerSize;
-
- pRADEONDRI->statusHandle = info->ringReadPtrHandle;
- pRADEONDRI->statusSize = info->ringReadMapSize;
-
- pRADEONDRI->gartTexHandle = info->gartTexHandle;
- pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
- pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
- pRADEONDRI->gartTexOffset = info->gartTexStart;
-
- pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
-
-#ifdef PER_CONTEXT_SAREA
- /* Set per-context SAREA size */
- pRADEONDRI->perctx_sarea_size = info->perctx_sarea_size;
-#endif
-
- info->directRenderingInited = TRUE;
-
- /* Wrap CloseScreen */
- info->DRICloseScreen = pScreen->CloseScreen;
- pScreen->CloseScreen = RADEONDRIDoCloseScreen;
-
- /* disable vblank at startup */
- RADEONDRISetVBlankInterrupt (pScrn, FALSE);
-
- return TRUE;
-}
-
-/**
- * This function will attempt to get the Radeon hardware back into shape
- * after a resume from disc.
- *
- * Charl P. Botha <http://cpbotha.net>
- */
-void RADEONDRIResume(ScreenPtr pScreen)
-{
- int _ret;
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (info->pKernelDRMVersion->version_minor >= 9) {
- xf86DrvMsg(pScreen->myNum, X_INFO,
- "[RESUME] Attempting to re-init Radeon hardware.\n");
- } else {
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "[RESUME] Cannot re-init Radeon hardware, DRM too old\n"
- "(need 1.9.0 or newer)\n");
- return;
- }
-
- if (info->cardType==CARD_AGP) {
- if (!RADEONSetAgpMode(info, pScreen))
- return;
-
- RADEONSetAgpBase(info);
- }
-
- _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME);
- if (_ret) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "%s: CP resume %d\n", __FUNCTION__, _ret);
- /* FIXME: return? */
- }
-
- RADEONEngineRestore(pScrn);
-
- RADEONDRICPInit(pScrn);
-}
-
-void RADEONDRIStop(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RING_LOCALS;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONDRIStop\n");
-
- /* Stop the CP */
- if (info->directRenderingInited) {
- /* If we've generated any CP commands, we must flush them to the
- * kernel module now.
- */
- RADEONCP_RELEASE(pScrn, info);
- RADEONCP_STOP(pScrn, info);
- }
- info->directRenderingInited = FALSE;
-}
-
-/* The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- */
-void RADEONDRICloseScreen(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- drmRadeonInit drmInfo;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONDRICloseScreen\n");
-
-#ifdef DAMAGE
- REGION_UNINIT(pScreen, &info->driRegion);
-#endif
-
- if (info->irq) {
- RADEONDRISetVBlankInterrupt (pScrn, FALSE);
- drmCtlUninstHandler(info->drmFD);
- info->irq = 0;
- info->ModeReg->gen_int_cntl = 0;
- }
-
- /* De-allocate vertex buffers */
- if (info->buffers) {
- drmUnmapBufs(info->buffers);
- info->buffers = NULL;
- }
-
- /* De-allocate all kernel resources */
- memset(&drmInfo, 0, sizeof(drmRadeonInit));
- drmInfo.func = DRM_RADEON_CLEANUP_CP;
- drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT,
- &drmInfo, sizeof(drmRadeonInit));
-
- /* De-allocate all GART resources */
- if (info->gartTex) {
- drmUnmap(info->gartTex, info->gartTexMapSize);
- info->gartTex = NULL;
- }
- if (info->buf) {
- drmUnmap(info->buf, info->bufMapSize);
- info->buf = NULL;
- }
- if (info->ringReadPtr) {
- drmUnmap(info->ringReadPtr, info->ringReadMapSize);
- info->ringReadPtr = NULL;
- }
- if (info->ring) {
- drmUnmap(info->ring, info->ringMapSize);
- info->ring = NULL;
- }
- if (info->agpMemHandle != DRM_AGP_NO_HANDLE) {
- drmAgpUnbind(info->drmFD, info->agpMemHandle);
- drmAgpFree(info->drmFD, info->agpMemHandle);
- info->agpMemHandle = DRM_AGP_NO_HANDLE;
- drmAgpRelease(info->drmFD);
- }
- if (info->pciMemHandle) {
- drmScatterGatherFree(info->drmFD, info->pciMemHandle);
- info->pciMemHandle = 0;
- }
-
- if (info->pciGartBackup) {
- xfree(info->pciGartBackup);
- info->pciGartBackup = NULL;
- }
-
- /* De-allocate all DRI resources */
- DRICloseScreen(pScreen);
-
- /* De-allocate all DRI data structures */
- if (info->pDRIInfo) {
- if (info->pDRIInfo->devPrivate) {
- xfree(info->pDRIInfo->devPrivate);
- info->pDRIInfo->devPrivate = NULL;
- }
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
- }
- if (info->pVisualConfigs) {
- xfree(info->pVisualConfigs);
- info->pVisualConfigs = NULL;
- }
- if (info->pVisualConfigsPriv) {
- xfree(info->pVisualConfigsPriv);
- info->pVisualConfigsPriv = NULL;
- }
-}
-
-/* Use callbacks from dri.c to support pageflipping mode for a single
- * 3d context without need for any specific full-screen extension.
- *
- * Also use these callbacks to allocate and free 3d-specific memory on
- * demand.
- */
-
-
-#ifdef DAMAGE
-
-/* Use the damage layer to maintain a list of dirty rectangles.
- * These are blitted to the back buffer to keep both buffers clean
- * during page-flipping when the 3d application isn't fullscreen.
- *
- * An alternative to this would be to organize for all on-screen drawing
- * operations to be duplicated for the two buffers. That might be
- * faster, but seems like a lot more work...
- */
-
-
-static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int i, num;
- ScreenPtr pScreen = pScrn->pScreen;
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
-#ifdef USE_EXA
- PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
-#endif
- RegionRec region;
- BoxPtr pbox;
-
- if (!info->directRenderingInited || !info->CPStarted)
- return;
-
- /* Don't want to do this when no 3d is active and pages are
- * right-way-round
- */
- if (!pSAREAPriv->pfAllowPageFlip && pSAREAPriv->pfCurrentPage == 0)
- return;
-
- REGION_NULL(pScreen, ®ion);
- REGION_SUBTRACT(pScreen, ®ion, pReg, &info->driRegion);
-
- num = REGION_NUM_RECTS(®ion);
-
- if (!num) {
- goto out;
- }
-
- pbox = REGION_RECTS(®ion);
-
- /* pretty much a hack. */
-
-#ifdef USE_EXA
- if (info->useEXA) {
- CARD32 src_pitch_offset, dst_pitch_offset, datatype;
-
- RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset);
- dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10);
- RADEONGetDatatypeBpp(pScrn->bitsPerPixel, &datatype);
- info->xdir = info->ydir = 1;
-
- RADEONDoPrepareCopyCP(pScrn, src_pitch_offset, dst_pitch_offset, datatype,
- GXcopy, ~0);
- }
-#endif
-
-#ifdef USE_XAA
- if (!info->useEXA) {
- /* Make sure accel has been properly inited */
- if (info->accel == NULL || info->accel->SetupForScreenToScreenCopy == NULL)
- goto out;
- if (info->tilingEnabled)
- info->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
- (*info->accel->SetupForScreenToScreenCopy)(pScrn,
- 1, 1, GXcopy,
- (CARD32)(-1), -1);
- }
-#endif
-
- for (i = 0 ; i < num ; i++, pbox++) {
- int xa = max(pbox->x1, 0), xb = min(pbox->x2, pScrn->virtualX-1);
- int ya = max(pbox->y1, 0), yb = min(pbox->y2, pScrn->virtualY-1);
-
- if (xa <= xb && ya <= yb) {
-#ifdef USE_EXA
- if (info->useEXA) {
- RADEONCopyCP(pPix, xa, ya, xa, ya, xb - xa + 1, yb - ya + 1);
- }
-#endif
-
-#ifdef USE_XAA
- if (!info->useEXA) {
- (*info->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya,
- xa + info->backX,
- ya + info->backY,
- xb - xa + 1,
- yb - ya + 1);
- }
-#endif
- }
- }
-
-#ifdef USE_XAA
- info->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO;
-#endif
-
-out:
- REGION_NULL(pScreen, ®ion);
- DamageEmpty(info->pDamage);
-}
-
-#endif /* DAMAGE */
-
-static void RADEONEnablePageFlip(ScreenPtr pScreen)
-{
-#ifdef DAMAGE
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (info->allowPageFlip) {
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
- BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1,
- .y2 = pScrn->virtualY - 1 };
- RegionPtr pReg = REGION_CREATE(pScreen, &box, 1);
-
- pSAREAPriv->pfAllowPageFlip = 1;
- RADEONDRIRefreshArea(pScrn, pReg);
- REGION_DESTROY(pScreen, pReg);
- }
-#endif
-}
-
-static void RADEONDisablePageFlip(ScreenPtr pScreen)
-{
- /* Tell the clients not to pageflip. How?
- * -- Field in sarea, plus bumping the window counters.
- * -- DRM needs to cope with Front-to-Back swapbuffers.
- */
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
-
- pSAREAPriv->pfAllowPageFlip = 0;
-}
-
-static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen)
-{
- RADEONDisablePageFlip(pScreen);
-}
-
-static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen)
-{
- /* Let the remaining 3d app start page flipping again */
- RADEONEnablePageFlip(pScreen);
-}
-
-static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#ifdef USE_XAA
- FBAreaPtr fbarea;
- int width, height;
-
- /* EXA allocates these areas up front, so it doesn't do the following
- * stuff.
- */
- if (!info->useEXA) {
- /* reserve offscreen area for back and depth buffers and textures */
-
- /* If we still have an area for the back buffer reserved, free it
- * first so we always start with all free offscreen memory, except
- * maybe for Xv
- */
- if (info->backArea) {
- xf86FreeOffscreenArea(info->backArea);
- info->backArea = NULL;
- }
-
- xf86PurgeUnlockedOffscreenAreas(pScreen);
-
- xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0);
-
- /* Free Xv linear offscreen memory if necessary
- * FIXME: This is hideous. What about telling xv "oh btw you have no memory
- * any more?" -- anholt
- */
- if (height < (info->depthTexLines + info->backLines)) {
- RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr;
- xf86FreeOffscreenLinear((FBLinearPtr)portPriv->video_memory);
- portPriv->video_memory = NULL;
- xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0);
- }
-
- /* Reserve placeholder area so the other areas will match the
- * pre-calculated offsets
- * FIXME: We may have other locked allocations and thus this would allocate
- * in the wrong place. The XV surface allocations seem likely. -- anholt
- */
- fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
- height
- - info->depthTexLines
- - info->backLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!fbarea)
- xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve placeholder "
- "offscreen area, you might experience screen corruption\n");
-
- info->backArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
- info->backLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!info->backArea)
- xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen "
- "area for back buffer, you might experience screen "
- "corruption\n");
-
- info->depthTexArea = xf86AllocateOffscreenArea(pScreen,
- pScrn->displayWidth,
- info->depthTexLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!info->depthTexArea)
- xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen "
- "area for depth buffer and textures, you might "
- "experience screen corruption\n");
-
- xf86FreeOffscreenArea(fbarea);
- }
-#endif /* USE_XAA */
-
- info->have3DWindows = 1;
-
- RADEONChangeSurfaces(pScrn);
- RADEONEnablePageFlip(pScreen);
-
- info->want_vblank_interrupts = TRUE;
- RADEONDRISetVBlankInterrupt(pScrn, TRUE);
-
- if (info->cursor)
- xf86ForceHWCursor (pScreen, TRUE);
-}
-
-static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
-
- /* Try flipping back to the front page if necessary */
- if (pSAREAPriv->pfCurrentPage == 1)
- drmCommandNone(info->drmFD, DRM_RADEON_FLIP);
-
- /* Shut down shadowing if we've made it back to the front page */
- if (pSAREAPriv->pfCurrentPage == 0) {
- RADEONDisablePageFlip(pScreen);
-#ifdef USE_XAA
- if (!info->useEXA) {
- xf86FreeOffscreenArea(info->backArea);
- info->backArea = NULL;
- }
-#endif
- } else {
- xf86DrvMsg(pScreen->myNum, X_WARNING,
- "[dri] RADEONDRITransitionTo2d: "
- "kernel failed to unflip buffers.\n");
- }
-
-#ifdef USE_XAA
- if (!info->useEXA)
- xf86FreeOffscreenArea(info->depthTexArea);
-#endif
-
- info->have3DWindows = 0;
-
- RADEONChangeSurfaces(pScrn);
-
- info->want_vblank_interrupts = FALSE;
- RADEONDRISetVBlankInterrupt(pScrn, FALSE);
-
- if (info->cursor)
- xf86ForceHWCursor (pScreen, FALSE);
-}
-
-#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \
- (DRIINFO_MAJOR_VERSION == 5 && \
- DRIINFO_MINOR_VERSION >= 1))
-static void
-RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- REGION_UNINIT(pScreen, &info->driRegion);
- REGION_NULL(pScreen, &info->driRegion);
-
- if (num > 0) {
- int i;
-
- for (i = 0; i < num; i++) {
- WindowPtr pWin = ppWin[i];
-
- if (pWin) {
- REGION_UNION(pScreen, &info->driRegion, &pWin->clipList,
- &info->driRegion);
- }
- }
- }
-}
-#endif
-
-void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (info->cardType != CARD_PCIE ||
- info->pKernelDRMVersion->version_minor < 19)
- return;
-
- if (info->FbSecureSize==0)
- return;
-
- /* set the old default size of pci gart table */
- if (info->pKernelDRMVersion->version_minor < 26)
- info->pciGartSize = 32768;
-
- info->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn);
-
- /* allocate space to back up PCIEGART table */
- info->pciGartBackup = xnfcalloc(1, info->pciGartSize);
- if (info->pciGartBackup == NULL)
- return;
-
- info->pciGartOffset = (info->FbMapSize - info->FbSecureSize);
-
-
-}
-
-int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int page_size = getpagesize();
- int ret_size;
- int num_pages;
-
- num_pages = (info->pciAperSize * 1024 * 1024) / page_size;
-
- ret_size = num_pages * sizeof(unsigned int);
-
- return ret_size;
-}
-
-int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
-{
- drmRadeonSetParam radeonsetparam;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int ret;
-
- memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
- radeonsetparam.param = param;
- radeonsetparam.value = value;
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
- &radeonsetparam, sizeof(drmRadeonSetParam));
- return ret;
-}
diff --git a/src/radeon_dri.h b/src/radeon_dri.h
deleted file mode 100644
index 3b54626..0000000
--- a/src/radeon_dri.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- *
- */
-
-#ifndef _RADEON_DRI_
-#define _RADEON_DRI_
-
-#include "xf86drm.h"
-
-/* DRI Driver defaults */
-#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
-#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM
-#define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */
-#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */
-
-#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */
-
-#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
-
-#define RADEON_CARD_TYPE_RADEON 1
-
-#define RADEONCP_USE_RING_BUFFER(m) \
- (((m) == RADEON_CSQ_PRIBM_INDDIS) || \
- ((m) == RADEON_CSQ_PRIBM_INDBM))
-
-typedef struct {
- /* DRI screen private data */
- int deviceID; /* PCI device ID */
- int width; /* Width in pixels of display */
- int height; /* Height in scanlines of display */
- int depth; /* Depth of display (8, 15, 16, 24) */
- int bpp; /* Bit depth of display (8, 16, 24, 32) */
-
- int IsPCI; /* Current card is a PCI card */
- int AGPMode;
-
- int frontOffset; /* Start of front buffer */
- int frontPitch;
- int backOffset; /* Start of shared back buffer */
- int backPitch;
- int depthOffset; /* Start of shared depth buffer */
- int depthPitch;
- int textureOffset;/* Start of texture data in frame buffer */
- int textureSize;
- int log2TexGran;
-
- /* MMIO register data */
- drm_handle_t registerHandle;
- drmSize registerSize;
-
- /* CP in-memory status information */
- drm_handle_t statusHandle;
- drmSize statusSize;
-
- /* CP GART Texture data */
- drm_handle_t gartTexHandle;
- drmSize gartTexMapSize;
- int log2GARTTexGran;
- int gartTexOffset;
- unsigned int sarea_priv_offset;
-
-#ifdef PER_CONTEXT_SAREA
- drmSize perctx_sarea_size;
-#endif
-} RADEONDRIRec, *RADEONDRIPtr;
-
-#endif
diff --git a/src/radeon_dripriv.h b/src/radeon_dripriv.h
deleted file mode 100644
index fcde08e..0000000
--- a/src/radeon_dripriv.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- *
- */
-
-#ifndef _RADEON_DRIPRIV_H_
-#define _RADEON_DRIPRIV_H_
-
-#include "GL/glxint.h"
-#include "xf86drm.h"
-#include "radeon_common.h"
-
-#define RADEON_MAX_DRAWABLES 256
-
-extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs,
- void **configprivs);
-
-typedef struct {
- /* Nothing here yet */
- int dummy;
-} RADEONConfigPrivRec, *RADEONConfigPrivPtr;
-
-typedef struct {
-#ifdef PER_CONTEXT_SAREA
- drm_context_t ctx_id;
- drm_handle_t sarea_handle;
-#else
- /* Nothing here yet */
- int dummy;
-#endif
-} RADEONDRIContextRec, *RADEONDRIContextPtr;
-
-#endif
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
deleted file mode 100644
index 5cf8d51..0000000
--- a/src/radeon_driver.c
+++ /dev/null
@@ -1,5478 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- *
- * Credits:
- *
- * Thanks to Ani Joshi <ajoshi at shell.unixbox.com> for providing source
- * code to his Radeon driver. Portions of this file are based on the
- * initialization code for that driver.
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- * This server does not yet support these XFree86 4.0 features:
- * !!!! FIXME !!!!
- * DDC1 & DDC2
- * shadowfb
- * overlay planes
- *
- * Modified by Marc Aurele La France (tsi at xfree86.org) for ATI driver merge.
- *
- * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f at yahoo.com)
- * based on the sis driver by Thomas Winischhofer.
- *
- */
-
-#include <string.h>
-#include <stdio.h>
-
- /* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#include "radeon_atombios.h"
-
-#ifdef XF86DRI
-#define _XF86DRI_SERVER_
-#include "radeon_dri.h"
-#include "radeon_sarea.h"
-#include "sarea.h"
-#endif
-
-#include "fb.h"
-
- /* colormap initialization */
-#include "micmap.h"
-#include "dixstruct.h"
-
- /* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "xf86RAC.h"
-#include "xf86RandR12.h"
-#include "xf86Resources.h"
-#include "xf86cmap.h"
-#include "vbe.h"
-
-#include "shadow.h"
- /* vgaHW definitions */
-#ifdef WITH_VGAHW
-#include "vgaHW.h"
-#endif
-
-#define DPMS_SERVER
-#include <X11/extensions/dpms.h>
-
-#include "atipciids.h"
-#include "radeon_chipset_gen.h"
-
-
-#include "radeon_chipinfo_gen.h"
-
- /* Forward definitions for driver functions */
-static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen);
-static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode);
-static void RADEONSave(ScrnInfoPtr pScrn);
-
-static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode);
-static void RADEONForceSomeClocks(ScrnInfoPtr pScrn);
-static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-
-#ifdef XF86DRI
-static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-#endif
-
-extern DisplayModePtr
-RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
-
-extern void
-RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-
-#ifdef USE_XAA
-#ifdef XF86DRI
-extern Bool
-RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
-#endif /* XF86DRI */
-extern Bool
-RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
-#endif /* USE_XAA */
-
-static const OptionInfoRec RADEONOptions[] = {
- { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE },
-#ifdef XF86DRI
- { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE },
- { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE },
- { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE },
- { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE },
- { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE },
- { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE },
- { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE },
-#ifdef USE_EXA
- { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE },
-#endif
-#endif
- { OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE },
- { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE },
- { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE },
- { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE },
-#ifdef XvExtension
- { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE },
- { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE },
- { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE },
- { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE },
- { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE },
-#endif
-#ifdef RENDER
- { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE },
-#endif
- { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE },
- { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE },
- { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE },
- { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE },
-#if defined(__powerpc__)
- { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE },
-#endif
- { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE },
- { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE },
- { -1, NULL, OPTV_NONE, {0}, FALSE }
-};
-
-const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; }
-
-static int getRADEONEntityIndex(void)
-{
- int *radeon_entity_index = LoaderSymbol("gRADEONEntityIndex");
- if (!radeon_entity_index)
- return -1;
- else
- return *radeon_entity_index;
-}
-
-struct RADEONInt10Save {
- CARD32 MEM_CNTL;
- CARD32 MEMSIZE;
- CARD32 MPP_TB_CONFIG;
-};
-
-static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
-static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn);
-
-static void *
-radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
- CARD32 *size, void *closure)
-{
- ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int stride;
-
- stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
- *size = stride;
-
- return ((CARD8 *)info->FB + pScrn->fbOffset +
- row * stride + offset);
-}
-static Bool
-RADEONCreateScreenResources (ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- PixmapPtr pixmap;
-
- pScreen->CreateScreenResources = info->CreateScreenResources;
- if (!(*pScreen->CreateScreenResources)(pScreen))
- return FALSE;
- pScreen->CreateScreenResources = RADEONCreateScreenResources;
-
- if (info->r600_shadow_fb) {
- pixmap = pScreen->GetScreenPixmap(pScreen);
-
- if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
- radeonShadowWindow, 0, NULL))
- return FALSE;
- }
- return TRUE;
-}
-
-RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
-{
- DevUnion *pPriv;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- pPriv = xf86GetEntityPrivate(info->pEnt->index,
- getRADEONEntityIndex());
- return pPriv->ptr;
-}
-
-static void
-RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 CardTmp;
- static struct RADEONInt10Save SaveStruct = { 0, 0, 0 };
-
- if (!IS_AVIVO_VARIANT) {
- /* Save the values and zap MEM_CNTL */
- SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
- SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
- SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
-
- /*
- * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
- */
- OUTREG(RADEON_MEM_CNTL, 0);
- CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu;
- CardTmp |= 0x04 << 24;
- OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
- }
-
- *pPtr = (void *)&SaveStruct;
-}
-
-static void
-RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- struct RADEONInt10Save *pSave = ptr;
- CARD32 CardTmp;
-
- /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */
- if (!pSave || !pSave->MEM_CNTL)
- return;
-
- if (IS_AVIVO_VARIANT)
- return;
-
- /*
- * If either MEM_CNTL is currently zero or inconistent (configured for
- * two channels with the two channels configured differently), restore
- * the saved registers.
- */
- CardTmp = INREG(RADEON_MEM_CNTL);
- if (!CardTmp ||
- ((CardTmp & 1) &&
- (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) {
- /* Restore the saved registers */
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring MEM_CNTL (%08lx), setting to %08lx\n",
- (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL);
- OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL);
-
- CardTmp = INREG(RADEON_CONFIG_MEMSIZE);
- if (CardTmp != pSave->MEMSIZE) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n",
- (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE);
- OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE);
- }
- }
-
- CardTmp = INREG(RADEON_MPP_TB_CONFIG);
- if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n",
- (unsigned long)CardTmp >> 24,
- (unsigned long)pSave->MPP_TB_CONFIG >> 24);
- CardTmp &= 0x00ffffffu;
- CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u);
- OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
- }
-}
-
-/* Allocate our private RADEONInfoRec */
-static Bool RADEONGetRec(ScrnInfoPtr pScrn)
-{
- if (pScrn->driverPrivate) return TRUE;
-
- pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1);
- return TRUE;
-}
-
-/* Free our private RADEONInfoRec */
-static void RADEONFreeRec(ScrnInfoPtr pScrn)
-{
- if (!pScrn || !pScrn->driverPrivate) return;
- xfree(pScrn->driverPrivate);
- pScrn->driverPrivate = NULL;
-}
-
-/* Memory map the MMIO region. Used during pre-init and by RADEONMapMem,
- * below
- */
-static Bool RADEONMapMMIO(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifndef XSERVER_LIBPCIACCESS
-
- info->MMIO = xf86MapPciMem(pScrn->scrnIndex,
- VIDMEM_MMIO | VIDMEM_READSIDEEFFECT,
- info->PciTag,
- info->MMIOAddr,
- info->MMIOSize);
-
- if (!info->MMIO) return FALSE;
-
-#else
-
- void** result = (void**)&info->MMIO;
- int err = pci_device_map_range(info->PciInfo,
- info->MMIOAddr,
- info->MMIOSize,
- PCI_DEV_MAP_FLAG_WRITABLE,
- result);
-
- if (err) {
- xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
- "Unable to map MMIO aperture. %s (%d)\n",
- strerror (err), err);
- return FALSE;
- }
-
-#endif
-
- return TRUE;
-}
-
-/* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem,
- * below
- */
-static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifndef XSERVER_LIBPCIACCESS
- xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize);
-#else
- pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize);
-#endif
-
- info->MMIO = NULL;
- return TRUE;
-}
-
-/* Memory map the frame buffer. Used by RADEONMapMem, below. */
-static Bool RADEONMapFB(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize);
-
-#ifndef XSERVER_LIBPCIACCESS
-
- info->FB = xf86MapPciMem(pScrn->scrnIndex,
- VIDMEM_FRAMEBUFFER,
- info->PciTag,
- info->LinearAddr,
- info->FbMapSize);
-
- if (!info->FB) return FALSE;
-
-#else
-
- int err = pci_device_map_range(info->PciInfo,
- info->LinearAddr,
- info->FbMapSize,
- PCI_DEV_MAP_FLAG_WRITABLE |
- PCI_DEV_MAP_FLAG_WRITE_COMBINE,
- &info->FB);
-
- if (err) {
- xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
- "Unable to map FB aperture. %s (%d)\n",
- strerror (err), err);
- return FALSE;
- }
-
-#endif
-
- return TRUE;
-}
-
-/* Unmap the frame buffer. Used by RADEONUnmapMem, below. */
-static Bool RADEONUnmapFB(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifndef XSERVER_LIBPCIACCESS
- xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize);
-#else
- pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize);
-#endif
-
- info->FB = NULL;
- return TRUE;
-}
-
-/* Memory map the MMIO region and the frame buffer */
-static Bool RADEONMapMem(ScrnInfoPtr pScrn)
-{
- if (!RADEONMapMMIO(pScrn)) return FALSE;
- if (!RADEONMapFB(pScrn)) {
- RADEONUnmapMMIO(pScrn);
- return FALSE;
- }
- return TRUE;
-}
-
-/* Unmap the MMIO region and the frame buffer */
-static Bool RADEONUnmapMem(ScrnInfoPtr pScrn)
-{
- if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE;
- return TRUE;
-}
-
-void RADEONPllErrataAfterIndex(RADEONInfoPtr info)
-{
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
- return;
-
- /* This workaround is necessary on rv200 and RS200 or PLL
- * reads may return garbage (among others...)
- */
- (void)INREG(RADEON_CLOCK_CNTL_DATA);
- (void)INREG(RADEON_CRTC_GEN_CNTL);
-}
-
-void RADEONPllErrataAfterData(RADEONInfoPtr info)
-{
- unsigned char *RADEONMMIO = info->MMIO;
-
- /* This workarounds is necessary on RV100, RS100 and RS200 chips
- * or the chip could hang on a subsequent access
- */
- if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) {
- /* we can't deal with posted writes here ... */
- usleep(5000);
- }
-
- /* This function is required to workaround a hardware bug in some (all?)
- * revisions of the R300. This workaround should be called after every
- * CLOCK_CNTL_INDEX register access. If not, register reads afterward
- * may not be correct.
- */
- if (info->ChipErrata & CHIP_ERRATA_R300_CG) {
- CARD32 save, tmp;
-
- save = INREG(RADEON_CLOCK_CNTL_INDEX);
- tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
- OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
- tmp = INREG(RADEON_CLOCK_CNTL_DATA);
- OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
- }
-}
-
-/* Read PLL register */
-unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 data;
-
- OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
- RADEONPllErrataAfterIndex(info);
- data = INREG(RADEON_CLOCK_CNTL_DATA);
- RADEONPllErrataAfterData(info);
-
- return data;
-}
-
-/* Write PLL information */
-void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
- RADEON_PLL_WR_EN));
- RADEONPllErrataAfterIndex(info);
- OUTREG(RADEON_CLOCK_CNTL_DATA, data);
- RADEONPllErrataAfterData(info);
-}
-
-/* Read MC register */
-unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 data;
-
- if (info->ChipFamily == CHIP_FAMILY_RS690)
- {
- OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
- data = INREG(RS690_MC_DATA);
- } else if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
- (void)INREG(AVIVO_MC_INDEX);
- data = INREG(AVIVO_MC_DATA);
-
- OUTREG(AVIVO_MC_INDEX, 0);
- (void)INREG(AVIVO_MC_INDEX);
- } else {
- OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
- (void)INREG(R300_MC_IND_INDEX);
- data = INREG(R300_MC_IND_DATA);
-
- OUTREG(R300_MC_IND_INDEX, 0);
- (void)INREG(R300_MC_IND_INDEX);
- }
-
- return data;
-}
-
-/* Write MC information */
-void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->ChipFamily == CHIP_FAMILY_RS690)
- {
- OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) |
- RS690_MC_INDEX_WR_EN));
- OUTREG(RS690_MC_DATA, data);
- OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
- } else if (IS_AVIVO_VARIANT) {
- OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
- (void)INREG(AVIVO_MC_INDEX);
- OUTREG(AVIVO_MC_DATA, data);
- OUTREG(AVIVO_MC_INDEX, 0);
- (void)INREG(AVIVO_MC_INDEX);
- } else {
- OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) |
- R300_MC_IND_WR_EN));
- (void)INREG(R300_MC_IND_INDEX);
- OUTREG(R300_MC_IND_DATA, data);
- OUTREG(R300_MC_IND_INDEX, 0);
- (void)INREG(R300_MC_IND_INDEX);
- }
-}
-
-Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- /* no idea where this is on r600 yet */
- return TRUE;
- } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
- if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
- return TRUE;
- else
- return FALSE;
- } else if (info->ChipFamily == CHIP_FAMILY_RS690) {
- if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
- return TRUE;
- else
- return FALSE;
- } else {
- if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
- return TRUE;
- else
- return FALSE;
- }
-}
-
-#define LOC_FB 0x1
-#define LOC_AGP 0x2
-void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- if (mask & LOC_FB)
- OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
- if (mask & LOC_AGP) {
- OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
- OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
- }
- } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
- if (mask & LOC_FB)
- OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc);
- if (mask & LOC_AGP)
- OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc);
- (void)INMC(pScrn, RV515_MC_AGP_LOCATION);
- } else if (info->ChipFamily == CHIP_FAMILY_RS690) {
- if (mask & LOC_FB)
- OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc);
- if (mask & LOC_AGP)
- OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc);
- } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
- if (mask & LOC_FB)
- OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc);
- if (mask & LOC_AGP)
- OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc);
- (void)INMC(pScrn, R520_MC_FB_LOCATION);
- } else {
- if (mask & LOC_FB)
- OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
- if (mask & LOC_AGP)
- OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
- }
-}
-
-void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- if (mask & LOC_FB)
- *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
- if (mask & LOC_AGP) {
- *agp_loc = INREG(R600_MC_VM_AGP_BOT);
- *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
- }
- } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
- if (mask & LOC_FB)
- *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION);
- if (mask & LOC_AGP) {
- *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
- *agp_loc_hi = 0;
- }
- } else if (info->ChipFamily == CHIP_FAMILY_RS690) {
- if (mask & LOC_FB)
- *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION);
- if (mask & LOC_AGP) {
- *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION);
- *agp_loc_hi = 0;
- }
- } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
- if (mask & LOC_FB)
- *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION);
- if (mask & LOC_AGP) {
- *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION);
- *agp_loc_hi = 0;
- }
- } else {
- if (mask & LOC_FB)
- *fb_loc = INREG(RADEON_MC_FB_LOCATION);
- if (mask & LOC_AGP)
- *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
- }
-}
-
-#if 0
-/* Read PAL information (only used for debugging) */
-static int RADEONINPAL(int idx)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_PALETTE_INDEX, idx << 16);
- return INREG(RADEON_PALETTE_DATA);
-}
-#endif
-
-/* Wait for vertical sync on primary CRTC */
-void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 crtc_gen_cntl;
- struct timeval timeout;
-
- crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
- if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
- !(crtc_gen_cntl & RADEON_CRTC_EN))
- return;
-
- /* Clear the CRTC_VBLANK_SAVE bit */
- OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
-
- /* Wait for it to go back up */
- radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT);
- while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) &&
- !radeon_timedout(&timeout))
- usleep(100);
-}
-
-/* Wait for vertical sync on secondary CRTC */
-void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 crtc2_gen_cntl;
- struct timeval timeout;
-
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
- !(crtc2_gen_cntl & RADEON_CRTC2_EN))
- return;
-
- /* Clear the CRTC2_VBLANK_SAVE bit */
- OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
-
- /* Wait for it to go back up */
- radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT);
- while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) &&
- !radeon_timedout(&timeout))
- usleep(100);
-}
-
-
-/* Compute log base 2 of val */
-int RADEONMinBits(int val)
-{
- int bits;
-
- if (!val) return 1;
- for (bits = 0; val; val >>= 1, ++bits);
- return bits;
-}
-
-/* Compute n/d with rounding */
-static int RADEONDiv(int n, int d)
-{
- return (n + (d / 2)) / d;
-}
-
-static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPLLPtr pll = &info->pll;
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned char ppll_div_sel;
- unsigned mpll_fb_div, spll_fb_div, M;
- unsigned xclk, tmp, ref_div;
- int hTotal, vTotal, num, denom, m, n;
- float hz, prev_xtal, vclk, xtal, mpll, spll;
- long total_usecs;
- struct timeval start, stop, to1, to2;
- unsigned int f1, f2, f3;
- int tries = 0;
-
- prev_xtal = 0;
- again:
- xtal = 0;
- if (++tries > 10)
- goto failed;
-
- gettimeofday(&to1, NULL);
- f1 = INREG(RADEON_CRTC_CRNT_FRAME);
- for (;;) {
- f2 = INREG(RADEON_CRTC_CRNT_FRAME);
- if (f1 != f2)
- break;
- gettimeofday(&to2, NULL);
- if ((to2.tv_sec - to1.tv_sec) > 1) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n");
- goto failed;
- }
- }
- gettimeofday(&start, NULL);
- for(;;) {
- f3 = INREG(RADEON_CRTC_CRNT_FRAME);
- if (f3 != f2)
- break;
- gettimeofday(&to2, NULL);
- if ((to2.tv_sec - start.tv_sec) > 1)
- goto failed;
- }
- gettimeofday(&stop, NULL);
-
- if ((stop.tv_sec - start.tv_sec) != 0)
- goto again;
- total_usecs = abs(stop.tv_usec - start.tv_usec);
- if (total_usecs == 0)
- goto again;
- hz = 1000000.0/(float)total_usecs;
-
- hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8;
- vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1);
- vclk = (float)(hTotal * (float)(vTotal * hz));
-
- switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) {
- case 0:
- default:
- num = 1;
- denom = 1;
- break;
- case 1:
- n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff);
- m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff);
- num = 2*n;
- denom = 2*m;
- break;
- case 2:
- n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff);
- m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff);
- num = 2*n;
- denom = 2*m;
- break;
- }
-
- ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
- RADEONPllErrataAfterIndex(info);
-
- n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
- m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff);
-
- num *= n;
- denom *= m;
-
- switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
- case 1:
- denom *= 2;
- break;
- case 2:
- denom *= 4;
- break;
- case 3:
- denom *= 8;
- break;
- case 4:
- denom *= 3;
- break;
- case 6:
- denom *= 6;
- break;
- case 7:
- denom *= 12;
- break;
- }
-
- xtal = (int)(vclk *(float)denom/(float)num);
-
- if ((xtal > 26900000) && (xtal < 27100000))
- xtal = 2700;
- else if ((xtal > 14200000) && (xtal < 14400000))
- xtal = 1432;
- else if ((xtal > 29400000) && (xtal < 29600000))
- xtal = 2950;
- else
- goto again;
- failed:
- if (xtal == 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! "
- "Using default 27Mhz\n");
- xtal = 2700;
- } else {
- if (prev_xtal == 0) {
- prev_xtal = xtal;
- tries = 0;
- goto again;
- } else if (prev_xtal != xtal) {
- prev_xtal = 0;
- goto again;
- }
- }
-
- tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV);
- ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff;
-
- /* Some sanity check based on the BIOS code .... */
- if (ref_div < 2) {
- CARD32 tmp;
- tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV);
- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300)
- || (info->ChipFamily == CHIP_FAMILY_RS400))
- ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
- R300_PPLL_REF_DIV_ACC_SHIFT;
- else
- ref_div = tmp & RADEON_PPLL_REF_DIV_MASK;
- if (ref_div < 2)
- ref_div = 12;
- }
-
- /* Calculate "base" xclk straight from MPLL, though that isn't
- * really useful (hopefully). This isn't called XCLK anymore on
- * radeon's...
- */
- mpll_fb_div = (tmp & 0xff00) >> 8;
- spll_fb_div = (tmp & 0xff0000) >> 16;
- M = (tmp & 0xff);
- xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M));
-
- /*
- * Calculate MCLK based on MCLK-A
- */
- mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M;
- spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M;
-
- tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7;
- switch(tmp) {
- case 1: info->mclk = mpll; break;
- case 2: info->mclk = mpll / 2.0; break;
- case 3: info->mclk = mpll / 4.0; break;
- case 4: info->mclk = mpll / 8.0; break;
- case 7: info->mclk = spll; break;
- default:
- info->mclk = 200.00;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source"
- " setting %d, can't probe MCLK value !\n", tmp);
- }
-
- /*
- * Calculate SCLK
- */
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7;
- switch(tmp) {
- case 1: info->sclk = spll; break;
- case 2: info->sclk = spll / 2.0; break;
- case 3: info->sclk = spll / 4.0; break;
- case 4: info->sclk = spll / 8.0; break;
- case 7: info->sclk = mpll; break;
- default:
- info->sclk = 200.00;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source"
- " setting %d, can't probe SCLK value !\n", tmp);
- }
-
- /* we're done, hopefully these are sane values */
- pll->reference_div = ref_div;
- pll->xclk = xclk;
- pll->reference_freq = xtal;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, "
- "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk);
-
- return TRUE;
-}
-
-static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR (pScrn);
- RADEONPLLPtr pll = &info->pll;
- double min_dotclock;
-
- if (RADEONGetClockInfoFromBIOS(pScrn)) {
- if (pll->reference_div < 2) {
- /* retrive it from register setting for fitting into current PLL algorithm.
- We'll probably need a new routine to calculate the best ref_div from BIOS
- provided min_input_pll and max_input_pll
- */
- CARD32 tmp;
- tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV);
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
- pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
- } else {
- pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
- }
-
- if (pll->reference_div < 2) pll->reference_div = 12;
- }
- } else {
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING,
- "Video BIOS not detected, using default clock settings!\n");
-
- /* Default min/max PLL values */
- if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) {
- pll->pll_in_min = 100;
- pll->pll_in_max = 1350;
- pll->pll_out_min = 20000;
- pll->pll_out_max = 50000;
- } else {
- pll->pll_in_min = 40;
- pll->pll_in_max = 500;
- pll->pll_out_min = 12500;
- pll->pll_out_max = 35000;
- }
-
- if (!RADEONProbePLLParameters(pScrn)) {
- if (info->IsIGP)
- pll->reference_freq = 1432;
- else
- pll->reference_freq = 2700;
-
- pll->reference_div = 12;
- pll->xclk = 10300;
-
- info->sclk = 200.00;
- info->mclk = 200.00;
- }
- }
-
- /* card limits for computing PLLs */
- if (IS_AVIVO_VARIANT) {
- pll->min_post_div = 2;
- pll->max_post_div = 0x7f;
- } else {
- pll->min_post_div = 1;
- pll->max_post_div = 12; //16 on crtc0
- }
- pll->min_ref_div = 2;
- pll->max_ref_div = 0x3ff;
- pll->min_feedback_div = 4;
- pll->max_feedback_div = 0x7ff;
- pll->best_vco = 0;
-
- xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n",
- pll->reference_freq,
- pll->reference_div,
- (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max,
- pll->xclk);
-
- /* (Some?) Radeon BIOSes seem too lie about their minimum dot
- * clocks. Allow users to override the detected minimum dot clock
- * value (e.g., and allow it to be suitable for TV sets).
- */
- if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK,
- OPTUNITS_MHZ, &min_dotclock)) {
- if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Illegal minimum dotclock specified %.2f MHz "
- "(option ignored)\n",
- min_dotclock);
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Forced minimum dotclock to %.2f MHz "
- "(instead of detected %.2f MHz)\n",
- min_dotclock, ((double)pll->pll_out_min/1000));
- pll->pll_out_min = min_dotclock * 1000;
- }
- }
-}
-
-
-
-/* This is called by RADEONPreInit to set up the default visual */
-static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb))
- return FALSE;
-
- switch (pScrn->depth) {
- case 8:
- case 15:
- case 16:
- case 24:
- break;
-
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Given depth (%d) is not supported by %s driver\n",
- pScrn->depth, RADEON_DRIVER_NAME);
- return FALSE;
- }
-
- xf86PrintDepthBpp(pScrn);
-
- info->fifo_slots = 0;
- info->pix24bpp = xf86GetBppFromDepth(pScrn,
- pScrn->depth);
- info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel;
- info->CurrentLayout.depth = pScrn->depth;
- info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8;
- info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16
- ? pScrn->bitsPerPixel
- : pScrn->depth);
-
- if (info->pix24bpp == 24) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Radeon does NOT support 24bpp\n");
- return FALSE;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n",
- pScrn->depth,
- info->CurrentLayout.pixel_bytes,
- info->CurrentLayout.pixel_bytes > 1 ? "s" : "",
- info->pix24bpp);
-
- if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE;
-
- if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Default visual (%s) is not supported at depth %d\n",
- xf86GetVisualName(pScrn->defaultVisual), pScrn->depth);
- return FALSE;
- }
- return TRUE;
-}
-
-/* This is called by RADEONPreInit to handle all color weight issues */
-static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- /* Save flag for 6 bit DAC to use for
- setting CRTC registers. Otherwise use
- an 8 bit DAC, even if xf86SetWeight sets
- pScrn->rgbBits to some value other than
- 8. */
- info->dac6bits = FALSE;
-
- if (pScrn->depth > 8) {
- rgb defaultWeight = { 0, 0, 0 };
-
- if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE;
- } else {
- pScrn->rgbBits = 8;
- if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) {
- pScrn->rgbBits = 6;
- info->dac6bits = TRUE;
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d bits per RGB (%d bit DAC)\n",
- pScrn->rgbBits, info->dac6bits ? 6 : 8);
-
- return TRUE;
-}
-
-void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONInfoPtr info)
-{
- save->mc_fb_location = info->mc_fb_location;
- save->mc_agp_location = info->mc_agp_location;
-
- if (IS_AVIVO_VARIANT) {
- save->mc_agp_location_hi = info->mc_agp_location_hi;
- } else {
- save->display_base_addr = info->fbLocation;
- save->display2_base_addr = info->fbLocation;
- save->ov0_base_addr = info->fbLocation;
- }
-}
-
-static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 mem_size;
- CARD32 aper_size;
-
- radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location,
- &info->mc_agp_location, &info->mc_agp_location_hi);
-
- /* We shouldn't use info->videoRam here which might have been clipped
- * but the real video RAM instead
- */
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- mem_size = INREG(R600_CONFIG_MEMSIZE);
- aper_size = INREG(R600_CONFIG_APER_SIZE);
- } else {
- mem_size = INREG(RADEON_CONFIG_MEMSIZE);
- aper_size = INREG(RADEON_CONFIG_APER_SIZE);
- }
-
- if (mem_size == 0)
- mem_size = 0x800000;
-
- /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
- Novell bug 204882 + along with lots of ubuntu ones */
- if (aper_size > mem_size)
- mem_size = aper_size;
-
-#ifdef XF86DRI
- /* Apply memory map limitation if using an old DRI */
- if (info->directRenderingEnabled && !info->newMemoryMap) {
- if (aper_size < mem_size)
- mem_size = aper_size;
- }
-#endif
-
- if (info->ChipFamily != CHIP_FAMILY_RS690) {
- if (info->IsIGP)
- info->mc_fb_location = INREG(RADEON_NB_TOM);
- else
-#ifdef XF86DRI
- /* Old DRI has restrictions on the memory map */
- if ( info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 10 )
- info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
- else
-#endif
- {
- CARD32 aper0_base;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- aper0_base = INREG(R600_CONFIG_F0_BASE);
- } else {
- aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
- }
-
- /* Recent chips have an "issue" with the memory controller, the
- * location must be aligned to the size. We just align it down,
- * too bad if we walk over the top of system memory, we don't
- * use DMA without a remapped anyway.
- * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
- */
- if (info->ChipFamily == CHIP_FAMILY_RV280 ||
- info->ChipFamily == CHIP_FAMILY_R300 ||
- info->ChipFamily == CHIP_FAMILY_R350 ||
- info->ChipFamily == CHIP_FAMILY_RV350 ||
- info->ChipFamily == CHIP_FAMILY_RV380 ||
- info->ChipFamily == CHIP_FAMILY_R420 ||
- info->ChipFamily == CHIP_FAMILY_RV410)
- aper0_base &= ~(mem_size - 1);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->mc_fb_location = (aper0_base >> 24) |
- (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
- ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
- } else {
- info->mc_fb_location = (aper0_base >> 16) |
- ((aper0_base + mem_size - 1) & 0xffff0000U);
- }
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
- } else {
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
- }
- /* Just disable the damn AGP apertures for now, it may be
- * re-enabled later by the DRM
- */
-
- if (IS_AVIVO_VARIANT) {
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
- } else {
- OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
- }
- info->mc_agp_location = 0x003f0000;
- } else
- info->mc_agp_location = 0xffffffc0;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "RADEONInitMemoryMap() : \n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " mem_size : 0x%08x\n", (unsigned)mem_size);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_AGP_LOCATION : 0x%08x\n",
- (unsigned)info->mc_agp_location);
-}
-
-static void RADEONGetVRamType(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp;
-
- if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) ||
- (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30)))
- info->IsDDR = TRUE;
- else
- info->IsDDR = FALSE;
-
- tmp = INREG(RADEON_MEM_CNTL);
- if (IS_R300_VARIANT) {
- tmp &= R300_MEM_NUM_CHANNELS_MASK;
- switch (tmp) {
- case 0: info->RamWidth = 64; break;
- case 1: info->RamWidth = 128; break;
- case 2: info->RamWidth = 256; break;
- default: info->RamWidth = 128; break;
- }
- } else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
- (info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200)){
- if (tmp & RV100_HALF_MODE) info->RamWidth = 32;
- else info->RamWidth = 64;
- if (!pRADEONEnt->HasCRTC2) {
- info->RamWidth /= 4;
- info->IsDDR = TRUE;
- }
- } else {
- if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128;
- else info->RamWidth = 64;
- }
-
- /* This may not be correct, as some cards can have half of channel disabled
- * ToDo: identify these cases
- */
-}
-
-/*
- * Depending on card genertation, chipset bugs, etc... the amount of vram
- * accessible to the CPU can vary. This function is our best shot at figuring
- * it out. Returns a value in KB.
- */
-static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 aper_size;
- unsigned char byte;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
- else
- aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
-
-#ifdef XF86DRI
- /* If we use the DRI, we need to check if it's a version that has the
- * bug of always cropping MC_FB_LOCATION to one aperture, in which case
- * we need to limit the amount of accessible video memory
- */
- if (info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 23) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[dri] limiting video memory to one aperture of %uK\n",
- (unsigned)aper_size);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[dri] detected radeon kernel module version 1.%d but"
- " 1.23 or newer is required for full memory mapping.\n",
- info->pKernelDRMVersion->version_minor);
- info->newMemoryMap = FALSE;
- return aper_size;
- }
- info->newMemoryMap = TRUE;
-#endif /* XF86DRI */
-
- /* Set HDP_APER_CNTL only on cards that are known not to be broken,
- * that is has the 2nd generation multifunction PCI interface
- */
- if (info->ChipFamily == CHIP_FAMILY_RV280 ||
- info->ChipFamily == CHIP_FAMILY_RV350 ||
- info->ChipFamily == CHIP_FAMILY_RV380 ||
- info->ChipFamily == CHIP_FAMILY_R420 ||
- info->ChipFamily == CHIP_FAMILY_RV410 ||
- IS_AVIVO_VARIANT) {
- OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
- ~RADEON_HDP_APER_CNTL);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Generation 2 PCI interface, using max accessible memory\n");
- return aper_size * 2;
- }
-
- /* Older cards have all sorts of funny issues to deal with. First
- * check if it's a multifunction card by reading the PCI config
- * header type... Limit those to one aperture size
- */
- PCI_READ_BYTE(info->PciInfo, &byte, 0xe);
- if (byte & 0x80) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Generation 1 PCI interface in multifunction mode"
- ", accessible memory limited to one aperture\n");
- return aper_size;
- }
-
- /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
- * have set it up. We don't write this as it's broken on some ASICs but
- * we expect the BIOS to have done the right thing (might be too optimistic...)
- */
- if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
- return aper_size * 2;
-
- return aper_size;
-}
-
-static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- EntityInfoPtr pEnt = info->pEnt;
- GDevPtr dev = pEnt->device;
- unsigned char *RADEONMMIO = info->MMIO;
- MessageType from = X_PROBED;
- CARD32 accessible, bar_size;
-
- if (info->ChipFamily == CHIP_FAMILY_RS690) {
- pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE);
- } else if (info->IsIGP) {
- CARD32 tom = INREG(RADEON_NB_TOM);
-
- pScrn->videoRam = (((tom >> 16) -
- (tom & 0xffff) + 1) << 6);
-
- OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024);
- } else {
-
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
- else {
- /* Read VRAM size from card */
- pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
-
- /* Some production boards of m6 will return 0 if it's 8 MB */
- if (pScrn->videoRam == 0) {
- pScrn->videoRam = 8192;
- OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
- }
- }
- }
-
- /* Get accessible memory */
- accessible = RADEONGetAccessibleVRAM(pScrn);
-
- /* Crop it to the size of the PCI BAR */
- bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
- if (bar_size == 0)
- bar_size = 0x20000;
- if (accessible > bar_size)
- accessible = bar_size;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n",
- pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size);
- if (pScrn->videoRam > accessible)
- pScrn->videoRam = accessible;
-
- if (!IS_AVIVO_VARIANT)
- info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
- info->BusCntl = INREG(RADEON_BUS_CNTL);
-
- RADEONGetVRamType(pScrn);
-
- if (dev->videoRam) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Video RAM override, using %d kB instead of %d kB\n",
- dev->videoRam,
- pScrn->videoRam);
- from = X_CONFIG;
- pScrn->videoRam = dev->videoRam;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR");
-
- if (info->IsPrimary) {
- pScrn->videoRam /= 2;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %dk of videoram for primary head\n",
- pScrn->videoRam);
- }
-
- if (info->IsSecondary) {
- pScrn->videoRam /= 2;
- info->LinearAddr += pScrn->videoRam * 1024;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %dk of videoram for secondary head\n",
- pScrn->videoRam);
- }
-
- pScrn->videoRam &= ~1023;
- info->FbMapSize = pScrn->videoRam * 1024;
-
- /* if the card is PCI Express reserve the last 32k for the gart table */
-#ifdef XF86DRI
- if (info->cardType == CARD_PCIE && info->directRenderingEnabled)
- /* work out the size of pcie aperture */
- info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn);
- else
-#endif
- info->FbSecureSize = 0;
-
- return TRUE;
-}
-
-
-/* This is called by RADEONPreInit to handle config file overrides for
- * things like chipset and memory regions. Also determine memory size
- * and type. If memory type ever needs an override, put it in this
- * routine.
- */
-static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- EntityInfoPtr pEnt = info->pEnt;
- GDevPtr dev = pEnt->device;
- unsigned char *RADEONMMIO = info->MMIO;
- MessageType from = X_PROBED;
- int i;
-#ifdef XF86DRI
- const char *s;
- uint32_t cmd_stat;
-#endif
-
- /* Chipset */
- from = X_PROBED;
- if (dev->chipset && *dev->chipset) {
- info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset);
- from = X_CONFIG;
- } else if (dev->chipID >= 0) {
- info->Chipset = dev->chipID;
- from = X_CONFIG;
- } else {
- info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
- }
-
- pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset);
- if (!pScrn->chipset) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "ChipID 0x%04x is not recognized\n", info->Chipset);
- return FALSE;
- }
- if (info->Chipset < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Chipset \"%s\" is not recognized\n", pScrn->chipset);
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Chipset: \"%s\" (ChipID = 0x%04x)\n",
- pScrn->chipset,
- info->Chipset);
-
- pRADEONEnt->HasCRTC2 = TRUE;
- info->IsMobility = FALSE;
- info->IsIGP = FALSE;
- info->IsDellServer = FALSE;
- info->HasSingleDAC = FALSE;
- info->InternalTVOut = TRUE;
-
- for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
- if (info->Chipset == RADEONCards[i].pci_device_id) {
- RADEONCardInfo *card = &RADEONCards[i];
- info->ChipFamily = card->chip_family;
- info->IsMobility = card->mobility;
- info->IsIGP = card->igp;
- pRADEONEnt->HasCRTC2 = !card->nocrtc2;
- info->HasSingleDAC = card->singledac;
- info->InternalTVOut = !card->nointtvout;
- break;
- }
- }
-
- switch (info->Chipset) {
- case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */
- case PCI_CHIP_RN50_5969:
- case PCI_CHIP_RV100_QY:
- case PCI_CHIP_RV100_QZ:
- /* DELL triple-head configuration. */
- if ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) &&
- ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) ||
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a))) {
- info->IsDellServer = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n");
- }
- break;
- default:
- break;
- }
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "R600 support is mostly incomplete and very experimental\n");
- }
-
- if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "R500 support is under development. Please report any issues to xorg-driver-ati at lists.x.org\n");
- }
-
- from = X_PROBED;
- info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL;
- pScrn->memPhysBase = info->LinearAddr;
- if (dev->MemBase) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Linear address override, using 0x%016lx instead of 0x%016lx\n",
- dev->MemBase,
- info->LinearAddr);
- info->LinearAddr = dev->MemBase;
- from = X_CONFIG;
- } else if (!info->LinearAddr) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "No valid linear framebuffer address\n");
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Linear framebuffer at 0x%016lx\n", info->LinearAddr);
-
-#ifndef XSERVER_LIBPCIACCESS
- /* BIOS */
- from = X_PROBED;
- info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000;
- if (dev->BiosBase) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "BIOS address override, using 0x%08lx instead of 0x%08lx\n",
- dev->BiosBase,
- info->BIOSAddr);
- info->BIOSAddr = dev->BiosBase;
- from = X_CONFIG;
- }
- if (info->BIOSAddr) {
- xf86DrvMsg(pScrn->scrnIndex, from,
- "BIOS at 0x%08lx\n", info->BIOSAddr);
- }
-#endif
-
- /* Read registers used to determine options */
- /* Check chip errata */
- info->ChipErrata = 0;
-
- if (info->ChipFamily == CHIP_FAMILY_R300 &&
- (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
- == RADEON_CFG_ATI_REV_A11)
- info->ChipErrata |= CHIP_ERRATA_R300_CG;
-
- if (info->ChipFamily == CHIP_FAMILY_RV200 ||
- info->ChipFamily == CHIP_FAMILY_RS200)
- info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
-
- if (info->ChipFamily == CHIP_FAMILY_RV100 ||
- info->ChipFamily == CHIP_FAMILY_RS100 ||
- info->ChipFamily == CHIP_FAMILY_RS200)
- info->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
-
-#ifdef XF86DRI
- /* AGP/PCI */
- /* Proper autodetection of an AGP capable device requires examining
- * PCI config registers to determine if the device implements extended
- * PCI capabilities, and then walking the capability list as indicated
- * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP
- * capability is present. The procedure is outlined as follows:
- *
- * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device
- * to determine wether or not this device implements any extended
- * capabilities. If this bit is zero, then the device is a PCI 2.1
- * or earlier device and is not AGP capable, and we can conclude it
- * to be a PCI device.
- *
- * 2) If bit 4 of the status register is set, then the device implements
- * extended capabilities. There is an 8 bit wide capabilities pointer
- * register located at offset 0x34 in PCI config space which points to
- * the first capability in a linked list of extended capabilities that
- * this device implements. The lower two bits of this register are
- * reserved and MBZ so must be masked out.
- *
- * 3) The extended capabilities list is formed by one or more extended
- * capabilities structures which are aligned on DWORD boundaries.
- * The first byte of the structure is the capability ID (CAP_ID)
- * indicating what extended capability this structure refers to. The
- * second byte of the structure is an offset from the beginning of
- * PCI config space pointing to the next capability in the linked
- * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower
- * two bits of this pointer are reserved and MBZ. By examining the
- * CAP_ID of each capability and walking through the list, we will
- * either find the AGP_CAP_ID (0x02) indicating this device is an
- * AGP device, or we'll reach the end of the list, indicating it is
- * a PCI device.
- *
- * Mike A. Harris <mharris at redhat.com>
- *
- * References:
- * - PCI Local Bus Specification Revision 2.2, Chapter 6
- * - AGP Interface Specification Revision 2.0, Section 6.1.5
- */
-
- info->cardType = CARD_PCI;
-
- PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG);
- if (cmd_stat & RADEON_CAP_LIST) {
- uint32_t cap_ptr, cap_id;
-
- PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
- cap_ptr &= RADEON_CAP_PTR_MASK;
-
- while(cap_ptr != RADEON_CAP_ID_NULL) {
- PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr);
- if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
- info->cardType = CARD_AGP;
- break;
- }
- if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
- info->cardType = CARD_PCIE;
- break;
- }
- cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
- }
- }
-
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n",
- (info->cardType==CARD_PCI) ? "PCI" :
- (info->cardType==CARD_PCIE) ? "PCIE" : "AGP");
-
- /* treat PCIE IGP cards as PCI */
- if (info->cardType == CARD_PCIE && info->IsIGP)
- info->cardType = CARD_PCI;
-
- if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) {
- if (strcmp(s, "AGP") == 0) {
- info->cardType = CARD_AGP;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n");
- } else if (strcmp(s, "PCI") == 0) {
- info->cardType = CARD_PCI;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n");
- } else if (strcmp(s, "PCIE") == 0) {
- info->cardType = CARD_PCIE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n");
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Invalid BusType option, using detected type\n");
- }
- }
-#endif
- xf86GetOptValBool(info->Options, OPTION_SHOWCACHE, &info->showCache);
- if (info->showCache)
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Option ShowCache enabled\n");
-
-#ifdef RENDER
- info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL,
- info->Chipset != PCI_CHIP_RN50_515E &&
- info->Chipset != PCI_CHIP_RN50_5969);
-#endif
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- info->r600_shadow_fb = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "using shadow framebuffer\n");
- if (!xf86LoadSubModule(pScrn, "shadow"))
- return FALSE;
- }
- return TRUE;
-}
-
-
-static void RADEONPreInitDDC(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- /* vbeInfoPtr pVbe; */
-
- info->ddc1 = FALSE;
- info->ddc_bios = FALSE;
- if (!xf86LoadSubModule(pScrn, "ddc")) {
- info->ddc2 = FALSE;
- } else {
- info->ddc2 = TRUE;
- }
-
- /* DDC can use I2C bus */
- /* Load I2C if we have the code to use it */
- if (info->ddc2) {
- xf86LoadSubModule(pScrn, "i2c");
- }
-}
-
-/* This is called by RADEONPreInit to initialize gamma correction */
-static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn)
-{
- Gamma zeros = { 0.0, 0.0, 0.0 };
-
- if (!xf86SetGamma(pScrn, zeros)) return FALSE;
- return TRUE;
-}
-
-/* This is called by RADEONPreInit to initialize the hardware cursor */
-static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
- if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
- }
- return TRUE;
-}
-
-/* This is called by RADEONPreInit to initialize hardware acceleration */
-static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- MessageType from;
-#if defined(USE_EXA) && defined(USE_XAA)
- char *optstr;
-#endif
-
- info->useEXA = FALSE;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT,
- "No acceleration support available on R600 yet.\n");
- return TRUE;
- }
-
- if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- int errmaj = 0, errmin = 0;
-
- from = X_DEFAULT;
-#if defined(USE_EXA)
-#if defined(USE_XAA)
- optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD);
- if (optstr != NULL) {
- if (xf86NameCmp(optstr, "EXA") == 0) {
- from = X_CONFIG;
- info->useEXA = TRUE;
- } else if (xf86NameCmp(optstr, "XAA") == 0) {
- from = X_CONFIG;
- }
- }
-#else /* USE_XAA */
- info->useEXA = TRUE;
-#endif /* !USE_XAA */
-#endif /* USE_EXA */
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Using %s acceleration architecture\n",
- info->useEXA ? "EXA" : "XAA");
-
-#ifdef USE_EXA
- if (info->useEXA) {
- info->exaReq.majorversion = EXA_VERSION_MAJOR;
- info->exaReq.minorversion = EXA_VERSION_MINOR;
-
- if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL,
- &info->exaReq, &errmaj, &errmin)) {
- LoaderErrorMsg(NULL, "exa", errmaj, errmin);
- return FALSE;
- }
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- info->xaaReq.majorversion = 1;
- info->xaaReq.minorversion = 2;
-
- if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL,
- &info->xaaReq, &errmaj, &errmin)) {
- info->xaaReq.minorversion = 1;
-
- if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL,
- &info->xaaReq, &errmaj, &errmin)) {
- info->xaaReq.minorversion = 0;
-
- if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL,
- &info->xaaReq, &errmaj, &errmin)) {
- LoaderErrorMsg(NULL, "xaa", errmaj, errmin);
- return FALSE;
- }
- }
- }
- }
-#endif /* USE_XAA */
- }
-
- return TRUE;
-}
-
-static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
-{
-#if !defined(__powerpc__) && !defined(__sparc__)
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 fp2_gen_ctl_save = 0;
-
- if (xf86LoadSubModule(pScrn, "int10")) {
- /* The VGA BIOS on the RV100/QY cannot be read when the digital output
- * is enabled. Clear and restore FP2_ON around int10 to avoid this.
- */
- if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) {
- fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL);
- if (fp2_gen_ctl_save & RADEON_FP2_ON) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n");
- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON);
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n");
- *ppInt10 = xf86InitInt10(info->pEnt->index);
-
- if (fp2_gen_ctl_save & RADEON_FP2_ON) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n");
- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save);
- }
- }
-#endif
- return TRUE;
-}
-
-#ifdef XF86DRI
-static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- MessageType from;
- char *reason;
-
- info->directRenderingEnabled = FALSE;
- info->directRenderingInited = FALSE;
- info->CPInUse = FALSE;
- info->CPStarted = FALSE;
- info->pLibDRMVersion = NULL;
- info->pKernelDRMVersion = NULL;
-
- if (xf86IsEntityShared(info->pEnt->index)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct Rendering Disabled -- "
- "Dual-head configuration is not working with "
- "DRI at present.\n"
- "Please use the radeon MergedFB option if you "
- "want Dual-head with DRI.\n");
- return FALSE;
- }
- if (info->IsSecondary)
- return FALSE;
-
- if (info->Chipset == PCI_CHIP_RN50_515E ||
- info->Chipset == PCI_CHIP_RN50_5969 ||
- info->Chipset == PCI_CHIP_RC410_5A61 ||
- info->Chipset == PCI_CHIP_RC410_5A62 ||
- info->Chipset == PCI_CHIP_RS485_5975 ||
- info->ChipFamily >= CHIP_FAMILY_R600) {
- if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct rendering for RN50/RC410/RS485/R600 forced on -- "
- "This is NOT officially supported at the hardware level "
- "and may cause instability or lockups\n");
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Direct rendering not officially supported on RN50/RC410/R600\n");
- return FALSE;
- }
- }
-
-
- if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Direct rendering forced off\n");
- return FALSE;
- }
-
- if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[dri] Acceleration disabled, not initializing the DRI\n");
- return FALSE;
- }
-
- if (!RADEONDRIGetVersion(pScrn))
- return FALSE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "[dri] Found DRI library version %d.%d.%d and kernel"
- " module version %d.%d.%d\n",
- info->pLibDRMVersion->version_major,
- info->pLibDRMVersion->version_minor,
- info->pLibDRMVersion->version_patchlevel,
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel);
-
- if (info->Chipset == PCI_CHIP_RS400_5A41 ||
- info->Chipset == PCI_CHIP_RS400_5A42 ||
- info->Chipset == PCI_CHIP_RC410_5A61 ||
- info->Chipset == PCI_CHIP_RC410_5A62 ||
- info->Chipset == PCI_CHIP_RS480_5954 ||
- info->Chipset == PCI_CHIP_RS480_5955 ||
- info->Chipset == PCI_CHIP_RS482_5974 ||
- info->Chipset == PCI_CHIP_RS485_5975) {
-
- if (info->pKernelDRMVersion->version_minor < 27) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n");
- return FALSE;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Direct rendering experimental on RS400/Xpress 200 enabled\n");
- }
-
- if (xf86ReturnOptValBool(info->Options, OPTION_CP_PIO, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CP into PIO mode\n");
- info->CPMode = RADEON_DEFAULT_CP_PIO_MODE;
- } else {
- info->CPMode = RADEON_DEFAULT_CP_BM_MODE;
- }
-
- info->gartSize = RADEON_DEFAULT_GART_SIZE;
- info->ringSize = RADEON_DEFAULT_RING_SIZE;
- info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
- info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
- info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
- info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
-
- if ((xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE, (int *)&(info->gartSize))) ||
- (xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE_OLD, (int *)&(info->gartSize)))) {
- switch (info->gartSize) {
- case 4:
- case 8:
- case 16:
- case 32:
- case 64:
- case 128:
- case 256:
- break;
-
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal GART size: %d MB\n", info->gartSize);
- return FALSE;
- }
- }
-
- if (xf86GetOptValInteger(info->Options,
- OPTION_RING_SIZE, &(info->ringSize))) {
- if (info->ringSize < 1 || info->ringSize >= (int)info->gartSize) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal ring buffer size: %d MB\n",
- info->ringSize);
- return FALSE;
- }
- }
-
- if (xf86GetOptValInteger(info->Options,
- OPTION_PCIAPER_SIZE, &(info->pciAperSize))) {
- switch(info->pciAperSize) {
- case 32:
- case 64:
- case 128:
- case 256:
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal pci aper size: %d MB\n",
- info->pciAperSize);
- return FALSE;
- }
- }
-
-
- if (xf86GetOptValInteger(info->Options,
- OPTION_BUFFER_SIZE, &(info->bufSize))) {
- if (info->bufSize < 1 || info->bufSize >= (int)info->gartSize) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
- return FALSE;
- }
- if (info->bufSize > 2) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Clamping vertex/indirect buffers size to 2 MB\n");
- info->bufSize = 2;
- }
- }
-
- if (info->ringSize + info->bufSize + info->gartTexSize >
- (int)info->gartSize) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Buffers are too big for requested GART space\n");
- return FALSE;
- }
-
- info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
-
- if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT,
- &(info->CPusecTimeout))) {
- /* This option checked by the RADEON DRM kernel module */
- }
-
- /* Two options to try and squeeze as much texture memory as possible
- * for dedicated 3d rendering boxes
- */
- info->noBackBuffer = xf86ReturnOptValBool(info->Options,
- OPTION_NO_BACKBUFFER,
- FALSE);
-
- info->allowPageFlip = 0;
-
-#ifdef DAMAGE
- if (info->noBackBuffer) {
- from = X_DEFAULT;
- reason = " because back buffer disabled";
- } else {
- from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP,
- &info->allowPageFlip) ? X_CONFIG : X_DEFAULT;
- reason = "";
- }
-#else
- from = X_DEFAULT;
- reason = " because Damage layer not available at build time";
-#endif
-
- xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n",
- info->allowPageFlip ? "en" : "dis", reason);
-
- info->DMAForXv = TRUE;
- from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv)
- ? X_CONFIG : X_INFO;
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Will %stry to use DMA for Xv image transfers\n",
- info->DMAForXv ? "" : "not ");
-
- return TRUE;
-}
-#endif /* XF86DRI */
-
-static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- info->allowColorTiling = xf86ReturnOptValBool(info->Options,
- OPTION_COLOR_TILING, TRUE);
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- /* this may be 4096 on r4xx -- need to double check */
- info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/
- info->MaxLines = 4096;
- } else {
- info->MaxSurfaceWidth = 2048;
- info->MaxLines = 2048;
- }
-
- if (!info->allowColorTiling)
- return;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- info->allowColorTiling = FALSE;
-
- /* for zaphod disable tiling for now */
- if (info->IsPrimary || info->IsSecondary)
- info->allowColorTiling = FALSE;
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 14) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[dri] color tiling disabled because of version "
- "mismatch.\n"
- "[dri] radeon.o kernel module version is %d.%d.%d but "
- "1.14.0 or later is required for color tiling.\n",
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel);
- info->allowColorTiling = FALSE;
- return;
- }
-#endif /* XF86DRI */
-
- if (info->allowColorTiling) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n");
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n");
- }
-}
-
-
-static Bool RADEONPreInitXv(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD16 mm_table;
- CARD16 bios_header;
- CARD16 pll_info_block;
-#ifdef XvExtension
- char* microc_path = NULL;
- char* microc_type = NULL;
- MessageType from;
-
- if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY,
- &(info->videoKey))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n",
- info->videoKey);
- } else {
- info->videoKey = 0x1E;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n",
- info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100);
- } else {
- info->RageTheatreCrystal=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n",
- info->RageTheatreTunerPort);
- } else {
- info->RageTheatreTunerPort=-1;
- }
-
- if(info->RageTheatreTunerPort>5){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n");
- info->RageTheatreTunerPort=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n",
- info->RageTheatreCompositePort);
- } else {
- info->RageTheatreCompositePort=-1;
- }
-
- if(info->RageTheatreCompositePort>6){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n");
- info->RageTheatreCompositePort=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n",
- info->RageTheatreSVideoPort);
- } else {
- info->RageTheatreSVideoPort=-1;
- }
-
- if(info->RageTheatreSVideoPort>6){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n");
- info->RageTheatreSVideoPort=-1;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n",
- info->tunerType);
- } else {
- info->tunerType=-1;
- }
-
- if(info->tunerType>31){
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n");
- info->tunerType=-1;
- }
-
- if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path);
- info->RageTheatreMicrocPath = microc_path;
- } else {
- info->RageTheatreMicrocPath= NULL;
- }
-
- if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type);
- info->RageTheatreMicrocType = microc_type;
- } else {
- info->RageTheatreMicrocType= NULL;
- }
-
- if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) {
- if ((info->overlay_scaler_buffer_width < 1024) ||
- (info->overlay_scaler_buffer_width > 2048) ||
- ((info->overlay_scaler_buffer_width % 64) != 0)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n");
- from = X_DEFAULT;
- info->overlay_scaler_buffer_width = 0;
- } else
- from = X_CONFIG;
- } else {
- from = X_DEFAULT;
- info->overlay_scaler_buffer_width = 0;
- }
- if (!info->overlay_scaler_buffer_width) {
- /* overlay scaler line length differs for different revisions
- this needs to be maintained by hand */
- switch(info->ChipFamily){
- case CHIP_FAMILY_R200:
- case CHIP_FAMILY_R300:
- case CHIP_FAMILY_RV350:
- info->overlay_scaler_buffer_width = 1920;
- break;
- default:
- info->overlay_scaler_buffer_width = 1536;
- }
- }
- xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n",
- info->overlay_scaler_buffer_width);
-#endif
-
- /* Rescue MM_TABLE before VBIOS is freed */
- info->MM_TABLE_valid = FALSE;
-
- if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n"
- "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n"
- "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n"
- );
- info->MM_TABLE_valid = FALSE;
- return TRUE;
- }
-
- bios_header=info->VBIOS[0x48];
- bios_header+=(((int)info->VBIOS[0x49]+0)<<8);
-
- mm_table=info->VBIOS[bios_header+0x38];
- if(mm_table==0)
- {
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n");
- info->MM_TABLE_valid = FALSE;
- return TRUE;
- }
- mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2;
-
- if(mm_table>0)
- {
- memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE));
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
- info->MM_TABLE.table_revision,
- info->MM_TABLE.table_size,
- info->MM_TABLE.tuner_type,
- info->MM_TABLE.audio_chip,
- info->MM_TABLE.product_id,
- info->MM_TABLE.tuner_voltage_teletext_fm,
- info->MM_TABLE.i2s_config,
- info->MM_TABLE.video_decoder_type,
- info->MM_TABLE.video_decoder_host_config,
- info->MM_TABLE.input[0],
- info->MM_TABLE.input[1],
- info->MM_TABLE.input[2],
- info->MM_TABLE.input[3],
- info->MM_TABLE.input[4]);
-
- /* Is it an MM_TABLE we know about ? */
- if(info->MM_TABLE.table_size != 0xc){
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n"
- "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n"
- "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n"
- );
- info->MM_TABLE_valid = FALSE;
- return TRUE;
- }
- info->MM_TABLE_valid = TRUE;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table);
- info->MM_TABLE_valid = FALSE;
- }
-
- pll_info_block=info->VBIOS[bios_header+0x30];
- pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8);
-
- info->video_decoder_type=info->VBIOS[pll_info_block+0x08];
- info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8);
-
- return TRUE;
-}
-
-static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
-{
- RADEONGetBIOSInfo(pScrn, pInt10);
-#if 0
- RADEONGetBIOSInitTableOffsets(pScrn);
- RADEONPostCardFromBIOSTables(pScrn);
-#endif
-}
-
-static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
-
- if (info->IsPrimary) {
- xf86OutputDestroy(config->output[0]);
- while(config->num_output > 1) {
- xf86OutputDestroy(config->output[1]);
- }
- } else {
- while(config->num_output > 1) {
- xf86OutputDestroy(config->output[1]);
- }
- }
-}
-
-static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn)
-{
- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int i;
- int mask;
- int found = 0;
-
- if (!info->IsPrimary && !info->IsSecondary)
- mask = 3;
- else if (info->IsPrimary)
- mask = 1;
- else
- mask = 2;
-
- if (!RADEONAllocateControllers(pScrn, mask))
- return FALSE;
-
- RADEONGetClockInfo(pScrn);
-
- if (!RADEONSetupConnectors(pScrn)) {
- return FALSE;
- }
-
- if (info->IsPrimary || info->IsSecondary) {
- /* fixup outputs for zaphod */
- RADEONFixZaphodOutputs(pScrn);
- }
-
- RADEONPrintPortMap(pScrn);
-
- info->first_load_no_devices = FALSE;
- for (i = 0; i < config->num_output; i++) {
- xf86OutputPtr output = config->output[i];
-
- output->status = (*output->funcs->detect) (output);
- ErrorF("finished output detect: %d\n", i);
- if (info->IsPrimary || info->IsSecondary) {
- if (output->status != XF86OutputStatusConnected)
- return FALSE;
- }
- if (output->status != XF86OutputStatusDisconnected)
- found++;
- }
-
- if (!found) {
- /* nothing connected, light up some defaults so the server comes up */
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n");
- info->first_load_no_devices = TRUE;
- }
-
- ErrorF("finished all detect\n");
- return TRUE;
-}
-
-static void
-RADEONProbeDDC(ScrnInfoPtr pScrn, int indx)
-{
- vbeInfoPtr pVbe;
-
- if (xf86LoadSubModule(pScrn, "vbe")) {
- pVbe = VBEInit(NULL,indx);
- ConfiguredMonitor = vbeDoEDID(pVbe, NULL);
- }
-}
-
-static Bool
-RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height)
-{
- scrn->virtualX = width;
- scrn->virtualY = height;
- /* RADEONSetPitch(scrn); */
- return TRUE;
-}
-
-static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = {
- RADEONCRTCResize
-};
-
-Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
-{
- xf86CrtcConfigPtr xf86_config;
- RADEONInfoPtr info;
- xf86Int10InfoPtr pInt10 = NULL;
- void *int10_save = NULL;
- const char *s;
- int crtc_max_X, crtc_max_Y;
- RADEONEntPtr pRADEONEnt;
- DevUnion* pPriv;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONPreInit\n");
- if (pScrn->numEntities != 1) return FALSE;
-
- if (!RADEONGetRec(pScrn)) return FALSE;
-
- info = RADEONPTR(pScrn);
- info->MMIO = NULL;
-
- info->IsSecondary = FALSE;
- info->IsPrimary = FALSE;
-
- info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
- if (info->pEnt->location.type != BUS_PCI) goto fail;
-
- pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
- getRADEONEntityIndex());
- pRADEONEnt = pPriv->ptr;
-
- if(xf86IsEntityShared(pScrn->entityList[0]))
- {
- if(xf86IsPrimInitDone(pScrn->entityList[0]))
- {
- info->IsSecondary = TRUE;
- pRADEONEnt->pSecondaryScrn = pScrn;
- info->SavedReg = &pRADEONEnt->SavedReg;
- info->ModeReg = &pRADEONEnt->ModeReg;
- }
- else
- {
- info->IsPrimary = TRUE;
- xf86SetPrimInitDone(pScrn->entityList[0]);
- pRADEONEnt->pPrimaryScrn = pScrn;
- pRADEONEnt->HasSecondary = FALSE;
- info->SavedReg = &pRADEONEnt->SavedReg;
- info->ModeReg = &pRADEONEnt->ModeReg;
- }
- } else {
- info->SavedReg = &pRADEONEnt->SavedReg;
- info->ModeReg = &pRADEONEnt->ModeReg;
- }
-
- info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
- info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
- info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffUL;
- info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2);
- if (info->pEnt->device->IOBase) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "MMIO address override, using 0x%08lx instead of 0x%08lx\n",
- info->pEnt->device->IOBase,
- info->MMIOAddr);
- info->MMIOAddr = info->pEnt->device->IOBase;
- } else if (!info->MMIOAddr) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n");
- goto fail1;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "MMIO registers at 0x%016lx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024);
-
- if(!RADEONMapMMIO(pScrn)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Memory map the MMIO region failed\n");
- goto fail1;
- }
-
-#if !defined(__alpha__)
- if (
-#ifndef XSERVER_LIBPCIACCESS
- xf86GetPciDomain(info->PciTag) ||
-#endif
- !xf86IsPrimaryPci(info->PciInfo))
- RADEONPreInt10Save(pScrn, &int10_save);
-#else
- /* [Alpha] On the primary, the console already ran the BIOS and we're
- * going to run it again - so make sure to "fix up" the card
- * so that (1) we can read the BIOS ROM and (2) the BIOS will
- * get the memory config right.
- */
- RADEONPreInt10Save(pScrn, &int10_save);
-#endif
-
- if (flags & PROBE_DETECT) {
- RADEONProbeDDC(pScrn, info->pEnt->index);
- RADEONPostInt10Check(pScrn, int10_save);
- if(info->MMIO) RADEONUnmapMMIO(pScrn);
- return TRUE;
- }
-
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "PCI bus %d card %d func %d\n",
- PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo),
- PCI_DEV_FUNC(info->PciInfo));
-
- if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive))
- goto fail;
-
- if (xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr))
- goto fail;
-
- pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR;
- pScrn->monitor = pScrn->confScreen->monitor;
-
- /* Allocate an xf86CrtcConfig */
- xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs);
- xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
-
-
- if (!RADEONPreInitVisual(pScrn))
- goto fail;
-
- /* We can't do this until we have a
- pScrn->display. */
- xf86CollectOptions(pScrn, NULL);
- if (!(info->Options = xalloc(sizeof(RADEONOptions))))
- goto fail;
-
- memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
- xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
-
- /* By default, don't do VGA IOs on ppc/sparc */
-#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW)
- info->VGAAccess = FALSE;
-#else
- info->VGAAccess = TRUE;
-#endif
-
-#ifdef WITH_VGAHW
- xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess);
- if (info->VGAAccess) {
- if (!xf86LoadSubModule(pScrn, "vgahw"))
- info->VGAAccess = FALSE;
- else {
- if (!vgaHWGetHWRec(pScrn))
- info->VGAAccess = FALSE;
- }
- if (!info->VGAAccess)
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed,"
- " trying to run without it\n");
- } else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
- " VGA module load skipped\n");
- if (info->VGAAccess)
- vgaHWGetIOBase(VGAHWPTR(pScrn));
-#endif
-
-
- if (!RADEONPreInitWeight(pScrn))
- goto fail;
-
- info->DispPriority = 1;
- if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) {
- if (strcmp(s, "AUTO") == 0) {
- info->DispPriority = 1;
- } else if (strcmp(s, "BIOS") == 0) {
- info->DispPriority = 0;
- } else if (strcmp(s, "HIGH") == 0) {
- info->DispPriority = 2;
- } else
- info->DispPriority = 1;
- }
-
- if (!RADEONPreInitInt10(pScrn, &pInt10))
- goto fail;
-
- RADEONPostInt10Check(pScrn, int10_save);
-
- if (!RADEONPreInitChipType(pScrn))
- goto fail;
-
- RADEONPreInitBIOS(pScrn, pInt10);
-
-#ifdef XF86DRI
- /* PreInit DRI first of all since we need that for getting a proper
- * memory map
- */
- info->directRenderingEnabled = RADEONPreInitDRI(pScrn);
-#endif
- if (!RADEONPreInitVRAM(pScrn))
- goto fail;
-
- RADEONPreInitColorTiling(pScrn);
-
- /* we really need an FB manager... */
- if (pScrn->display->virtualX) {
- crtc_max_X = pScrn->display->virtualX;
- crtc_max_Y = pScrn->display->virtualY;
- if (info->allowColorTiling) {
- if (crtc_max_X > info->MaxSurfaceWidth ||
- crtc_max_Y > info->MaxLines) {
- info->allowColorTiling = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Requested desktop size exceeds surface limts for tiling, ColorTiling disabled\n");
- }
- }
- if (crtc_max_X > 8192)
- crtc_max_X = 8192;
- if (crtc_max_Y > 8192)
- crtc_max_Y = 8192;
- } else {
- if (pScrn->videoRam <= 16384) {
- crtc_max_X = 1600;
- crtc_max_Y = 1200;
- } else {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- crtc_max_X = 2560;
- crtc_max_Y = 1200;
- } else {
- crtc_max_X = 2048;
- crtc_max_Y = 1200;
- }
- }
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n",
- crtc_max_X, crtc_max_Y);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "For a larger or smaller max desktop size, add a Virtual line to your xorg.conf\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "If you are having trouble with 3D, "
- "reduce the desktop size by adjusting the Virtual line to your xorg.conf\n");
-
- /*xf86CrtcSetSizeRange (pScrn, 320, 200, info->MaxSurfaceWidth, info->MaxLines);*/
- xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y);
-
- RADEONPreInitDDC(pScrn);
-
- if (!RADEONPreInitControllers(pScrn))
- goto fail;
-
-
- ErrorF("before xf86InitialConfiguration\n");
-
- if (!xf86InitialConfiguration (pScrn, FALSE))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n");
- goto fail;
- }
-
- ErrorF("after xf86InitialConfiguration\n");
-
- RADEONSetPitch(pScrn);
-
- /* Set display resolution */
- xf86SetDpi(pScrn, 0, 0);
-
- /* Get ScreenInit function */
- if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
-
- if (!RADEONPreInitGamma(pScrn)) goto fail;
-
- if (!RADEONPreInitCursor(pScrn)) goto fail;
-
- if (!RADEONPreInitAccel(pScrn)) goto fail;
-
- if (!RADEONPreInitXv(pScrn)) goto fail;
-
- if (!xf86RandR12PreInit (pScrn))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n");
- goto fail;
- }
-
- if (pScrn->modes == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
- goto fail;
- }
-
-
- /* Free int10 info */
- if (pInt10)
- xf86FreeInt10(pInt10);
-
- if(info->MMIO) RADEONUnmapMMIO(pScrn);
- info->MMIO = NULL;
-
- xf86DrvMsg(pScrn->scrnIndex, X_NOTICE,
- "For information on using the multimedia capabilities\n\tof this"
- " adapter, please see http://gatos.sf.net.\n");
-
- xf86DrvMsg(pScrn->scrnIndex, X_NOTICE,
- "MergedFB support has been removed and replaced with"
- " xrandr 1.2 support\n");
-
- return TRUE;
-
-fail:
- /* Pre-init failed. */
- /* Free the video bios (if applicable) */
- if (info->VBIOS) {
- xfree(info->VBIOS);
- info->VBIOS = NULL;
- }
-
- /* Free int10 info */
- if (pInt10)
- xf86FreeInt10(pInt10);
-
-#ifdef WITH_VGAHW
- if (info->VGAAccess)
- vgaHWFreeHWRec(pScrn);
-#endif
-
- if(info->MMIO) RADEONUnmapMMIO(pScrn);
- info->MMIO = NULL;
-
- fail1:
- RADEONFreeRec(pScrn);
-
- return FALSE;
-}
-
-/* Load a palette */
-static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors,
- int *indices, LOCO *colors, VisualPtr pVisual)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
- int index, j;
- CARD16 lut_r[256], lut_g[256], lut_b[256];
- int c;
-
-#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
-#endif
-
- if (info->accelOn && pScrn->pScreen)
- RADEON_SYNC(info, pScrn);
-
- {
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- for (i = 0 ; i < 256; i++) {
- lut_r[i] = radeon_crtc->lut_r[i] << 8;
- lut_g[i] = radeon_crtc->lut_g[i] << 8;
- lut_b[i] = radeon_crtc->lut_b[i] << 8;
- }
-
- switch (info->CurrentLayout.depth) {
- case 15:
- for (i = 0; i < numColors; i++) {
- index = indices[i];
- for (j = 0; j < 8; j++) {
- lut_r[index * 8 + j] = colors[index].red << 8;
- lut_g[index * 8 + j] = colors[index].green << 8;
- lut_b[index * 8 + j] = colors[index].blue << 8;
- }
- }
- case 16:
- for (i = 0; i < numColors; i++) {
- index = indices[i];
-
- if (i <= 31) {
- for (j = 0; j < 8; j++) {
- lut_r[index * 8 + j] = colors[index].red << 8;
- lut_b[index * 8 + j] = colors[index].blue << 8;
- }
- }
-
- for (j = 0; j < 4; j++) {
- lut_g[index * 4 + j] = colors[index].green << 8;
- }
- }
- default:
- for (i = 0; i < numColors; i++) {
- index = indices[i];
- lut_r[index] = colors[index].red << 8;
- lut_g[index] = colors[index].green << 8;
- lut_b[index] = colors[index].blue << 8;
- }
- break;
- }
-
- /* Make the change through RandR */
-#ifdef RANDR_12_INTERFACE
- if (crtc->randr_crtc)
- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
- else
-#endif
- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
- }
- }
-
-#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
-#endif
-}
-
-static void RADEONBlockHandler(int i, pointer blockData,
- pointer pTimeout, pointer pReadmask)
-{
- ScreenPtr pScreen = screenInfo.screens[i];
- ScrnInfoPtr pScrn = xf86Screens[i];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- pScreen->BlockHandler = info->BlockHandler;
- (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
- pScreen->BlockHandler = RADEONBlockHandler;
-
- if (info->VideoTimerCallback)
- (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
-
-#if defined(RENDER) && defined(USE_XAA)
- if(info->RenderCallback)
- (*info->RenderCallback)(pScrn);
-#endif
-
-#ifdef USE_EXA
- info->engineMode = EXA_ENGINEMODE_UNKNOWN;
-#endif
-}
-
-static void
-RADEONPointerMoved(int index, int x, int y)
-{
- ScrnInfoPtr pScrn = xf86Screens[index];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int newX = x, newY = y;
-
- switch (info->rotation) {
- case RR_Rotate_0:
- break;
- case RR_Rotate_90:
- newX = y;
- newY = pScrn->pScreen->width - x - 1;
- break;
- case RR_Rotate_180:
- newX = pScrn->pScreen->width - x - 1;
- newY = pScrn->pScreen->height - y - 1;
- break;
- case RR_Rotate_270:
- newX = pScrn->pScreen->height - y - 1;
- newY = x;
- break;
- }
-
- (*info->PointerMoved)(index, newX, newY);
-}
-
-static void
-RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = info->ModeReg;
-
- save->bios_0_scratch = info->SavedReg->bios_0_scratch;
- save->bios_1_scratch = info->SavedReg->bios_1_scratch;
- save->bios_2_scratch = info->SavedReg->bios_2_scratch;
- save->bios_3_scratch = info->SavedReg->bios_3_scratch;
- save->bios_4_scratch = info->SavedReg->bios_4_scratch;
- save->bios_5_scratch = info->SavedReg->bios_5_scratch;
- save->bios_6_scratch = info->SavedReg->bios_6_scratch;
- save->bios_7_scratch = info->SavedReg->bios_7_scratch;
-
- if (info->IsAtomBios) {
- /* let the bios control the backlight */
- save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
- /* tell the bios not to handle mode switching */
- save->bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch);
- OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch);
- } else {
- OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch);
- OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
- }
- } else {
- /* let the bios control the backlight */
- save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
- /* tell the bios not to handle mode switching */
- save->bios_6_scratch |= RADEON_DISPLAY_SWITCHING_DIS;
- /* tell the bios a driver is loaded */
- save->bios_7_scratch |= RADEON_DRV_LOADED;
-
- OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch);
- OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
- //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch);
- }
-
-}
-
-
-/* Called at the start of each server generation. */
-Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
- int argc, char **argv)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int hasDRI = 0;
- int i;
-#ifdef RENDER
- int subPixelOrder = SubPixelUnknown;
- char* s;
-#endif
-
-
- info->accelOn = FALSE;
-#ifdef USE_XAA
- info->accel = NULL;
-#endif
-#ifdef XF86DRI
- pScrn->fbOffset = info->frontOffset;
-#endif
-
- if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
-#ifdef XF86DRI
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "RADEONScreenInit %lx %ld %d\n",
- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
-#else
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONScreenInit %lx %ld\n",
- pScrn->memPhysBase, pScrn->fbOffset);
-#endif
- if (!RADEONMapMem(pScrn)) return FALSE;
-
-#ifdef XF86DRI
- info->fbX = 0;
- info->fbY = 0;
-#endif
-
- info->PaletteSavedOnVT = FALSE;
-
- info->crtc_on = FALSE;
- info->crtc2_on = FALSE;
-
- RADEONSave(pScrn);
-
- /* set initial bios scratch reg state */
- RADEONInitBIOSRegisters(pScrn);
-
- /* blank the outputs/crtcs */
- RADEONBlank(pScrn);
-
- if (info->IsMobility && !IS_AVIVO_VARIANT) {
- if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
- RADEONSetDynamicClock(pScrn, 1);
- } else {
- RADEONSetDynamicClock(pScrn, 0);
- }
- }
-
- if (IS_R300_VARIANT || IS_RV100_VARIANT)
- RADEONForceSomeClocks(pScrn);
-
- if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Color tiling not supported with virtual x resolutions larger than %d, disabling\n",
- info->MaxSurfaceWidth);
- info->allowColorTiling = FALSE;
- }
- if (info->allowColorTiling) {
- info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
- }
-
- /* Visual setup */
- miClearVisualTypes();
- if (!miSetVisualTypes(pScrn->depth,
- miGetDefaultVisualMask(pScrn->depth),
- pScrn->rgbBits,
- pScrn->defaultVisual)) return FALSE;
- miSetPixmapDepths ();
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- MessageType from;
-
- info->depthBits = pScrn->depth;
-
- from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS,
- &info->depthBits)
- ? X_CONFIG : X_DEFAULT;
-
- if (info->depthBits != 16 && info->depthBits != 24) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Value for Option \"DepthBits\" must be 16 or 24\n");
- info->depthBits = pScrn->depth;
- from = X_DEFAULT;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from,
- "Using %d bit depth buffer\n", info->depthBits);
- }
-
-
- hasDRI = info->directRenderingEnabled;
-#endif /* XF86DRI */
-
- /* Initialize the memory map, this basically calculates the values
- * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION
- */
- RADEONInitMemoryMap(pScrn);
-
- /* empty the surfaces */
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int j;
- for (j = 0; j < 8; j++) {
- OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0);
- OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0);
- }
-
-#ifdef XF86DRI
- /* Depth moves are disabled by default since they are extremely slow */
- info->depthMoves = xf86ReturnOptValBool(info->Options,
- OPTION_DEPTH_MOVE, FALSE);
- if (info->depthMoves && info->allowColorTiling) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n");
- } else if (info->depthMoves) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Depth moves don't work without color tiling, disabled\n");
- info->depthMoves = FALSE;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Depth moves disabled by default\n");
- }
-#endif
-
- /* Initial setup of surfaces */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Setting up initial surfaces\n");
- RADEONChangeSurfaces(pScrn);
-
- /* Memory manager setup */
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Setting up accel memmap\n");
-
-#ifdef USE_EXA
- if (info->useEXA) {
-#ifdef XF86DRI
- MessageType from = X_DEFAULT;
-
- if (hasDRI) {
- info->accelDFS = info->cardType != CARD_AGP;
-
- if (xf86GetOptValInteger(info->Options, OPTION_ACCEL_DFS,
- &info->accelDFS)) {
- from = X_CONFIG;
- }
-
- /* Reserve approx. half of offscreen memory for local textures by
- * default, can be overridden with Option "FBTexPercent".
- * Round down to a whole number of texture regions.
- */
- info->textureSize = 50;
-
- if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
- &(info->textureSize))) {
- if (info->textureSize < 0 || info->textureSize > 100) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal texture memory percentage: %dx, setting to default 50%%\n",
- info->textureSize);
- info->textureSize = 50;
- }
- }
- }
-
- xf86DrvMsg(pScrn->scrnIndex, from,
- "%ssing accelerated EXA DownloadFromScreen hook\n",
- info->accelDFS ? "U" : "Not u");
-#endif /* XF86DRI */
-
- if (!RADEONSetupMemEXA(pScreen))
- return FALSE;
- }
-#endif
-
-#if defined(XF86DRI) && defined(USE_XAA)
- if (!info->useEXA && hasDRI) {
- info->textureSize = -1;
- if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
- &(info->textureSize))) {
- if (info->textureSize < 0 || info->textureSize > 100) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal texture memory percentage: %dx, using default behaviour\n",
- info->textureSize);
- info->textureSize = -1;
- }
- }
- if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen))
- return FALSE;
- pScrn->fbOffset = info->frontOffset;
- }
-#endif
-
-#ifdef USE_XAA
- if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen))
- return FALSE;
-#endif
-
- info->dst_pitch_offset = (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
-
- /* Setup DRI after visuals have been established, but before fbScreenInit is
- * called. fbScreenInit will eventually call the driver's InitGLXVisuals
- * call back. */
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- /* FIXME: When we move to dynamic allocation of back and depth
- * buffers, we will want to revisit the following check for 3
- * times the virtual size of the screen below.
- */
- int width_bytes = (pScrn->displayWidth *
- info->CurrentLayout.pixel_bytes);
- int maxy = info->FbMapSize / width_bytes;
-
- if (maxy <= pScrn->virtualY * 3) {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Static buffer allocation failed. Disabling DRI.\n");
- xf86DrvMsg(scrnIndex, X_ERROR,
- "At least %d kB of video memory needed at this "
- "resolution and depth.\n",
- (pScrn->displayWidth * pScrn->virtualY *
- info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
- info->directRenderingEnabled = FALSE;
- } else {
- info->directRenderingEnabled = RADEONDRIScreenInit(pScreen);
- }
- }
-
- /* Tell DRI about new memory map */
- if (info->directRenderingEnabled && info->newMemoryMap) {
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[drm] failed to enable new memory map\n");
- RADEONDRICloseScreen(pScreen);
- info->directRenderingEnabled = FALSE;
- }
- }
-#endif
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing fb layer\n");
-
- if (info->r600_shadow_fb) {
- info->fb_shadow = xcalloc(1,
- pScrn->displayWidth * pScrn->virtualY *
- ((pScrn->bitsPerPixel + 7) >> 3));
- if (info->fb_shadow == NULL) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Failed to allocate shadow framebuffer\n");
- info->r600_shadow_fb = FALSE;
- } else {
- if (!fbScreenInit(pScreen, info->fb_shadow,
- pScrn->virtualX, pScrn->virtualY,
- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
- pScrn->bitsPerPixel))
- return FALSE;
- }
- }
-
- if (info->r600_shadow_fb == FALSE) {
- /* Init fb layer */
- if (!fbScreenInit(pScreen, info->FB,
- pScrn->virtualX, pScrn->virtualY,
- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
- pScrn->bitsPerPixel))
- return FALSE;
- }
-
- xf86SetBlackWhitePixels(pScreen);
-
- if (pScrn->bitsPerPixel > 8) {
- VisualPtr visual;
-
- visual = pScreen->visuals + pScreen->numVisuals;
- while (--visual >= pScreen->visuals) {
- if ((visual->class | DynamicClass) == DirectColor) {
- visual->offsetRed = pScrn->offset.red;
- visual->offsetGreen = pScrn->offset.green;
- visual->offsetBlue = pScrn->offset.blue;
- visual->redMask = pScrn->mask.red;
- visual->greenMask = pScrn->mask.green;
- visual->blueMask = pScrn->mask.blue;
- }
- }
- }
-
- /* Must be after RGB order fixed */
- fbPictureInit (pScreen, 0, 0);
-
-#ifdef RENDER
- if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) {
- if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB;
- else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
- else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
- PictureSetSubpixelOrder (pScreen, subPixelOrder);
- }
-#endif
-
- pScrn->vtSema = TRUE;
-
- /* xf86CrtcRotate() accesses pScrn->pScreen */
- pScrn->pScreen = pScreen;
-
-#if 1
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
-
- /* Mark that we'll need to re-set the mode for sure */
- memset(&crtc->mode, 0, sizeof(crtc->mode));
- if (!crtc->desiredMode.CrtcHDisplay) {
- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode);
- crtc->desiredRotation = RR_Rotate_0;
- crtc->desiredX = 0;
- crtc->desiredY = 0;
- }
-
- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, crtc->desiredX, crtc->desiredY))
- return FALSE;
-
- }
-#else
- /* seems to do the wrong thing on some cards??? */
- if (!xf86SetDesiredModes (pScrn))
- return FALSE;
-#endif
-
- RADEONSaveScreen(pScreen, SCREEN_SAVER_ON);
-
- /* Backing store setup */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing backing store\n");
- miInitializeBackingStore(pScreen);
- xf86SetBackingStore(pScreen);
-
- /* DRI finalisation */
-#ifdef XF86DRI
- if (info->directRenderingEnabled && info->cardType==CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19)
- {
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->pciGartOffset) < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failed set pci gart location\n");
-
- if (info->pKernelDRMVersion->version_minor >= 26) {
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->pciGartSize) < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failed set pci gart table size\n");
- }
- }
- if (info->directRenderingEnabled) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "DRI Finishing init !\n");
- info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen);
- }
- if (info->directRenderingEnabled) {
- /* DRI final init might have changed the memory map, we need to adjust
- * our local image to make sure we restore them properly on mode
- * changes or VT switches
- */
- RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
-
- if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
- /* we need to re-calculate bandwidth because of AGPMode difference. */
- RADEONInitDispBandwidth(pScrn);
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
-
- /* we might already be in tiled mode, tell drm about it */
- if (info->directRenderingEnabled && info->tilingEnabled) {
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failed changing tiling status\n");
- }
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct rendering disabled\n");
- }
-#endif
-
- /* Make sure surfaces are allright since DRI setup may have changed them */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Setting up final surfaces\n");
-
- RADEONChangeSurfaces(pScrn);
-
-
- /* Enable aceleration */
- if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing Acceleration\n");
- if (RADEONAccelInit(pScreen)) {
- xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
- info->accelOn = TRUE;
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Acceleration initialization failed\n");
- xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
- info->accelOn = FALSE;
- }
- } else {
- xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
- info->accelOn = FALSE;
- }
-
- /* Init DPMS */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing DPMS\n");
- xf86DPMSInit(pScreen, xf86DPMSSet, 0);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing Cursor\n");
-
- /* Set Silken Mouse */
- xf86SetSilkenMouse(pScreen);
-
- /* Cursor setup */
- miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
-
- /* Hardware cursor setup */
- if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
- if (RADEONCursorInit(pScreen)) {
-#ifdef USE_XAA
- if (!info->useEXA) {
- int width, height;
-
- if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
- 0, 0, 0)) {
- xf86DrvMsg(scrnIndex, X_INFO,
- "Largest offscreen area available: %d x %d\n",
- width, height);
- }
- }
-#endif /* USE_XAA */
- } else {
- xf86DrvMsg(scrnIndex, X_ERROR,
- "Hardware cursor initialization failed\n");
- xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
- }
- } else {
- xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
- }
-
- /* DGA setup */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing DGA\n");
- RADEONDGAInit(pScreen);
-
- /* Init Xv */
- if (info->ChipFamily < CHIP_FAMILY_R600) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing Xv\n");
- RADEONInitVideo(pScreen);
- }
-
- if (info->r600_shadow_fb == TRUE) {
- if (!shadowSetup(pScreen)) {
- return FALSE;
- }
- }
-
- /* Provide SaveScreen & wrap BlockHandler and CloseScreen */
- /* Wrap CloseScreen */
- info->CloseScreen = pScreen->CloseScreen;
- pScreen->CloseScreen = RADEONCloseScreen;
- pScreen->SaveScreen = RADEONSaveScreen;
- info->BlockHandler = pScreen->BlockHandler;
- pScreen->BlockHandler = RADEONBlockHandler;
- info->CreateScreenResources = pScreen->CreateScreenResources;
- pScreen->CreateScreenResources = RADEONCreateScreenResources;
-
- if (!xf86CrtcScreenInit (pScreen))
- return FALSE;
-
- /* Wrap pointer motion to flip touch screen around */
- info->PointerMoved = pScrn->PointerMoved;
- pScrn->PointerMoved = RADEONPointerMoved;
-
- /* Colormap setup */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Initializing color map\n");
- if (!miCreateDefColormap(pScreen)) return FALSE;
- if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8,
- RADEONLoadPalette, NULL,
- CMAP_PALETTED_TRUECOLOR
-#if 0 /* This option messes up text mode! (eich at suse.de) */
- | CMAP_LOAD_EVEN_IF_OFFSCREEN
-#endif
- | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE;
-
- /* Note unused options */
- if (serverGeneration == 1)
- xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONScreenInit finished\n");
-
- return TRUE;
-}
-
-/* Write memory mapping registers */
-void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int timeout;
- CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
-
- radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc,
- &mc_agp_loc, &mc_agp_loc_hi);
-
- if (info->IsSecondary)
- return;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "RADEONRestoreMemMapRegisters() : \n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_FB_LOCATION : 0x%08x 0x%08x\n",
- (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_AGP_LOCATION : 0x%08x\n",
- (unsigned)restore->mc_agp_location);
-
- if (IS_AVIVO_VARIANT) {
-
- if (mc_fb_loc != restore->mc_fb_location ||
- mc_agp_loc != restore->mc_agp_location) {
- CARD32 tmp;
-
- RADEONWaitForIdleMMIO(pScrn);
-
- OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
- OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
-
- /* Stop display & memory access */
- tmp = INREG(AVIVO_D1CRTC_CONTROL);
- OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
-
- tmp = INREG(AVIVO_D2CRTC_CONTROL);
- OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
-
- tmp = INREG(AVIVO_D2CRTC_CONTROL);
-
- usleep(10000);
- timeout = 0;
- while (!(avivo_get_mc_idle(pScrn))) {
- if (++timeout > 1000000) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout trying to update memory controller settings !\n");
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "You will probably crash now ... \n");
- /* Nothing we can do except maybe try to kill the server,
- * let's wait 2 seconds to leave the above message a chance
- * to maybe hit the disk and continue trying to setup despite
- * the MC being non-idle
- */
- usleep(2000000);
- }
- usleep(10);
- }
-
- radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP,
- restore->mc_fb_location,
- restore->mc_agp_location,
- restore->mc_agp_location_hi);
-
- if (info->ChipFamily < CHIP_FAMILY_R600) {
- OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location);
- } else {
- OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000);
- }
-
- /* Reset the engine and HDP */
- RADEONEngineReset(pScrn);
- }
- } else {
-
- /* Write memory mapping registers only if their value change
- * since we must ensure no access is done while they are
- * reprogrammed
- */
- if (mc_fb_loc != restore->mc_fb_location ||
- mc_agp_loc != restore->mc_agp_location) {
- CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
- CARD32 old_mc_status, status_idle;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- " Map Changed ! Applying ...\n");
-
- /* Make sure engine is idle. We assume the CCE is stopped
- * at this point
- */
- RADEONWaitForIdleMMIO(pScrn);
-
- if (info->IsIGP)
- goto igp_no_mcfb;
-
- /* Capture MC_STATUS in case things go wrong ... */
- old_mc_status = INREG(RADEON_MC_STATUS);
-
- /* Stop display & memory access */
- ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
- OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
- crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
- OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
- crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
- RADEONWaitForVerticalSync(pScrn);
- OUTREG(RADEON_CRTC_GEN_CNTL,
- (crtc_gen_cntl
- & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN))
- | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
-
- if (pRADEONEnt->HasCRTC2) {
- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
- RADEONWaitForVerticalSync2(pScrn);
- OUTREG(RADEON_CRTC2_GEN_CNTL,
- (crtc2_gen_cntl
- & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN))
- | RADEON_CRTC2_DISP_REQ_EN_B);
- }
-
- /* Make sure the chip settles down (paranoid !) */
- usleep(100000);
-
- /* Wait for MC idle */
- if (IS_R300_VARIANT)
- status_idle = R300_MC_IDLE;
- else
- status_idle = RADEON_MC_IDLE;
-
- timeout = 0;
- while (!(INREG(RADEON_MC_STATUS) & status_idle)) {
- if (++timeout > 1000000) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout trying to update memory controller settings !\n");
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
- (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status);
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "You will probably crash now ... \n");
- /* Nothing we can do except maybe try to kill the server,
- * let's wait 2 seconds to leave the above message a chance
- * to maybe hit the disk and continue trying to setup despite
- * the MC being non-idle
- */
- usleep(2000000);
- }
- usleep(10);
- }
-
- /* Update maps, first clearing out AGP to make sure we don't get
- * a temporary overlap
- */
- OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
- OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location);
- radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location,
- 0xfffffffc, 0);
- igp_no_mcfb:
- radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0,
- restore->mc_agp_location, 0);
- /* Make sure map fully reached the chip */
- (void)INREG(RADEON_MC_FB_LOCATION);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- " Map applied, resetting engine ...\n");
-
- /* Reset the engine and HDP */
- RADEONEngineReset(pScrn);
-
- /* Make sure we have sane offsets before re-enabling the CRTCs, disable
- * stereo, clear offsets, and wait for offsets to catch up with hw
- */
-
- OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
- OUTREG(RADEON_CRTC_OFFSET, 0);
- OUTREG(RADEON_CUR_OFFSET, 0);
- timeout = 0;
- while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) {
- if (timeout++ > 1000000) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout waiting for CRTC offset to update !\n");
- break;
- }
- usleep(1000);
- }
- if (pRADEONEnt->HasCRTC2) {
- OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
- OUTREG(RADEON_CRTC2_OFFSET, 0);
- OUTREG(RADEON_CUR2_OFFSET, 0);
- timeout = 0;
- while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) {
- if (timeout++ > 1000000) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Timeout waiting for CRTC2 offset to update !\n");
- break;
- }
- usleep(1000);
- }
- }
- }
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Updating display base addresses...\n");
-
- OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr);
- if (pRADEONEnt->HasCRTC2)
- OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr);
- OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr);
- (void)INREG(RADEON_OV0_BASE_ADDR);
-
- /* More paranoia delays, wait 100ms */
- usleep(100000);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Memory map updated.\n");
- }
-}
-
-#ifdef XF86DRI
-static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 fb, agp, agp_hi;
- int changed;
-
- if (info->IsSecondary)
- return;
-
- radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi);
-
- if (fb != info->mc_fb_location || agp != info->mc_agp_location ||
- agp_hi || info->mc_agp_location_hi)
- changed = 1;
-
- if (changed) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "DRI init changed memory map, adjusting ...\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
- (long unsigned int)info->mc_fb_location, (long unsigned int)fb);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
- (long unsigned int)info->mc_agp_location, (long unsigned int)agp);
- info->mc_fb_location = fb;
- info->mc_agp_location = agp;
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
- else
- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
-
- info->dst_pitch_offset =
- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
- RADEONInitMemMapRegisters(pScrn, save, info);
- RADEONRestoreMemMapRegisters(pScrn, save);
- }
-
-#ifdef USE_EXA
- if (info->accelDFS)
- {
- drmRadeonGetParam gp;
- int gart_base;
-
- memset(&gp, 0, sizeof(gp));
- gp.param = RADEON_PARAM_GART_BASE;
- gp.value = &gart_base;
-
- if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &gp,
- sizeof(gp)) < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Failed to determine GART area MC location, not using "
- "accelerated DownloadFromScreen hook!\n");
- info->accelDFS = FALSE;
- } else {
- info->gartLocation = gart_base;
- }
- }
-#endif /* USE_EXA */
-}
-#endif
-
-/* restore original surface info (for fb console). */
-static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int surfnr;
-
- for ( surfnr = 0; surfnr < 8; surfnr++ ) {
- OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]);
- OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]);
- }
-}
-
-/* save original surface info (for fb console). */
-static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int surfnr;
-
- for ( surfnr = 0; surfnr < 8; surfnr++ ) {
- save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr);
- save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr);
- save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr);
- }
-}
-
-void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
-{
- /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed.
- Everything else is left as untiled. This means we need to use eplicit src/dst pitch control
- when blitting, based on the src/target address, and can no longer use a default offset.
- But OTOH we don't need to dynamically change surfaces (for xv for instance), and some
- ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works...
- For simplicity, just always update everything (just let the ioctl fail - could do better).
- All surface addresses are relative to RADEON_MC_FB_LOCATION */
-
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int cpp = info->CurrentLayout.pixel_bytes;
- /* depth/front/back pitch must be identical (and the same as displayWidth) */
- int width_bytes = pScrn->displayWidth * cpp;
- int bufferSize = ((((pScrn->virtualY + 15) & ~15) * width_bytes
- + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
- unsigned int color_pattern, swap_pattern;
-
- if (!info->allowColorTiling)
- return;
-
- swap_pattern = 0;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- switch (pScrn->bitsPerPixel) {
- case 16:
- swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
- break;
-
- case 32:
- swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
- break;
- }
-#endif
- if (info->ChipFamily < CHIP_FAMILY_R200) {
- color_pattern = RADEON_SURF_TILE_COLOR_MACRO;
- } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- color_pattern = R300_SURF_TILE_COLOR_MACRO;
- } else {
- color_pattern = R200_SURF_TILE_COLOR_MACRO;
- }
-#ifdef XF86DRI
- if (info->directRenderingInited) {
- drmRadeonSurfaceFree drmsurffree;
- drmRadeonSurfaceAlloc drmsurfalloc;
- int retvalue;
- int depthCpp = (info->depthBits - 8) / 4;
- int depth_width_bytes = pScrn->displayWidth * depthCpp;
- int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes
- + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
- unsigned int depth_pattern;
-
- drmsurffree.address = info->frontOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
- &drmsurffree, sizeof(drmsurffree));
-
- if (!((info->ChipFamily == CHIP_FAMILY_RV100) ||
- (info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200))) {
- drmsurffree.address = info->depthOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
- &drmsurffree, sizeof(drmsurffree));
- }
-
- if (!info->noBackBuffer) {
- drmsurffree.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
- &drmsurffree, sizeof(drmsurffree));
- }
-
- drmsurfalloc.size = bufferSize;
- drmsurfalloc.address = info->frontOffset;
- drmsurfalloc.flags = swap_pattern;
-
- if (info->tilingEnabled) {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- drmsurfalloc.flags |= (width_bytes / 8) | color_pattern;
- else
- drmsurfalloc.flags |= (width_bytes / 16) | color_pattern;
- }
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
- &drmsurfalloc, sizeof(drmsurfalloc));
- if (retvalue < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "drm: could not allocate surface for front buffer!\n");
-
- if ((info->have3DWindows) && (!info->noBackBuffer)) {
- drmsurfalloc.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
- &drmsurfalloc, sizeof(drmsurfalloc));
- if (retvalue < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "drm: could not allocate surface for back buffer!\n");
- }
-
- if (info->ChipFamily < CHIP_FAMILY_R200) {
- if (depthCpp == 2)
- depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP;
- else
- depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP;
- } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- if (depthCpp == 2)
- depth_pattern = R300_SURF_TILE_COLOR_MACRO;
- else
- depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP;
- } else {
- if (depthCpp == 2)
- depth_pattern = R200_SURF_TILE_DEPTH_16BPP;
- else
- depth_pattern = R200_SURF_TILE_DEPTH_32BPP;
- }
-
- /* rv100 and probably the derivative igps don't have depth tiling on all the time? */
- if (info->have3DWindows &&
- (!((info->ChipFamily == CHIP_FAMILY_RV100) ||
- (info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200)))) {
- drmRadeonSurfaceAlloc drmsurfalloc;
- drmsurfalloc.size = depthBufferSize;
- drmsurfalloc.address = info->depthOffset;
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern;
- else
- drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
- &drmsurfalloc, sizeof(drmsurfalloc));
- if (retvalue < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "drm: could not allocate surface for depth buffer!\n");
- }
- }
- else
-#endif
- {
- unsigned int surf_info = swap_pattern;
- unsigned char *RADEONMMIO = info->MMIO;
- /* we don't need anything like WaitForFifo, no? */
- if (info->tilingEnabled) {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- surf_info |= (width_bytes / 8) | color_pattern;
- else
- surf_info |= (width_bytes / 16) | color_pattern;
- }
- OUTREG(RADEON_SURFACE0_INFO, surf_info);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0);
- OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1);
-/* xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "surface0 set to %x, LB 0x%x UB 0x%x\n",
- surf_info, 0, bufferSize - 1024);*/
- }
-
- /* Update surface images */
- RADEONSaveSurfaces(pScrn, info->ModeReg);
-}
-
-/* Read memory map */
-static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location,
- &save->mc_agp_location, &save->mc_agp_location_hi);
-
- if (!IS_AVIVO_VARIANT) {
- save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR);
- save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR);
- save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR);
- }
-}
-
-
-#if 0
-/* Read palette data */
-static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int i;
-
-#ifdef ENABLE_FLAT_PANEL
- /* Select palette 0 (main CRTC) if using FP-enabled chip */
- /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */
-#endif
- PAL_SELECT(1);
- INPAL_START(0);
- for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT();
- PAL_SELECT(0);
- INPAL_START(0);
- for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT();
- save->palette_valid = TRUE;
-}
-#endif
-
-void
-avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- struct avivo_state *state = &save->avivo;
-
- // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
- // state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
- state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL);
- state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL);
-
- state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN);
- state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL);
-
- state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
- state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
- state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV);
- state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC);
- state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
- state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL);
- state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL);
- state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL);
-
- state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
- state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV);
- state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV);
- state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC);
- state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
- state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL);
- state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL);
- state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
-
- state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL);
-
- state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL);
- state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END);
- state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A);
- state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL);
- state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B);
- state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL);
-
- state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL);
- state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END);
- state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A);
- state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL);
- state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B);
- state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL);
-
- state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL);
- state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL);
- state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL);
- state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL);
-
- state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL);
-
- state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE);
- state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
- state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL);
- state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS);
- state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS);
- state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH);
- state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X);
- state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y);
- state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START);
- state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START);
- state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END);
- state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END);
-
- state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
- state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
- state->grph1.scl_enable = INREG(AVIVO_D1SCL_SCALER_ENABLE);
- state->grph1.scl_tap_control = INREG(AVIVO_D1SCL_SCALER_TAP_CONTROL);
-
- state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
-
- state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL);
- state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END);
- state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A);
- state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL);
- state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B);
- state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL);
-
- state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL);
- state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END);
- state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A);
- state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL);
- state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B);
- state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL);
-
- state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL);
- state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL);
- state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL);
- state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL);
-
- state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL);
-
- state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE);
- state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
- state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL);
- state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS);
- state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS);
- state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH);
- state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X);
- state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y);
- state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START);
- state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START);
- state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END);
- state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END);
-
- state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
- state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
- state->grph2.scl_enable = INREG(AVIVO_D2SCL_SCALER_ENABLE);
- state->grph2.scl_tap_control = INREG(AVIVO_D2SCL_SCALER_TAP_CONTROL);
-
- state->daca.enable = INREG(AVIVO_DACA_ENABLE);
- state->daca.source_select = INREG(AVIVO_DACA_SOURCE_SELECT);
- state->daca.force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL);
- state->daca.powerdown = INREG(AVIVO_DACA_POWERDOWN);
-
- state->dacb.enable = INREG(AVIVO_DACB_ENABLE);
- state->dacb.source_select = INREG(AVIVO_DACB_SOURCE_SELECT);
- state->dacb.force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL);
- state->dacb.powerdown = INREG(AVIVO_DACB_POWERDOWN);
-
- state->tmds1.cntl = INREG(AVIVO_TMDSA_CNTL);
- state->tmds1.source_select = INREG(AVIVO_TMDSA_SOURCE_SELECT);
- state->tmds1.bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL);
- state->tmds1.data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION);
- state->tmds1.transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE);
- state->tmds1.transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL);
-
- state->tmds2.cntl = INREG(AVIVO_LVTMA_CNTL);
- state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT);
- state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
- state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- state->tmds2.transmitter_enable = INREG(R600_LVTMA_TRANSMITTER_ENABLE);
- state->tmds2.transmitter_cntl = INREG(R600_LVTMA_TRANSMITTER_CONTROL);
- state->lvtma_pwrseq_cntl = INREG(R600_LVTMA_PWRSEQ_CNTL);
- state->lvtma_pwrseq_state = INREG(R600_LVTMA_PWRSEQ_STATE);
- } else {
- state->tmds2.transmitter_enable = INREG(R500_LVTMA_TRANSMITTER_ENABLE);
- state->tmds2.transmitter_cntl = INREG(R500_LVTMA_TRANSMITTER_CONTROL);
- state->lvtma_pwrseq_cntl = INREG(R500_LVTMA_PWRSEQ_CNTL);
- state->lvtma_pwrseq_state = INREG(R500_LVTMA_PWRSEQ_STATE);
- }
-
- if (state->crtc1.control & AVIVO_CRTC_EN)
- info->crtc_on = TRUE;
-
- if (state->crtc2.control & AVIVO_CRTC_EN)
- info->crtc2_on = TRUE;
-
-}
-
-void
-avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- struct avivo_state *state = &restore->avivo;
-
- // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
- // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
- // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
-
-
- OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en);
- OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control);
-
- OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src);
- OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div);
- OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div);
- OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src);
- OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div);
- OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl);
- OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl);
- OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl);
-
- OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src);
- OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div);
- OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div);
- OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src);
- OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div);
- OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl);
- OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl);
- OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl);
-
- OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source);
-
- OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total);
- OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end);
- OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a);
- OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl);
- OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b);
- OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl);
-
- OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total);
- OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end);
- OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a);
- OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl);
- OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b);
- OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl);
-
- OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control);
- OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control);
- OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control);
- OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control);
-
- OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control);
-
- OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
- OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
- OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr);
- OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset);
- OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start);
- OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start);
- OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end);
- OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end);
-
- OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
- OUTREG(AVIVO_D1SCL_SCALER_ENABLE, state->grph1.scl_enable);
- OUTREG(AVIVO_D1SCL_SCALER_TAP_CONTROL, state->grph1.scl_tap_control);
-
- OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
-
- OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total);
- OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end);
- OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a);
- OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl);
- OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b);
- OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl);
-
- OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total);
- OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end);
- OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a);
- OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl);
- OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b);
- OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl);
-
- OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control);
- OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control);
- OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control);
- OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control);
-
- OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control);
-
- OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
- OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
- OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
- OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr);
- OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch);
- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset);
- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset);
- OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start);
- OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start);
- OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end);
- OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end);
-
- OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
- OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
- OUTREG(AVIVO_D2SCL_SCALER_ENABLE, state->grph2.scl_enable);
- OUTREG(AVIVO_D2SCL_SCALER_TAP_CONTROL, state->grph2.scl_tap_control);
-
- OUTREG(AVIVO_DACA_ENABLE, state->daca.enable);
- OUTREG(AVIVO_DACA_SOURCE_SELECT, state->daca.source_select);
- OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->daca.force_output_cntl);
- OUTREG(AVIVO_DACA_POWERDOWN, state->daca.powerdown);
-
- OUTREG(AVIVO_TMDSA_CNTL, state->tmds1.cntl);
- OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1.bit_depth_cntl);
- OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1.data_sync);
- OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1.transmitter_enable);
- OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1.transmitter_cntl);
- OUTREG(AVIVO_TMDSA_SOURCE_SELECT, state->tmds1.source_select);
-
- OUTREG(AVIVO_DACB_ENABLE, state->dacb.enable);
- OUTREG(AVIVO_DACB_SOURCE_SELECT, state->dacb.source_select);
- OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dacb.force_output_cntl);
- OUTREG(AVIVO_DACB_POWERDOWN, state->dacb.powerdown);
-
- OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl);
- OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl);
- OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync);
- OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
- OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
- OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
- OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
- } else {
- OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
- OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
- OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
- OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
- }
-
- OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
- OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
-}
-
-void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- struct avivo_state *state = &restore->avivo;
-
- OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
- OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
-}
-
-static void
-RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch);
- OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch);
- OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch);
- OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch);
- OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch);
- OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch);
- OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch);
- OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch);
- } else {
- OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch);
- OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch);
- OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch);
- OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch);
- OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
- OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
- OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch);
- OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch);
- }
-}
-
-static void
-RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH);
- save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH);
- save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH);
- save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH);
- save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH);
- save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH);
- save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH);
- save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH);
- } else {
- save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
- save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH);
- save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH);
- save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH);
- save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH);
- save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
- save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
- save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH);
- }
-}
-
-/* Save everything needed to restore the original VC state */
-static void RADEONSave(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = info->SavedReg;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONSave\n");
-
-#ifdef WITH_VGAHW
- if (info->VGAAccess) {
- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- vgaHWUnlock(hwp);
-# if defined(__powerpc__)
- /* temporary hack to prevent crashing on PowerMacs when trying to
- * read VGA fonts and colormap, will find a better solution
- * in the future. TODO: Check if there's actually some VGA stuff
- * setup in the card at all !!
- */
- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
-# else
- /* Save mode * & fonts & cmap */
- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL);
-# endif
- vgaHWLock(hwp);
- }
-#endif
-
- if (IS_AVIVO_VARIANT) {
- RADEONSaveMemMapRegisters(pScrn, save);
- avivo_save(pScrn, save);
- } else {
- save->dp_datatype = INREG(RADEON_DP_DATATYPE);
- save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
- save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
- RADEONPllErrataAfterIndex(info);
-
- RADEONSaveMemMapRegisters(pScrn, save);
- RADEONSaveCommonRegisters(pScrn, save);
- RADEONSavePLLRegisters(pScrn, save);
- RADEONSaveCrtcRegisters(pScrn, save);
- RADEONSaveFPRegisters(pScrn, save);
- RADEONSaveDACRegisters(pScrn, save);
- if (pRADEONEnt->HasCRTC2) {
- RADEONSaveCrtc2Registers(pScrn, save);
- RADEONSavePLL2Registers(pScrn, save);
- }
- if (info->InternalTVOut)
- RADEONSaveTVRegisters(pScrn, save);
- }
-
- RADEONSaveBIOSRegisters(pScrn, save);
- RADEONSaveSurfaces(pScrn, save);
-
-}
-
-/* Restore the original (text) mode */
-void RADEONRestore(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr restore = info->SavedReg;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- xf86CrtcPtr crtc;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONRestore\n");
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE);
-#endif
-
- RADEONBlank(pScrn);
-
- if (IS_AVIVO_VARIANT) {
- RADEONRestoreMemMapRegisters(pScrn, restore);
- avivo_restore(pScrn, restore);
- } else {
- OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
- RADEONPllErrataAfterIndex(info);
- OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
- OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
- OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
- OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
-
- if (!info->IsSecondary) {
- RADEONRestoreMemMapRegisters(pScrn, restore);
- RADEONRestoreCommonRegisters(pScrn, restore);
-
- if (pRADEONEnt->HasCRTC2) {
- RADEONRestoreCrtc2Registers(pScrn, restore);
- RADEONRestorePLL2Registers(pScrn, restore);
- }
-
- RADEONRestoreCrtcRegisters(pScrn, restore);
- RADEONRestorePLLRegisters(pScrn, restore);
- RADEONRestoreRMXRegisters(pScrn, restore);
- RADEONRestoreFPRegisters(pScrn, restore);
- RADEONRestoreFP2Registers(pScrn, restore);
- RADEONRestoreLVDSRegisters(pScrn, restore);
-
- if (info->InternalTVOut)
- RADEONRestoreTVRegisters(pScrn, restore);
- }
-
- RADEONRestoreBIOSRegisters(pScrn, restore);
- RADEONRestoreSurfaces(pScrn, restore);
- }
-
-#if 1
- /* Temp fix to "solve" VT switch problems. When switching VTs on
- * some systems, the console can either hang or the fonts can be
- * corrupted. This hack solves the problem 99% of the time. A
- * correct fix is being worked on.
- */
- usleep(100000);
-#endif
-
- /* need to make sure we don't enable a crtc by accident or we may get a hang */
- if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) {
- if (info->crtc2_on && xf86_config->num_crtc > 1) {
- crtc = xf86_config->crtc[1];
- crtc->funcs->dpms(crtc, DPMSModeOn);
- }
- }
- if (info->crtc_on) {
- crtc = xf86_config->crtc[0];
- crtc->funcs->dpms(crtc, DPMSModeOn);
- }
-
-#ifdef WITH_VGAHW
- if (info->VGAAccess) {
- vgaHWPtr hwp = VGAHWPTR(pScrn);
- vgaHWUnlock(hwp);
-# if defined(__powerpc__)
- /* Temporary hack to prevent crashing on PowerMacs when trying to
- * write VGA fonts, will find a better solution in the future
- */
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
-# else
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL );
-# endif
- vgaHWLock(hwp);
- }
-#endif
-
- /* to restore console mode, DAC registers should be set after every other registers are set,
- * otherwise,we may get blank screen
- */
- if (IS_AVIVO_VARIANT)
- avivo_restore_vga_regs(pScrn, restore);
- RADEONRestoreDACRegisters(pScrn, restore);
-
-#if 0
- RADEONWaitForVerticalSync(pScrn);
-#endif
-}
-
-#if 0
-/* Define initial palette for requested video mode. This doesn't do
- * anything for XFree86 4.0.
- */
-static void RADEONInitPalette(RADEONSavePtr save)
-{
- save->palette_valid = FALSE;
-}
-#endif
-
-static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- Bool unblank;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONSaveScreen(%d)\n", mode);
-
- unblank = xf86IsUnblank(mode);
- if (unblank) SetTimeSinceLastInputEvent();
-
- if ((pScrn != NULL) && pScrn->vtSema) {
- if (unblank)
- RADEONUnblank(pScrn);
- else
- RADEONBlank(pScrn);
- }
- return TRUE;
-}
-
-Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- Bool tilingOld = info->tilingEnabled;
- Bool ret;
-#ifdef XF86DRI
- Bool CPStarted = info->CPStarted;
-
- if (CPStarted) {
- DRILock(pScrn->pScreen, 0);
- RADEONCP_STOP(pScrn, info);
- }
-#endif
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONSwitchMode() !n");
-
- if (info->allowColorTiling) {
- info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
-#ifdef XF86DRI
- if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
- RADEONSAREAPrivPtr pSAREAPriv;
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "[drm] failed changing tiling status\n");
- pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
- info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
- }
-#endif
- }
-
- if (info->accelOn)
- RADEON_SYNC(info, pScrn);
-
- ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
-
- if (info->tilingEnabled != tilingOld) {
- /* need to redraw front buffer, I guess this can be considered a hack ? */
- xf86EnableDisableFBAccess(scrnIndex, FALSE);
- RADEONChangeSurfaces(pScrn);
- xf86EnableDisableFBAccess(scrnIndex, TRUE);
- /* xf86SetRootClip would do, but can't access that here */
- }
-
- if (info->accelOn) {
- RADEON_SYNC(info, pScrn);
- RADEONEngineRestore(pScrn);
- }
-
-#ifdef XF86DRI
- if (CPStarted) {
- RADEONCP_START(pScrn, info);
- DRIUnlock(pScrn->pScreen);
- }
-#endif
-
- /* reset ecp for overlay */
- info->ecp_div = -1;
-
- return ret;
-}
-
-#ifdef X_XF86MiscPassMessage
-Bool RADEONHandleMessage(int scrnIndex, const char* msgtype,
- const char* msgval, char** retmsg)
-{
- ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex,
- msgtype, msgval);
- *retmsg = "";
- return 0;
-}
-#endif
-
-#ifndef HAVE_XF86MODEBANDWIDTH
-/** Calculates the memory bandwidth (in MiB/sec) of a mode. */
-_X_HIDDEN unsigned int
-xf86ModeBandwidth(DisplayModePtr mode, int depth)
-{
- float a_active, a_total, active_percent, pixels_per_second;
- int bytes_per_pixel = (depth + 7) / 8;
-
- if (!mode->HTotal || !mode->VTotal || !mode->Clock)
- return 0;
-
- a_active = mode->HDisplay * mode->VDisplay;
- a_total = mode->HTotal * mode->VTotal;
- active_percent = a_active / a_total;
- pixels_per_second = active_percent * mode->Clock * 1000.0;
-
- return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024));
-}
-#endif
-
-/* Used to disallow modes that are not supported by the hardware */
-ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode,
- Bool verbose, int flag)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-
- /*
- * RN50 has effective maximum mode bandwidth of about 300MiB/s.
- * XXX should really do this for all chips by properly computing
- * memory bandwidth and an overhead factor.
- */
- if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
- if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
- return MODE_BANDWIDTH;
- }
-
- /* There are problems with double scan mode at high clocks
- * They're likely related PLL and display buffer settings.
- * Disable these modes for now.
- */
- if (mode->Flags & V_DBLSCAN) {
- if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768))
- return MODE_CLOCK_RANGE;
- }
- return MODE_OK;
-}
-
-/* Adjust viewport into virtual desktop such that (0,0) in viewport
- * space is (x,y) in virtual space.
- */
-void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0;
-#ifdef XF86DRI
- RADEONSAREAPrivPtr pSAREAPriv;
- XF86DRISAREAPtr pSAREA;
-#endif
-
-#if 0 /* Verbose */
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone);
-#endif
-
- if (info->showCache && y) {
- int lastline = info->FbMapSize /
- ((pScrn->displayWidth * pScrn->bitsPerPixel) / 8);
-
- lastline -= pScrn->currentMode->VDisplay;
- y += (pScrn->virtualY - 1) * (y / 3 + 1);
- if (y > lastline) y = lastline;
- }
-
- Base = pScrn->fbOffset;
-
- /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
- drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes
- flickering when scrolling vertically in a virtual screen, possibly because crtc will
- pick up the new offset value at the end of each scanline, but the new offset_cntl value
- only after a vsync. We'd probably need to wait (in drm) for vsync and only then update
- OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */
- if (crtc2) {
- reg = RADEON_CRTC2_OFFSET;
- regcntl = RADEON_CRTC2_OFFSET_CNTL;
- xytilereg = R300_CRTC2_TILE_X0_Y0;
- } else {
- reg = RADEON_CRTC_OFFSET;
- regcntl = RADEON_CRTC_OFFSET_CNTL;
- xytilereg = R300_CRTC_TILE_X0_Y0;
- }
- crtcoffsetcntl = INREG(regcntl) & ~0xf;
-#if 0
- /* try to get rid of flickering when scrolling at least for 2d */
-#ifdef XF86DRI
- if (!info->have3DWindows)
-#endif
- crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
-#endif
- if (info->tilingEnabled) {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- /* On r300/r400 when tiling is enabled crtc_offset is set to the address of
- * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc
- * Makes tiling MUCH easier.
- */
- crtcxytile = x | (y << 16);
- Base &= ~0x7ff;
- } else {
- int byteshift = info->CurrentLayout.bitsPerPixel >> 4;
- /* crtc uses 256(bytes)x8 "half-tile" start addresses? */
- int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11;
- Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
- crtcoffsetcntl = crtcoffsetcntl | (y % 16);
- }
- }
- else {
- int offset = y * info->CurrentLayout.displayWidth + x;
- switch (info->CurrentLayout.pixel_code) {
- case 15:
- case 16: offset *= 2; break;
- case 24: offset *= 3; break;
- case 32: offset *= 4; break;
- }
- Base += offset;
- }
-
- Base &= ~7; /* 3 lower bits are always 0 */
-
-#ifdef XF86DRI
- if (info->directRenderingInited) {
- /* note cannot use pScrn->pScreen since this is unitialized when called from
- RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */
- /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for
- *** pageflipping!
- ***/
- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
- /* can't get at sarea in a semi-sane way? */
- pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
-
- if (crtc2) {
- pSAREAPriv->crtc2_base = Base;
- }
- else {
- pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes)
- % info->CurrentLayout.displayWidth;
- pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes)
- / info->CurrentLayout.displayWidth;
- pSAREA->frame.width = pScrn->frameX1 - x + 1;
- pSAREA->frame.height = pScrn->frameY1 - y + 1;
- }
-
- if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
- }
- }
-#endif
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- OUTREG(xytilereg, crtcxytile);
- } else {
- OUTREG(regcntl, crtcoffsetcntl);
- }
-
- OUTREG(reg, Base);
-}
-
-void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
- xf86OutputPtr output = config->output[config->compat_output];
- xf86CrtcPtr crtc = output->crtc;
-
-#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
-#endif
-
- if (info->accelOn)
- RADEON_SYNC(info, pScrn);
-
- if (crtc && crtc->enabled) {
- if (crtc == pRADEONEnt->pCrtc[0])
- RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE);
- else
- RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE);
- crtc->x = output->initial_x + x;
- crtc->y = output->initial_y + y;
- }
-
-
-#ifdef XF86DRI
- if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
-#endif
-}
-
-/* Called when VT switching back to the X server. Reinitialize the
- * video mode.
- */
-Bool RADEONEnterVT(int scrnIndex, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONEnterVT\n");
-
- if ((INREG(RADEON_CONFIG_MEMSIZE)) == 0) { /* Softboot V_BIOS */
- xf86Int10InfoPtr pInt;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n");
- pInt = xf86InitInt10 (info->pEnt->index);
- if (pInt) {
- pInt->num = 0xe6;
- xf86ExecX86int10 (pInt);
- xf86FreeInt10 (pInt);
- }
- }
-
- /* Makes sure the engine is idle before doing anything */
- RADEONWaitForIdleMMIO(pScrn);
-
- if (info->IsMobility && !IS_AVIVO_VARIANT) {
- if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
- RADEONSetDynamicClock(pScrn, 1);
- } else {
- RADEONSetDynamicClock(pScrn, 0);
- }
- }
-
- if (IS_R300_VARIANT || IS_RV100_VARIANT)
- RADEONForceSomeClocks(pScrn);
-
- pScrn->vtSema = TRUE;
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
- /* Mark that we'll need to re-set the mode for sure */
- memset(&crtc->mode, 0, sizeof(crtc->mode));
- if (!crtc->desiredMode.CrtcHDisplay) {
- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode);
- crtc->desiredRotation = RR_Rotate_0;
- crtc->desiredX = 0;
- crtc->desiredY = 0;
- }
-
- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation,
- crtc->desiredX, crtc->desiredY))
- return FALSE;
-
- }
-
- RADEONRestoreSurfaces(pScrn, info->ModeReg);
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
- {
- /* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize);
- }
-
- /* get the DRI back into shape after resume */
- RADEONDRISetVBlankInterrupt (pScrn, TRUE);
- RADEONDRIResume(pScrn->pScreen);
- RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
-
- }
-#endif
- /* this will get XVideo going again, but only if XVideo was initialised
- during server startup (hence the info->adaptor if). */
- if (info->adaptor)
- RADEONResetVideo(pScrn);
-
- if (info->accelOn)
- RADEONEngineRestore(pScrn);
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled) {
- RADEONCP_START(pScrn, info);
- DRIUnlock(pScrn->pScreen);
- }
-#endif
-
- // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
-
- return TRUE;
-}
-
-/* Called when VT switching away from the X server. Restore the
- * original text mode.
- */
-void RADEONLeaveVT(int scrnIndex, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONLeaveVT\n");
-#ifdef XF86DRI
- if (RADEONPTR(pScrn)->directRenderingInited) {
-
- RADEONDRISetVBlankInterrupt (pScrn, FALSE);
- DRILock(pScrn->pScreen, 0);
- RADEONCP_STOP(pScrn, info);
-
- if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
- {
- /* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
- }
-
- /* Make sure 3D clients will re-upload textures to video RAM */
- if (info->textureSize) {
- RADEONSAREAPrivPtr pSAREAPriv =
- (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen);
- drmTextureRegionPtr list = pSAREAPriv->texList[0];
- int age = ++pSAREAPriv->texAge[0], i = 0;
-
- do {
- list[i].age = age;
- i = list[i].next;
- } while (i != 0);
- }
- }
-#endif
-
- RADEONRestore(pScrn);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Ok, leaving now...\n");
-}
-
-/* Called at the end of each server generation. Restore the original
- * text mode, unmap video memory, and unwrap and call the saved
- * CloseScreen function.
- */
-static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONCloseScreen\n");
-
- /* Mark acceleration as stopped or we might try to access the engine at
- * wrong times, especially if we had DRI, after DRI has been stopped
- */
- info->accelOn = FALSE;
-
-#ifdef XF86DRI
-#ifdef DAMAGE
- if (info->pDamage) {
- PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
-
- DamageUnregister(&pPix->drawable, info->pDamage);
- DamageDestroy(info->pDamage);
- info->pDamage = NULL;
- }
-#endif
-
- RADEONDRIStop(pScreen);
-#endif
-
-#ifdef USE_XAA
- if(!info->useEXA && info->RenderTex) {
- xf86FreeOffscreenLinear(info->RenderTex);
- info->RenderTex = NULL;
- }
-#endif /* USE_XAA */
-
- if (pScrn->vtSema) {
- RADEONRestore(pScrn);
- }
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Disposing accel...\n");
-#ifdef USE_EXA
- if (info->exa) {
- exaDriverFini(pScreen);
- xfree(info->exa);
- info->exa = NULL;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- if (info->accel)
- XAADestroyInfoRec(info->accel);
- info->accel = NULL;
-
- if (info->scratch_save)
- xfree(info->scratch_save);
- info->scratch_save = NULL;
- }
-#endif /* USE_XAA */
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Disposing cursor info\n");
- if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
- info->cursor = NULL;
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Disposing DGA\n");
- if (info->DGAModes) xfree(info->DGAModes);
- info->DGAModes = NULL;
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Unmapping memory\n");
- RADEONUnmapMem(pScrn);
-
- pScrn->vtSema = FALSE;
-
- xf86ClearPrimInitDone(info->pEnt->index);
-
- pScreen->BlockHandler = info->BlockHandler;
- pScreen->CloseScreen = info->CloseScreen;
- return (*pScreen->CloseScreen)(scrnIndex, pScreen);
-}
-
-void RADEONFreeScreen(int scrnIndex, int flags)
-{
- ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "RADEONFreeScreen\n");
-
- /* when server quits at PreInit, we don't need do this anymore*/
- if (!info) return;
-
-#ifdef WITH_VGAHW
- if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
- vgaHWFreeHWRec(pScrn);
-#endif
- RADEONFreeRec(pScrn);
-}
-
-static void RADEONForceSomeClocks(ScrnInfoPtr pScrn)
-{
- /* It appears from r300 and rv100 may need some clocks forced-on */
- CARD32 tmp;
-
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
-}
-
-static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp;
- switch(mode) {
- case 0: /* Turn everything OFF (ForceON to everything)*/
- if ( !pRADEONEnt->HasCRTC2 ) {
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
- RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
- RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
- RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
- RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
- RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
- RADEON_SCLK_FORCE_RB);
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
- } else if (info->ChipFamily == CHIP_FAMILY_RV350) {
- /* for RV350/M10, no delays are required. */
- tmp = INPLL(pScrn, R300_SCLK_CNTL2);
- tmp |= (R300_SCLK_FORCE_TCL |
- R300_SCLK_FORCE_GA |
- R300_SCLK_FORCE_CBA);
- OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
-
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
- RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
- RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
- R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
- RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
- R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
- R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
- R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
- tmp |= RADEON_SCLK_MORE_FORCEON;
- OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
- tmp |= (RADEON_FORCEON_MCLKA |
- RADEON_FORCEON_MCLKB |
- RADEON_FORCEON_YCLKA |
- RADEON_FORCEON_YCLKB |
- RADEON_FORCEON_MC);
- OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
- tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
- RADEON_PIXCLK_DAC_ALWAYS_ONb |
- R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
- RADEON_PIX2CLK_DAC_ALWAYS_ONb |
- RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
- R300_DVOCLK_ALWAYS_ONb |
- RADEON_PIXCLK_BLEND_ALWAYS_ONb |
- RADEON_PIXCLK_GV_ALWAYS_ONb |
- R300_PIXCLK_DVO_ALWAYS_ONb |
- RADEON_PIXCLK_LVDS_ALWAYS_ONb |
- RADEON_PIXCLK_TMDS_ALWAYS_ONb |
- R300_PIXCLK_TRANS_ALWAYS_ONb |
- R300_PIXCLK_TVO_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb |
- R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
- } else {
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
- tmp |= RADEON_SCLK_FORCE_SE;
-
- if ( !pRADEONEnt->HasCRTC2 ) {
- tmp |= ( RADEON_SCLK_FORCE_RB |
- RADEON_SCLK_FORCE_TDM |
- RADEON_SCLK_FORCE_TAM |
- RADEON_SCLK_FORCE_PB |
- RADEON_SCLK_FORCE_RE |
- RADEON_SCLK_FORCE_VIP |
- RADEON_SCLK_FORCE_IDCT |
- RADEON_SCLK_FORCE_TOP |
- RADEON_SCLK_FORCE_DISP1 |
- RADEON_SCLK_FORCE_DISP2 |
- RADEON_SCLK_FORCE_HDP );
- } else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- (info->ChipFamily == CHIP_FAMILY_R350)) {
- tmp |= ( RADEON_SCLK_FORCE_HDP |
- RADEON_SCLK_FORCE_DISP1 |
- RADEON_SCLK_FORCE_DISP2 |
- RADEON_SCLK_FORCE_TOP |
- RADEON_SCLK_FORCE_IDCT |
- RADEON_SCLK_FORCE_VIP);
- }
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
-
- usleep(16000);
-
- if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- (info->ChipFamily == CHIP_FAMILY_R350)) {
- tmp = INPLL(pScrn, R300_SCLK_CNTL2);
- tmp |= ( R300_SCLK_FORCE_TCL |
- R300_SCLK_FORCE_GA |
- R300_SCLK_FORCE_CBA);
- OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
- usleep(16000);
- }
-
- if (info->IsIGP) {
- tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
- tmp &= ~(RADEON_FORCEON_MCLKA |
- RADEON_FORCEON_YCLKA);
- OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
- usleep(16000);
- }
-
- if ((info->ChipFamily == CHIP_FAMILY_RV200) ||
- (info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280)) {
- tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
- tmp |= RADEON_SCLK_MORE_FORCEON;
- OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
- usleep(16000);
- }
-
- tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
- RADEON_PIX2CLK_DAC_ALWAYS_ONb |
- RADEON_PIXCLK_BLEND_ALWAYS_ONb |
- RADEON_PIXCLK_GV_ALWAYS_ONb |
- RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
- RADEON_PIXCLK_LVDS_ALWAYS_ONb |
- RADEON_PIXCLK_TMDS_ALWAYS_ONb);
-
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
- usleep(16000);
-
- tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
- tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
- RADEON_PIXCLK_DAC_ALWAYS_ONb);
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Disabled\n");
- break;
- case 1:
- if (!pRADEONEnt->HasCRTC2) {
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) >
- RADEON_CFG_ATI_REV_A13) {
- tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
- }
- tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
- RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
- RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
- RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
- RADEON_SCLK_FORCE_TDM);
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
- } else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- (info->ChipFamily == CHIP_FAMILY_R350) ||
- (info->ChipFamily == CHIP_FAMILY_RV350)) {
- if (info->ChipFamily == CHIP_FAMILY_RV350) {
- tmp = INPLL(pScrn, R300_SCLK_CNTL2);
- tmp &= ~(R300_SCLK_FORCE_TCL |
- R300_SCLK_FORCE_GA |
- R300_SCLK_FORCE_CBA);
- tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
- R300_SCLK_GA_MAX_DYN_STOP_LAT |
- R300_SCLK_CBA_MAX_DYN_STOP_LAT);
- OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
-
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
- RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
- RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
- R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
- RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
- R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
- R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
- R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
- tmp |= RADEON_DYN_STOP_LAT_MASK;
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
- tmp &= ~RADEON_SCLK_MORE_FORCEON;
- tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
- OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
- tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
- RADEON_PIXCLK_DAC_ALWAYS_ONb);
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
- RADEON_PIX2CLK_DAC_ALWAYS_ONb |
- RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
- R300_DVOCLK_ALWAYS_ONb |
- RADEON_PIXCLK_BLEND_ALWAYS_ONb |
- RADEON_PIXCLK_GV_ALWAYS_ONb |
- R300_PIXCLK_DVO_ALWAYS_ONb |
- RADEON_PIXCLK_LVDS_ALWAYS_ONb |
- RADEON_PIXCLK_TMDS_ALWAYS_ONb |
- R300_PIXCLK_TRANS_ALWAYS_ONb |
- R300_PIXCLK_TVO_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb);
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
-
- tmp = INPLL(pScrn, RADEON_MCLK_MISC);
- tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
- RADEON_IO_MCLK_DYN_ENABLE);
- OUTPLL(pScrn, RADEON_MCLK_MISC, tmp);
-
- tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
- tmp |= (RADEON_FORCEON_MCLKA |
- RADEON_FORCEON_MCLKB);
-
- tmp &= ~(RADEON_FORCEON_YCLKA |
- RADEON_FORCEON_YCLKB |
- RADEON_FORCEON_MC);
-
- /* Some releases of vbios have set DISABLE_MC_MCLKA
- and DISABLE_MC_MCLKB bits in the vbios table. Setting these
- bits will cause H/W hang when reading video memory with dynamic clocking
- enabled. */
- if ((tmp & R300_DISABLE_MC_MCLKA) &&
- (tmp & R300_DISABLE_MC_MCLKB)) {
- /* If both bits are set, then check the active channels */
- tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
- if (info->RamWidth == 64) {
- if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
- tmp &= ~R300_DISABLE_MC_MCLKB;
- else
- tmp &= ~R300_DISABLE_MC_MCLKA;
- } else {
- tmp &= ~(R300_DISABLE_MC_MCLKA |
- R300_DISABLE_MC_MCLKB);
- }
- }
-
- OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
- } else {
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- tmp &= ~(R300_SCLK_FORCE_VAP);
- tmp |= RADEON_SCLK_FORCE_CP;
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
- usleep(15000);
-
- tmp = INPLL(pScrn, R300_SCLK_CNTL2);
- tmp &= ~(R300_SCLK_FORCE_TCL |
- R300_SCLK_FORCE_GA |
- R300_SCLK_FORCE_CBA);
- OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
- }
- } else {
- tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL);
-
- tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
- RADEON_DISP_DYN_STOP_LAT_MASK |
- RADEON_DYN_STOP_MODE_MASK);
-
- tmp |= (RADEON_ENGIN_DYNCLK_MODE |
- (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
- OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp);
- usleep(15000);
-
- tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
- tmp |= RADEON_SCLK_DYN_START_CNTL;
- OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
- usleep(15000);
-
- /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
- to lockup randomly, leave them as set by BIOS.
- */
- tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
- /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
- tmp &= ~RADEON_SCLK_FORCEON_MASK;
-
- /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
- if (((info->ChipFamily == CHIP_FAMILY_RV250) &&
- ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
- RADEON_CFG_ATI_REV_A13)) ||
- ((info->ChipFamily == CHIP_FAMILY_RV100) &&
- ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
- RADEON_CFG_ATI_REV_A13))){
- tmp |= RADEON_SCLK_FORCE_CP;
- tmp |= RADEON_SCLK_FORCE_VIP;
- }
-
- OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
-
- if ((info->ChipFamily == CHIP_FAMILY_RV200) ||
- (info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280)) {
- tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
- tmp &= ~RADEON_SCLK_MORE_FORCEON;
-
- /* RV200::A11 A12 RV250::A11 A12 */
- if (((info->ChipFamily == CHIP_FAMILY_RV200) ||
- (info->ChipFamily == CHIP_FAMILY_RV250)) &&
- ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
- RADEON_CFG_ATI_REV_A13)) {
- tmp |= RADEON_SCLK_MORE_FORCEON;
- }
- OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
- usleep(15000);
- }
-
- /* RV200::A11 A12, RV250::A11 A12 */
- if (((info->ChipFamily == CHIP_FAMILY_RV200) ||
- (info->ChipFamily == CHIP_FAMILY_RV250)) &&
- ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
- RADEON_CFG_ATI_REV_A13)) {
- tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL);
- tmp |= RADEON_TCL_BYPASS_DISABLE;
- OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp);
- }
- usleep(15000);
-
- /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/
- tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
- RADEON_PIX2CLK_DAC_ALWAYS_ONb |
- RADEON_PIXCLK_BLEND_ALWAYS_ONb |
- RADEON_PIXCLK_GV_ALWAYS_ONb |
- RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
- RADEON_PIXCLK_LVDS_ALWAYS_ONb |
- RADEON_PIXCLK_TMDS_ALWAYS_ONb);
-
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
- usleep(15000);
-
- tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
- tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
- RADEON_PIXCLK_DAC_ALWAYS_ONb);
-
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
- usleep(15000);
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Enabled\n");
- break;
- default:
- break;
- }
-}
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
deleted file mode 100644
index 4da4841..0000000
--- a/src/radeon_exa.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * Copyright 2005 Eric Anholt
- * Copyright 2005 Benjamin Herrenschmidt
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Authors:
- * Eric Anholt <anholt at FreeBSD.org>
- * Zack Rusin <zrusin at trolltech.com>
- * Benjamin Herrenschmidt <benh at kernel.crashing.org>
- *
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#ifdef XF86DRI
-#include "radeon_dri.h"
-#endif
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#ifdef XF86DRI
-#include "radeon_sarea.h"
-#endif
-
-#include "xf86.h"
-
-
-/***********************************************************************/
-#define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86Screens[pScr->myNum]; \
- RADEONInfoPtr info = RADEONPTR(pScrn)
-
-#define RADEON_TRACE_FALL 0
-#define RADEON_TRACE_DRAW 0
-
-#if RADEON_TRACE_FALL
-#define RADEON_FALLBACK(x) \
-do { \
- ErrorF("%s: ", __FUNCTION__); \
- ErrorF x; \
- return FALSE; \
-} while (0)
-#else
-#define RADEON_FALLBACK(x) return FALSE
-#endif
-
-#if RADEON_TRACE_DRAW
-#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
-#else
-#define TRACE
-#endif
-
-static struct {
- int rop;
- int pattern;
-} RADEON_ROP[] = {
- { RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */
- { RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */
- { RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */
- { RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */
- { RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */
- { RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */
- { RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */
- { RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */
- { RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */
- { RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */
- { RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */
- { RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */
- { RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */
- { RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */
- { RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */
- { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */
-};
-
-/* Compute log base 2 of val. */
-static __inline__ int
-RADEONLog2(int val)
-{
- int bits;
-
- for (bits = 0; val != 0; val >>= 1, ++bits)
- ;
- return bits - 1;
-}
-
-static __inline__ CARD32 F_TO_DW(float val)
-{
- union {
- float f;
- CARD32 l;
- } tmp;
- tmp.f = val;
- return tmp.l;
-}
-
-/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
- * require src and dest datatypes to be equal.
- */
-Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type)
-{
- switch (bpp) {
- case 8:
- *type = ATI_DATATYPE_CI8;
- return TRUE;
- case 16:
- *type = ATI_DATATYPE_RGB565;
- return TRUE;
- case 24:
- *type = ATI_DATATYPE_CI8;
- return TRUE;
- case 32:
- *type = ATI_DATATYPE_ARGB8888;
- return TRUE;
- default:
- RADEON_FALLBACK(("Unsupported bpp: %d\n", bpp));
- return FALSE;
- }
-}
-
-static Bool RADEONPixmapIsColortiled(PixmapPtr pPix)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
-
- /* This doesn't account for the back buffer, which we may want to wrap in
- * a pixmap at some point for the purposes of DRI buffer moves.
- */
- if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0)
- return TRUE;
- else
- return FALSE;
-}
-
-static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset,
- unsigned int offset, unsigned int pitch)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
-
- if (pitch > 16320 || pitch % info->exa->pixmapPitchAlign != 0)
- RADEON_FALLBACK(("Bad pitch 0x%08x\n", pitch));
-
- if (offset % info->exa->pixmapOffsetAlign != 0)
- RADEON_FALLBACK(("Bad offset 0x%08x\n", offset));
-
- pitch = pitch >> 6;
- *pitch_offset = (pitch << 22) | (offset >> 10);
-
- /* If it's the front buffer, we've got to note that it's tiled? */
- if (RADEONPixmapIsColortiled(pPix))
- *pitch_offset |= RADEON_DST_TILE_MACRO;
- return TRUE;
-}
-
-Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- CARD32 pitch, offset;
- int bpp;
-
- bpp = pPix->drawable.bitsPerPixel;
- if (bpp == 24)
- bpp = 8;
-
- offset = exaGetPixmapOffset(pPix) + info->fbLocation;
- pitch = exaGetPixmapPitch(pPix);
-
- return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch);
-}
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-
-static unsigned long swapper_surfaces[3];
-
-static Bool RADEONPrepareAccess(PixmapPtr pPix, int index)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 offset = exaGetPixmapOffset(pPix);
- int bpp, soff;
- CARD32 size, flags;
-
- /* Front buffer is always set with proper swappers */
- if (offset == 0)
- return TRUE;
-
- /* If same bpp as front buffer, just do nothing as the main
- * swappers will apply
- */
- bpp = pPix->drawable.bitsPerPixel;
- if (bpp == pScrn->bitsPerPixel)
- return TRUE;
-
- /* We need to setup a separate swapper, let's request a
- * surface. We need to align the size first
- */
- size = exaGetPixmapSize(pPix);
- size = (size + RADEON_BUFFER_ALIGN) & ~(RADEON_BUFFER_ALIGN);
-
- /* Set surface to tiling disabled with appropriate swapper */
- switch (bpp) {
- case 16:
- flags = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
- break;
- case 32:
- flags = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
- break;
- default:
- flags = 0;
- }
-#if defined(XF86DRI)
- if (info->directRenderingEnabled && info->allowColorTiling) {
- drmRadeonSurfaceAlloc drmsurfalloc;
- int rc;
-
- drmsurfalloc.address = offset;
- drmsurfalloc.size = size;
- drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */
-
- rc = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
- &drmsurfalloc, sizeof(drmsurfalloc));
- if (rc < 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "drm: could not allocate surface for access"
- " swapper, err: %d!\n", rc);
- return FALSE;
- }
- swapper_surfaces[index] = offset;
-
- return TRUE;
- }
-#endif
- soff = (index + 1) * 0x10;
- OUTREG(RADEON_SURFACE0_INFO + soff, flags);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset);
- OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1);
- swapper_surfaces[index] = offset;
- return TRUE;
-}
-
-static void RADEONFinishAccess(PixmapPtr pPix, int index)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 offset = exaGetPixmapOffset(pPix);
- int soff;
-
- /* Front buffer is always set with proper swappers */
- if (offset == 0)
- return;
-
- if (swapper_surfaces[index] == 0)
- return;
-#if defined(XF86DRI)
- if (info->directRenderingEnabled && info->allowColorTiling) {
- drmRadeonSurfaceFree drmsurffree;
-
- drmsurffree.address = offset;
- drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
- &drmsurffree, sizeof(drmsurffree));
- swapper_surfaces[index] = 0;
- return;
- }
-#endif
- soff = (index + 1) * 0x10;
- OUTREG(RADEON_SURFACE0_INFO + soff, 0);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0);
- OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0);
- swapper_surfaces[index] = 0;
-}
-
-#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
-
-#define RADEON_SWITCH_TO_2D() \
-do { \
- CARD32 wait_until = 0; \
- BEGIN_ACCEL(1); \
- switch (info->engineMode) { \
- case EXA_ENGINEMODE_UNKNOWN: \
- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \
- case EXA_ENGINEMODE_3D: \
- wait_until |= RADEON_WAIT_3D_IDLECLEAN; \
- case EXA_ENGINEMODE_2D: \
- break; \
- } \
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \
- FINISH_ACCEL(); \
- info->engineMode = EXA_ENGINEMODE_2D; \
-} while (0);
-
-#define RADEON_SWITCH_TO_3D() \
-do { \
- CARD32 wait_until = 0; \
- BEGIN_ACCEL(1); \
- switch (info->engineMode) { \
- case EXA_ENGINEMODE_UNKNOWN: \
- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \
- case EXA_ENGINEMODE_2D: \
- wait_until |= RADEON_WAIT_2D_IDLECLEAN; \
- case EXA_ENGINEMODE_3D: \
- break; \
- } \
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \
- FINISH_ACCEL(); \
- info->engineMode = EXA_ENGINEMODE_3D; \
-} while (0);
-
-#define ENTER_DRAW(x) TRACE
-#define LEAVE_DRAW(x) TRACE
-/***********************************************************************/
-
-#define ACCEL_MMIO
-#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
-#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n))
-#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
-#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
-#define FINISH_ACCEL()
-
-#ifdef RENDER
-#include "radeon_exa_render.c"
-#endif
-#include "radeon_exa_funcs.c"
-
-#undef ACCEL_MMIO
-#undef ACCEL_PREAMBLE
-#undef BEGIN_ACCEL
-#undef OUT_ACCEL_REG
-#undef FINISH_ACCEL
-
-#ifdef XF86DRI
-
-#define ACCEL_CP
-#define ACCEL_PREAMBLE() \
- RING_LOCALS; \
- RADEONCP_REFRESH(pScrn, info)
-#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
-#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
-#define FINISH_ACCEL() ADVANCE_RING()
-
-#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
-
-#ifdef RENDER
-#include "radeon_exa_render.c"
-#endif
-#include "radeon_exa_funcs.c"
-
-#endif /* XF86DRI */
-
-/*
- * Once screen->off_screen_base is set, this function
- * allocates the remaining memory appropriately
- */
-Bool RADEONSetupMemEXA (ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int cpp = info->CurrentLayout.pixel_bytes;
- int screen_size;
- int byteStride = pScrn->displayWidth * cpp;
-
- if (info->exa != NULL) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
- return FALSE;
- }
- info->exa = exaDriverAlloc();
- if (info->exa == NULL)
- return FALSE;
-
- /* Need to adjust screen size for 16 line tiles, and then make it align to.
- * the buffer alignment requirement.
- */
- if (info->allowColorTiling)
- screen_size = RADEON_ALIGN(pScrn->virtualY, 16) * byteStride;
- else
- screen_size = pScrn->virtualY * byteStride;
-
- info->exa->memoryBase = info->FB + pScrn->fbOffset;
- info->exa->memorySize = info->FbMapSize - info->FbSecureSize;
- info->exa->offScreenBase = screen_size;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocating from a screen of %ld kb\n",
- info->exa->memorySize / 1024);
-
-
- /* Reserve static area for hardware cursor */
- if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
- int cursor_size = 64 * 4 * 64;
- int c;
-
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- radeon_crtc->cursor_offset = info->exa->offScreenBase;
- info->exa->offScreenBase += cursor_size;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
- (cursor_size * xf86_config->num_crtc) / 1024,
- c,
- (unsigned int)radeon_crtc->cursor_offset);
- }
-
-
- }
-
-#if defined(XF86DRI)
- if (info->directRenderingEnabled) {
- int depthCpp = (info->depthBits - 8) / 4, l, next, depth_size;
-
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for front buffer at offset 0x%08x\n",
- screen_size / 1024, info->frontOffset);
- RADEONDRIAllocatePCIGARTTable(pScreen);
-
- if (info->cardType==CARD_PCIE)
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for PCI GART at offset 0x%08x\n",
- info->pciGartSize / 1024,
- (int)info->pciGartOffset);
-
- /* Reserve a static area for the back buffer the same size as the
- * visible screen. XXX: This would be better initialized in ati_dri.c
- * when GLX is set up, but the offscreen memory manager's allocations
- * don't last through VT switches, while the kernel's understanding of
- * offscreen locations does.
- */
- info->backPitch = pScrn->displayWidth;
- next = RADEON_ALIGN(info->exa->offScreenBase, RADEON_BUFFER_ALIGN);
- if (!info->noBackBuffer &&
- next + screen_size <= info->exa->memorySize)
- {
- info->backOffset = next;
- info->exa->offScreenBase = next + screen_size;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for back buffer at offset 0x%08x\n",
- screen_size / 1024, info->backOffset);
- }
-
- /* Reserve the static depth buffer, and adjust pitch and height to
- * handle tiling.
- */
- info->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
- depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->depthPitch * depthCpp;
- next = RADEON_ALIGN(info->exa->offScreenBase, RADEON_BUFFER_ALIGN);
- if (next + depth_size <= info->exa->memorySize)
- {
- info->depthOffset = next;
- info->exa->offScreenBase = next + depth_size;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for depth buffer at offset 0x%08x\n",
- depth_size / 1024, info->depthOffset);
- }
-
- info->textureSize *= (info->exa->memorySize -
- info->exa->offScreenBase) / 100;
-
- l = RADEONLog2(info->textureSize / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY)
- l = RADEON_LOG_TEX_GRANULARITY;
- info->textureSize = (info->textureSize >> l) << l;
- if (info->textureSize >= 512 * 1024) {
- info->textureOffset = info->exa->offScreenBase;
- info->exa->offScreenBase += info->textureSize;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for textures at offset 0x%08x\n",
- info->textureSize / 1024, info->textureOffset);
- } else {
- /* Minimum texture size is for 2 256x256x32bpp textures */
- info->textureSize = 0;
- }
- } else
-#endif /* XF86DRI */
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for front buffer at offset 0x%08x\n",
- screen_size / 1024, 0);
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %ld kb for X Server offscreen at offset 0x%08lx\n",
- (info->exa->memorySize - info->exa->offScreenBase) /
- 1024, info->exa->offScreenBase);
-
- return TRUE;
-}
-
-#ifdef XF86DRI
-
-#ifndef ExaOffscreenMarkUsed
-extern void ExaOffscreenMarkUsed(PixmapPtr);
-#endif
-
-unsigned long long
-RADEONTexOffsetStart(PixmapPtr pPix)
-{
- exaMoveInPixmap(pPix);
- ExaOffscreenMarkUsed(pPix);
-
- return RADEONPTR(xf86Screens[pPix->drawable.pScreen->myNum])->fbLocation +
- exaGetPixmapOffset(pPix);
-}
-#endif
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
deleted file mode 100644
index 10221c0..0000000
--- a/src/radeon_exa_funcs.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * Copyright 2005 Eric Anholt
- * Copyright 2005 Benjamin Herrenschmidt
- * Copyright 2006 Tungsten Graphics, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Authors:
- * Eric Anholt <anholt at FreeBSD.org>
- * Zack Rusin <zrusin at trolltech.com>
- * Benjamin Herrenschmidt <benh at kernel.crashing.org>
- * Michel Dänzer <michel at tungstengraphics.com>
- *
- */
-
-#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
-#error Cannot define both MMIO and CP acceleration!
-#endif
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#ifdef ACCEL_MMIO
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
-#else
-#ifdef ACCEL_CP
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-#else
-#error No accel type defined!
-#endif
-#endif
-
-#include <errno.h>
-#include <string.h>
-
-#include "radeon.h"
-
-#include "exa.h"
-
-static int
-FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
-{
- RINFO_FROM_SCREEN(pScreen);
-
- TRACE;
-
- return ++info->exaSyncMarker;
-}
-
-static void
-FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- TRACE;
-
- if (info->exaMarkerSynced != marker) {
- FUNC_NAME(RADEONWaitForIdle)(pScrn);
- info->exaMarkerSynced = marker;
- }
-
- RADEONPTR(pScrn)->engineMode = EXA_ENGINEMODE_UNKNOWN;
-}
-
-static Bool
-FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- CARD32 datatype, dst_pitch_offset;
- ACCEL_PREAMBLE();
-
- TRACE;
-
- if (pPix->drawable.bitsPerPixel == 24)
- RADEON_FALLBACK(("24bpp unsupported\n"));
- if (!RADEONGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype))
- RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n"));
- if (!RADEONGetPixmapOffsetPitch(pPix, &dst_pitch_offset))
- RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch failed\n"));
-
- RADEON_SWITCH_TO_2D();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL,
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_SOLID_COLOR |
- (datatype << 8) |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP[alu].pattern |
- RADEON_GMC_CLR_CMP_CNTL_DIS);
- OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, pm);
- OUT_ACCEL_REG(RADEON_DP_CNTL,
- (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-
-static void
-FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
-{
-
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- ACCEL_PREAMBLE();
-
- TRACE;
-
- BEGIN_ACCEL(2);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (y1 << 16) | x1);
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1));
- FINISH_ACCEL();
-}
-
-static void
-FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix)
-{
- TRACE;
-}
-
-void
-FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, CARD32 src_pitch_offset,
- CARD32 dst_pitch_offset, CARD32 datatype, int rop,
- Pixel planemask)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- RADEON_SWITCH_TO_2D();
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL,
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_NONE |
- (datatype << 8) |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP[rop].rop |
- RADEON_DP_SRC_SOURCE_MEMORY |
- RADEON_GMC_CLR_CMP_CNTL_DIS);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_CNTL,
- ((info->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
- (info->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0)));
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset);
- OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset);
- FINISH_ACCEL();
-}
-
-static Bool
-FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst,
- int xdir, int ydir,
- int rop,
- Pixel planemask)
-{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- CARD32 datatype, src_pitch_offset, dst_pitch_offset;
-
- TRACE;
-
- info->xdir = xdir;
- info->ydir = ydir;
-
- if (pDst->drawable.bitsPerPixel == 24)
- RADEON_FALLBACK(("24bpp unsupported"));
- if (!RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype))
- RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n"));
- if (!RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset))
- RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch source failed\n"));
- if (!RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_offset))
- RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch dest failed\n"));
-
- FUNC_NAME(RADEONDoPrepareCopy)(pScrn, src_pitch_offset, dst_pitch_offset,
- datatype, rop, planemask);
-
- return TRUE;
-}
-
-void
-FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
- int srcX, int srcY,
- int dstX, int dstY,
- int w, int h)
-{
-
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- ACCEL_PREAMBLE();
-
- TRACE;
-
- if (info->xdir < 0) {
- srcX += w - 1;
- dstX += w - 1;
- }
- if (info->ydir < 0) {
- srcY += h - 1;
- dstY += h - 1;
- }
-
- BEGIN_ACCEL(3);
-
- OUT_ACCEL_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX);
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
-
- FINISH_ACCEL();
-}
-
-static void
-FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst)
-{
- TRACE;
-}
-
-static Bool
-FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h,
- char *src, int src_pitch)
-{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- CARD8 *dst = info->FB + exaGetPixmapOffset(pDst);
- unsigned int dst_pitch = exaGetPixmapPitch(pDst);
- unsigned int bpp = pDst->drawable.bitsPerPixel;
-#ifdef ACCEL_CP
- unsigned int hpass;
- CARD32 buf_pitch, dst_pitch_off;
-#endif
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg->surface_cntl &
- ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
- RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
-#endif
-
- TRACE;
-
- if (bpp < 8)
- return FALSE;
-
-#ifdef ACCEL_CP
- if (info->directRenderingEnabled &&
- RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) {
- CARD8 *buf;
- int cpp = bpp / 8;
- ACCEL_PREAMBLE();
-
- RADEON_SWITCH_TO_2D();
- while ((buf = RADEONHostDataBlit(pScrn,
- cpp, w, dst_pitch_off, &buf_pitch,
- x, &y, (unsigned int*)&h, &hpass)) != 0) {
- RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (CARD8 *)src,
- hpass, buf_pitch, src_pitch);
- src += hpass * src_pitch;
- }
-
- exaMarkSync(pDst->drawable.pScreen);
- return TRUE;
- }
-#endif
-
- /* Do we need that sync here ? probably not .... */
- exaWaitSync(pDst->drawable.pScreen);
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- switch(bpp) {
- case 15:
- case 16:
- swapper |= RADEON_NONSURF_AP0_SWP_16BPP
- | RADEON_NONSURF_AP1_SWP_16BPP;
- break;
- case 24:
- case 32:
- swapper |= RADEON_NONSURF_AP0_SWP_32BPP
- | RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- }
- OUTREG(RADEON_SURFACE_CNTL, swapper);
-#endif
- w *= bpp / 8;
- dst += (x * bpp / 8) + (y * dst_pitch);
-
- while (h--) {
- memcpy(dst, src, w);
- src += src_pitch;
- dst += dst_pitch;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-#endif
-
- return TRUE;
-}
-
-#ifdef ACCEL_CP
-/* Emit blit with arbitrary source and destination offsets and pitches */
-static void
-RADEONBlitChunk(ScrnInfoPtr pScrn, CARD32 datatype, CARD32 src_pitch_offset,
- CARD32 dst_pitch_offset, int srcX, int srcY, int dstX, int dstY,
- int w, int h)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- ACCEL_PREAMBLE();
-
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL,
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_NONE |
- (datatype << 8) |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP3_S |
- RADEON_DP_SRC_SOURCE_MEMORY |
- RADEON_GMC_CLR_CMP_CNTL_DIS |
- RADEON_GMC_WR_MSK_DIS);
- OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, src_pitch_offset);
- OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, dst_pitch_offset);
- OUT_ACCEL_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX);
- OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX);
- OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
- FINISH_ACCEL();
-}
-#endif
-
-static Bool
-FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
- char *dst, int dst_pitch)
-{
- RINFO_FROM_SCREEN(pSrc->drawable.pScreen);
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg->surface_cntl &
- ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
- RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
-#endif
- CARD8 *src = info->FB + exaGetPixmapOffset(pSrc);
- int src_pitch = exaGetPixmapPitch(pSrc);
- int bpp = pSrc->drawable.bitsPerPixel;
-#ifdef ACCEL_CP
- CARD32 datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0;
- drmBufPtr scratch;
-#endif
-
- TRACE;
-
-#ifdef ACCEL_CP
- /*
- * Try to accelerate download. Use an indirect buffer as scratch space,
- * blitting the bits to one half while copying them out of the other one and
- * then swapping the halves.
- */
- if (info->accelDFS && bpp != 24 && RADEONGetDatatypeBpp(bpp, &datatype) &&
- RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset) &&
- (scratch = RADEONCPGetBuffer(pScrn)))
- {
- int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8;
- int hpass = min(h, scratch->total/2 / scratch_pitch);
- CARD32 scratch_pitch_offset = scratch_pitch << 16
- | (info->gartLocation + info->bufStart
- + scratch->idx * scratch->total) >> 10;
- drmRadeonIndirect indirect;
- ACCEL_PREAMBLE();
-
- RADEON_SWITCH_TO_2D();
-
- /* Kick the first blit as early as possible */
- RADEONBlitChunk(pScrn, datatype, src_pitch_offset, scratch_pitch_offset,
- x, y, 0, 0, w, hpass);
- FLUSH_RING();
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- switch (bpp) {
- case 16:
- swap = RADEON_HOST_DATA_SWAP_16BIT;
- break;
- case 32:
- swap = RADEON_HOST_DATA_SWAP_32BIT;
- break;
- }
-#endif
-
- while (h) {
- int oldhpass = hpass, i = 0;
-
- src = (CARD8*)scratch->address + scratch_off;
-
- y += oldhpass;
- h -= oldhpass;
- hpass = min(h, scratch->total/2 / scratch_pitch);
-
- /* Prepare next blit if anything's left */
- if (hpass) {
- scratch_off = scratch->total/2 - scratch_off;
- RADEONBlitChunk(pScrn, datatype, src_pitch_offset, scratch_pitch_offset + (scratch_off >> 10),
- x, y, 0, 0, w, hpass);
- }
-
- /*
- * Wait for previous blit to complete.
- *
- * XXX: Doing here essentially the same things this ioctl does in
- * the DRM results in corruption with 'small' transfers, apparently
- * because the data doesn't actually land in system RAM before the
- * memcpy. I suspect the ioctl helps mostly due to its latency; what
- * we'd really need is a way to reliably wait for the host interface
- * to be done with pushing the data to the host.
- */
- while ((drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY)
- && (i++ < RADEON_TIMEOUT))
- ;
-
- /* Kick next blit */
- if (hpass)
- FLUSH_RING();
-
- /* Copy out data from previous blit */
- if (wpass == scratch_pitch && wpass == dst_pitch) {
- RADEONCopySwap((CARD8*)dst, src, wpass * oldhpass, swap);
- dst += dst_pitch * oldhpass;
- } else while (oldhpass--) {
- RADEONCopySwap((CARD8*)dst, src, wpass, swap);
- src += scratch_pitch;
- dst += dst_pitch;
- }
- }
-
- indirect.idx = scratch->idx;
- indirect.start = indirect.end = 0;
- indirect.discard = 1;
-
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
- &indirect, sizeof(drmRadeonIndirect));
-
- info->exaMarkerSynced = info->exaSyncMarker;
-
- return TRUE;
- }
-#endif
-
- /* Can't accelerate download */
- exaWaitSync(pSrc->drawable.pScreen);
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- switch(bpp) {
- case 15:
- case 16:
- swapper |= RADEON_NONSURF_AP0_SWP_16BPP
- | RADEON_NONSURF_AP1_SWP_16BPP;
- break;
- case 24:
- case 32:
- swapper |= RADEON_NONSURF_AP0_SWP_32BPP
- | RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- }
- OUTREG(RADEON_SURFACE_CNTL, swapper);
-#endif
-
- src += (x * bpp / 8) + (y * src_pitch);
- w *= bpp / 8;
-
- while (h--) {
- memcpy(dst, src, w);
- src += src_pitch;
- dst += dst_pitch;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-#endif
-
- return TRUE;
-}
-
-Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
-{
- RINFO_FROM_SCREEN(pScreen);
-
- if (info->exa == NULL) {
- xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
- return FALSE;
- }
-
- info->exa->exa_major = EXA_VERSION_MAJOR;
- info->exa->exa_minor = EXA_VERSION_MINOR;
-
- info->exa->PrepareSolid = FUNC_NAME(RADEONPrepareSolid);
- info->exa->Solid = FUNC_NAME(RADEONSolid);
- info->exa->DoneSolid = FUNC_NAME(RADEONDoneSolid);
-
- info->exa->PrepareCopy = FUNC_NAME(RADEONPrepareCopy);
- info->exa->Copy = FUNC_NAME(RADEONCopy);
- info->exa->DoneCopy = FUNC_NAME(RADEONDoneCopy);
-
- info->exa->MarkSync = FUNC_NAME(RADEONMarkSync);
- info->exa->WaitMarker = FUNC_NAME(RADEONSync);
- info->exa->UploadToScreen = FUNC_NAME(RADEONUploadToScreen);
- info->exa->DownloadFromScreen = FUNC_NAME(RADEONDownloadFromScreen);
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- info->exa->PrepareAccess = RADEONPrepareAccess;
- info->exa->FinishAccess = RADEONFinishAccess;
-#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
-
- info->exa->flags = EXA_OFFSCREEN_PIXMAPS;
- info->exa->pixmapOffsetAlign = RADEON_BUFFER_ALIGN + 1;
- info->exa->pixmapPitchAlign = 64;
-
-#ifdef RENDER
- if (info->RenderAccel) {
- if ((info->ChipFamily >= CHIP_FAMILY_R600) ||
- (info->ChipFamily == CHIP_FAMILY_RS400))
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "unsupported on XPRESS, R500 and newer cards.\n");
- else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS690)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "enabled for R300 type cards.\n");
- info->exa->CheckComposite = R300CheckComposite;
- info->exa->PrepareComposite =
- FUNC_NAME(R300PrepareComposite);
- info->exa->Composite = FUNC_NAME(RadeonComposite);
- info->exa->DoneComposite = RadeonDoneComposite;
- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_R200)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "enabled for R200 type cards.\n");
- info->exa->CheckComposite = R200CheckComposite;
- info->exa->PrepareComposite =
- FUNC_NAME(R200PrepareComposite);
- info->exa->Composite = FUNC_NAME(RadeonComposite);
- info->exa->DoneComposite = RadeonDoneComposite;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "enabled for R100 type cards.\n");
- info->exa->CheckComposite = R100CheckComposite;
- info->exa->PrepareComposite =
- FUNC_NAME(R100PrepareComposite);
- info->exa->Composite = FUNC_NAME(RadeonComposite);
- info->exa->DoneComposite = RadeonDoneComposite;
- }
- }
-#endif
-
-#if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3)
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n");
-
- info->exa->maxPitchBytes = 16320;
- info->exa->maxX = info->exa->Composite ? 2048 : 8192;
-#else
- info->exa->maxX = info->exa->Composite ? 2048 : 16320 / 4;
-#endif
- info->exa->maxY = info->exa->Composite ? 2048 : 8192;
-
- RADEONEngineInit(pScrn);
-
- if (!exaDriverInit(pScreen, info->exa)) {
- xfree(info->exa);
- return FALSE;
- }
- exaMarkSync(pScreen);
-
- return TRUE;
-}
-
-#undef FUNC_NAME
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
deleted file mode 100644
index 9bbccb5..0000000
--- a/src/radeon_exa_render.c
+++ /dev/null
@@ -1,1439 +0,0 @@
-/*
- * Copyright 2005 Eric Anholt
- * Copyright 2005 Benjamin Herrenschmidt
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Authors:
- * Eric Anholt <anholt at FreeBSD.org>
- * Zack Rusin <zrusin at trolltech.com>
- * Benjamin Herrenschmidt <benh at kernel.crashing.org>
- *
- */
-
-#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
-#error Cannot define both MMIO and CP acceleration!
-#endif
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#ifdef ACCEL_MMIO
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
-#else
-#ifdef ACCEL_CP
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-#else
-#error No accel type defined!
-#endif
-#endif
-
-#ifndef ACCEL_CP
-#define ONLY_ONCE
-#endif
-
-/* Only include the following (generic) bits once. */
-#ifdef ONLY_ONCE
-static Bool is_transform[2];
-static PictTransform *transform[2];
-
-struct blendinfo {
- Bool dst_alpha;
- Bool src_alpha;
- CARD32 blend_cntl;
-};
-
-static struct blendinfo RadeonBlendOp[] = {
- /* Clear */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO},
- /* Src */
- {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO},
- /* Dst */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE},
- /* Over */
- {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* OverReverse */
- {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE},
- /* In */
- {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO},
- /* InReverse */
- {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA},
- /* Out */
- {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO},
- /* OutReverse */
- {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* Atop */
- {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* AtopReverse */
- {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA},
- /* Xor */
- {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* Add */
- {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE},
-};
-
-struct formatinfo {
- int fmt;
- CARD32 card_fmt;
-};
-
-/* Note on texture formats:
- * TXFORMAT_Y8 expands to (Y,Y,Y,1). TXFORMAT_I8 expands to (I,I,I,I)
- */
-static struct formatinfo R100TexFormats[] = {
- {PICT_a8r8g8b8, RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP},
- {PICT_x8r8g8b8, RADEON_TXFORMAT_ARGB8888},
- {PICT_r5g6b5, RADEON_TXFORMAT_RGB565},
- {PICT_a1r5g5b5, RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP},
- {PICT_x1r5g5b5, RADEON_TXFORMAT_ARGB1555},
- {PICT_a8, RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP},
-};
-
-static struct formatinfo R200TexFormats[] = {
- {PICT_a8r8g8b8, R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP},
- {PICT_x8r8g8b8, R200_TXFORMAT_ARGB8888},
- {PICT_a8b8g8r8, R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP},
- {PICT_x8b8g8r8, R200_TXFORMAT_ABGR8888},
- {PICT_r5g6b5, R200_TXFORMAT_RGB565},
- {PICT_a1r5g5b5, R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP},
- {PICT_x1r5g5b5, R200_TXFORMAT_ARGB1555},
- {PICT_a8, R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP},
-};
-
-static struct formatinfo R300TexFormats[] = {
- {PICT_a8r8g8b8, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)},
- {PICT_x8r8g8b8, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)},
- {PICT_a8b8g8r8, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)},
- {PICT_x8b8g8r8, R300_EASY_TX_FORMAT(Z, Y, X, ONE, W8Z8Y8X8)},
- {PICT_r5g6b5, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)},
- {PICT_a1r5g5b5, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)},
- {PICT_x1r5g5b5, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W1Z5Y5X5)},
- {PICT_a8, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)},
-};
-
-/* Common Radeon setup code */
-
-static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
-{
- switch (pDstPicture->format) {
- case PICT_a8r8g8b8:
- case PICT_x8r8g8b8:
- *dst_format = RADEON_COLOR_FORMAT_ARGB8888;
- break;
- case PICT_r5g6b5:
- *dst_format = RADEON_COLOR_FORMAT_RGB565;
- break;
- case PICT_a1r5g5b5:
- case PICT_x1r5g5b5:
- *dst_format = RADEON_COLOR_FORMAT_ARGB1555;
- break;
- case PICT_a8:
- *dst_format = RADEON_COLOR_FORMAT_RGB8;
- break;
- default:
- RADEON_FALLBACK(("Unsupported dest format 0x%x\n",
- (int)pDstPicture->format));
- }
-
- return TRUE;
-}
-
-static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
-{
- switch (pDstPicture->format) {
- case PICT_a8r8g8b8:
- case PICT_x8r8g8b8:
- *dst_format = R300_COLORFORMAT_ARGB8888;
- break;
- case PICT_r5g6b5:
- *dst_format = R300_COLORFORMAT_RGB565;
- break;
- case PICT_a1r5g5b5:
- case PICT_x1r5g5b5:
- *dst_format = R300_COLORFORMAT_ARGB1555;
- break;
- case PICT_a8:
- *dst_format = R300_COLORFORMAT_I8;
- break;
- default:
- ErrorF("Unsupported dest format 0x%x\n",
- (int)pDstPicture->format);
- return FALSE;
- }
- return TRUE;
-}
-
-static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format)
-{
- CARD32 sblend, dblend;
-
- sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK;
- dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK;
-
- /* If there's no dst alpha channel, adjust the blend op so that we'll treat
- * it as always 1.
- */
- if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) {
- if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
- sblend = RADEON_SRC_BLEND_GL_ONE;
- else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA)
- sblend = RADEON_SRC_BLEND_GL_ZERO;
- }
-
- /* If the source alpha is being used, then we should only be in a case where
- * the source blend factor is 0, and the source blend value is the mask
- * channels multiplied by the source picture's alpha.
- */
- if (pMask && pMask->componentAlpha && RadeonBlendOp[op].src_alpha) {
- if (dblend == RADEON_DST_BLEND_GL_SRC_ALPHA) {
- dblend = RADEON_DST_BLEND_GL_SRC_COLOR;
- } else if (dblend == RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA) {
- dblend = RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR;
- }
- }
-
- return sblend | dblend;
-}
-
-union intfloat {
- float f;
- CARD32 i;
-};
-
-/* R100-specific code */
-
-static Bool R100CheckCompositeTexture(PicturePtr pPict, int unit)
-{
- int w = pPict->pDrawable->width;
- int h = pPict->pDrawable->height;
- int i;
-
- if ((w > 0x7ff) || (h > 0x7ff))
- RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
-
- for (i = 0; i < sizeof(R100TexFormats) / sizeof(R100TexFormats[0]); i++) {
- if (R100TexFormats[i].fmt == pPict->format)
- break;
- }
- if (i == sizeof(R100TexFormats) / sizeof(R100TexFormats[0]))
- RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
- (int)pPict->format));
-
- if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0))
- RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h));
-
- if (pPict->filter != PictFilterNearest &&
- pPict->filter != PictFilterBilinear)
- {
- RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter));
- }
-
- return TRUE;
-}
-
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
- int unit)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- CARD32 txfilter, txformat, txoffset, txpitch;
- int w = pPict->pDrawable->width;
- int h = pPict->pDrawable->height;
- int i;
- ACCEL_PREAMBLE();
-
- txpitch = exaGetPixmapPitch(pPix);
- txoffset = exaGetPixmapOffset(pPix) + info->fbLocation;
-
- if ((txoffset & 0x1f) != 0)
- RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset));
- if ((txpitch & 0x1f) != 0)
- RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-
- for (i = 0; i < sizeof(R100TexFormats) / sizeof(R100TexFormats[0]); i++)
- {
- if (R100TexFormats[i].fmt == pPict->format)
- break;
- }
- txformat = R100TexFormats[i].card_fmt;
- if (RADEONPixmapIsColortiled(pPix))
- txoffset |= RADEON_TXO_MACRO_TILE;
-
- if (pPict->repeat) {
- if ((h != 1) &&
- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
- RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
- w, (unsigned)txpitch));
-
- txformat |= RADEONLog2(w) << RADEON_TXFORMAT_WIDTH_SHIFT;
- txformat |= RADEONLog2(h) << RADEON_TXFORMAT_HEIGHT_SHIFT;
- } else
- txformat |= RADEON_TXFORMAT_NON_POWER2;
- txformat |= unit << 24; /* RADEON_TXFORMAT_ST_ROUTE_STQX */
-
- info->texW[unit] = 1;
- info->texH[unit] = 1;
-
- switch (pPict->filter) {
- case PictFilterNearest:
- txfilter = (RADEON_MAG_FILTER_NEAREST | RADEON_MIN_FILTER_NEAREST);
- break;
- case PictFilterBilinear:
- txfilter = (RADEON_MAG_FILTER_LINEAR | RADEON_MIN_FILTER_LINEAR);
- break;
- default:
- RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
- }
-
- BEGIN_ACCEL(5);
- if (unit == 0) {
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, txfilter);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, txoffset);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
- (pPix->drawable.width - 1) |
- ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, txpitch - 32);
- } else {
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_1, txfilter);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_1, txformat);
- OUT_ACCEL_REG(RADEON_PP_TXOFFSET_1, txoffset);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_1,
- (pPix->drawable.width - 1) |
- ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_1, txpitch - 32);
- }
- FINISH_ACCEL();
-
- if (pPict->transform != 0) {
- is_transform[unit] = TRUE;
- transform[unit] = pPict->transform;
- } else {
- is_transform[unit] = FALSE;
- }
-
- return TRUE;
-}
-
-#ifdef ONLY_ONCE
-static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
- PicturePtr pMaskPicture, PicturePtr pDstPicture)
-{
- CARD32 tmp1;
-
- /* Check for unsupported compositing operations. */
- if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
- RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-
- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) {
- /* Check if it's component alpha that relies on a source alpha and on
- * the source value. We can only get one of those into the single
- * source value that we get to blend with.
- */
- if (RadeonBlendOp[op].src_alpha &&
- (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) !=
- RADEON_SRC_BLEND_GL_ZERO)
- {
- RADEON_FALLBACK(("Component alpha not supported with source "
- "alpha and source value blending.\n"));
- }
- }
-
- if (pDstPicture->pDrawable->width >= (1 << 11) ||
- pDstPicture->pDrawable->height >= (1 << 11))
- {
- RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n",
- pDstPicture->pDrawable->width,
- pDstPicture->pDrawable->height));
- }
-
- if (!R100CheckCompositeTexture(pSrcPicture, 0))
- return FALSE;
- if (pMaskPicture != NULL && !R100CheckCompositeTexture(pMaskPicture, 1))
- return FALSE;
-
- if (!RADEONGetDestFormat(pDstPicture, &tmp1))
- return FALSE;
-
- return TRUE;
-}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R100PrepareComposite)(int op,
- PicturePtr pSrcPicture,
- PicturePtr pMaskPicture,
- PicturePtr pDstPicture,
- PixmapPtr pSrc,
- PixmapPtr pMask,
- PixmapPtr pDst)
-{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- CARD32 dst_format, dst_offset, dst_pitch, colorpitch;
- CARD32 pp_cntl, blendcntl, cblend, ablend;
- int pixel_shift;
- ACCEL_PREAMBLE();
-
- TRACE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- RADEONGetDestFormat(pDstPicture, &dst_format);
- pixel_shift = pDst->drawable.bitsPerPixel >> 4;
-
- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
- dst_pitch = exaGetPixmapPitch(pDst);
- colorpitch = dst_pitch >> pixel_shift;
- if (RADEONPixmapIsColortiled(pDst))
- colorpitch |= RADEON_COLOR_TILE_ENABLE;
-
- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
- dst_pitch = exaGetPixmapPitch(pDst);
- if ((dst_offset & 0x0f) != 0)
- RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset));
- if (((dst_pitch >> pixel_shift) & 0x7) != 0)
- RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
-
- if (!FUNC_NAME(R100TextureSetup)(pSrcPicture, pSrc, 0))
- return FALSE;
- pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
-
- if (pMask != NULL) {
- if (!FUNC_NAME(R100TextureSetup)(pMaskPicture, pMask, 1))
- return FALSE;
- pp_cntl |= RADEON_TEX_1_ENABLE;
- } else {
- is_transform[1] = FALSE;
- }
-
- RADEON_SWITCH_TO_3D();
-
- BEGIN_ACCEL(8);
- OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE);
- OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
- OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
-
- /* IN operator: Multiply src by mask components or mask alpha.
- * BLEND_CTL_ADD is A * B + C.
- * If a source is a8, we have to explicitly zero its color values.
- * If the destination is a8, we have to route the alpha to red, I think.
- * If we're doing component alpha where the source for blending is going to
- * be the source alpha (and there's no source value used), we have to zero
- * the source's color values.
- */
- cblend = RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX | RADEON_COLOR_ARG_C_ZERO;
- ablend = RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX | RADEON_ALPHA_ARG_C_ZERO;
-
- if (pDstPicture->format == PICT_a8 ||
- (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha))
- {
- cblend |= RADEON_COLOR_ARG_A_T0_ALPHA;
- } else if (pSrcPicture->format == PICT_a8)
- cblend |= RADEON_COLOR_ARG_A_ZERO;
- else
- cblend |= RADEON_COLOR_ARG_A_T0_COLOR;
- ablend |= RADEON_ALPHA_ARG_A_T0_ALPHA;
-
- if (pMask) {
- if (pMaskPicture->componentAlpha &&
- pDstPicture->format != PICT_a8)
- cblend |= RADEON_COLOR_ARG_B_T1_COLOR;
- else
- cblend |= RADEON_COLOR_ARG_B_T1_ALPHA;
- ablend |= RADEON_ALPHA_ARG_B_T1_ALPHA;
- } else {
- cblend |= RADEON_COLOR_ARG_B_ZERO | RADEON_COMP_ARG_B;
- ablend |= RADEON_ALPHA_ARG_B_ZERO | RADEON_COMP_ARG_B;
- }
-
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, cblend);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, ablend);
- OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
- RADEON_SE_VTX_FMT_ST0 |
- RADEON_SE_VTX_FMT_ST1);
- /* Op operator. */
- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
-
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blendcntl);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-#ifdef ONLY_ONCE
-
-static Bool R200CheckCompositeTexture(PicturePtr pPict, int unit)
-{
- int w = pPict->pDrawable->width;
- int h = pPict->pDrawable->height;
- int i;
-
- if ((w > 0x7ff) || (h > 0x7ff))
- RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
-
- for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++)
- {
- if (R200TexFormats[i].fmt == pPict->format)
- break;
- }
- if (i == sizeof(R200TexFormats) / sizeof(R200TexFormats[0]))
- RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
- (int)pPict->format));
-
- if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0))
- RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h));
-
- if (pPict->filter != PictFilterNearest &&
- pPict->filter != PictFilterBilinear)
- RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter));
-
- return TRUE;
-}
-
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
- int unit)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- CARD32 txfilter, txformat, txoffset, txpitch;
- int w = pPict->pDrawable->width;
- int h = pPict->pDrawable->height;
- int i;
- ACCEL_PREAMBLE();
-
- txpitch = exaGetPixmapPitch(pPix);
- txoffset = exaGetPixmapOffset(pPix) + info->fbLocation;
-
- if ((txoffset & 0x1f) != 0)
- RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset));
- if ((txpitch & 0x1f) != 0)
- RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-
- for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++)
- {
- if (R200TexFormats[i].fmt == pPict->format)
- break;
- }
- txformat = R200TexFormats[i].card_fmt;
- if (RADEONPixmapIsColortiled(pPix))
- txoffset |= R200_TXO_MACRO_TILE;
-
- if (pPict->repeat) {
- if ((h != 1) &&
- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
- RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
- w, (unsigned)txpitch));
-
- txformat |= RADEONLog2(w) << R200_TXFORMAT_WIDTH_SHIFT;
- txformat |= RADEONLog2(h) << R200_TXFORMAT_HEIGHT_SHIFT;
- } else
- txformat |= R200_TXFORMAT_NON_POWER2;
- txformat |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT;
-
- info->texW[unit] = w;
- info->texH[unit] = h;
-
- switch (pPict->filter) {
- case PictFilterNearest:
- txfilter = (R200_MAG_FILTER_NEAREST |
- R200_MIN_FILTER_NEAREST);
- break;
- case PictFilterBilinear:
- txfilter = (R200_MAG_FILTER_LINEAR |
- R200_MIN_FILTER_LINEAR);
- break;
- default:
- RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
- }
-
- BEGIN_ACCEL(6);
- if (unit == 0) {
- OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_0, (pPix->drawable.width - 1) |
- ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXPITCH_0, txpitch - 32);
- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, txoffset);
- } else {
- OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_1, (pPix->drawable.width - 1) |
- ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch - 32);
- OUT_ACCEL_REG(R200_PP_TXOFFSET_1, txoffset);
- }
- FINISH_ACCEL();
-
- if (pPict->transform != 0) {
- is_transform[unit] = TRUE;
- transform[unit] = pPict->transform;
- } else {
- is_transform[unit] = FALSE;
- }
-
- return TRUE;
-}
-
-#ifdef ONLY_ONCE
-static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
- PicturePtr pDstPicture)
-{
- CARD32 tmp1;
-
- TRACE;
-
- /* Check for unsupported compositing operations. */
- if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
- RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-
- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) {
- /* Check if it's component alpha that relies on a source alpha and on
- * the source value. We can only get one of those into the single
- * source value that we get to blend with.
- */
- if (RadeonBlendOp[op].src_alpha &&
- (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) !=
- RADEON_SRC_BLEND_GL_ZERO)
- {
- RADEON_FALLBACK(("Component alpha not supported with source "
- "alpha and source value blending.\n"));
- }
- }
-
- if (!R200CheckCompositeTexture(pSrcPicture, 0))
- return FALSE;
- if (pMaskPicture != NULL && !R200CheckCompositeTexture(pMaskPicture, 1))
- return FALSE;
-
- if (!RADEONGetDestFormat(pDstPicture, &tmp1))
- return FALSE;
-
- return TRUE;
-}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
- PicturePtr pMaskPicture, PicturePtr pDstPicture,
- PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
-{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- CARD32 dst_format, dst_offset, dst_pitch;
- CARD32 pp_cntl, blendcntl, cblend, ablend, colorpitch;
- int pixel_shift;
- ACCEL_PREAMBLE();
-
- TRACE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- RADEONGetDestFormat(pDstPicture, &dst_format);
- pixel_shift = pDst->drawable.bitsPerPixel >> 4;
-
- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
- dst_pitch = exaGetPixmapPitch(pDst);
- colorpitch = dst_pitch >> pixel_shift;
- if (RADEONPixmapIsColortiled(pDst))
- colorpitch |= RADEON_COLOR_TILE_ENABLE;
-
- if ((dst_offset & 0x0f) != 0)
- RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset));
- if (((dst_pitch >> pixel_shift) & 0x7) != 0)
- RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
-
- if (!FUNC_NAME(R200TextureSetup)(pSrcPicture, pSrc, 0))
- return FALSE;
- pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
-
- if (pMask != NULL) {
- if (!FUNC_NAME(R200TextureSetup)(pMaskPicture, pMask, 1))
- return FALSE;
- pp_cntl |= RADEON_TEX_1_ENABLE;
- } else {
- is_transform[1] = FALSE;
- }
-
- RADEON_SWITCH_TO_3D();
-
- BEGIN_ACCEL(11);
-
- OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE);
- OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
-
- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
- (2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
-
- OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
-
- /* IN operator: Multiply src by mask components or mask alpha.
- * BLEND_CTL_ADD is A * B + C.
- * If a picture is a8, we have to explicitly zero its color values.
- * If the destination is a8, we have to route the alpha to red, I think.
- * If we're doing component alpha where the source for blending is going to
- * be the source alpha (and there's no source value used), we have to zero
- * the source's color values.
- */
- cblend = R200_TXC_OP_MADD | R200_TXC_ARG_C_ZERO;
- ablend = R200_TXA_OP_MADD | R200_TXA_ARG_C_ZERO;
-
- if (pDstPicture->format == PICT_a8 ||
- (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha))
- {
- cblend |= R200_TXC_ARG_A_R0_ALPHA;
- } else if (pSrcPicture->format == PICT_a8)
- cblend |= R200_TXC_ARG_A_ZERO;
- else
- cblend |= R200_TXC_ARG_A_R0_COLOR;
- ablend |= R200_TXA_ARG_A_R0_ALPHA;
-
- if (pMask) {
- if (pMaskPicture->componentAlpha &&
- pDstPicture->format != PICT_a8)
- cblend |= R200_TXC_ARG_B_R1_COLOR;
- else
- cblend |= R200_TXC_ARG_B_R1_ALPHA;
- ablend |= R200_TXA_ARG_B_R1_ALPHA;
- } else {
- cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B;
- ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B;
- }
-
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, cblend);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0, ablend);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
-
- /* Op operator. */
- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blendcntl);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-#ifdef ONLY_ONCE
-
-static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit)
-{
- int w = pPict->pDrawable->width;
- int h = pPict->pDrawable->height;
- int i;
-
- if ((w > 0x7ff) || (h > 0x7ff))
- RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
-
- for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
- {
- if (R300TexFormats[i].fmt == pPict->format)
- break;
- }
- if (i == sizeof(R300TexFormats) / sizeof(R300TexFormats[0]))
- RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
- (int)pPict->format));
-
- if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0))
- RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h));
-
- if (pPict->filter != PictFilterNearest &&
- pPict->filter != PictFilterBilinear)
- RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter));
-
- return TRUE;
-}
-
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
- int unit)
-{
- RINFO_FROM_SCREEN(pPix->drawable.pScreen);
- CARD32 txfilter, txformat0, txformat1, txoffset, txpitch;
- int w = pPict->pDrawable->width;
- int h = pPict->pDrawable->height;
- int i, pixel_shift;
- ACCEL_PREAMBLE();
-
- TRACE;
-
- txpitch = exaGetPixmapPitch(pPix);
- txoffset = exaGetPixmapOffset(pPix) + info->fbLocation;
-
- if ((txoffset & 0x1f) != 0)
- RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset));
- if ((txpitch & 0x1f) != 0)
- RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-
- pixel_shift = pPix->drawable.bitsPerPixel >> 4;
- txpitch >>= pixel_shift;
- txpitch -= 1;
-
- if (RADEONPixmapIsColortiled(pPix))
- txoffset |= R300_MACRO_TILE;
-
- for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
- {
- if (R300TexFormats[i].fmt == pPict->format)
- break;
- }
-
- txformat1 = R300TexFormats[i].card_fmt;
-
- txformat0 = (((w - 1) << R300_TXWIDTH_SHIFT) |
- ((h - 1) << R300_TXHEIGHT_SHIFT));
-
- if (pPict->repeat) {
- ErrorF("repeat\n");
- if ((h != 1) &&
- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
- RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
- w, (unsigned)txpitch));
- } else
- txformat0 |= R300_TXPITCH_EN;
-
-
- info->texW[unit] = w;
- info->texH[unit] = h;
-
- txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
-
- switch (pPict->filter) {
- case PictFilterNearest:
- txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
- break;
- case PictFilterBilinear:
- txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
- break;
- default:
- RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
- }
-
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0x0);
- OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
- OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
- OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
- OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset);
- FINISH_ACCEL();
-
- if (pPict->transform != 0) {
- is_transform[unit] = TRUE;
- transform[unit] = pPict->transform;
- } else {
- is_transform[unit] = FALSE;
- }
-
- return TRUE;
-}
-
-#ifdef ONLY_ONCE
-
-static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
- PicturePtr pDstPicture)
-{
- CARD32 tmp1;
- ScreenPtr pScreen = pDstPicture->pDrawable->pScreen;
- PixmapPtr pSrcPixmap, pDstPixmap;
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
-
- TRACE;
-
- /* Check for unsupported compositing operations. */
- if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
- RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-
-#if 1
- /* Throw out cases that aren't going to be our rotation first */
- if (pMaskPicture != NULL || op != PictOpSrc || pSrcPicture->pDrawable == NULL)
- RADEON_FALLBACK(("Junk driver\n"));
-
- if (pSrcPicture->pDrawable->type != DRAWABLE_WINDOW ||
- pDstPicture->pDrawable->type != DRAWABLE_PIXMAP) {
- RADEON_FALLBACK(("bad drawable\n"));
- }
-
- pSrcPixmap = (*pScreen->GetWindowPixmap) ((WindowPtr) pSrcPicture->pDrawable);
- pDstPixmap = (PixmapPtr)pDstPicture->pDrawable;
-
- /* Check if the dest is one of our shadow pixmaps */
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
-
- if (crtc->rotatedPixmap == pDstPixmap)
- break;
- }
- if (i == xf86_config->num_crtc)
- RADEON_FALLBACK(("no rotated pixmap\n"));
-
- if (pSrcPixmap != pScreen->GetScreenPixmap(pScreen))
- RADEON_FALLBACK(("src not screen\n"));
-#endif
-
-
- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) {
- /* Check if it's component alpha that relies on a source alpha and on
- * the source value. We can only get one of those into the single
- * source value that we get to blend with.
- */
- if (RadeonBlendOp[op].src_alpha &&
- (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) !=
- RADEON_SRC_BLEND_GL_ZERO)
- {
- RADEON_FALLBACK(("Component alpha not supported with source "
- "alpha and source value blending.\n"));
- }
- }
-
- if (!R300CheckCompositeTexture(pSrcPicture, 0))
- return FALSE;
- if (pMaskPicture != NULL && !R300CheckCompositeTexture(pMaskPicture, 1))
- return FALSE;
-
- if (!R300GetDestFormat(pDstPicture, &tmp1))
- return FALSE;
-
- return TRUE;
-
-}
-#endif /* ONLY_ONCE */
-
-static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
- PicturePtr pMaskPicture, PicturePtr pDstPicture,
- PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
-{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- CARD32 dst_format, dst_offset, dst_pitch;
- CARD32 txenable, colorpitch;
- CARD32 blendcntl;
- int pixel_shift;
- int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
- ACCEL_PREAMBLE();
-
- TRACE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- R300GetDestFormat(pDstPicture, &dst_format);
- pixel_shift = pDst->drawable.bitsPerPixel >> 4;
-
- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
- dst_pitch = exaGetPixmapPitch(pDst);
- colorpitch = dst_pitch >> pixel_shift;
-
- if (RADEONPixmapIsColortiled(pDst))
- colorpitch |= R300_COLORTILE;
-
- colorpitch |= dst_format;
-
- if ((dst_offset & 0x0f) != 0)
- RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset));
- if (((dst_pitch >> pixel_shift) & 0x7) != 0)
- RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
-
- if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0))
- return FALSE;
- txenable = R300_TEX_0_ENABLE;
-
- if (pMask != NULL) {
- if (!FUNC_NAME(R300TextureSetup)(pMaskPicture, pMask, 1))
- return FALSE;
- txenable |= R300_TEX_1_ENABLE;
- } else {
- is_transform[1] = FALSE;
- }
-
- RADEON_SWITCH_TO_3D();
-
- /* setup the VAP */
-
- if (has_tcl) {
- BEGIN_ACCEL(28);
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
- } else {
- BEGIN_ACCEL(10);
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
- OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
- }
-
- OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
- if (has_tcl) {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (10 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
- (0 << R300_SKIP_DWORDS_2_SHIFT) |
- (11 << R300_DST_VEC_LOC_2_SHIFT) |
- R300_LAST_VEC_2 |
- R300_SIGNED_2));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_2_SHIFT)));
- } else {
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
- (0 << R300_SKIP_DWORDS_2_SHIFT) |
- (7 << R300_DST_VEC_LOC_2_SHIFT) |
- R300_LAST_VEC_2 |
- R300_SIGNED_2));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_1_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_2_SHIFT)));
- }
-
- /* setup the vertex shader */
- if (has_tcl) {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
-
- OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
-
- OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
- }
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
- ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
- (2 << R300_TEX_1_COMP_CNT_SHIFT)));
-
- FINISH_ACCEL();
-
- /* setup pixel shader */
- if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
- BEGIN_ACCEL(16);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R300_RS_IP_0,
- (R300_RS_TEX_PTR(0) |
- R300_RS_COL_PTR(0) |
- R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
- OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
- OUT_ACCEL_REG(R300_US_CODE_OFFSET,
- (R300_ALU_CODE_OFFSET(0) |
- R300_ALU_CODE_SIZE(1) |
- R300_TEX_CODE_OFFSET(0) |
- R300_TEX_CODE_SIZE(1)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
- OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0);
- OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0);
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
- OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
- FINISH_ACCEL();
- } else {
- BEGIN_ACCEL(23);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
-
- OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
- OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
- OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
- OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
- OUT_ACCEL_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
- // 7807
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK);
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED);
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-
- // 0x78105
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
- R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK);
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
- R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST | R500_RGB_SRCP_OP_1_MINUS_2RGB0); //0x10040000
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
- R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST | R500_ALPHA_SRCP_OP_1_MINUS_2A0); //0x10040000
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA,
- R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC0 |
- R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1);//0x00db0220
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1);//0x00c0c000)
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0);//0x20490000
- FINISH_ACCEL();
- }
-
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
- OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
-
- OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
- OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
-
- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
-
-#if 0
- /* IN operator: Multiply src by mask components or mask alpha.
- * BLEND_CTL_ADD is A * B + C.
- * If a picture is a8, we have to explicitly zero its color values.
- * If the destination is a8, we have to route the alpha to red, I think.
- * If we're doing component alpha where the source for blending is going to
- * be the source alpha (and there's no source value used), we have to zero
- * the source's color values.
- */
- cblend = R200_TXC_OP_MADD | R200_TXC_ARG_C_ZERO;
- ablend = R200_TXA_OP_MADD | R200_TXA_ARG_C_ZERO;
-
- if (pDstPicture->format == PICT_a8 ||
- (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha))
- {
- cblend |= R200_TXC_ARG_A_R0_ALPHA;
- } else if (pSrcPicture->format == PICT_a8)
- cblend |= R200_TXC_ARG_A_ZERO;
- else
- cblend |= R200_TXC_ARG_A_R0_COLOR;
- ablend |= R200_TXA_ARG_A_R0_ALPHA;
-
- if (pMask) {
- if (pMaskPicture->componentAlpha &&
- pDstPicture->format != PICT_a8)
- cblend |= R200_TXC_ARG_B_R1_COLOR;
- else
- cblend |= R200_TXC_ARG_B_R1_ALPHA;
- ablend |= R200_TXA_ARG_B_R1_ALPHA;
- } else {
- cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B;
- ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B;
- }
-
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, cblend);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0, ablend);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
-
- /* Op operator. */
- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blendcntl);
-#endif
-
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-#define VTX_COUNT 6
-
-#ifdef ACCEL_CP
-
-#define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
-do { \
- OUT_RING_F(_dstX); \
- OUT_RING_F(_dstY); \
- OUT_RING_F(_srcX); \
- OUT_RING_F(_srcY); \
- OUT_RING_F(_maskX); \
- OUT_RING_F(_maskY); \
-} while (0)
-
-#else /* ACCEL_CP */
-
-#define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \
-do { \
- OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
- OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
- OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
- OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
- OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \
- OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \
-} while (0)
-
-#endif /* !ACCEL_CP */
-
-#ifdef ONLY_ONCE
-static inline void transformPoint(PictTransform *transform, xPointFixed *point)
-{
- PictVector v;
- v.vector[0] = point->x;
- v.vector[1] = point->y;
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform, &v);
- point->x = v.vector[0];
- point->y = v.vector[1];
-}
-#endif
-
-static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
- int srcX, int srcY,
- int maskX, int maskY,
- int dstX, int dstY,
- int w, int h)
-{
- RINFO_FROM_SCREEN(pDst->drawable.pScreen);
- int vtx_count;
- xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
- xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
- ACCEL_PREAMBLE();
-
- ENTER_DRAW(0);
-
- /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
- srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
-
- srcTopLeft.x = IntToxFixed(srcX);
- srcTopLeft.y = IntToxFixed(srcY);
- srcTopRight.x = IntToxFixed(srcX + w);
- srcTopRight.y = IntToxFixed(srcY);
- srcBottomLeft.x = IntToxFixed(srcX);
- srcBottomLeft.y = IntToxFixed(srcY + h);
- srcBottomRight.x = IntToxFixed(srcX + w);
- srcBottomRight.y = IntToxFixed(srcY + h);
-
- maskTopLeft.x = IntToxFixed(maskX);
- maskTopLeft.y = IntToxFixed(maskY);
- maskTopRight.x = IntToxFixed(maskX + w);
- maskTopRight.y = IntToxFixed(maskY);
- maskBottomLeft.x = IntToxFixed(maskX);
- maskBottomLeft.y = IntToxFixed(maskY + h);
- maskBottomRight.x = IntToxFixed(maskX + w);
- maskBottomRight.y = IntToxFixed(maskY + h);
-
- if (is_transform[0]) {
- transformPoint(transform[0], &srcTopLeft);
- transformPoint(transform[0], &srcTopRight);
- transformPoint(transform[0], &srcBottomLeft);
- transformPoint(transform[0], &srcBottomRight);
- }
- if (is_transform[1]) {
- transformPoint(transform[1], &maskTopLeft);
- transformPoint(transform[1], &maskTopRight);
- transformPoint(transform[1], &maskBottomLeft);
- transformPoint(transform[1], &maskBottomRight);
- }
-
- vtx_count = VTX_COUNT;
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- BEGIN_ACCEL(1);
- OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
- FINISH_ACCEL();
- }
-
-#ifdef ACCEL_CP
- if (info->ChipFamily < CHIP_FAMILY_R200) {
- BEGIN_RING(4 * vtx_count + 3);
- OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
- 4 * vtx_count + 1));
- OUT_RING(RADEON_CP_VC_FRMT_XY |
- RADEON_CP_VC_FRMT_ST0 |
- RADEON_CP_VC_FRMT_ST1);
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
- RADEON_CP_VC_CNTL_PRIM_WALK_RING |
- RADEON_CP_VC_CNTL_MAOS_ENABLE |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
- } else {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- BEGIN_RING(4 * vtx_count + 6);
- else
- BEGIN_RING(4 * vtx_count + 2);
-
- OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
- 4 * vtx_count));
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
- RADEON_CP_VC_CNTL_PRIM_WALK_RING |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
- }
-
-#else /* ACCEL_CP */
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- BEGIN_ACCEL(3 + vtx_count * 4);
- else
- BEGIN_ACCEL(1 + vtx_count * 4);
-
- if (info->ChipFamily < CHIP_FAMILY_R200) {
- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
- RADEON_VF_PRIM_WALK_DATA |
- RADEON_VF_RADEON_MODE |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
- } else {
- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
- RADEON_VF_PRIM_WALK_DATA |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
- }
-#endif
-
- VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]);
- VTX_OUT((float)dstX, (float)(dstY + h),
- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
- xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
- VTX_OUT((float)(dstX + w), (float)(dstY + h),
- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
- xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
- VTX_OUT((float)(dstX + w), (float)dstY,
- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
- xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]);
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- }
-
-#ifdef ACCEL_CP
- ADVANCE_RING();
-#else
- FINISH_ACCEL();
-#endif /* !ACCEL_CP */
-
- LEAVE_DRAW(0);
-}
-#undef VTX_OUT
-
-#ifdef ONLY_ONCE
-static void RadeonDoneComposite(PixmapPtr pDst)
-{
- ENTER_DRAW(0);
- LEAVE_DRAW(0);
-}
-#endif /* ONLY_ONCE */
-
-#undef ONLY_ONCE
-#undef FUNC_NAME
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
deleted file mode 100644
index 7f532a8..0000000
--- a/src/radeon_macros.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * !!!! FIXME !!!!
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
-
-
-#ifndef _RADEON_MACROS_H_
-#define _RADEON_MACROS_H_
-
-#include "compiler.h"
-
-#define RADEON_BIOS8(v) (info->VBIOS[v])
-#define RADEON_BIOS16(v) (info->VBIOS[v] | \
- (info->VBIOS[(v) + 1] << 8))
-#define RADEON_BIOS32(v) (info->VBIOS[v] | \
- (info->VBIOS[(v) + 1] << 8) | \
- (info->VBIOS[(v) + 2] << 16) | \
- (info->VBIOS[(v) + 3] << 24))
-
- /* Memory mapped register access macros */
-#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
-#define INREG16(addr) MMIO_IN16(RADEONMMIO, addr)
-#define INREG(addr) MMIO_IN32(RADEONMMIO, addr)
-#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val)
-#define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val)
-#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val)
-
-#define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr)))
-
-
-#define OUTREGP(addr, val, mask) \
-do { \
- CARD32 tmp = INREG(addr); \
- tmp &= (mask); \
- tmp |= ((val) & ~(mask)); \
- OUTREG(addr, tmp); \
-} while (0)
-
-#define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr)
-
-#define OUTPLL(pScrn, addr, val) RADEONOUTPLL(pScrn, addr, val)
-
-#define OUTPLLP(pScrn, addr, val, mask) \
-do { \
- CARD32 tmp_ = INPLL(pScrn, addr); \
- tmp_ &= (mask); \
- tmp_ |= ((val) & ~(mask)); \
- OUTPLL(pScrn, addr, tmp_); \
-} while (0)
-
-#define OUTPAL_START(idx) \
-do { \
- if (IS_AVIVO_VARIANT) { \
- OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \
- } else { \
- OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
- } \
-} while (0)
-
-#define OUTPAL_NEXT(r, g, b) \
-do { \
- if (IS_AVIVO_VARIANT) { \
- OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 22) | ((g) << 12) | ((b) << 2)); \
- } else { \
- OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
- } \
-} while (0)
-
-#define OUTPAL_NEXT_CARD32(v) \
-do { \
- OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \
-} while (0)
-
-#define OUTPAL(idx, r, g, b) \
-do { \
- OUTPAL_START((idx)); \
- OUTPAL_NEXT((r), (g), (b)); \
-} while (0)
-
-#define INPAL_START(idx) \
-do { \
- if (IS_AVIVO_VARIANT) { \
- OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \
- } else { \
- OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
- } \
-} while (0)
-
-#define INPAL_NEXT() \
-do { \
- if (IS_AVIVO_VARIANT) { \
- INREG(AVIVO_DC_LUT_30_COLOR); \
- } else { \
- INREG(RADEON_PALETTE_DATA); \
- } \
-} while (0)
-
-#define PAL_SELECT(idx) \
-do { \
- if (IS_AVIVO_VARIANT) { \
- if (!idx) { \
- OUTREG(AVIVO_DC_LUT_RW_SELECT, 0); \
- } else { \
- OUTREG(AVIVO_DC_LUT_RW_SELECT, 1); \
- } \
- } else { \
- if (!idx) { \
- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
- (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \
- } else { \
- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
- RADEON_DAC2_PALETTE_ACC_CTL); \
- } \
- } \
-} while (0)
-
-#define INMC(pScrn, addr) RADEONINMC(pScrn, addr)
-
-#define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val)
-
-#endif
diff --git a/src/radeon_misc.c b/src/radeon_misc.c
deleted file mode 100644
index 1115118..0000000
--- a/src/radeon_misc.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "radeon_probe.h"
-#include "radeon_version.h"
-
-#include "xf86.h"
-
-/* Module loader interface for subsidiary driver module */
-
-static XF86ModuleVersionInfo RADEONVersionRec =
-{
- RADEON_DRIVER_NAME,
- MODULEVENDORSTRING,
- MODINFOSTRING1,
- MODINFOSTRING2,
- XORG_VERSION_CURRENT,
- RADEON_VERSION_MAJOR, RADEON_VERSION_MINOR, RADEON_VERSION_PATCH,
- ABI_CLASS_VIDEODRV,
- ABI_VIDEODRV_VERSION,
- MOD_CLASS_VIDEODRV,
- {0, 0, 0, 0}
-};
-
-/*
- * RADEONSetup --
- *
- * This function is called every time the module is loaded.
- */
-static pointer
-RADEONSetup
-(
- pointer Module,
- pointer Options,
- int *ErrorMajor,
- int *ErrorMinor
-)
-{
- static Bool Inited = FALSE;
-
- if (!Inited) {
- Inited = TRUE;
- xf86AddDriver(&RADEON, Module, HaveDriverFuncs);
- }
-
- return (pointer)TRUE;
-}
-
-/* The following record must be called radeonModuleData */
-_X_EXPORT XF86ModuleData radeonModuleData =
-{
- &RADEONVersionRec,
- RADEONSetup,
- NULL
-};
diff --git a/src/radeon_mm_i2c.c b/src/radeon_mm_i2c.c
deleted file mode 100644
index 0524fa9..0000000
--- a/src/radeon_mm_i2c.c
+++ /dev/null
@@ -1,642 +0,0 @@
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <math.h>
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include <X11/extensions/Xv.h>
-#include "radeon_video.h"
-#include "atipciids.h"
-
-#include "xf86.h"
-
-/* i2c stuff */
-#include "xf86i2c.h"
-#include "fi1236.h"
-#include "msp3430.h"
-#include "tda9885.h"
-#include "uda1380.h"
-#include "i2c_def.h"
-
-
-static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv);
-
-/* Wait for 10ms at the most for the I2C_GO register to drop. */
-#define I2C_WAIT_FOR_GO() { \
- int i2ctries = 0; \
- RADEONWaitForIdleMMIO(pScrn); \
- write_mem_barrier(); \
- while (i2ctries < 10) { \
- reg = INREG8(RADEON_I2C_CNTL_0+1); \
- if (!(reg & (RADEON_I2C_GO >> 8))) \
- break; \
- if (reg & (RADEON_I2C_ABORT >> 8)) \
- break; \
- usleep(1000); \
- i2ctries++; \
- } \
-}
-
-/* Wait, and dump the status in the 'status' register. If we time out or
- * receive an abort signal, halt/restart the I2C bus and leave _ABORT in the
- * status register. */
-#define I2C_WAIT_WITH_STATUS() { \
- I2C_WAIT_FOR_GO() \
- if (reg & ((RADEON_I2C_ABORT >> 8) | (RADEON_I2C_GO >> 8))) { \
- RADEON_I2C_Halt(pScrn); \
- status = RADEON_I2C_ABORT; \
- } \
- else \
- status = RADEON_I2C_WaitForAck(pScrn, pPriv); \
-}
-
-/****************************************************************************
- * I2C_WaitForAck (void) *
- * *
- * Function: polls the I2C status bits, waiting for an acknowledge or *
- * an error condition. *
- * Inputs: NONE *
- * Outputs: I2C_DONE - the I2C transfer was completed *
- * I2C_NACK - an NACK was received from the slave *
- * I2C_HALT - a timeout condition has occured *
- ****************************************************************************/
-static CARD8 RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- CARD8 retval = 0;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- long counter = 0;
-
- usleep(1000);
- while(1)
- {
- RADEONWaitForIdleMMIO(pScrn);
- retval = INREG8(RADEON_I2C_CNTL_0);
- if (retval & RADEON_I2C_HALT)
- {
- return (RADEON_I2C_HALT);
- }
- if (retval & RADEON_I2C_NACK)
- {
- return (RADEON_I2C_NACK);
- }
- if(retval & RADEON_I2C_DONE)
- {
- return RADEON_I2C_DONE;
- }
- counter++;
- /* 50ms ought to be long enough. */
- if(counter > 50)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Timeout condition on Radeon i2c bus\n");
- return RADEON_I2C_HALT;
- }
- usleep(1000);
- }
-}
-
-static void RADEON_I2C_Halt (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD8 reg;
-
- /* reset status flags */
- RADEONWaitForIdleMMIO(pScrn);
- reg = INREG8 (RADEON_I2C_CNTL_0 + 0) & ~(RADEON_I2C_DONE|RADEON_I2C_NACK|RADEON_I2C_HALT);
- OUTREG8 (RADEON_I2C_CNTL_0 + 0, reg);
-
- /* issue ABORT call */
- RADEONWaitForIdleMMIO(pScrn);
- reg = INREG8 (RADEON_I2C_CNTL_0 + 1) & 0xE7;
- OUTREG8 (RADEON_I2C_CNTL_0 + 1, (reg |((RADEON_I2C_GO|RADEON_I2C_ABORT) >> 8)));
-
- /* wait for GO bit to go low */
- I2C_WAIT_FOR_GO();
-}
-
-
-static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite,
- I2CByte *ReadBuffer, int nRead)
-{
- int loop, status;
- CARD32 i2c_cntl_0, i2c_cntl_1;
- CARD8 reg;
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr);
- ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- status=RADEON_I2C_DONE;
-
- RADEONWaitForIdleMMIO(pScrn);
- if(nWrite>0){
-/* RADEONWaitForFifo(pScrn, 4+nWrite); */
-
- /* Clear the status bits of the I2C Controller */
- OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
-
- /* Write the address into the buffer first */
- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1));
-
- /* Write Value into the buffer */
- for (loop = 0; loop < nWrite; loop++)
- {
- OUTREG8(RADEON_I2C_DATA, WriteBuffer[loop]);
- }
-
- i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
- nWrite | 0x100;
- OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
-
- i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
- RADEON_I2C_GO | RADEON_I2C_START | ((nRead >0)?0:RADEON_I2C_STOP) | RADEON_I2C_DRIVE_EN;
- OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
-
- I2C_WAIT_WITH_STATUS();
-
- if(status!=RADEON_I2C_DONE){
- RADEON_I2C_Halt(pScrn);
- return FALSE;
- }
- }
-
-
- if(nRead > 0) {
- RADEONWaitForFifo(pScrn, 4+nRead);
-
- OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
-
- /* Write the address into the buffer first */
- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1));
-
- i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
- nRead | 0x100;
- OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
-
- i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
- RADEON_I2C_GO | RADEON_I2C_START | RADEON_I2C_STOP | RADEON_I2C_DRIVE_EN | RADEON_I2C_RECEIVE;
- OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
-
- I2C_WAIT_WITH_STATUS();
-
- /* Write Value into the buffer */
- for (loop = 0; loop < nRead; loop++)
- {
- RADEONWaitForFifo(pScrn, 1);
- if((status == RADEON_I2C_HALT) || (status == RADEON_I2C_NACK))
- {
- ReadBuffer[loop]=0xff;
- } else {
- RADEONWaitForIdleMMIO(pScrn);
- ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff;
- }
- }
- }
-
- if(status!=RADEON_I2C_DONE){
- RADEON_I2C_Halt(pScrn);
- return FALSE;
- }
- return TRUE;
-}
-
-static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite,
- I2CByte *ReadBuffer, int nRead)
-{
- int loop, status;
- CARD32 i2c_cntl_0, i2c_cntl_1;
- CARD8 reg;
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr);
- ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- status=RADEON_I2C_DONE;
-
- RADEONWaitForIdleMMIO(pScrn);
- if(nWrite>0){
-/* RADEONWaitForFifo(pScrn, 4+nWrite); */
-
- /* Clear the status bits of the I2C Controller */
- OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
-
- /* Write the address into the buffer first */
- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1));
-
- /* Write Value into the buffer */
- for (loop = 0; loop < nWrite; loop++)
- {
- OUTREG8(RADEON_I2C_DATA, WriteBuffer[loop]);
- }
-
- i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
- nWrite | 0x010;
- OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
-
- i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
- RADEON_I2C_GO | RADEON_I2C_START | ((nRead >0)?0:RADEON_I2C_STOP) | RADEON_I2C_DRIVE_EN;
- OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
-
- I2C_WAIT_WITH_STATUS();
-
- if(status!=RADEON_I2C_DONE){
- RADEON_I2C_Halt(pScrn);
- return FALSE;
- }
- }
-
-
- if(nRead > 0) {
- RADEONWaitForFifo(pScrn, 4+nRead);
-
- OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST);
-
- /* Write the address into the buffer first */
- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1));
-
- i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL |
- nRead | 0x010;
- OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1);
-
- i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) |
- RADEON_I2C_GO | RADEON_I2C_START | RADEON_I2C_STOP | RADEON_I2C_DRIVE_EN | RADEON_I2C_RECEIVE;
- OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0);
-
- I2C_WAIT_WITH_STATUS();
-
- RADEONWaitForIdleMMIO(pScrn);
- /* Write Value into the buffer */
- for (loop = 0; loop < nRead; loop++)
- {
- if((status == RADEON_I2C_HALT) || (status == RADEON_I2C_NACK))
- {
- ReadBuffer[loop]=0xff;
- } else {
- ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff;
- }
- }
- }
-
- if(status!=RADEON_I2C_DONE){
- RADEON_I2C_Halt(pScrn);
- return FALSE;
- }
- return TRUE;
-}
-
-#if 0
-static Bool RADEONProbeAddress(I2CBusPtr b, I2CSlaveAddr addr)
-{
- I2CByte a;
- I2CDevRec d;
-
- d.DevName = "Probing";
- d.SlaveAddr = addr;
- d.pI2CBus = b;
- d.NextDev = NULL;
-
- return I2C_WriteRead(&d, NULL, 0, &a, 1);
-}
-#endif
-
-#define I2C_CLOCK_FREQ (60000.0)
-
-
-const struct
-{
- char *name;
- int type;
-} RADEON_tuners[32] =
- {
- /* name ,index to tuner_parms table */
- {"NO TUNER" , -1},
- {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
- {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
- {"Philips FI1216 (or compatible)" , TUNER_TYPE_FI1216},
- {"Philips FI1246 (or compatible)" , TUNER_TYPE_FI1246},
- {"Philips FI1216MF (or compatible)" , TUNER_TYPE_FI1216},
- {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
- {"Philips FI1256 (or compatible)" , TUNER_TYPE_FI1256},
- {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
- {"Philips FI1216 (or compatible)" , TUNER_TYPE_FI1216},
- {"Philips FI1246 (or compatible)" , TUNER_TYPE_FI1246},
- {"Philips FI1216MF (or compatible)" , TUNER_TYPE_FI1216},
- {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236},
- {"TEMIC-FN5AL" , TUNER_TYPE_TEMIC_FN5AL},
- {"FQ1216ME/P" , TUNER_TYPE_FI1216},
- {"FI1236W" , TUNER_TYPE_FI1236W},
- {"Philips FI1216ME (or compatible)" , TUNER_TYPE_FM1216ME},
- /*{"Alps TSCxx" , -1},*/
- {"Philips FM1236/F" , TUNER_TYPE_FI1236W},
- {"Philips FI1216ME (or compatible)" , TUNER_TYPE_FM1216ME},
- {"UNKNOWN-19" , -1},
- {"UNKNOWN-20" , -1},
- {"UNKNOWN-21" , -1},
- {"UNKNOWN-22" , -1},
- {"UNKNOWN-23" , -1},
- {"UNKNOWN-24" , -1},
- {"UNKNOWN-25" , -1},
- {"UNKNOWN-26" , -1},
- {"UNKNOWN-27" , -1},
- {"UNKNOWN-28" , -1},
- {"Microtuner MT2032" , TUNER_TYPE_MT2032},
- {"Microtuner MT2032" , TUNER_TYPE_MT2032},
- {"UNKNOWN-31" , -1}
- };
-
-
-void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG8(RADEON_I2C_CNTL_1+2, ((RADEON_I2C_SEL | RADEON_I2C_EN)>>16));
- OUTREG8(RADEON_I2C_CNTL_0+0, (RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST | RADEON_I2C_DRIVE_EN | RADEON_I2C_DRIVE_SEL));
-}
-
-void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- double nm;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPLLPtr pll = &(info->pll);
-
- pPriv->i2c = NULL;
- pPriv->fi1236 = NULL;
- pPriv->msp3430 = NULL;
- pPriv->tda9885 = NULL;
- pPriv->uda1380 = NULL;
- #if 0 /* put back on when saa7114 support is present */
- pPriv->saa7114 = NULL;
- #endif
-
- /* Blacklist chipsets that lockup - these are usually older mobility chips */
-
- switch(info->Chipset){
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility M6, disabling multimedia i2c\n");
- return;
- case PCI_CHIP_RADEON_LW:
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility M7, disabling multimedia i2c\n");
- return;
- /*case PCI_CHIP_RV250_If:
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon 9000 - skipping multimedia i2c initialization code.\n");
- return;*/
- case PCI_CHIP_RV370_5460:
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility X300, disabling multimedia i2c\n");
- return;
- }
-
- /* no multimedia capabilities detected and no information was provided to substitute for it */
- if(!info->MM_TABLE_valid &&
- !(info->tunerType>=0))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No video input capabilities detected and no information is provided - disabling multimedia i2c\n");
- return;
- }
-
-
- if(pPriv->i2c!=NULL) return; /* for some reason we are asked to init it again.. Stop ! */
-
- if(!xf86LoadSubModule(pScrn,"i2c"))
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to initialize i2c bus\n");
- pPriv->i2c = NULL;
- return;
- }
- pPriv->i2c=CreateI2CBusRec();
- pPriv->i2c->scrnIndex=pScrn->scrnIndex;
- pPriv->i2c->BusName="Radeon multimedia bus";
- pPriv->i2c->DriverPrivate.ptr=(pointer)pPriv;
- switch(info->ChipFamily){
- case CHIP_FAMILY_RV350:
- case CHIP_FAMILY_R350:
- case CHIP_FAMILY_R300:
- case CHIP_FAMILY_RV250:
- case CHIP_FAMILY_R200:
- case CHIP_FAMILY_RV200:
- pPriv->i2c->I2CWriteRead=R200_I2CWriteRead;
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Using R200 i2c bus access method\n");
- break;
- default:
- pPriv->i2c->I2CWriteRead=RADEONI2CWriteRead;
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Using Radeon bus access method\n");
- }
- if(!I2CBusInit(pPriv->i2c))
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Failed to register i2c bus\n");
- }
-
-#if 1
- switch(info->ChipFamily){
- case CHIP_FAMILY_RV200:
- nm=(pll->reference_freq * 40000.0)/(1.0*I2C_CLOCK_FREQ);
- break;
- case CHIP_FAMILY_R300:
- case CHIP_FAMILY_R200:
- if(info->MM_TABLE_valid && (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_MT2032)){
- nm=(pll->reference_freq * 40000.0)/(4.0*I2C_CLOCK_FREQ);
- break;
- }
- default:
- nm=(pll->reference_freq * 10000.0)/(4.0*I2C_CLOCK_FREQ);
- }
-#else
- nm=(pll->xclk * 40000.0)/(1.0*I2C_CLOCK_FREQ);
-#endif
- for(pPriv->radeon_N=1; pPriv->radeon_N<255; pPriv->radeon_N++)
- if((pPriv->radeon_N * (pPriv->radeon_N-1)) > nm)break;
- pPriv->radeon_M=pPriv->radeon_N-1;
- pPriv->radeon_i2c_timing=2*pPriv->radeon_N;
-
-
-#if 0
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref=%d M=0x%02x N=0x%02x timing=0x%02x\n", pll->reference_freq, pPriv->radeon_M, pPriv->radeon_N, pPriv->radeon_i2c_timing);
- pPriv->radeon_M=0x32;
- pPriv->radeon_N=0x33;
- pPriv->radeon_i2c_timing=2*pPriv->radeon_N;
-#endif
- RADEONResetI2C(pScrn, pPriv);
-
-#if 0 /* I don't know whether standalone boards are supported with Radeons */
- /* looks like none of them have AMC connectors anyway */
- if(!info->MM_TABLE_valid)RADEON_read_eeprom(pPriv);
-#endif
-
- if(!xf86LoadSubModule(pScrn,"fi1236"))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize fi1236 driver\n");
- }
- else
- {
- if(pPriv->fi1236 == NULL)
- {
- pPriv->fi1236 = xf86_Detect_FI1236(pPriv->i2c, FI1236_ADDR_1);
- }
- if(pPriv->fi1236 == NULL)
- {
- pPriv->fi1236 = xf86_Detect_FI1236(pPriv->i2c, FI1236_ADDR_2);
- }
- }
- if(pPriv->fi1236 != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected %s device at 0x%02x\n",
- RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].name,
- FI1236_ADDR(pPriv->fi1236));
- if(info->MM_TABLE_valid)xf86_FI1236_set_tuner_type(pPriv->fi1236, RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type);
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE not found (standalone board ?), forcing tuner type to NTSC\n");
- xf86_FI1236_set_tuner_type(pPriv->fi1236, TUNER_TYPE_FI1236);
- }
- }
-
- if(info->MM_TABLE_valid && (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_MT2032)){
- if(!xf86LoadSubModule(pScrn,"tda9885"))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize tda9885 driver\n");
- }
- else
- {
- if(pPriv->tda9885 == NULL)
- {
- pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_1);
- }
- if(pPriv->tda9885 == NULL)
- {
- pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_2);
- }
- if(pPriv->tda9885 != NULL)
- {
- RADEON_TDA9885_Init(pPriv);
- }
- }
- }
-
- if(info->MM_TABLE_valid && ((RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_FM1216ME)
- || (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_FI1236W)))
- {
- if(!xf86LoadSubModule(pScrn,"tda9885"))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize tda9885 driver\n");
- }
- else
- {
- if(pPriv->tda9885 == NULL)
- {
- pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_1);
- }
- if(pPriv->tda9885 == NULL)
- {
- pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_2);
- }
- if(pPriv->tda9885 != NULL)
- {
- RADEON_TDA9885_Init(pPriv);
- pPriv->fi1236->afc_source = (void*)pPriv->tda9885;
- }
- }
- }
-
- if(!xf86LoadSubModule(pScrn,"uda1380"))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize uda1380 driver\n");
- }
- else
- {
- if(pPriv->uda1380 == NULL)
- {
- pPriv->uda1380 = xf86_Detect_uda1380(pPriv->i2c, UDA1380_ADDR_1);
- }
- if(pPriv->uda1380 == NULL)
- {
- pPriv->uda1380 = xf86_Detect_uda1380(pPriv->i2c, UDA1380_ADDR_2);
- }
- if(pPriv->uda1380 != NULL)
- {
- xf86_uda1380_init(pPriv->uda1380);
- }
- }
-
-
- if(!xf86LoadSubModule(pScrn,"msp3430"))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize msp3430 driver\n");
- }
- else
- {
- if(pPriv->msp3430 == NULL)
- {
- pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_1);
- }
- if(pPriv->msp3430 == NULL)
- {
- pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_2);
- }
-#if 0 /* this would confuse bt829 with msp3430 */
- if(pPriv->msp3430 == NULL)
- {
- pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_3);
- }
-#endif
- }
- if(pPriv->msp3430 != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected MSP3430 at 0x%02x\n",
- MSP3430_ADDR(pPriv->msp3430));
- pPriv->msp3430->standard = MSP3430_NTSC;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_1;
- xf86_ResetMSP3430(pPriv->msp3430);
- xf86_InitMSP3430(pPriv->msp3430);
- xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume));
- }
-
-#if 0 /* put this back when saa7114 driver is ready */
- if(!xf86LoadSubModule(pScrn,"saa7114"))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize saa7114 driver\n");
- }
- else
- {
- if(pPriv->saa7114 == NULL)
- {
- pPriv->saa7114 = xf86_DetectSAA7114(pPriv->i2c, SAA7114_ADDR_1);
- }
- if(pPriv->saa7114 == NULL)
- {
- pPriv->saa7114 = xf86_DetectSAA7114(pPriv->i2c, SAA7114_ADDR_2);
- }
- }
- if(pPriv->saa7114 != NULL)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected SAA7114 at 0x%02x\n",
- pPriv->saa7114->d.SlaveAddr);
- xf86_InitSAA7114(pPriv->saa7114);
- }
-#endif
-
-}
-
-static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv)
-{
-TDA9885Ptr t=pPriv->tda9885;
-t->sound_trap=0;
-t->auto_mute_fm=1; /* ? */
-t->carrier_mode=0; /* ??? */
-t->modulation=2; /* negative FM */
-t->forced_mute_audio=0;
-t->port1=1;
-t->port2=1;
-t->top_adjustment=0x10;
-t->deemphasis=1;
-t->audio_gain=0;
-t->minimum_gain=0;
-t->gating=0;
-t->vif_agc=1; /* set to 1 ? - depends on design */
-t->gating=0;
-}
diff --git a/src/radeon_modes.c b/src/radeon_modes.c
deleted file mode 100644
index 2c72395..0000000
--- a/src/radeon_modes.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- */
-
-#include <string.h>
-#include <stdio.h>
-
-#include "xf86.h"
- /* Driver data structures */
-#include "randrstr.h"
-#include "radeon_probe.h"
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_version.h"
-#include "radeon_atombios.h"
-
-#include "xf86Modes.h"
- /* DDC support */
-#include "xf86DDC.h"
-#include <randrstr.h>
-
-void RADEONSetPitch (ScrnInfoPtr pScrn)
-{
- int dummy = pScrn->virtualX;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int pitch_mask = 0;
- int align_large;
-
- align_large = info->allowColorTiling || IS_AVIVO_VARIANT;
-
- /* FIXME: May need to validate line pitch here */
- switch (pScrn->depth / 8) {
- case 1: pitch_mask = align_large ? 255 : 127;
- break;
- case 2: pitch_mask = align_large ? 127 : 31;
- break;
- case 3:
- case 4: pitch_mask = align_large ? 63 : 15;
- break;
- }
- dummy = (pScrn->virtualX + pitch_mask) & ~pitch_mask;
- pScrn->displayWidth = dummy;
- info->CurrentLayout.displayWidth = pScrn->displayWidth;
-
-}
-
-static DisplayModePtr
-RADEONTVModes(xf86OutputPtr output)
-{
- DisplayModePtr new = NULL;
-
- /* just a place holder */
- new = xf86CVTMode(800, 600, 60.00, FALSE, FALSE);
- new->type = M_T_DRIVER | M_T_PREFERRED;
-
- return new;
-}
-
-static DisplayModePtr
-RADEONATOMTVModes(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- DisplayModePtr last = NULL;
- DisplayModePtr new = NULL;
- DisplayModePtr first = NULL;
- int max_v, i;
- /* Add some common sizes */
- int widths[5] = {640, 720, 800, 848, 1024};
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- max_v = 480;
- else
- max_v = 600;
-
- for (i = 0; i < 5; i++) {
- new = xf86CVTMode(widths[i], max_v, 60.0, FALSE, FALSE);
-
- new->type = M_T_DRIVER;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M) {
- if (widths[i] == 640)
- new->type |= M_T_PREFERRED;
- } else {
- if (widths[i] == 800)
- new->type |= M_T_PREFERRED;
- }
-
- new->next = NULL;
- new->prev = last;
-
- if (last) last->next = new;
- last = new;
- if (!first) first = new;
- }
-
- if (last) {
- last->next = NULL; //first;
- first->prev = NULL; //last;
- }
-
- return first;
-}
-
-/* This is used only when no mode is specified for FP and no ddc is
- * available. We force it to native mode, if possible.
- */
-static DisplayModePtr RADEONFPNativeMode(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- DisplayModePtr new = NULL;
- char stmp[32];
-
- if (radeon_output->PanelXRes != 0 &&
- radeon_output->PanelYRes != 0 &&
- radeon_output->DotClock != 0) {
-
- new = xnfcalloc(1, sizeof (DisplayModeRec));
- sprintf(stmp, "%dx%d", radeon_output->PanelXRes, radeon_output->PanelYRes);
- new->name = xnfalloc(strlen(stmp) + 1);
- strcpy(new->name, stmp);
- new->HDisplay = radeon_output->PanelXRes;
- new->VDisplay = radeon_output->PanelYRes;
-
- new->HTotal = new->HDisplay + radeon_output->HBlank;
- new->HSyncStart = new->HDisplay + radeon_output->HOverPlus;
- new->HSyncEnd = new->HSyncStart + radeon_output->HSyncWidth;
- new->VTotal = new->VDisplay + radeon_output->VBlank;
- new->VSyncStart = new->VDisplay + radeon_output->VOverPlus;
- new->VSyncEnd = new->VSyncStart + radeon_output->VSyncWidth;
-
- new->Clock = radeon_output->DotClock;
- new->Flags = 0;
-
- if (new) {
- new->type = M_T_DRIVER | M_T_PREFERRED;
-
- new->next = NULL;
- new->prev = NULL;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode: %dx%d\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes);
- }
-
- return new;
-}
-
-/* this function is basically a hack to add the screen modes */
-static void RADEONAddScreenModes(xf86OutputPtr output, DisplayModePtr *modeList)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- DisplayModePtr last = NULL;
- DisplayModePtr new = NULL;
- DisplayModePtr first = NULL;
- int count = 0;
- int i, width, height;
- char **ppModeName = pScrn->display->modes;
-
- first = last = *modeList;
-
- /* We have a flat panel connected to the primary display, and we
- * don't have any DDC info.
- */
- for (i = 0; ppModeName[i] != NULL; i++) {
-
- if (sscanf(ppModeName[i], "%dx%d", &width, &height) != 2) continue;
-
- if (radeon_output->type == OUTPUT_LVDS) {
- /* already added the native mode */
- if (width == radeon_output->PanelXRes && height == radeon_output->PanelYRes)
- continue;
-
- /* Note: We allow all non-standard modes as long as they do not
- * exceed the native resolution of the panel. Since these modes
- * need the internal RMX unit in the video chips (and there is
- * only one per card), this will only apply to the primary head.
- */
- if (width < 320 || width > radeon_output->PanelXRes ||
- height < 200 || height > radeon_output->PanelYRes) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Mode %s is out of range.\n", ppModeName[i]);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Valid FP modes must be between 320x200-%dx%d\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes);
- continue;
- }
- }
-
- new = xf86CVTMode(width, height, 60.0, FALSE, FALSE);
-
- new->type |= M_T_USERDEF;
-
- new->next = NULL;
- new->prev = last;
-
- if (last) last->next = new;
- last = new;
- if (!first) first = new;
-
- count++;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Adding Screen mode: %s\n", new->name);
- }
-
-
- /* Close the doubly-linked mode list, if we found any usable modes */
- if (last) {
- last->next = NULL; //first;
- first->prev = NULL; //last;
- *modeList = first;
- }
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Total number of valid Screen mode(s) added: %d\n", count);
-
-}
-
-DisplayModePtr
-RADEONProbeOutputModes(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- DisplayModePtr modes = NULL;
- AtomBiosArgRec atomBiosArg;
- AtomBiosResult atomBiosResult;
-
- ErrorF("in RADEONProbeOutputModes\n");
-
- if (output->status == XF86OutputStatusConnected) {
- if (OUTPUT_IS_TV) {
- if (IS_AVIVO_VARIANT)
- modes = RADEONATOMTVModes(output);
- else
- modes = RADEONTVModes(output);
- } else if (radeon_output->type == OUTPUT_CV) {
- atomBiosResult = RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- ATOMBIOS_GET_CV_MODES, &atomBiosArg);
- if (atomBiosResult == ATOM_SUCCESS) {
- modes = atomBiosArg.modes;
- }
- } else {
- if (output->MonInfo)
- modes = xf86OutputGetEDIDModes (output);
- if (modes == NULL) {
- if ((radeon_output->type == OUTPUT_LVDS) && info->IsAtomBios) {
- atomBiosResult = RHDAtomBiosFunc(pScrn->scrnIndex,
- info->atomBIOS,
- ATOMBIOS_GET_PANEL_EDID, &atomBiosArg);
- if (atomBiosResult == ATOM_SUCCESS) {
- output->MonInfo = xf86InterpretEDID(pScrn->scrnIndex,
- atomBiosArg.EDIDBlock);
- modes = xf86OutputGetEDIDModes(output);
- }
- }
- if (modes == NULL) {
- if (radeon_output->type == OUTPUT_LVDS)
- modes = RADEONFPNativeMode(output);
- /* add the screen modes */
- RADEONAddScreenModes(output, &modes);
- }
- }
- }
- }
-
- return modes;
-}
-
diff --git a/src/radeon_output.c b/src/radeon_output.c
deleted file mode 100644
index 62cc5d4..0000000
--- a/src/radeon_output.c
+++ /dev/null
@@ -1,2803 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include <stdio.h>
-
-/* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "vgaHW.h"
-#include "xf86Modes.h"
-
-/* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#include "radeon_tv.h"
-#include "radeon_atombios.h"
-
-const char *MonTypeName[10] = {
- "AUTO",
- "NONE",
- "CRT",
- "LVDS",
- "TMDS",
- "CTV",
- "STV",
- "CV",
- "HDMI",
- "DP"
-};
-
-const RADEONMonitorType MonTypeID[10] = {
- MT_UNKNOWN, /* this is just a dummy value for AUTO DETECTION */
- MT_NONE, /* NONE -> NONE */
- MT_CRT, /* CRT -> CRT */
- MT_LCD, /* Laptop LCDs are driven via LVDS port */
- MT_DFP, /* DFPs are driven via TMDS */
- MT_CTV, /* CTV -> CTV */
- MT_STV, /* STV -> STV */
- MT_CV,
- MT_HDMI,
- MT_DP
-};
-
-const char *TMDSTypeName[5] = {
- "None",
- "Internal",
- "External",
- "LVTMA",
- "DDIA"
-};
-
-const char *DACTypeName[4] = {
- "None",
- "Primary",
- "TVDAC/ExtDAC",
- "ExtDac"
-};
-
-const char *ConnectorTypeName[17] = {
- "None",
- "VGA",
- "DVI-I",
- "DVI-D",
- "DVI-A",
- "STV",
- "CTV",
- "LVDS",
- "Digital",
- "SCART",
- "HDMI-A",
- "HDMI-B",
- "Unsupported",
- "Unsupported",
- "DIN",
- "DisplayPort",
- "Unsupported"
-};
-
-const char *OutputType[11] = {
- "None",
- "VGA",
- "DVI",
- "DVI",
- "DVI",
- "LVDS",
- "S-video",
- "Composite",
- "Component",
- "HDMI",
- "DisplayPort",
-};
-
-static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] =
-{
- {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_UNKNOW*/
- {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_LEGACY*/
- {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RADEON*/
- {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV100*/
- {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS100*/
- {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV200*/
- {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS200*/
- {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R200*/
- {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV250*/
- {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS300*/
- {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /*CHIP_FAMILY_RV280*/
- {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R300*/
- {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R350*/
- {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV350*/
- {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV380*/
- {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/
- {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */
- {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */
-};
-
-static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] =
-{
- 0x00000000, /* unknown */
- 0x00000000, /* legacy */
- 0x00000000, /* r100 */
- 0x00280000, /* rv100 */
- 0x00000000, /* rs100 */
- 0x00880000, /* rv200 */
- 0x00000000, /* rs200 */
- 0x00000000, /* r200 */
- 0x00770000, /* rv250 */
- 0x00290000, /* rs300 */
- 0x00560000, /* rv280 */
- 0x00780000, /* r300 */
- 0x00770000, /* r350 */
- 0x00780000, /* rv350 */
- 0x00780000, /* rv380 */
- 0x01080000, /* r420 */
- 0x01080000, /* rv410 */ /* FIXME: just values from r420 used... */
- 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */
-};
-
-
-static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output);
-static void RADEONUpdatePanelSize(xf86OutputPtr output);
-static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
-#define AVIVO_I2C_DISABLE 0
-#define AVIVO_I2C_ENABLE 1
-static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state);
-
-extern void atombios_output_mode_set(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode);
-extern void legacy_output_mode_set(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode);
-extern void atombios_output_dpms(xf86OutputPtr output, int mode);
-extern void legacy_output_dpms(xf86OutputPtr output, int mode);
-extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
-extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
-extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
-extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
-static void
-radeon_bios_output_dpms(xf86OutputPtr output, int mode);
-static void
-radeon_bios_output_crtc(xf86OutputPtr output);
-static void
-radeon_bios_output_lock(xf86OutputPtr output, Bool lock);
-
-void RADEONPrintPortMap(ScrnInfoPtr pScrn)
-{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- RADEONOutputPrivatePtr radeon_output;
- xf86OutputPtr output;
- int o;
-
- for (o = 0; o < xf86_config->num_output; o++) {
- output = xf86_config->output[o];
- radeon_output = output->driver_private;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- 0x%x\n",
- o,
- MonTypeName[radeon_output->MonType+1],
- ConnectorTypeName[radeon_output->ConnectorType],
- DACTypeName[radeon_output->DACType],
- TMDSTypeName[radeon_output->TMDSType],
- (unsigned int)radeon_output->ddc_i2c.mask_clk_reg);
- }
-
-}
-
-static RADEONMonitorType
-avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONMonitorType MonType = MT_NONE;
- xf86MonPtr MonInfo = NULL;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (radeon_output->pI2CBus) {
- AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE);
- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE);
- }
- if (MonInfo) {
- if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
- xf86OutputSetEDID(output, MonInfo);
- if (radeon_output->type == OUTPUT_LVDS)
- MonType = MT_LCD;
- else if (radeon_output->type == OUTPUT_DVI_D)
- MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_HDMI)
- MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
- MonType = MT_DFP;
- else
- MonType = MT_CRT;
- } else MonType = MT_NONE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Output: %s, Detected Monitor Type: %d\n", output->name, MonType);
-
- return MonType;
-}
-
-static RADEONMonitorType
-RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 DDCReg;
- RADEONMonitorType MonType = MT_NONE;
- xf86MonPtr MonInfo = NULL;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int i, j;
-
- if (!radeon_output->ddc_i2c.valid)
- return MT_NONE;
-
- DDCReg = radeon_output->ddc_i2c.mask_clk_reg;
-
- /* Read and output monitor info using DDC2 over I2C bus */
- if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) {
- OUTREG(DDCReg, INREG(DDCReg) &
- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
-
- /* For some old monitors (like Compaq Presario FP500), we need
- * following process to initialize/stop DDC
- */
- OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1));
- for (j = 0; j < 3; j++) {
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
- usleep(13000);
-
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 10; i++) {
- usleep(15000);
- if (INREG(DDCReg) & RADEON_GPIO_Y_1)
- break;
- }
- if (i == 10) continue;
-
- usleep(15000);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
- usleep(15000);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
- usleep(15000);
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
- usleep(15000);
-
- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
- usleep(15000);
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 5; i++) {
- usleep(15000);
- if (INREG(DDCReg) & RADEON_GPIO_Y_1)
- break;
- }
- usleep(15000);
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
- usleep(15000);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
- usleep(15000);
- if (MonInfo) break;
- }
- } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) {
- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus);
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n");
- MonType = MT_NONE;
- }
-
- OUTREG(DDCReg, INREG(DDCReg) &
- ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1));
-
- if (MonInfo) {
- if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
- xf86OutputSetEDID(output, MonInfo);
- if (radeon_output->type == OUTPUT_LVDS)
- MonType = MT_LCD;
- else if (radeon_output->type == OUTPUT_DVI_D)
- MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_HDMI)
- MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
- MonType = MT_DFP;
- else
- MonType = MT_CRT;
- } else MonType = MT_NONE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Output: %s, Detected Monitor Type: %d\n", output->name, MonType);
-
- return MonType;
-}
-
-
-/* Primary Head (DVI or Laptop Int. panel)*/
-/* A ddc capable display connected on DVI port */
-/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
-void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (radeon_output->MonType == MT_UNKNOWN) {
- if (IS_AVIVO_VARIANT) {
- radeon_output->MonType = avivo_display_ddc_connected(pScrn, output);
- if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS)
- radeon_output->MonType = MT_LCD;
- else
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- }
- } else {
- radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
- if (!radeon_output->MonType) {
- if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI)
- radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output);
- if (!radeon_output->MonType) {
- if (info->IsAtomBios)
- radeon_output->MonType = atombios_dac_detect(pScrn, output);
- else
- radeon_output->MonType = legacy_dac_detect(pScrn, output);
- }
- }
- }
- }
-
- /* update panel info for RMX */
- if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP)
- RADEONUpdatePanelSize(output);
-
- /* panel is probably busted or not connected */
- if ((radeon_output->MonType == MT_LCD) &&
- ((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0)))
- radeon_output->MonType = MT_NONE;
-
- if (output->MonInfo) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n",
- output->name);
- xf86PrintEDID( output->MonInfo );
- }
-}
-
-#ifndef __powerpc__
-
-static RADEONMonitorType
-RADEONDetectLidStatus(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONMonitorType MonType = MT_NONE;
-#ifdef __linux__
- char lidline[50]; /* 50 should be sufficient for our purposes */
- FILE *f = fopen ("/proc/acpi/button/lid/LID/state", "r");
-
- if (f != NULL) {
- while (fgets(lidline, sizeof lidline, f)) {
- if (!strncmp(lidline, "state:", strlen ("state:"))) {
- if (strstr(lidline, "open")) {
- fclose(f);
- ErrorF("proc lid open\n");
- return MT_LCD;
- }
- else if (strstr(lidline, "closed")) {
- fclose(f);
- ErrorF("proc lid closed\n");
- return MT_NONE;
- }
- }
- }
- fclose(f);
- }
-#endif
-
- if (!info->IsAtomBios) {
- unsigned char *RADEONMMIO = info->MMIO;
-
- /* see if the lid is closed -- only works at boot */
- if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10)
- MonType = MT_NONE;
- else
- MonType = MT_LCD;
- } else
- MonType = MT_LCD;
-
- return MonType;
-}
-
-#endif /* __powerpc__ */
-
-static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONMonitorType MonType = MT_NONE;
-
- if (radeon_output->type == OUTPUT_LVDS) {
- if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS, TRUE))
- MonType = MT_LCD;
- else
-#if defined(__powerpc__)
- MonType = MT_LCD;
-#else
- MonType = RADEONDetectLidStatus(pScrn);
-#endif
- } /*else if (radeon_output->type == OUTPUT_DVI) {
- if (radeon_output->TMDSType == TMDS_INT) {
- if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
- MonType = MT_DFP;
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- if (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
- MonType = MT_DFP;
- }
- }*/
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Detected non-DDC Monitor Type: %d\n", MonType);
-
- return MonType;
-
-}
-
-static void
-radeon_dpms(xf86OutputPtr output, int mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
-
- if (IS_AVIVO_VARIANT) {
- atombios_output_dpms(output, mode);
- } else {
- legacy_output_dpms(output, mode);
- }
- radeon_bios_output_dpms(output, mode);
-
-}
-
-static void
-radeon_save(xf86OutputPtr output)
-{
-
-}
-
-static void
-radeon_restore(xf86OutputPtr restore)
-{
-
-}
-
-static int
-radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-
- /*
- * RN50 has effective maximum mode bandwidth of about 300MiB/s.
- * XXX should really do this for all chips by properly computing
- * memory bandwidth and an overhead factor.
- */
- if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
- if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300)
- return MODE_BANDWIDTH;
- }
-
- if (OUTPUT_IS_TV) {
- /* FIXME: Update when more modes are added */
- if (IS_AVIVO_VARIANT) {
- int max_v;
-
- /* tv-scaler can scale horizontal width
- * but frame ends must match tv_pll
- * for now cap v size
- */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- max_v = 480;
- else
- max_v = 600;
-
- if (pMode->VDisplay == max_v)
- return MODE_OK;
- else
- return MODE_CLOCK_RANGE;
- } else {
- if (pMode->HDisplay == 800 && pMode->VDisplay == 600)
- return MODE_OK;
- else
- return MODE_CLOCK_RANGE;
- }
- }
-
- if (radeon_output->type == OUTPUT_LVDS) {
- if (radeon_output->rmx_type == RMX_OFF) {
- if (pMode->HDisplay != radeon_output->PanelXRes ||
- pMode->VDisplay != radeon_output->PanelYRes)
- return MODE_PANEL;
- }
- if (pMode->HDisplay > radeon_output->PanelXRes ||
- pMode->VDisplay > radeon_output->PanelYRes)
- return MODE_PANEL;
- }
-
- return MODE_OK;
-}
-
-static Bool
-radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- radeon_output->Flags &= ~RADEON_USE_RMX;
-
- /* decide if we are using RMX */
- if ((radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP)
- && radeon_output->rmx_type != RMX_OFF) {
- xf86CrtcPtr crtc = output->crtc;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- if (IS_AVIVO_VARIANT || radeon_crtc->crtc_id == 0) {
- if (mode->HDisplay < radeon_output->PanelXRes ||
- mode->VDisplay < radeon_output->PanelYRes) {
- radeon_output->Flags |= RADEON_USE_RMX;
- if (IS_AVIVO_VARIANT) {
- /* set to the panel's native mode */
- adjusted_mode->HDisplay = radeon_output->PanelXRes;
- adjusted_mode->HDisplay = radeon_output->PanelYRes;
- adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank;
- adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus;
- adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + radeon_output->HSyncWidth;
- adjusted_mode->VTotal = radeon_output->PanelYRes + radeon_output->VBlank;
- adjusted_mode->VSyncStart = radeon_output->PanelYRes + radeon_output->VOverPlus;
- adjusted_mode->VSyncEnd = adjusted_mode->VSyncStart + radeon_output->VSyncWidth;
- /* update crtc values */
- xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
- /* adjust crtc values */
- adjusted_mode->CrtcHDisplay = radeon_output->PanelXRes;
- adjusted_mode->CrtcVDisplay = radeon_output->PanelYRes;
- adjusted_mode->CrtcHTotal = adjusted_mode->CrtcHDisplay + radeon_output->HBlank;
- adjusted_mode->CrtcHSyncStart = adjusted_mode->CrtcHDisplay + radeon_output->HOverPlus;
- adjusted_mode->CrtcHSyncEnd = adjusted_mode->CrtcHSyncStart + radeon_output->HSyncWidth;
- adjusted_mode->CrtcVTotal = adjusted_mode->CrtcVDisplay + radeon_output->VBlank;
- adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + radeon_output->VOverPlus;
- adjusted_mode->CrtcVSyncEnd = adjusted_mode->CrtcVSyncStart + radeon_output->VSyncWidth;
- } else {
- /* set to the panel's native mode */
- adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank;
- adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus;
- adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + radeon_output->HSyncWidth;
- adjusted_mode->VTotal = radeon_output->PanelYRes + radeon_output->VBlank;
- adjusted_mode->VSyncStart = radeon_output->PanelYRes + radeon_output->VOverPlus;
- adjusted_mode->VSyncEnd = adjusted_mode->VSyncStart + radeon_output->VSyncWidth;
- adjusted_mode->Clock = radeon_output->DotClock;
- /* update crtc values */
- xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
- /* adjust crtc values */
- adjusted_mode->CrtcHTotal = adjusted_mode->CrtcHDisplay + radeon_output->HBlank;
- adjusted_mode->CrtcHSyncStart = adjusted_mode->CrtcHDisplay + radeon_output->HOverPlus;
- adjusted_mode->CrtcHSyncEnd = adjusted_mode->CrtcHSyncStart + radeon_output->HSyncWidth;
- adjusted_mode->CrtcVTotal = adjusted_mode->CrtcVDisplay + radeon_output->VBlank;
- adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + radeon_output->VOverPlus;
- adjusted_mode->CrtcVSyncEnd = adjusted_mode->CrtcVSyncStart + radeon_output->VSyncWidth;
- }
- adjusted_mode->Clock = radeon_output->DotClock;
- adjusted_mode->Flags = radeon_output->Flags;
- }
- }
- }
-
- return TRUE;
-}
-
-static void
-radeon_mode_prepare(xf86OutputPtr output)
-{
- radeon_bios_output_lock(output, TRUE);
- radeon_dpms(output, DPMSModeOff);
-}
-
-static void
-radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
- DisplayModePtr adjusted_mode)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
-
- if (IS_AVIVO_VARIANT)
- atombios_output_mode_set(output, mode, adjusted_mode);
- else
- legacy_output_mode_set(output, mode, adjusted_mode);
- radeon_bios_output_crtc(output);
-
-}
-
-static void
-radeon_mode_commit(xf86OutputPtr output)
-{
- radeon_dpms(output, DPMSModeOn);
- radeon_bios_output_lock(output, FALSE);
-}
-
-static void
-radeon_bios_output_lock(xf86OutputPtr output, Bool lock)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = info->ModeReg;
-
- if (info->IsAtomBios) {
- if (lock) {
- save->bios_6_scratch |= (ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE);
- } else {
- save->bios_6_scratch &= ~(ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE);
- }
- } else {
- if (lock) {
- save->bios_6_scratch |= (RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE);
- } else {
- save->bios_6_scratch &= ~(RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE);
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch);
- else
- OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
-}
-
-static void
-radeon_bios_output_dpms(xf86OutputPtr output, int mode)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = info->ModeReg;
-
- if (info->IsAtomBios) {
- if (mode == DPMSModeOn) {
- if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_CV) {
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_CV_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
- } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
- } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
- } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
- save->bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
- }
- }
- } else {
- if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_CV) {
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
- } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
- } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
- } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) {
- save->bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
- save->bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
- }
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch);
- OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch);
- } else {
- OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch);
- OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch);
- }
- } else {
- if (mode == DPMSModeOn) {
- save->bios_6_scratch &= ~(RADEON_DPMS_MASK | RADEON_SCREEN_BLANKING);
- save->bios_6_scratch |= RADEON_DPMS_ON;
- if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- save->bios_5_scratch |= RADEON_TV1_ON;
- save->bios_6_scratch |= RADEON_TV_DPMS_ON;
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY)
- save->bios_5_scratch |= RADEON_CRT1_ON;
- else
- save->bios_5_scratch |= RADEON_CRT2_ON;
- save->bios_6_scratch |= RADEON_CRT_DPMS_ON;
- } else if (radeon_output->MonType == MT_LCD) {
- save->bios_5_scratch |= RADEON_LCD1_ON;
- save->bios_6_scratch |= RADEON_LCD_DPMS_ON;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT)
- save->bios_5_scratch |= RADEON_DFP1_ON;
- else
- save->bios_5_scratch |= RADEON_DFP2_ON;
- save->bios_6_scratch |= RADEON_DFP_DPMS_ON;
- }
- } else {
- save->bios_6_scratch &= ~RADEON_DPMS_MASK;
- save->bios_6_scratch |= (RADEON_DPMS_OFF | RADEON_SCREEN_BLANKING);
- if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- save->bios_5_scratch &= ~RADEON_TV1_ON;
- save->bios_6_scratch &= ~RADEON_TV_DPMS_ON;
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY)
- save->bios_5_scratch &= ~RADEON_CRT1_ON;
- else
- save->bios_5_scratch &= ~RADEON_CRT2_ON;
- save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
- } else if (radeon_output->MonType == MT_LCD) {
- save->bios_5_scratch &= ~RADEON_LCD1_ON;
- save->bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT)
- save->bios_5_scratch &= ~RADEON_DFP1_ON;
- else
- save->bios_5_scratch &= ~RADEON_DFP2_ON;
- save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
- }
- }
- OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
- OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
- }
-}
-
-static void
-radeon_bios_output_crtc(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = info->ModeReg;
- xf86CrtcPtr crtc = output->crtc;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- if (info->IsAtomBios) {
- if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
- save->bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 18);
- }
- } else if (radeon_output->MonType == MT_CV) {
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 24);
- }
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 16);
- } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 20);
- }
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 17);
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 19);
- } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 23);
- } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) {
- save->bios_2_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
- save->bios_3_scratch |= (radeon_crtc->crtc_id << 25);
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch);
- else
- OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch);
- } else {
- if (radeon_output->MonType == MT_STV ||
- radeon_output->MonType == MT_CTV) {
- save->bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
- save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_TV1_CRTC_SHIFT);
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- save->bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
- save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT1_CRTC_SHIFT);
- } else {
- save->bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
- save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT2_CRTC_SHIFT);
- }
- } else if (radeon_output->MonType == MT_LCD) {
- save->bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
- save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_LCD1_CRTC_SHIFT);
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- save->bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
- save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP1_CRTC_SHIFT);
- } else {
- save->bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
- save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP2_CRTC_SHIFT);
- }
- }
- OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
- }
-}
-
-static void
-radeon_bios_output_connected(xf86OutputPtr output, Bool connected)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = info->ModeReg;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- return;
-
- if (info->IsAtomBios) {
- if (connected) {
- if (radeon_output->MonType == MT_STV) {
- /* taken care of by load detection */
- } else if (radeon_output->MonType == MT_CTV) {
- /* taken care of by load detection */
- } else if (radeon_output->MonType == MT_CV) {
- /* taken care of by load detection */
- } else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
- save->bios_0_scratch |= ATOM_S0_CRT1_COLOR;
- else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
- save->bios_0_scratch |= ATOM_S0_CRT2_COLOR;
- } else if (radeon_output->MonType == MT_LCD) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
- save->bios_0_scratch |= ATOM_S0_LCD1;
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
- save->bios_0_scratch |= ATOM_S0_DFP1;
- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
- save->bios_0_scratch |= ATOM_S0_DFP2;
- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
- save->bios_0_scratch |= ATOM_S0_DFP3;
- }
- } else {
- if (OUTPUT_IS_TV) {
- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_TV1_MASK;
- }
- if (radeon_output->type == OUTPUT_CV) {
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_CV_MASK;
- }
- if (radeon_output->DACType) {
- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
- else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
- }
- if (radeon_output->type == OUTPUT_LVDS) {
- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_LCD1;
- }
- if (radeon_output->TMDSType) {
- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_DFP1;
- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_DFP2;
- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
- save->bios_0_scratch &= ~ATOM_S0_DFP3;
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- OUTREG(R600_BIOS_0_SCRATCH, save->bios_0_scratch);
- else
- OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch);
- } else {
- if (connected) {
- if (radeon_output->MonType == MT_STV)
- save->bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
- else if (radeon_output->MonType == MT_CTV)
- save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP;
- else if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY)
- save->bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
- else
- save->bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
- } else if (radeon_output->MonType == MT_LCD)
- save->bios_4_scratch |= RADEON_LCD1_ATTACHED;
- else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT)
- save->bios_4_scratch |= RADEON_DFP1_ATTACHED;
- else
- save->bios_4_scratch |= RADEON_DFP2_ATTACHED;
- }
- } else {
- if (OUTPUT_IS_TV)
- save->bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
- else if (radeon_output->DACType == DAC_TVDAC)
- save->bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
- if (radeon_output->DACType == DAC_PRIMARY)
- save->bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
- if (radeon_output->type == OUTPUT_LVDS)
- save->bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
- if (radeon_output->TMDSType == TMDS_INT)
- save->bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
- if (radeon_output->TMDSType == TMDS_EXT)
- save->bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
- }
- OUTREG(RADEON_BIOS_4_SCRATCH, save->bios_4_scratch);
- }
-
-}
-
-static xf86OutputStatus
-radeon_detect(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- Bool connected = TRUE;
-
- radeon_output->MonType = MT_UNKNOWN;
- radeon_bios_output_connected(output, FALSE);
- RADEONConnectorFindMonitor(pScrn, output);
-
- /* nothing connected, light up some defaults so the server comes up */
- if (radeon_output->MonType == MT_NONE &&
- info->first_load_no_devices) {
- if (info->IsMobility) {
- if (radeon_output->type == OUTPUT_LVDS) {
- radeon_output->MonType = MT_LCD;
- info->first_load_no_devices = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Using LVDS default\n");
- }
- } else {
- if (radeon_output->type == OUTPUT_VGA ||
- radeon_output->type == OUTPUT_DVI_I) {
- radeon_output->MonType = MT_CRT;
- info->first_load_no_devices = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Using VGA default\n");
- } else if (radeon_output->type == OUTPUT_DVI_D) {
- radeon_output->MonType = MT_DFP;
- info->first_load_no_devices = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Using DVI default\n");
- }
- }
- }
-
- radeon_bios_output_connected(output, TRUE);
-
- /* set montype so users can force outputs on even if detection fails */
- if (radeon_output->MonType == MT_NONE) {
- connected = FALSE;
- if (radeon_output->type == OUTPUT_LVDS)
- radeon_output->MonType = MT_LCD;
- else if (radeon_output->type == OUTPUT_VGA)
- radeon_output->MonType = MT_CRT;
- else if (radeon_output->type == OUTPUT_STV)
- radeon_output->MonType = MT_STV;
- else if (radeon_output->type == OUTPUT_CTV)
- radeon_output->MonType = MT_CTV;
- else if (radeon_output->type == OUTPUT_CV)
- radeon_output->MonType = MT_CV;
- else if (radeon_output->type == OUTPUT_DVI_D)
- radeon_output->MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_HDMI)
- radeon_output->MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_DVI_A)
- radeon_output->MonType = MT_CRT;
- else if (radeon_output->type == OUTPUT_DVI_I) {
- if (radeon_output->DVIType == DVI_ANALOG)
- radeon_output->MonType = MT_CRT;
- else if (radeon_output->DVIType == DVI_DIGITAL)
- radeon_output->MonType = MT_DFP;
- }
- }
-
- if (radeon_output->MonType == MT_UNKNOWN) {
- output->subpixel_order = SubPixelUnknown;
- return XF86OutputStatusUnknown;
- } else {
-
- switch(radeon_output->MonType) {
- case MT_LCD:
- case MT_DFP:
- output->subpixel_order = SubPixelHorizontalRGB;
- break;
- default:
- output->subpixel_order = SubPixelNone;
- break;
- }
-
-#if 0
- if (!connected) {
- /* default to unknown for flaky chips/connectors
- * so we can get something on the screen
- */
- if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) &&
- (radeon_output->DACType == DAC_TVDAC) &&
- (info->ChipFamily == CHIP_FAMILY_RS400)) {
- radeon_output->MonType = MT_CRT;
- return XF86OutputStatusUnknown;
- } else if ((info->ChipFamily == CHIP_FAMILY_RS400) &&
- radeon_output->type == OUTPUT_DVI_D) {
- radeon_output->MonType = MT_DFP; /* MT_LCD ??? */
- return XF86OutputStatusUnknown;
- }
- }
-#endif
-
- if (connected)
- return XF86OutputStatusConnected;
- else
- return XF86OutputStatusDisconnected;
- }
-
-}
-
-static DisplayModePtr
-radeon_get_modes(xf86OutputPtr output)
-{
- DisplayModePtr modes;
- modes = RADEONProbeOutputModes(output);
- return modes;
-}
-
-static void
-radeon_destroy (xf86OutputPtr output)
-{
- if (output->driver_private)
- xfree(output->driver_private);
-}
-
-static void
-radeon_set_backlight_level(xf86OutputPtr output, int level)
-{
-#if 0
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char * RADEONMMIO = info->MMIO;
- CARD32 lvds_gen_cntl;
-
- lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL);
- lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
- lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_LEVEL_MASK;
- lvds_gen_cntl |= (level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & RADEON_LVDS_BL_MOD_LEVEL_MASK;
- //usleep (radeon_output->PanelPwrDly * 1000);
- OUTREG(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
- lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
- //usleep (radeon_output->PanelPwrDly * 1000);
- OUTREG(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
-#endif
-}
-
-static Atom backlight_atom;
-static Atom tmds_pll_atom;
-static Atom rmx_atom;
-static Atom monitor_type_atom;
-static Atom load_detection_atom;
-static Atom tv_hsize_atom;
-static Atom tv_hpos_atom;
-static Atom tv_vpos_atom;
-static Atom tv_std_atom;
-#define RADEON_MAX_BACKLIGHT_LEVEL 255
-
-static void
-radeon_create_resources(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- INT32 range[2];
- int data, err;
- const char *s;
-
- /* backlight control */
- if (radeon_output->type == OUTPUT_LVDS) {
- backlight_atom = MAKE_ATOM("backlight");
-
- range[0] = 0;
- range[1] = RADEON_MAX_BACKLIGHT_LEVEL;
- err = RRConfigureOutputProperty(output->randr_output, backlight_atom,
- FALSE, TRUE, FALSE, 2, range);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- /* Set the current value of the backlight property */
- //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT;
- data = RADEON_MAX_BACKLIGHT_LEVEL;
- err = RRChangeOutputProperty(output->randr_output, backlight_atom,
- XA_INTEGER, 32, PropModeReplace, 1, &data,
- FALSE, TRUE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
- }
-
- if (radeon_output->DACType == DAC_PRIMARY ||
- radeon_output->DACType == DAC_TVDAC) {
- load_detection_atom = MAKE_ATOM("load_detection");
-
- range[0] = 0; /* off */
- range[1] = 1; /* on */
- err = RRConfigureOutputProperty(output->randr_output, load_detection_atom,
- FALSE, TRUE, FALSE, 2, range);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
-
- if (radeon_output->load_detection)
- data = 1; /* user forces on tv dac load detection */
- else
- data = 0; /* shared tvdac between vga/dvi/tv */
-
- err = RRChangeOutputProperty(output->randr_output, load_detection_atom,
- XA_INTEGER, 32, PropModeReplace, 1, &data,
- FALSE, TRUE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
- }
-
- if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) {
- tmds_pll_atom = MAKE_ATOM("tmds_pll");
-
- err = RRConfigureOutputProperty(output->randr_output, tmds_pll_atom,
- FALSE, FALSE, FALSE, 0, NULL);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- /* Set the current value of the property */
-#if defined(__powerpc__)
- s = "driver";
-#else
- s = "bios";
-#endif
- if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TMDS_PLL, FALSE)) {
- s = "driver";
- }
-
- err = RRChangeOutputProperty(output->randr_output, tmds_pll_atom,
- XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
- FALSE, FALSE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
-
- }
-
- /* RMX control - fullscreen, centered, keep ratio, off */
- /* actually more of a crtc property as only crtc1 has rmx */
- if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI) {
- rmx_atom = MAKE_ATOM("scaler");
-
- err = RRConfigureOutputProperty(output->randr_output, rmx_atom,
- FALSE, FALSE, FALSE, 0, NULL);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- /* Set the current value of the property */
- if (radeon_output->type == OUTPUT_LVDS)
- s = "full";
- else
- s = "off";
- err = RRChangeOutputProperty(output->randr_output, rmx_atom,
- XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
- FALSE, FALSE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
- }
-
- /* force auto/analog/digital for DVI-I ports */
- if (radeon_output->type == OUTPUT_DVI_I) {
- monitor_type_atom = MAKE_ATOM("dvi_monitor_type");
-
- err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom,
- FALSE, FALSE, FALSE, 0, NULL);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- /* Set the current value of the backlight property */
- s = "auto";
- err = RRChangeOutputProperty(output->randr_output, monitor_type_atom,
- XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
- FALSE, FALSE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
- }
-
- if (OUTPUT_IS_TV) {
- if (!IS_AVIVO_VARIANT) {
- tv_hsize_atom = MAKE_ATOM("tv_horizontal_size");
-
- range[0] = -MAX_H_SIZE;
- range[1] = MAX_H_SIZE;
- err = RRConfigureOutputProperty(output->randr_output, tv_hsize_atom,
- FALSE, TRUE, FALSE, 2, range);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- data = 0;
- err = RRChangeOutputProperty(output->randr_output, tv_hsize_atom,
- XA_INTEGER, 32, PropModeReplace, 1, &data,
- FALSE, TRUE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
-
- tv_hpos_atom = MAKE_ATOM("tv_horizontal_position");
-
- range[0] = -MAX_H_POSITION;
- range[1] = MAX_H_POSITION;
- err = RRConfigureOutputProperty(output->randr_output, tv_hpos_atom,
- FALSE, TRUE, FALSE, 2, range);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- data = 0;
- err = RRChangeOutputProperty(output->randr_output, tv_hpos_atom,
- XA_INTEGER, 32, PropModeReplace, 1, &data,
- FALSE, TRUE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
-
- tv_vpos_atom = MAKE_ATOM("tv_vertical_position");
-
- range[0] = -MAX_V_POSITION;
- range[1] = MAX_V_POSITION;
- err = RRConfigureOutputProperty(output->randr_output, tv_vpos_atom,
- FALSE, TRUE, FALSE, 2, range);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
- data = 0;
- err = RRChangeOutputProperty(output->randr_output, tv_vpos_atom,
- XA_INTEGER, 32, PropModeReplace, 1, &data,
- FALSE, TRUE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
- }
-
- tv_std_atom = MAKE_ATOM("tv_standard");
-
- err = RRConfigureOutputProperty(output->randr_output, tv_std_atom,
- FALSE, FALSE, FALSE, 0, NULL);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error, %d\n", err);
- }
-
- /* Set the current value of the property */
- switch (radeon_output->tvStd) {
- case TV_STD_PAL:
- s = "pal";
- break;
- case TV_STD_PAL_M:
- s = "pal-m";
- break;
- case TV_STD_PAL_60:
- s = "pal-60";
- break;
- case TV_STD_NTSC_J:
- s = "ntsc-j";
- break;
- case TV_STD_SCART_PAL:
- s = "scart-pal";
- break;
- case TV_STD_NTSC:
- default:
- s = "ntsc";
- break;
- }
-
- err = RRChangeOutputProperty(output->randr_output, tv_std_atom,
- XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
- FALSE, FALSE);
- if (err != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error, %d\n", err);
- }
- }
-}
-
-static Bool
-radeon_set_property(xf86OutputPtr output, Atom property,
- RRPropertyValuePtr value)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- INT32 val;
-
-
- if (property == backlight_atom) {
- if (value->type != XA_INTEGER ||
- value->format != 32 ||
- value->size != 1) {
- return FALSE;
- }
-
- val = *(INT32 *)value->data;
- if (val < 0 || val > RADEON_MAX_BACKLIGHT_LEVEL)
- return FALSE;
-
-#if defined(__powerpc__)
- val = RADEON_MAX_BACKLIGHT_LEVEL - val;
-#endif
-
- radeon_set_backlight_level(output, val);
-
- } else if (property == load_detection_atom) {
- if (value->type != XA_INTEGER ||
- value->format != 32 ||
- value->size != 1) {
- return FALSE;
- }
-
- val = *(INT32 *)value->data;
- if (val < 0 || val > 1)
- return FALSE;
-
- radeon_output->load_detection = val;
-
- } else if (property == rmx_atom) {
- const char *s;
- if (value->type != XA_STRING || value->format != 8)
- return FALSE;
- s = (char*)value->data;
- if (value->size == strlen("full") && !strncmp("full", s, strlen("full"))) {
- radeon_output->rmx_type = RMX_FULL;
- return TRUE;
- } else if (value->size == strlen("center") && !strncmp("center", s, strlen("center"))) {
- radeon_output->rmx_type = RMX_CENTER;
- return TRUE;
- } else if (value->size == strlen("off") && !strncmp("off", s, strlen("off"))) {
- radeon_output->rmx_type = RMX_OFF;
- return TRUE;
- }
- return FALSE;
- } else if (property == tmds_pll_atom) {
- const char *s;
- if (value->type != XA_STRING || value->format != 8)
- return FALSE;
- s = (char*)value->data;
- if (value->size == strlen("bios") && !strncmp("bios", s, strlen("bios"))) {
- if (!RADEONGetTMDSInfoFromBIOS(output))
- RADEONGetTMDSInfoFromTable(output);
- return TRUE;
- } else if (value->size == strlen("driver") && !strncmp("driver", s, strlen("driver"))) {
- RADEONGetTMDSInfoFromTable(output);
- return TRUE;
- }
- return FALSE;
- } else if (property == monitor_type_atom) {
- const char *s;
- if (value->type != XA_STRING || value->format != 8)
- return FALSE;
- s = (char*)value->data;
- if (value->size == strlen("auto") && !strncmp("auto", s, strlen("auto"))) {
- radeon_output->DVIType = DVI_AUTO;
- return TRUE;
- } else if (value->size == strlen("analog") && !strncmp("analog", s, strlen("analog"))) {
- radeon_output->DVIType = DVI_ANALOG;
- return TRUE;
- } else if (value->size == strlen("digital") && !strncmp("digital", s, strlen("digital"))) {
- radeon_output->DVIType = DVI_DIGITAL;
- return TRUE;
- }
- return FALSE;
- } else if (property == tv_hsize_atom) {
- if (value->type != XA_INTEGER ||
- value->format != 32 ||
- value->size != 1) {
- return FALSE;
- }
-
- val = *(INT32 *)value->data;
- if (val < -MAX_H_SIZE || val > MAX_H_SIZE)
- return FALSE;
-
- radeon_output->hSize = val;
- if (radeon_output->tv_on && !IS_AVIVO_VARIANT)
- RADEONUpdateHVPosition(output, &output->crtc->mode);
- return TRUE;
- } else if (property == tv_hpos_atom) {
- if (value->type != XA_INTEGER ||
- value->format != 32 ||
- value->size != 1) {
- return FALSE;
- }
-
- val = *(INT32 *)value->data;
- if (val < -MAX_H_POSITION || val > MAX_H_POSITION)
- return FALSE;
-
- radeon_output->hPos = val;
- if (radeon_output->tv_on && !IS_AVIVO_VARIANT)
- RADEONUpdateHVPosition(output, &output->crtc->mode);
- return TRUE;
- } else if (property == tv_vpos_atom) {
- if (value->type != XA_INTEGER ||
- value->format != 32 ||
- value->size != 1) {
- return FALSE;
- }
-
- val = *(INT32 *)value->data;
- if (val < -MAX_H_POSITION || val > MAX_H_POSITION)
- return FALSE;
-
- radeon_output->vPos = val;
- if (radeon_output->tv_on && !IS_AVIVO_VARIANT)
- RADEONUpdateHVPosition(output, &output->crtc->mode);
- return TRUE;
- } else if (property == tv_std_atom) {
- const char *s;
- if (value->type != XA_STRING || value->format != 8)
- return FALSE;
- s = (char*)value->data;
- if (value->size == strlen("ntsc") && !strncmp("ntsc", s, strlen("ntsc"))) {
- radeon_output->tvStd = TV_STD_NTSC;
- return TRUE;
- } else if (value->size == strlen("pal") && !strncmp("pal", s, strlen("pal"))) {
- radeon_output->tvStd = TV_STD_PAL;
- return TRUE;
- } else if (value->size == strlen("pal-m") && !strncmp("pal-m", s, strlen("pal-m"))) {
- radeon_output->tvStd = TV_STD_PAL_M;
- return TRUE;
- } else if (value->size == strlen("pal-60") && !strncmp("pal-60", s, strlen("pal-60"))) {
- radeon_output->tvStd = TV_STD_PAL_60;
- return TRUE;
- } else if (value->size == strlen("ntsc-j") && !strncmp("ntsc-j", s, strlen("ntsc-j"))) {
- radeon_output->tvStd = TV_STD_NTSC_J;
- return TRUE;
- } else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) {
- radeon_output->tvStd = TV_STD_SCART_PAL;
- return TRUE;
- } else if (value->size == strlen("pal-cn") && !strncmp("pal-cn", s, strlen("pal-cn"))) {
- radeon_output->tvStd = TV_STD_PAL_CN;
- return TRUE;
- } else if (value->size == strlen("secam") && !strncmp("secam", s, strlen("secam"))) {
- radeon_output->tvStd = TV_STD_SECAM;
- return TRUE;
- }
- return FALSE;
- }
-
- return TRUE;
-}
-
-static const xf86OutputFuncsRec radeon_output_funcs = {
- .create_resources = radeon_create_resources,
- .dpms = radeon_dpms,
- .save = radeon_save,
- .restore = radeon_restore,
- .mode_valid = radeon_mode_valid,
- .mode_fixup = radeon_mode_fixup,
- .prepare = radeon_mode_prepare,
- .mode_set = radeon_mode_set,
- .commit = radeon_mode_commit,
- .detect = radeon_detect,
- .get_modes = radeon_get_modes,
- .set_property = radeon_set_property,
- .destroy = radeon_destroy
-};
-
-void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output)
-{
- RADEONOutputType output = OUTPUT_NONE;
-
- switch(radeon_output->ConnectorType) {
- case CONNECTOR_VGA:
- output = OUTPUT_VGA; break;
- case CONNECTOR_DVI_I:
- output = OUTPUT_DVI_I; break;
- case CONNECTOR_DVI_D:
- output = OUTPUT_DVI_D; break;
- case CONNECTOR_DVI_A:
- output = OUTPUT_DVI_A; break;
- case CONNECTOR_DIN:
- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT)
- output = OUTPUT_CV;
- else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT)
- output = OUTPUT_STV;
- break;
- case CONNECTOR_STV:
- output = OUTPUT_STV; break;
- case CONNECTOR_CTV:
- output = OUTPUT_CTV; break;
- case CONNECTOR_LVDS:
- output = OUTPUT_LVDS; break;
- case CONNECTOR_HDMI_TYPE_A:
- case CONNECTOR_HDMI_TYPE_B:
- output = OUTPUT_HDMI; break;
- case CONNECTOR_DIGITAL:
- case CONNECTOR_NONE:
- case CONNECTOR_UNSUPPORTED:
- default:
- output = OUTPUT_NONE; break;
- }
- radeon_output->type = output;
-}
-
-#if 0
-static
-Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(AVIVO_I2C_STOP, 1);
- INREG(AVIVO_I2C_STOP);
- OUTREG(AVIVO_I2C_STOP, 0x0);
- return TRUE;
-}
-#endif
-
-static
-Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONI2CBusPtr pRADEONI2CBus = radeon_output->pI2CBus->DriverPrivate.ptr;
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 temp;
-
- temp = INREG(pRADEONI2CBus->mask_clk_reg);
- if (lock_state == AVIVO_I2C_ENABLE)
- temp |= (pRADEONI2CBus->put_clk_mask);
- else
- temp &= ~(pRADEONI2CBus->put_clk_mask);
- OUTREG(pRADEONI2CBus->mask_clk_reg, temp);
- temp = INREG(pRADEONI2CBus->mask_clk_reg);
-
- temp = INREG(pRADEONI2CBus->mask_data_reg);
- if (lock_state == AVIVO_I2C_ENABLE)
- temp |= (pRADEONI2CBus->put_data_mask);
- else
- temp &= ~(pRADEONI2CBus->put_data_mask);
- OUTREG(pRADEONI2CBus->mask_data_reg, temp);
- temp = INREG(pRADEONI2CBus->mask_data_reg);
-
- return TRUE;
-}
-
-static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned long val;
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr;
-
- /* Get the result */
- val = INREG(pRADEONI2CBus->get_clk_reg);
- *Clock = (val & pRADEONI2CBus->get_clk_mask) != 0;
- val = INREG(pRADEONI2CBus->get_data_reg);
- *data = (val & pRADEONI2CBus->get_data_mask) != 0;
-
-}
-
-static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned long val;
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr;
-
- val = INREG(pRADEONI2CBus->put_clk_reg) & (CARD32)~(pRADEONI2CBus->put_clk_mask);
- val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask);
- OUTREG(pRADEONI2CBus->put_clk_reg, val);
- /* read back to improve reliability on some cards. */
- val = INREG(pRADEONI2CBus->put_clk_reg);
-
- val = INREG(pRADEONI2CBus->put_data_reg) & (CARD32)~(pRADEONI2CBus->put_data_mask);
- val |= (data ? 0:pRADEONI2CBus->put_data_mask);
- OUTREG(pRADEONI2CBus->put_data_reg, val);
- /* read back to improve reliability on some cards. */
- val = INREG(pRADEONI2CBus->put_data_reg);
-
-}
-
-static Bool
-RADEONI2CInit(xf86OutputPtr output, I2CBusPtr *bus_ptr, char *name, Bool dvo)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- I2CBusPtr pI2CBus;
- RADEONI2CBusPtr pRADEONI2CBus;
-
- pI2CBus = xf86CreateI2CBusRec();
- if (!pI2CBus) return FALSE;
-
- pI2CBus->BusName = name;
- pI2CBus->scrnIndex = pScrn->scrnIndex;
- pI2CBus->I2CPutBits = RADEONI2CPutBits;
- pI2CBus->I2CGetBits = RADEONI2CGetBits;
- pI2CBus->AcknTimeout = 5;
-
- if (dvo) {
- pRADEONI2CBus = &(radeon_output->dvo_i2c);
- } else {
- pRADEONI2CBus = &(radeon_output->ddc_i2c);
- }
-
- pI2CBus->DriverPrivate.ptr = (pointer)pRADEONI2CBus;
-
- if (!xf86I2CBusInit(pI2CBus))
- return FALSE;
-
- *bus_ptr = pI2CBus;
- return TRUE;
-}
-
-RADEONI2CBusRec
-legacy_setup_i2c_bus(int ddc_line)
-{
- RADEONI2CBusRec i2c;
-
- i2c.mask_clk_mask = RADEON_GPIO_EN_1 | RADEON_GPIO_Y_1;
- i2c.mask_data_mask = RADEON_GPIO_EN_0 | RADEON_GPIO_Y_0;
- i2c.put_clk_mask = RADEON_GPIO_EN_1;
- i2c.put_data_mask = RADEON_GPIO_EN_0;
- i2c.get_clk_mask = RADEON_GPIO_Y_1;
- i2c.get_data_mask = RADEON_GPIO_Y_0;
- if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
- (ddc_line == RADEON_MDGPIO_EN_REG)) {
- i2c.mask_clk_reg = ddc_line;
- i2c.mask_data_reg = ddc_line;
- i2c.put_clk_reg = ddc_line;
- i2c.put_data_reg = ddc_line;
- i2c.get_clk_reg = ddc_line + 4;
- i2c.get_data_reg = ddc_line + 4;
- } else {
- i2c.mask_clk_reg = ddc_line;
- i2c.mask_data_reg = ddc_line;
- i2c.put_clk_reg = ddc_line;
- i2c.put_data_reg = ddc_line;
- i2c.get_clk_reg = ddc_line;
- i2c.get_data_reg = ddc_line;
- }
-
- if (ddc_line)
- i2c.valid = TRUE;
- else
- i2c.valid = FALSE;
-
- return i2c;
-}
-
-RADEONI2CBusRec
-atom_setup_i2c_bus(int ddc_line)
-{
- RADEONI2CBusRec i2c;
-
- if (ddc_line == AVIVO_GPIO_0) {
- i2c.put_clk_mask = (1 << 19);
- i2c.put_data_mask = (1 << 18);
- i2c.get_clk_mask = (1 << 19);
- i2c.get_data_mask = (1 << 18);
- i2c.mask_clk_mask = (1 << 19);
- i2c.mask_data_mask = (1 << 18);
- } else {
- i2c.put_clk_mask = (1 << 0);
- i2c.put_data_mask = (1 << 8);
- i2c.get_clk_mask = (1 << 0);
- i2c.get_data_mask = (1 << 8);
- i2c.mask_clk_mask = (1 << 0);
- i2c.mask_data_mask = (1 << 8);
- }
- i2c.mask_clk_reg = ddc_line;
- i2c.mask_data_reg = ddc_line;
- i2c.put_clk_reg = ddc_line + 0x8;
- i2c.put_data_reg = ddc_line + 0x8;
- i2c.get_clk_reg = ddc_line + 0xc;
- i2c.get_data_reg = ddc_line + 0xc;
- if (ddc_line)
- i2c.valid = TRUE;
- else
- i2c.valid = FALSE;
-
- return i2c;
-}
-
-static void
-RADEONGetPanelInfoFromReg (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
- CARD32 fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
-
- radeon_output->PanelPwrDly = 200;
- if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) {
- radeon_output->PanelYRes = ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
- RADEON_VERT_PANEL_SHIFT) + 1;
- } else {
- radeon_output->PanelYRes = (INREG(RADEON_CRTC_V_TOTAL_DISP)>>16) + 1;
- }
- if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) {
- radeon_output->PanelXRes = (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
- RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
- } else {
- radeon_output->PanelXRes = ((INREG(RADEON_CRTC_H_TOTAL_DISP)>>16) + 1) * 8;
- }
-
- if ((radeon_output->PanelXRes < 640) || (radeon_output->PanelYRes < 480)) {
- radeon_output->PanelXRes = 640;
- radeon_output->PanelYRes = 480;
- }
-
- // move this to crtc function
- if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) {
- CARD32 ppll_div_sel, ppll_val;
-
- ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
- RADEONPllErrataAfterIndex(info);
- ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel);
- if ((ppll_val & 0x000707ff) == 0x1bb)
- goto noprobe;
- info->FeedbackDivider = ppll_val & 0x7ff;
- info->PostDivider = (ppll_val >> 16) & 0x7;
- info->RefDivider = info->pll.reference_div;
- info->UseBiosDividers = TRUE;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Existing panel PLL dividers will be used.\n");
- }
- noprobe:
-
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Panel size %dx%d is derived, this may not be correct.\n"
- "If not, use PanelSize option to overwrite this setting\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes);
-}
-
-/* BIOS may not have right panel size, we search through all supported
- * DDC modes looking for the maximum panel size.
- */
-static void
-RADEONUpdatePanelSize(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int j;
- /* XXX: fixme */
- //xf86MonPtr ddc = pScrn->monitor->DDC;
- xf86MonPtr ddc = output->MonInfo;
- DisplayModePtr p;
-
- // crtc should handle?
- if ((info->UseBiosDividers && radeon_output->DotClock != 0) || (ddc == NULL))
- return;
-
- /* Go thru detailed timing table first */
- for (j = 0; j < 4; j++) {
- if (ddc->det_mon[j].type == 0) {
- struct detailed_timings *d_timings =
- &ddc->det_mon[j].section.d_timings;
- int match = 0;
-
- /* If we didn't get a panel clock or guessed one, try to match the
- * mode with the panel size. We do that because we _need_ a panel
- * clock, or ValidateFPModes will fail, even when UseBiosDividers
- * is set.
- */
- if (radeon_output->DotClock == 0 &&
- radeon_output->PanelXRes == d_timings->h_active &&
- radeon_output->PanelYRes == d_timings->v_active)
- match = 1;
-
- /* If we don't have a BIOS provided panel data with fixed dividers,
- * check for a larger panel size
- */
- if (radeon_output->PanelXRes < d_timings->h_active &&
- radeon_output->PanelYRes < d_timings->v_active &&
- !info->UseBiosDividers)
- match = 1;
-
- if (match) {
- radeon_output->PanelXRes = d_timings->h_active;
- radeon_output->PanelYRes = d_timings->v_active;
- radeon_output->DotClock = d_timings->clock / 1000;
- radeon_output->HOverPlus = d_timings->h_sync_off;
- radeon_output->HSyncWidth = d_timings->h_sync_width;
- radeon_output->HBlank = d_timings->h_blanking;
- radeon_output->VOverPlus = d_timings->v_sync_off;
- radeon_output->VSyncWidth = d_timings->v_sync_width;
- radeon_output->VBlank = d_timings->v_blanking;
- radeon_output->Flags = (d_timings->interlaced ? V_INTERLACE : 0);
- switch (d_timings->misc) {
- case 0: radeon_output->Flags |= V_NHSYNC | V_NVSYNC; break;
- case 1: radeon_output->Flags |= V_PHSYNC | V_NVSYNC; break;
- case 2: radeon_output->Flags |= V_NHSYNC | V_PVSYNC; break;
- case 3: radeon_output->Flags |= V_PHSYNC | V_PVSYNC; break;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes);
- }
- }
- }
-
- if (info->UseBiosDividers && radeon_output->DotClock != 0)
- return;
-
- /* Search thru standard VESA modes from EDID */
- for (j = 0; j < 8; j++) {
- if ((radeon_output->PanelXRes < ddc->timings2[j].hsize) &&
- (radeon_output->PanelYRes < ddc->timings2[j].vsize)) {
- for (p = pScrn->monitor->Modes; p; p = p->next) {
- if ((ddc->timings2[j].hsize == p->HDisplay) &&
- (ddc->timings2[j].vsize == p->VDisplay)) {
- float refresh =
- (float)p->Clock * 1000.0 / p->HTotal / p->VTotal;
-
- if (abs((float)ddc->timings2[j].refresh - refresh) < 1.0) {
- /* Is this good enough? */
- radeon_output->PanelXRes = ddc->timings2[j].hsize;
- radeon_output->PanelYRes = ddc->timings2[j].vsize;
- radeon_output->HBlank = p->HTotal - p->HDisplay;
- radeon_output->HOverPlus = p->HSyncStart - p->HDisplay;
- radeon_output->HSyncWidth = p->HSyncEnd - p->HSyncStart;
- radeon_output->VBlank = p->VTotal - p->VDisplay;
- radeon_output->VOverPlus = p->VSyncStart - p->VDisplay;
- radeon_output->VSyncWidth = p->VSyncEnd - p->VSyncStart;
- radeon_output->DotClock = p->Clock;
- radeon_output->Flags = p->Flags;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n",
- radeon_output->PanelXRes, radeon_output->PanelYRes);
- }
- }
- }
- }
- }
-}
-
-static Bool
-RADEONGetLVDSInfo (xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- char* s;
-
- if (!RADEONGetLVDSInfoFromBIOS(output))
- RADEONGetPanelInfoFromReg(output);
-
- if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) {
- radeon_output->PanelPwrDly = 200;
- if (sscanf (s, "%dx%d", &radeon_output->PanelXRes, &radeon_output->PanelYRes) != 2) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s\n", s);
- RADEONGetPanelInfoFromReg(output);
- }
- }
-
- /* The panel size we collected from BIOS may not be the
- * maximum size supported by the panel. If not, we update
- * it now. These will be used if no matching mode can be
- * found from EDID data.
- */
- RADEONUpdatePanelSize(output);
-
- if (radeon_output->DotClock == 0) {
- DisplayModePtr tmp_mode = NULL;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No valid timing info from BIOS.\n");
- /* No timing information for the native mode,
- use whatever specified in the Modeline.
- If no Modeline specified, we'll just pick
- the VESA mode at 60Hz refresh rate which
- is likely to be the best for a flat panel.
- */
- tmp_mode = pScrn->monitor->Modes;
- while(tmp_mode) {
- if ((tmp_mode->HDisplay == radeon_output->PanelXRes) &&
- (tmp_mode->VDisplay == radeon_output->PanelYRes)) {
-
- float refresh =
- (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal;
- if ((abs(60.0 - refresh) < 1.0) ||
- (tmp_mode->type == 0)) {
- radeon_output->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay;
- radeon_output->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay;
- radeon_output->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart;
- radeon_output->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay;
- radeon_output->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay;
- radeon_output->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart;
- radeon_output->DotClock = tmp_mode->Clock;
- radeon_output->Flags = 0;
- break;
- }
- }
-
- tmp_mode = tmp_mode->next;
-
- if (tmp_mode == pScrn->monitor->Modes)
- break;
- }
- if ((radeon_output->DotClock == 0) && !output->MonInfo) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Panel size is not correctly detected.\n"
- "Please try to use PanelSize option for correct settings.\n");
- return FALSE;
- }
- }
-
- return TRUE;
-}
-
-static void
-RADEONGetTMDSInfoFromTable(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int i;
-
- for (i=0; i<4; i++) {
- radeon_output->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value;
- radeon_output->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq;
- }
-}
-
-static void
-RADEONGetTMDSInfo(xf86OutputPtr output)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int i;
-
- for (i=0; i<4; i++) {
- radeon_output->tmds_pll[i].value = 0;
- radeon_output->tmds_pll[i].freq = 0;
- }
-
- if (RADEONGetTMDSInfoFromBIOS(output)) return;
-
- RADEONGetTMDSInfoFromTable(output);
-
-}
-
-static void
-RADEONGetTVInfo(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- char *optstr;
-
- radeon_output->hPos = 0;
- radeon_output->vPos = 0;
- radeon_output->hSize = 0;
-
- if (!RADEONGetTVInfoFromBIOS(output)) {
- /* set some reasonable defaults */
- radeon_output->default_tvStd = TV_STD_NTSC;
- radeon_output->tvStd = TV_STD_NTSC;
- radeon_output->TVRefClk = 27.000000000;
- radeon_output->SupportedTVStds = TV_STD_NTSC | TV_STD_PAL;
- }
-
- optstr = (char *)xf86GetOptValString(info->Options, OPTION_TVSTD);
- if (optstr) {
- if (!strncmp("ntsc", optstr, strlen("ntsc")))
- radeon_output->tvStd = TV_STD_NTSC;
- else if (!strncmp("pal", optstr, strlen("pal")))
- radeon_output->tvStd = TV_STD_PAL;
- else if (!strncmp("pal-m", optstr, strlen("pal-m")))
- radeon_output->tvStd = TV_STD_PAL_M;
- else if (!strncmp("pal-60", optstr, strlen("pal-60")))
- radeon_output->tvStd = TV_STD_PAL_60;
- else if (!strncmp("ntsc-j", optstr, strlen("ntsc-j")))
- radeon_output->tvStd = TV_STD_NTSC_J;
- else if (!strncmp("scart-pal", optstr, strlen("scart-pal")))
- radeon_output->tvStd = TV_STD_SCART_PAL;
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid TV Standard: %s\n", optstr);
- }
- }
-
-}
-
-static void
-RADEONGetTVDacAdjInfo(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (!RADEONGetDAC2InfoFromBIOS(output)) {
- radeon_output->ps2_tvdac_adj = default_tvdac_adj[info->ChipFamily];
- if (info->IsMobility) { /* some mobility chips may different */
- if (info->ChipFamily == CHIP_FAMILY_RV250)
- radeon_output->ps2_tvdac_adj = 0x00880000;
- }
- radeon_output->pal_tvdac_adj = radeon_output->ps2_tvdac_adj;
- radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj;
- }
-
-}
-
-void RADEONInitConnector(xf86OutputPtr output)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- if (radeon_output->DACType == DAC_PRIMARY)
- radeon_output->load_detection = 1; /* primary dac, only drives vga */
- /*else if (radeon_output->DACType == DAC_TVDAC &&
- info->tvdac_use_count < 2)
- radeon_output->load_detection = 1;*/ /* only one output with tvdac */
- else if ((radeon_output->DACType == DAC_TVDAC) &&
- (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE)))
- radeon_output->load_detection = 1; /* shared tvdac between vga/dvi/tv */
- else
- radeon_output->load_detection = 0; /* shared tvdac between vga/dvi/tv */
-
- if (radeon_output->type == OUTPUT_LVDS) {
- radeon_output->rmx_type = RMX_FULL;
- RADEONGetLVDSInfo(output);
- }
-
- if (OUTPUT_IS_DVI) {
- I2CBusPtr pDVOBus;
- radeon_output->rmx_type = RMX_OFF;
- if ((!info->IsAtomBios) && radeon_output->TMDSType == TMDS_EXT) {
-#if defined(__powerpc__)
- radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- radeon_output->dvo_i2c_slave_addr = 0x70;
-#else
- if (!RADEONGetExtTMDSInfoFromBIOS(output)) {
- radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- radeon_output->dvo_i2c_slave_addr = 0x70;
- }
-#endif
- if (RADEONI2CInit(output, &pDVOBus, "DVO", TRUE)) {
- radeon_output->DVOChip =
- RADEONDVODeviceInit(pDVOBus,
- radeon_output->dvo_i2c_slave_addr);
- if (!radeon_output->DVOChip)
- xfree(pDVOBus);
- }
- } else
- RADEONGetTMDSInfo(output);
- }
-
- if (OUTPUT_IS_TV) {
- RADEONGetTVInfo(output);
- RADEONGetTVDacAdjInfo(output);
- }
-
- if (radeon_output->DACType == DAC_TVDAC) {
- radeon_output->tv_on = FALSE;
- RADEONGetTVDacAdjInfo(output);
- }
-
- if (radeon_output->ddc_i2c.valid)
- RADEONI2CInit(output, &radeon_output->pI2CBus, output->name, FALSE);
-
-}
-
-#if defined(__powerpc__)
-static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-
- switch (info->MacModel) {
- case RADEON_MAC_IBOOK:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
-
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].valid = TRUE;
- return TRUE;
- case RADEON_MAC_POWERBOOK_EXTERNAL:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_EXT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[1].valid = TRUE;
-
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].valid = TRUE;
- return TRUE;
-
- case RADEON_MAC_POWERBOOK_INTERNAL:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_INT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[1].valid = TRUE;
-
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].valid = TRUE;
- return TRUE;
- case RADEON_MAC_POWERBOOK_VGA:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_INT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[1].valid = TRUE;
-
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].valid = TRUE;
- return TRUE;
- case RADEON_MAC_MINI_EXTERNAL:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[0].TMDSType = TMDS_EXT;
- info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ddc_i2c.valid = FALSE;
- info->BiosConnector[1].valid = TRUE;
- return TRUE;
- case RADEON_MAC_MINI_INTERNAL:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[0].TMDSType = TMDS_INT;
- info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ddc_i2c.valid = FALSE;
- info->BiosConnector[1].valid = TRUE;
- return TRUE;
- case RADEON_MAC_IMAC_G5_ISIGHT:
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_INT;
- info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
-
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].valid = TRUE;
- return TRUE;
- default:
- return FALSE;
- }
-
- return FALSE;
-}
-#endif
-
-static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-
- if (!pRADEONEnt->HasCRTC2) {
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[0].DACType = DAC_PRIMARY;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[0].valid = TRUE;
- return;
- }
-
- if (IS_AVIVO_VARIANT) {
- if (info->IsMobility) {
- info->BiosConnector[0].ddc_i2c = atom_setup_i2c_bus(0x7e60);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = atom_setup_i2c_bus(0x7e40);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT;
- info->BiosConnector[1].valid = TRUE;
- } else {
- info->BiosConnector[0].ddc_i2c = atom_setup_i2c_bus(0x7e50);
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[0].TMDSType = TMDS_INT;
- info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = atom_setup_i2c_bus(0x7e40);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT;
- info->BiosConnector[1].valid = TRUE;
- }
-
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT;
- info->BiosConnector[2].valid = TRUE;
- } else {
- if (info->IsMobility) {
- /* Below is the most common setting, but may not be true */
- if (info->IsIGP) {
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].valid = TRUE;
-
- /* IGP only has TVDAC */
- if (info->ChipFamily == CHIP_FAMILY_RS400)
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- else
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_TVDAC;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
- } else {
-#if defined(__powerpc__)
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
-#else
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
-#endif
- info->BiosConnector[0].DACType = DAC_NONE;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
- info->BiosConnector[0].valid = TRUE;
-
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_NONE;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
- }
- } else {
- /* Below is the most common setting, but may not be true */
- if (info->IsIGP) {
- if (info->ChipFamily == CHIP_FAMILY_RS400)
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- else
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[0].valid = TRUE;
-
- /* not sure what a good default DDCType for DVI on
- * IGP desktop chips is
- */
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); /* DDC_DVI? */
- info->BiosConnector[1].DACType = DAC_NONE;
- info->BiosConnector[1].TMDSType = TMDS_EXT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D;
- info->BiosConnector[1].valid = TRUE;
- } else {
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- info->BiosConnector[0].DACType = DAC_TVDAC;
- info->BiosConnector[0].TMDSType = TMDS_INT;
- info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[0].valid = TRUE;
-
-#if defined(__powerpc__)
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_EXT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[1].valid = TRUE;
-#else
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_EXT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
- info->BiosConnector[1].valid = TRUE;
-#endif
- }
- }
-
- if (info->InternalTVOut) {
- info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
- info->BiosConnector[2].DACType = DAC_TVDAC;
- info->BiosConnector[2].TMDSType = TMDS_NONE;
- info->BiosConnector[2].ddc_i2c.valid = FALSE;
- info->BiosConnector[2].valid = TRUE;
- }
-
- /* Some cards have the DDC lines swapped and we have no way to
- * detect it yet (Mac cards)
- */
- if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
- }
- }
-}
-
-#if defined(__powerpc__)
-
-/*
- * Returns RADEONMacModel or 0 based on lines 'detected as' and 'machine'
- * in /proc/cpuinfo (on Linux) */
-static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONMacModel ret = 0;
-#ifdef __linux__
- char cpuline[50]; /* 50 should be sufficient for our purposes */
- FILE *f = fopen ("/proc/cpuinfo", "r");
-
- /* Some macs (minis and powerbooks) use internal tmds, others use external tmds
- * and not just for dual-link TMDS, it shows up with single-link as well.
- * Unforunately, there doesn't seem to be any good way to figure it out.
- */
-
- /*
- * PowerBook5,[1-5]: external tmds, single-link
- * PowerBook5,[789]: external tmds, dual-link
- * PowerBook5,6: external tmds, single-link or dual-link
- * need to add another option to specify the external tmds chip
- * or find out what's used and add it.
- */
-
-
- if (f != NULL) {
- while (fgets(cpuline, sizeof cpuline, f)) {
- if (!strncmp(cpuline, "machine", strlen ("machine"))) {
- if (strstr(cpuline, "PowerBook5,1") ||
- strstr(cpuline, "PowerBook5,2") ||
- strstr(cpuline, "PowerBook5,3") ||
- strstr(cpuline, "PowerBook5,4") ||
- strstr(cpuline, "PowerBook5,5")) {
- ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* single link */
- info->ext_tmds_chip = RADEON_SIL_164; /* works on 5,2 */
- break;
- }
-
- if (strstr(cpuline, "PowerBook5,6")) {
- ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual or single link */
- break;
- }
-
- if (strstr(cpuline, "PowerBook5,7") ||
- strstr(cpuline, "PowerBook5,8") ||
- strstr(cpuline, "PowerBook5,9")) {
- ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual link */
- info->ext_tmds_chip = RADEON_SIL_1178; /* guess */
- break;
- }
-
- if (strstr(cpuline, "PowerBook3,3")) {
- ret = RADEON_MAC_POWERBOOK_VGA; /* vga rather than dvi */
- break;
- }
-
- if (strstr(cpuline, "PowerMac10,1")) {
- ret = RADEON_MAC_MINI_INTERNAL; /* internal tmds */
- break;
- }
- if (strstr(cpuline, "PowerMac10,2")) {
- ret = RADEON_MAC_MINI_EXTERNAL; /* external tmds */
- break;
- }
- } else if (!strncmp(cpuline, "detected as", strlen("detected as"))) {
- if (strstr(cpuline, "iBook")) {
- ret = RADEON_MAC_IBOOK;
- break;
- } else if (strstr(cpuline, "PowerBook")) {
- ret = RADEON_MAC_POWERBOOK_INTERNAL; /* internal tmds */
- break;
- } else if (strstr(cpuline, "iMac G5 (iSight)")) {
- ret = RADEON_MAC_IMAC_G5_ISIGHT;
- break;
- }
-
- /* No known PowerMac model detected */
- break;
- }
- }
-
- fclose (f);
- } else
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Cannot detect PowerMac model because /proc/cpuinfo not "
- "readable.\n");
-
-#endif /* __linux */
-
- if (ret) {
- xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Detected %s.\n",
- ret == RADEON_MAC_POWERBOOK_EXTERNAL ? "PowerBook with external DVI" :
- ret == RADEON_MAC_POWERBOOK_INTERNAL ? "PowerBook with integrated DVI" :
- ret == RADEON_MAC_POWERBOOK_VGA ? "PowerBook with VGA" :
- ret == RADEON_MAC_IBOOK ? "iBook" :
- ret == RADEON_MAC_MINI_EXTERNAL ? "Mac Mini with external DVI" :
- ret == RADEON_MAC_MINI_INTERNAL ? "Mac Mini with integrated DVI" :
- "iMac G5 iSight");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "If this is not correct, try Option \"MacModel\" and "
- "consider reporting to the\n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "xorg-driver-ati at lists.x.org mailing list"
-#ifdef __linux__
- " with the contents of /proc/cpuinfo"
-#endif
- ".\n");
- }
-
- return ret;
-}
-
-#endif /* __powerpc__ */
-
-/*
- * initialise the static data sos we don't have to re-do at randr change */
-Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- xf86OutputPtr output;
- char *optstr;
- int i = 0;
- int num_vga = 0;
- int num_dvi = 0;
- int num_hdmi = 0;
-
- /* We first get the information about all connectors from BIOS.
- * This is how the card is phyiscally wired up.
- * The information should be correct even on a OEM card.
- */
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- info->BiosConnector[i].valid = FALSE;
- info->BiosConnector[i].ddc_i2c.valid = FALSE;
- info->BiosConnector[i].DACType = DAC_NONE;
- info->BiosConnector[i].TMDSType = TMDS_NONE;
- info->BiosConnector[i].ConnectorType = CONNECTOR_NONE;
- }
-
-#if defined(__powerpc__)
- info->MacModel = 0;
- optstr = (char *)xf86GetOptValString(info->Options, OPTION_MAC_MODEL);
- if (optstr) {
- if (!strncmp("ibook", optstr, strlen("ibook")))
- info->MacModel = RADEON_MAC_IBOOK;
- else if (!strncmp("powerbook-duallink", optstr, strlen("powerbook-duallink"))) /* alias */
- info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL;
- else if (!strncmp("powerbook-external", optstr, strlen("powerbook-external")))
- info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL;
- else if (!strncmp("powerbook-internal", optstr, strlen("powerbook-internal")))
- info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL;
- else if (!strncmp("powerbook-vga", optstr, strlen("powerbook-vga")))
- info->MacModel = RADEON_MAC_POWERBOOK_VGA;
- else if (!strncmp("powerbook", optstr, strlen("powerbook"))) /* alias */
- info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL;
- else if (!strncmp("mini-internal", optstr, strlen("mini-internal")))
- info->MacModel = RADEON_MAC_MINI_INTERNAL;
- else if (!strncmp("mini-external", optstr, strlen("mini-external")))
- info->MacModel = RADEON_MAC_MINI_EXTERNAL;
- else if (!strncmp("mini", optstr, strlen("mini"))) /* alias */
- info->MacModel = RADEON_MAC_MINI_EXTERNAL;
- else if (!strncmp("imac-g5-isight", optstr, strlen("imac-g5-isight")))
- info->MacModel = RADEON_MAC_IMAC_G5_ISIGHT;
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid Mac Model: %s\n", optstr);
- }
- }
-
- if (!info->MacModel) {
- info->MacModel = RADEONDetectMacModel(pScrn);
- }
-
- if (info->MacModel){
- if (!RADEONSetupAppleConnectors(pScrn))
- RADEONSetupGenericConnectors(pScrn);
- } else
-#endif
- if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_CONNECTOR_TABLE, FALSE)) {
- RADEONSetupGenericConnectors(pScrn);
- } else {
- if (!RADEONGetConnectorInfoFromBIOS(pScrn))
- RADEONSetupGenericConnectors(pScrn);
- }
-
- if (!pRADEONEnt->HasCRTC2) {
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA)
- info->BiosConnector[i].DACType = DAC_PRIMARY;
- }
- }
-
- /* parse connector table option */
- optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE);
-
- if (optstr) {
- unsigned int ddc_line[2];
-
- for (i = 2; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- info->BiosConnector[i].valid = FALSE;
- }
- info->BiosConnector[0].valid = TRUE;
- info->BiosConnector[1].valid = TRUE;
- if (sscanf(optstr, "%u,%u,%u,%u,%u,%u,%u,%u",
- &ddc_line[0],
- &info->BiosConnector[0].DACType,
- &info->BiosConnector[0].TMDSType,
- &info->BiosConnector[0].ConnectorType,
- &ddc_line[1],
- &info->BiosConnector[1].DACType,
- &info->BiosConnector[1].TMDSType,
- &info->BiosConnector[1].ConnectorType) != 8) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid ConnectorTable option: %s\n", optstr);
- return FALSE;
- }
-
- info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(ddc_line[0]);
- info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(ddc_line[1]);
- }
-
- info->tvdac_use_count = 0;
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].valid) {
- if (info->BiosConnector[i].DACType == DAC_TVDAC)
- info->tvdac_use_count++;
-
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
- num_dvi++;
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
- num_vga++;
- } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
- num_hdmi++;
- }
- }
- }
-
- /* clear the enable masks */
- info->output_crt1 = 0;
- info->output_crt2 = 0;
- info->output_dfp1 = 0;
- info->output_dfp2 = 0;
- info->output_lcd1 = 0;
- info->output_tv1 = 0;
-
- for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].valid) {
-
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE)
- continue;
-
- RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
- if (!radeon_output) {
- return FALSE;
- }
- radeon_output->MonType = MT_UNKNOWN;
- radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType;
- radeon_output->devices = info->BiosConnector[i].devices;
- radeon_output->output_id = info->BiosConnector[i].output_id;
- radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c;
-
- if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
- radeon_output->DACType = DAC_NONE;
- else
- radeon_output->DACType = info->BiosConnector[i].DACType;
-
- if (radeon_output->ConnectorType == CONNECTOR_VGA)
- radeon_output->TMDSType = TMDS_NONE;
- else
- radeon_output->TMDSType = info->BiosConnector[i].TMDSType;
-
- RADEONSetOutputType(pScrn, radeon_output);
- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) {
- if (num_dvi > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1");
- num_dvi--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0");
- }
- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) {
- if (num_vga > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1");
- num_vga--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0");
- }
- } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
- (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) {
- if (num_hdmi > 1) {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-1");
- num_hdmi--;
- } else {
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-0");
- }
- } else
- output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]);
-
- if (!output) {
- return FALSE;
- }
- output->driver_private = radeon_output;
- output->possible_crtcs = 1;
- /* crtc2 can drive LVDS, it just doesn't have RMX */
- if (radeon_output->type != OUTPUT_LVDS)
- output->possible_crtcs |= 2;
-
- /* we can clone the DACs, and probably TV-out,
- but I'm not sure it's worth the trouble */
- output->possible_clones = 0;
-
- RADEONInitConnector(output);
- }
- }
-
- return TRUE;
-}
-
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
deleted file mode 100644
index 4ec7485..0000000
--- a/src/radeon_probe.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- */
-
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#include "atipciids.h"
-#include "atipcirename.h"
-
-#include "xf86.h"
-#define _XF86MISC_SERVER_
-#include <X11/extensions/xf86misc.h>
-#include "xf86Resources.h"
-
-#include "radeon_chipset_gen.h"
-
-#include "radeon_pci_chipset_gen.h"
-
-#ifdef XSERVER_LIBPCIACCESS
-#include "radeon_pci_device_match_gen.h"
-#endif
-
-#ifndef XSERVER_LIBPCIACCESS
-static Bool RADEONProbe(DriverPtr drv, int flags);
-#endif
-
-int gRADEONEntityIndex = -1;
-
-/* Return the options for supported chipset 'n'; NULL otherwise */
-static const OptionInfoRec *
-RADEONAvailableOptions(int chipid, int busid)
-{
- return RADEONOptionsWeak();
-}
-
-/* Return the string name for supported chipset 'n'; NULL otherwise. */
-static void
-RADEONIdentify(int flags)
-{
- xf86PrintChipsets(RADEON_NAME,
- "Driver for ATI Radeon chipsets",
- RADEONChipsets);
-}
-
-static Bool
-radeon_get_scrninfo(int entity_num)
-{
- ScrnInfoPtr pScrn = NULL;
- EntityInfoPtr pEnt;
-
- pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, RADEONPciChipsets,
- NULL,
- NULL, NULL, NULL, NULL);
-
- if (!pScrn)
- return FALSE;
-
- pScrn->driverVersion = RADEON_VERSION_CURRENT;
- pScrn->driverName = RADEON_DRIVER_NAME;
- pScrn->name = RADEON_NAME;
-#ifdef XSERVER_LIBPCIACCESS
- pScrn->Probe = NULL;
-#else
- pScrn->Probe = RADEONProbe;
-#endif
- pScrn->PreInit = RADEONPreInit;
- pScrn->ScreenInit = RADEONScreenInit;
- pScrn->SwitchMode = RADEONSwitchMode;
- pScrn->AdjustFrame = RADEONAdjustFrame;
- pScrn->EnterVT = RADEONEnterVT;
- pScrn->LeaveVT = RADEONLeaveVT;
- pScrn->FreeScreen = RADEONFreeScreen;
- pScrn->ValidMode = RADEONValidMode;
-
- pEnt = xf86GetEntityInfo(entity_num);
-
- /* Create a RADEONEntity for all chips, even with old single head
- * Radeon, need to use pRADEONEnt for new monitor detection routines.
- */
- {
- DevUnion *pPriv;
- RADEONEntPtr pRADEONEnt;
-
- xf86SetEntitySharable(entity_num);
-
- if (gRADEONEntityIndex == -1)
- gRADEONEntityIndex = xf86AllocateEntityPrivateIndex();
-
- pPriv = xf86GetEntityPrivate(pEnt->index,
- gRADEONEntityIndex);
-
- if (!pPriv->ptr) {
- int j;
- int instance = xf86GetNumEntityInstances(pEnt->index);
-
- for (j = 0; j < instance; j++)
- xf86SetEntityInstanceForScreen(pScrn, pEnt->index, j);
-
- pPriv->ptr = xnfcalloc(sizeof(RADEONEntRec), 1);
- pRADEONEnt = pPriv->ptr;
- pRADEONEnt->HasSecondary = FALSE;
- } else {
- pRADEONEnt = pPriv->ptr;
- pRADEONEnt->HasSecondary = TRUE;
- }
- }
-
- xfree(pEnt);
-
- return TRUE;
-}
-
-#ifndef XSERVER_LIBPCIACCESS
-
-/* Return TRUE if chipset is present; FALSE otherwise. */
-static Bool
-RADEONProbe(DriverPtr drv, int flags)
-{
- int numUsed;
- int numDevSections;
- int *usedChips;
- GDevPtr *devSections;
- Bool foundScreen = FALSE;
- int i;
-
- if (!xf86GetPciVideoInfo()) return FALSE;
-
- numDevSections = xf86MatchDevice(RADEON_NAME, &devSections);
-
- if (!numDevSections) return FALSE;
-
- numUsed = xf86MatchPciInstances(RADEON_NAME,
- PCI_VENDOR_ATI,
- RADEONChipsets,
- RADEONPciChipsets,
- devSections,
- numDevSections,
- drv,
- &usedChips);
-
- if (numUsed <= 0) return FALSE;
-
- if (flags & PROBE_DETECT) {
- foundScreen = TRUE;
- } else {
- for (i = 0; i < numUsed; i++) {
- if (radeon_get_scrninfo(usedChips[i]))
- foundScreen = TRUE;
- }
- }
-
- xfree(usedChips);
- xfree(devSections);
-
- return foundScreen;
-}
-
-#else /* XSERVER_LIBPCIACCESS */
-
-static Bool
-radeon_pci_probe(
- DriverPtr pDriver,
- int entity_num,
- struct pci_device *device,
- intptr_t match_data
-)
-{
- return radeon_get_scrninfo(entity_num);
-}
-
-#endif /* XSERVER_LIBPCIACCESS */
-
-_X_EXPORT DriverRec RADEON =
-{
- RADEON_VERSION_CURRENT,
- RADEON_DRIVER_NAME,
- RADEONIdentify,
-#ifdef XSERVER_LIBPCIACCESS
- NULL,
-#else
- RADEONProbe,
-#endif
- RADEONAvailableOptions,
- NULL,
- 0,
- NULL,
-#ifdef XSERVER_LIBPCIACCESS
- radeon_device_match,
- radeon_pci_probe
-#endif
-};
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
deleted file mode 100644
index 9c1bdc5..0000000
--- a/src/radeon_probe.h
+++ /dev/null
@@ -1,595 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- *
- * Modified by Marc Aurele La France <tsi at xfree86.org> for ATI driver merge.
- */
-
-#ifndef _RADEON_PROBE_H_
-#define _RADEON_PROBE_H_ 1
-
-#include <stdint.h>
-#include "xf86str.h"
-#include "xf86DDC.h"
-#include "randrstr.h"
-
-#define _XF86MISC_SERVER_
-#include <X11/extensions/xf86misc.h>
-
-#include "xf86Crtc.h"
-
-#ifdef USE_EXA
-#include "exa.h"
-#endif
-#ifdef USE_XAA
-#include "xaa.h"
-#endif
-
-extern DriverRec RADEON;
-
-typedef enum
-{
- MT_UNKNOWN = -1,
- MT_NONE = 0,
- MT_CRT = 1,
- MT_LCD = 2,
- MT_DFP = 3,
- MT_CTV = 4,
- MT_STV = 5,
- MT_CV = 6,
- MT_HDMI = 7, // this should really just be MT_DFP
- MT_DP = 8
-} RADEONMonitorType;
-
-typedef enum
-{
- CONNECTOR_NONE,
- CONNECTOR_VGA,
- CONNECTOR_DVI_I,
- CONNECTOR_DVI_D,
- CONNECTOR_DVI_A,
- CONNECTOR_STV,
- CONNECTOR_CTV,
- CONNECTOR_LVDS,
- CONNECTOR_DIGITAL,
- CONNECTOR_SCART,
- CONNECTOR_HDMI_TYPE_A,
- CONNECTOR_HDMI_TYPE_B,
- CONNECTOR_0XC,
- CONNECTOR_0XD,
- CONNECTOR_DIN,
- CONNECTOR_DISPLAY_PORT,
- CONNECTOR_UNSUPPORTED
-} RADEONConnectorType;
-
-typedef enum
-{
- DAC_NONE = 0,
- DAC_PRIMARY = 1,
- DAC_TVDAC = 2,
- DAC_EXT = 3
-} RADEONDacType;
-
-typedef enum
-{
- TMDS_NONE = 0,
- TMDS_INT = 1,
- TMDS_EXT = 2,
- TMDS_LVTMA = 3,
- TMDS_DDIA = 4
-} RADEONTmdsType;
-
-typedef enum
-{
- DVI_AUTO,
- DVI_DIGITAL,
- DVI_ANALOG
-} RADEONDviType;
-
-typedef enum
-{
- RMX_OFF,
- RMX_FULL,
- RMX_CENTER
-} RADEONRMXType;
-
-typedef struct {
- CARD32 freq;
- CARD32 value;
-}RADEONTMDSPll;
-
-typedef enum
-{
- OUTPUT_NONE,
- OUTPUT_VGA,
- OUTPUT_DVI_I,
- OUTPUT_DVI_D,
- OUTPUT_DVI_A,
- OUTPUT_LVDS,
- OUTPUT_STV,
- OUTPUT_CTV,
- OUTPUT_CV,
- OUTPUT_HDMI,
- OUTPUT_DP
-} RADEONOutputType;
-
-#define OUTPUT_IS_DVI ((radeon_output->type == OUTPUT_DVI_D || \
- radeon_output->type == OUTPUT_DVI_I || \
- radeon_output->type == OUTPUT_DVI_A))
-#define OUTPUT_IS_TV ((radeon_output->type == OUTPUT_STV || \
- radeon_output->type == OUTPUT_CTV))
-
-/* standards */
-typedef enum
-{
- TV_STD_NTSC = 1,
- TV_STD_PAL = 2,
- TV_STD_PAL_M = 4,
- TV_STD_PAL_60 = 8,
- TV_STD_NTSC_J = 16,
- TV_STD_SCART_PAL = 32,
- TV_STD_SECAM = 64,
- TV_STD_PAL_CN = 128,
-} TVStd;
-
-typedef struct
-{
- Bool valid;
- CARD32 mask_clk_reg;
- CARD32 mask_data_reg;
- CARD32 put_clk_reg;
- CARD32 put_data_reg;
- CARD32 get_clk_reg;
- CARD32 get_data_reg;
- CARD32 mask_clk_mask;
- CARD32 mask_data_mask;
- CARD32 put_clk_mask;
- CARD32 put_data_mask;
- CARD32 get_clk_mask;
- CARD32 get_data_mask;
-} RADEONI2CBusRec, *RADEONI2CBusPtr;
-
-typedef struct _RADEONCrtcPrivateRec {
-#ifdef USE_XAA
- FBLinearPtr rotate_mem_xaa;
-#endif
-#ifdef USE_EXA
- ExaOffscreenArea *rotate_mem_exa;
-#endif
- int crtc_id;
- int binding;
- CARD32 cursor_offset;
- /* Lookup table values to be set when the CRTC is enabled */
- CARD8 lut_r[256], lut_g[256], lut_b[256];
-
- uint32_t crtc_offset;
- int h_total, h_blank, h_sync_wid, h_sync_pol;
- int v_total, v_blank, v_sync_wid, v_sync_pol;
- int fb_format, fb_length;
- int fb_pitch, fb_width, fb_height;
- INT16 cursor_x;
- INT16 cursor_y;
-} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
-
-typedef struct {
- RADEONDacType DACType;
- RADEONTmdsType TMDSType;
- RADEONConnectorType ConnectorType;
- Bool valid;
- int output_id;
- int devices;
- int hpd_mask;
- RADEONI2CBusRec ddc_i2c;
-} RADEONBIOSConnector;
-
-typedef struct _RADEONOutputPrivateRec {
- int num;
- RADEONOutputType type;
- void *dev_priv;
- CARD32 ddc_line;
- RADEONDacType DACType;
- RADEONDviType DVIType;
- RADEONTmdsType TMDSType;
- RADEONConnectorType ConnectorType;
- RADEONMonitorType MonType;
- int crtc_num;
- int DDCReg;
- I2CBusPtr pI2CBus;
- RADEONI2CBusRec ddc_i2c;
- CARD32 ps2_tvdac_adj;
- CARD32 pal_tvdac_adj;
- CARD32 ntsc_tvdac_adj;
- /* panel stuff */
- int PanelXRes;
- int PanelYRes;
- int HOverPlus;
- int HSyncWidth;
- int HBlank;
- int VOverPlus;
- int VSyncWidth;
- int VBlank;
- int Flags; /* Saved copy of mode flags */
- int PanelPwrDly;
- int DotClock;
- RADEONTMDSPll tmds_pll[4];
- RADEONRMXType rmx_type;
- /* dvo */
- I2CDevPtr DVOChip;
- RADEONI2CBusRec dvo_i2c;
- int dvo_i2c_slave_addr;
- Bool dvo_duallink;
- /* TV out */
- TVStd default_tvStd;
- TVStd tvStd;
- int hPos;
- int vPos;
- int hSize;
- float TVRefClk;
- int SupportedTVStds;
- Bool tv_on;
- int load_detection;
-
- char *name;
- int output_id;
- int devices;
-} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
-
-struct avivo_pll_state {
- CARD32 ref_div_src;
- CARD32 ref_div;
- CARD32 fb_div;
- CARD32 post_div_src;
- CARD32 post_div;
- CARD32 ext_ppll_cntl;
- CARD32 pll_cntl;
- CARD32 int_ss_cntl;
-};
-
-
-struct avivo_crtc_state {
- CARD32 pll_source;
- CARD32 h_total;
- CARD32 h_blank_start_end;
- CARD32 h_sync_a;
- CARD32 h_sync_a_cntl;
- CARD32 h_sync_b;
- CARD32 h_sync_b_cntl;
- CARD32 v_total;
- CARD32 v_blank_start_end;
- CARD32 v_sync_a;
- CARD32 v_sync_a_cntl;
- CARD32 v_sync_b;
- CARD32 v_sync_b_cntl;
- CARD32 control;
- CARD32 blank_control;
- CARD32 interlace_control;
- CARD32 stereo_control;
- CARD32 cursor_control;
-};
-
-struct avivo_grph_state {
- CARD32 enable;
- CARD32 control;
- CARD32 prim_surf_addr;
- CARD32 sec_surf_addr;
- CARD32 pitch;
- CARD32 x_offset;
- CARD32 y_offset;
- CARD32 x_start;
- CARD32 y_start;
- CARD32 x_end;
- CARD32 y_end;
-
- CARD32 viewport_start;
- CARD32 viewport_size;
- CARD32 scl_enable;
- CARD32 scl_tap_control;
-};
-
-struct avivo_dac_state {
- CARD32 enable;
- CARD32 source_select;
- CARD32 force_output_cntl;
- CARD32 powerdown;
-};
-
-struct avivo_dig_state {
- CARD32 cntl;
- CARD32 bit_depth_cntl;
- CARD32 data_sync;
- CARD32 transmitter_enable;
- CARD32 transmitter_cntl;
- CARD32 source_select;
-};
-
-struct avivo_state
-{
- CARD32 hdp_fb_location;
- CARD32 mc_memory_map;
- CARD32 vga_memory_base;
- CARD32 vga_fb_start;
-
- CARD32 vga1_cntl;
- CARD32 vga2_cntl;
-
- CARD32 crtc_master_en;
- CARD32 crtc_tv_control;
-
- CARD32 lvtma_pwrseq_cntl;
- CARD32 lvtma_pwrseq_state;
-
- struct avivo_pll_state pll1;
- struct avivo_pll_state pll2;
-
- struct avivo_crtc_state crtc1;
- struct avivo_crtc_state crtc2;
-
- struct avivo_grph_state grph1;
- struct avivo_grph_state grph2;
-
- struct avivo_dac_state daca;
- struct avivo_dac_state dacb;
-
- struct avivo_dig_state tmds1;
- struct avivo_dig_state tmds2;
-
-};
-
-/*
- * Maximum length of horizontal/vertical code timing tables for state storage
- */
-#define MAX_H_CODE_TIMING_LEN 32
-#define MAX_V_CODE_TIMING_LEN 32
-
-typedef struct {
- struct avivo_state avivo;
-
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
-
- CARD32 bios_0_scratch;
- CARD32 bios_1_scratch;
- CARD32 bios_2_scratch;
- CARD32 bios_3_scratch;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 bios_7_scratch;
-
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_agp_location_hi;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_horz_vert_active;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int reference_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int reference_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-} RADEONSaveRec, *RADEONSavePtr;
-
-#define RADEON_MAX_CRTC 2
-#define RADEON_MAX_BIOS_CONNECTOR 16
-
-typedef struct
-{
- Bool HasSecondary;
- Bool HasCRTC2; /* All cards except original Radeon */
- /*
- * The next two are used to make sure CRTC2 is restored before CRTC_EXT,
- * otherwise it could lead to blank screens.
- */
- Bool IsSecondaryRestored;
- Bool RestorePrimary;
-
- Bool ReversedDAC; /* TVDAC used as primary dac */
- Bool ReversedTMDS; /* DDC_DVI is used for external TMDS */
- xf86CrtcPtr pCrtc[RADEON_MAX_CRTC];
- RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC];
-
- ScrnInfoPtr pSecondaryScrn;
- ScrnInfoPtr pPrimaryScrn;
-
- RADEONSaveRec ModeReg; /* Current mode */
- RADEONSaveRec SavedReg; /* Original (text) mode */
-
-} RADEONEntRec, *RADEONEntPtr;
-
-/* radeon_probe.c */
-extern PciChipsets RADEONPciChipsets[];
-
-/* radeon_driver.c */
-extern Bool RADEONPreInit(ScrnInfoPtr, int);
-extern Bool RADEONScreenInit(int, ScreenPtr, int, char **);
-extern Bool RADEONSwitchMode(int, DisplayModePtr, int);
-#ifdef X_XF86MiscPassMessage
-extern Bool RADEONHandleMessage(int, const char*, const char*,
- char**);
-#endif
-extern void RADEONAdjustFrame(int, int, int, int);
-extern Bool RADEONEnterVT(int, int);
-extern void RADEONLeaveVT(int, int);
-extern void RADEONFreeScreen(int, int);
-extern ModeStatus RADEONValidMode(int, DisplayModePtr, Bool, int);
-
-extern const OptionInfoRec *RADEONOptionsWeak(void);
-
-#endif /* _RADEON_PROBE_H_ */
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
deleted file mode 100644
index 046c52b..0000000
--- a/src/radeon_reg.h
+++ /dev/null
@@ -1,4812 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Rickard E. Faith <faith at valinux.com>
- * Alan Hourihane <alanh at fairlite.demon.co.uk>
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * !!!! FIXME !!!!
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
-
-/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
- * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
- * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
-
-#ifndef _RADEON_REG_H_
-#define _RADEON_REG_H_
-
-#define ATI_DATATYPE_VQ 0
-#define ATI_DATATYPE_CI4 1
-#define ATI_DATATYPE_CI8 2
-#define ATI_DATATYPE_ARGB1555 3
-#define ATI_DATATYPE_RGB565 4
-#define ATI_DATATYPE_RGB888 5
-#define ATI_DATATYPE_ARGB8888 6
-#define ATI_DATATYPE_RGB332 7
-#define ATI_DATATYPE_Y8 8
-#define ATI_DATATYPE_RGB8 9
-#define ATI_DATATYPE_CI16 10
-#define ATI_DATATYPE_VYUY_422 11
-#define ATI_DATATYPE_YVYU_422 12
-#define ATI_DATATYPE_AYUV_444 14
-#define ATI_DATATYPE_ARGB4444 15
-
- /* Registers for 2D/Video/Overlay */
-#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
-#define RADEON_AGP_BASE 0x0170
-#define RADEON_AGP_CNTL 0x0174
-# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
-# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
-# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
-# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
-# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
-# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
-# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
-# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
-#define RADEON_STATUS_PCI_CONFIG 0x06
-# define RADEON_CAP_LIST 0x100000
-#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
-# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
-# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
-# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
-# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
-#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
-#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
-# define RADEON_AGP_ENABLE (1<<8)
-#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
-#define RADEON_AGP_STATUS 0x0f5c /* PCI */
-# define RADEON_AGP_1X_MODE 0x01
-# define RADEON_AGP_2X_MODE 0x02
-# define RADEON_AGP_4X_MODE 0x04
-# define RADEON_AGP_FW_MODE 0x10
-# define RADEON_AGP_MODE_MASK 0x17
-# define RADEON_AGPv3_MODE 0x08
-# define RADEON_AGPv3_4X_MODE 0x01
-# define RADEON_AGPv3_8X_MODE 0x02
-#define RADEON_ATTRDR 0x03c1 /* VGA */
-#define RADEON_ATTRDW 0x03c0 /* VGA */
-#define RADEON_ATTRX 0x03c0 /* VGA */
-#define RADEON_AUX_SC_CNTL 0x1660
-# define RADEON_AUX1_SC_EN (1 << 0)
-# define RADEON_AUX1_SC_MODE_OR (0 << 1)
-# define RADEON_AUX1_SC_MODE_NAND (1 << 1)
-# define RADEON_AUX2_SC_EN (1 << 2)
-# define RADEON_AUX2_SC_MODE_OR (0 << 3)
-# define RADEON_AUX2_SC_MODE_NAND (1 << 3)
-# define RADEON_AUX3_SC_EN (1 << 4)
-# define RADEON_AUX3_SC_MODE_OR (0 << 5)
-# define RADEON_AUX3_SC_MODE_NAND (1 << 5)
-#define RADEON_AUX1_SC_BOTTOM 0x1670
-#define RADEON_AUX1_SC_LEFT 0x1664
-#define RADEON_AUX1_SC_RIGHT 0x1668
-#define RADEON_AUX1_SC_TOP 0x166c
-#define RADEON_AUX2_SC_BOTTOM 0x1680
-#define RADEON_AUX2_SC_LEFT 0x1674
-#define RADEON_AUX2_SC_RIGHT 0x1678
-#define RADEON_AUX2_SC_TOP 0x167c
-#define RADEON_AUX3_SC_BOTTOM 0x1690
-#define RADEON_AUX3_SC_LEFT 0x1684
-#define RADEON_AUX3_SC_RIGHT 0x1688
-#define RADEON_AUX3_SC_TOP 0x168c
-#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
-#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
-
-#define RADEON_BASE_CODE 0x0f0b
-#define RADEON_BIOS_0_SCRATCH 0x0010
-# define RADEON_FP_PANEL_SCALABLE (1 << 16)
-# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
-# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
-# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
-# define RADEON_DISPLAY_ROT_MASK (3 << 28)
-# define RADEON_DISPLAY_ROT_00 (0 << 28)
-# define RADEON_DISPLAY_ROT_90 (1 << 28)
-# define RADEON_DISPLAY_ROT_180 (2 << 28)
-# define RADEON_DISPLAY_ROT_270 (3 << 28)
-#define RADEON_BIOS_1_SCRATCH 0x0014
-#define RADEON_BIOS_2_SCRATCH 0x0018
-#define RADEON_BIOS_3_SCRATCH 0x001c
-#define RADEON_BIOS_4_SCRATCH 0x0020
-# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
-# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
-# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
-# define RADEON_LCD1_ATTACHED (1 << 2)
-# define RADEON_DFP1_ATTACHED (1 << 3)
-# define RADEON_TV1_ATTACHED_MASK (3 << 4)
-# define RADEON_TV1_ATTACHED_COMP (1 << 4)
-# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
-# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
-# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
-# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
-# define RADEON_DFP2_ATTACHED (1 << 11)
-#define RADEON_BIOS_5_SCRATCH 0x0024
-# define RADEON_LCD1_ON (1 << 0)
-# define RADEON_CRT1_ON (1 << 1)
-# define RADEON_TV1_ON (1 << 2)
-# define RADEON_DFP1_ON (1 << 3)
-# define RADEON_CRT2_ON (1 << 5)
-# define RADEON_CV1_ON (1 << 6)
-# define RADEON_DFP2_ON (1 << 7)
-# define RADEON_LCD1_CRTC_MASK (1 << 8)
-# define RADEON_LCD1_CRTC_SHIFT 8
-# define RADEON_CRT1_CRTC_MASK (1 << 9)
-# define RADEON_CRT1_CRTC_SHIFT 9
-# define RADEON_TV1_CRTC_MASK (1 << 10)
-# define RADEON_TV1_CRTC_SHIFT 10
-# define RADEON_DFP1_CRTC_MASK (1 << 11)
-# define RADEON_DFP1_CRTC_SHIFT 11
-# define RADEON_CRT2_CRTC_MASK (1 << 12)
-# define RADEON_CRT2_CRTC_SHIFT 12
-# define RADEON_CV1_CRTC_MASK (1 << 13)
-# define RADEON_CV1_CRTC_SHIFT 13
-# define RADEON_DFP2_CRTC_MASK (1 << 14)
-# define RADEON_DFP2_CRTC_SHIFT 14
-#define RADEON_BIOS_6_SCRATCH 0x0028
-# define RADEON_ACC_MODE_CHANGE (1 << 2)
-# define RADEON_EXT_DESKTOP_MODE (1 << 3)
-# define RADEON_LCD_DPMS_ON (1 << 20)
-# define RADEON_CRT_DPMS_ON (1 << 21)
-# define RADEON_TV_DPMS_ON (1 << 22)
-# define RADEON_DFP_DPMS_ON (1 << 23)
-# define RADEON_DPMS_MASK (3 << 24)
-# define RADEON_DPMS_ON (0 << 24)
-# define RADEON_DPMS_STANDBY (1 << 24)
-# define RADEON_DPMS_SUSPEND (2 << 24)
-# define RADEON_DPMS_OFF (3 << 24)
-# define RADEON_SCREEN_BLANKING (1 << 26)
-# define RADEON_DRIVER_CRITICAL (1 << 27)
-# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
-#define RADEON_BIOS_7_SCRATCH 0x002c
-# define RADEON_SYS_HOTKEY (1 << 10)
-# define RADEON_DRV_LOADED (1 << 12)
-#define RADEON_BIOS_ROM 0x0f30 /* PCI */
-#define RADEON_BIST 0x0f0f /* PCI */
-#define RADEON_BRUSH_DATA0 0x1480
-#define RADEON_BRUSH_DATA1 0x1484
-#define RADEON_BRUSH_DATA10 0x14a8
-#define RADEON_BRUSH_DATA11 0x14ac
-#define RADEON_BRUSH_DATA12 0x14b0
-#define RADEON_BRUSH_DATA13 0x14b4
-#define RADEON_BRUSH_DATA14 0x14b8
-#define RADEON_BRUSH_DATA15 0x14bc
-#define RADEON_BRUSH_DATA16 0x14c0
-#define RADEON_BRUSH_DATA17 0x14c4
-#define RADEON_BRUSH_DATA18 0x14c8
-#define RADEON_BRUSH_DATA19 0x14cc
-#define RADEON_BRUSH_DATA2 0x1488
-#define RADEON_BRUSH_DATA20 0x14d0
-#define RADEON_BRUSH_DATA21 0x14d4
-#define RADEON_BRUSH_DATA22 0x14d8
-#define RADEON_BRUSH_DATA23 0x14dc
-#define RADEON_BRUSH_DATA24 0x14e0
-#define RADEON_BRUSH_DATA25 0x14e4
-#define RADEON_BRUSH_DATA26 0x14e8
-#define RADEON_BRUSH_DATA27 0x14ec
-#define RADEON_BRUSH_DATA28 0x14f0
-#define RADEON_BRUSH_DATA29 0x14f4
-#define RADEON_BRUSH_DATA3 0x148c
-#define RADEON_BRUSH_DATA30 0x14f8
-#define RADEON_BRUSH_DATA31 0x14fc
-#define RADEON_BRUSH_DATA32 0x1500
-#define RADEON_BRUSH_DATA33 0x1504
-#define RADEON_BRUSH_DATA34 0x1508
-#define RADEON_BRUSH_DATA35 0x150c
-#define RADEON_BRUSH_DATA36 0x1510
-#define RADEON_BRUSH_DATA37 0x1514
-#define RADEON_BRUSH_DATA38 0x1518
-#define RADEON_BRUSH_DATA39 0x151c
-#define RADEON_BRUSH_DATA4 0x1490
-#define RADEON_BRUSH_DATA40 0x1520
-#define RADEON_BRUSH_DATA41 0x1524
-#define RADEON_BRUSH_DATA42 0x1528
-#define RADEON_BRUSH_DATA43 0x152c
-#define RADEON_BRUSH_DATA44 0x1530
-#define RADEON_BRUSH_DATA45 0x1534
-#define RADEON_BRUSH_DATA46 0x1538
-#define RADEON_BRUSH_DATA47 0x153c
-#define RADEON_BRUSH_DATA48 0x1540
-#define RADEON_BRUSH_DATA49 0x1544
-#define RADEON_BRUSH_DATA5 0x1494
-#define RADEON_BRUSH_DATA50 0x1548
-#define RADEON_BRUSH_DATA51 0x154c
-#define RADEON_BRUSH_DATA52 0x1550
-#define RADEON_BRUSH_DATA53 0x1554
-#define RADEON_BRUSH_DATA54 0x1558
-#define RADEON_BRUSH_DATA55 0x155c
-#define RADEON_BRUSH_DATA56 0x1560
-#define RADEON_BRUSH_DATA57 0x1564
-#define RADEON_BRUSH_DATA58 0x1568
-#define RADEON_BRUSH_DATA59 0x156c
-#define RADEON_BRUSH_DATA6 0x1498
-#define RADEON_BRUSH_DATA60 0x1570
-#define RADEON_BRUSH_DATA61 0x1574
-#define RADEON_BRUSH_DATA62 0x1578
-#define RADEON_BRUSH_DATA63 0x157c
-#define RADEON_BRUSH_DATA7 0x149c
-#define RADEON_BRUSH_DATA8 0x14a0
-#define RADEON_BRUSH_DATA9 0x14a4
-#define RADEON_BRUSH_SCALE 0x1470
-#define RADEON_BRUSH_Y_X 0x1474
-#define RADEON_BUS_CNTL 0x0030
-# define RADEON_BUS_MASTER_DIS (1 << 6)
-# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
-# define RADEON_BUS_RD_ABORT_EN (1 << 25)
-# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
-# define RADEON_BUS_WRT_BURST (1 << 29)
-# define RADEON_BUS_READ_BURST (1 << 30)
-#define RADEON_BUS_CNTL1 0x0034
-# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
-
-#define RADEON_CACHE_CNTL 0x1724
-#define RADEON_CACHE_LINE 0x0f0c /* PCI */
-#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
-#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
-#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
-# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
-#define RADEON_CLOCK_CNTL_DATA 0x000c
-#define RADEON_CLOCK_CNTL_INDEX 0x0008
-# define RADEON_PLL_WR_EN (1 << 7)
-# define RADEON_PLL_DIV_SEL (3 << 8)
-# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
-#define RADEON_CLK_PWRMGT_CNTL 0x0014
-# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
-# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
-# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
-# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
-# define RADEON_MC_BUSY (1 << 16)
-# define RADEON_DLL_READY (1 << 19)
-# define RADEON_CG_NO1_DEBUG_0 (1 << 24)
-# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
-# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
-# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
-# define RADEON_TVCLK_TURNOFF (1 << 31)
-#define RADEON_PLL_PWRMGT_CNTL 0x0015
-# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
-#define RADEON_CLR_CMP_CLR_3D 0x1a24
-#define RADEON_CLR_CMP_CLR_DST 0x15c8
-#define RADEON_CLR_CMP_CLR_SRC 0x15c4
-#define RADEON_CLR_CMP_CNTL 0x15c0
-# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
-# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
-# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
-#define RADEON_CLR_CMP_MASK 0x15cc
-# define RADEON_CLR_CMP_MSK 0xffffffff
-#define RADEON_CLR_CMP_MASK_3D 0x1A28
-#define RADEON_COMMAND 0x0f04 /* PCI */
-#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
-#define RADEON_CONFIG_APER_0_BASE 0x0100
-#define RADEON_CONFIG_APER_1_BASE 0x0104
-#define RADEON_CONFIG_APER_SIZE 0x0108
-#define RADEON_CONFIG_BONDS 0x00e8
-#define RADEON_CONFIG_CNTL 0x00e0
-# define RADEON_CFG_ATI_REV_A11 (0 << 16)
-# define RADEON_CFG_ATI_REV_A12 (1 << 16)
-# define RADEON_CFG_ATI_REV_A13 (2 << 16)
-# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
-#define RADEON_CONFIG_MEMSIZE 0x00f8
-#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
-#define RADEON_CONFIG_REG_1_BASE 0x010c
-#define RADEON_CONFIG_REG_APER_SIZE 0x0110
-#define RADEON_CONFIG_XSTRAP 0x00e4
-#define RADEON_CONSTANT_COLOR_C 0x1d34
-# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
-# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
-# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
-#define RADEON_CRC_CMDFIFO_ADDR 0x0740
-#define RADEON_CRC_CMDFIFO_DOUT 0x0744
-#define RADEON_GRPH_BUFFER_CNTL 0x02f0
-# define RADEON_GRPH_START_REQ_MASK (0x7f)
-# define RADEON_GRPH_START_REQ_SHIFT 0
-# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
-# define RADEON_GRPH_STOP_REQ_SHIFT 8
-# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
-# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
-# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
-# define RADEON_GRPH_BUFFER_SIZE (1<<29)
-# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
-# define RADEON_GRPH_STOP_CNTL (1<<31)
-#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
-# define RADEON_GRPH2_START_REQ_MASK (0x7f)
-# define RADEON_GRPH2_START_REQ_SHIFT 0
-# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
-# define RADEON_GRPH2_STOP_REQ_SHIFT 8
-# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
-# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
-# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
-# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
-# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
-# define RADEON_GRPH2_STOP_CNTL (1<<31)
-#define RADEON_CRTC_CRNT_FRAME 0x0214
-#define RADEON_CRTC_EXT_CNTL 0x0054
-# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
-# define RADEON_VGA_ATI_LINEAR (1 << 3)
-# define RADEON_XCRT_CNT_EN (1 << 6)
-# define RADEON_CRTC_HSYNC_DIS (1 << 8)
-# define RADEON_CRTC_VSYNC_DIS (1 << 9)
-# define RADEON_CRTC_DISPLAY_DIS (1 << 10)
-# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
-# define RADEON_CRTC_CRT_ON (1 << 15)
-#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
-# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
-# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
-# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
-#define RADEON_CRTC_GEN_CNTL 0x0050
-# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
-# define RADEON_CRTC_INTERLACE_EN (1 << 1)
-# define RADEON_CRTC_CSYNC_EN (1 << 4)
-# define RADEON_CRTC_ICON_EN (1 << 15)
-# define RADEON_CRTC_CUR_EN (1 << 16)
-# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
-# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
-# define RADEON_CRTC_EN (1 << 25)
-# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
-#define RADEON_CRTC2_GEN_CNTL 0x03f8
-# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
-# define RADEON_CRTC2_INTERLACE_EN (1 << 1)
-# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
-# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
-# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
-# define RADEON_CRTC2_CRT2_ON (1 << 7)
-# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
-# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
-# define RADEON_CRTC2_ICON_EN (1 << 15)
-# define RADEON_CRTC2_CUR_EN (1 << 16)
-# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
-# define RADEON_CRTC2_DISP_DIS (1 << 23)
-# define RADEON_CRTC2_EN (1 << 25)
-# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
-# define RADEON_CRTC2_CSYNC_EN (1 << 27)
-# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
-# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
-#define RADEON_CRTC_MORE_CNTL 0x27c
-# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
-# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
-# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
-# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
-#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
-#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
-# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
-# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
-# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
-# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
-# define RADEON_CRTC_H_SYNC_WID_SHIFT 16
-# define RADEON_CRTC_H_SYNC_POL (1 << 23)
-#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
-# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
-# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
-# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
-# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
-# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
-# define RADEON_CRTC2_H_SYNC_POL (1 << 23)
-#define RADEON_CRTC_H_TOTAL_DISP 0x0200
-# define RADEON_CRTC_H_TOTAL (0x03ff << 0)
-# define RADEON_CRTC_H_TOTAL_SHIFT 0
-# define RADEON_CRTC_H_DISP (0x01ff << 16)
-# define RADEON_CRTC_H_DISP_SHIFT 16
-#define RADEON_CRTC2_H_TOTAL_DISP 0x0300
-# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
-# define RADEON_CRTC2_H_TOTAL_SHIFT 0
-# define RADEON_CRTC2_H_DISP (0x01ff << 16)
-# define RADEON_CRTC2_H_DISP_SHIFT 16
-
-#define RADEON_CRTC_OFFSET_RIGHT 0x0220
-#define RADEON_CRTC_OFFSET 0x0224
-# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
-# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
-
-#define RADEON_CRTC2_OFFSET 0x0324
-# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
-# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
-#define RADEON_CRTC_OFFSET_CNTL 0x0228
-# define RADEON_CRTC_TILE_LINE_SHIFT 0
-# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
-# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
-# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
-# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
-# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
-# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
-# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
-# define R300_CRTC_X_Y_MODE_EN (1 << 9)
-# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
-# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
-# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
-# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
-# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
-# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
-# define R300_CRTC_MICRO_TILE_EN (1 << 13)
-# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
-# define R300_CRTC_MACRO_TILE_EN (1 << 15)
-# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
-# define RADEON_CRTC_TILE_EN (1 << 15)
-# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
-# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
-
-#define R300_CRTC_TILE_X0_Y0 0x0350
-#define R300_CRTC2_TILE_X0_Y0 0x0358
-
-#define RADEON_CRTC2_OFFSET_CNTL 0x0328
-# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
-# define RADEON_CRTC2_TILE_EN (1 << 15)
-#define RADEON_CRTC_PITCH 0x022c
-# define RADEON_CRTC_PITCH__SHIFT 0
-# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16
-
-#define RADEON_CRTC2_PITCH 0x032c
-#define RADEON_CRTC_STATUS 0x005c
-# define RADEON_CRTC_VBLANK_SAVE (1 << 1)
-# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
-#define RADEON_CRTC2_STATUS 0x03fc
-# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
-# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
-#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
-# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
-# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
-# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
-# define RADEON_CRTC_V_SYNC_WID_SHIFT 16
-# define RADEON_CRTC_V_SYNC_POL (1 << 23)
-#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
-# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
-# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
-# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
-# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
-# define RADEON_CRTC2_V_SYNC_POL (1 << 23)
-#define RADEON_CRTC_V_TOTAL_DISP 0x0208
-# define RADEON_CRTC_V_TOTAL (0x07ff << 0)
-# define RADEON_CRTC_V_TOTAL_SHIFT 0
-# define RADEON_CRTC_V_DISP (0x07ff << 16)
-# define RADEON_CRTC_V_DISP_SHIFT 16
-#define RADEON_CRTC2_V_TOTAL_DISP 0x0308
-# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
-# define RADEON_CRTC2_V_TOTAL_SHIFT 0
-# define RADEON_CRTC2_V_DISP (0x07ff << 16)
-# define RADEON_CRTC2_V_DISP_SHIFT 16
-#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
-# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
-#define RADEON_CRTC2_CRNT_FRAME 0x0314
-#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
-#define RADEON_CRTC2_STATUS 0x03fc
-#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
-#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
-#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
-#define RADEON_CUR_CLR0 0x026c
-#define RADEON_CUR_CLR1 0x0270
-#define RADEON_CUR_HORZ_VERT_OFF 0x0268
-#define RADEON_CUR_HORZ_VERT_POSN 0x0264
-#define RADEON_CUR_OFFSET 0x0260
-# define RADEON_CUR_LOCK (1 << 31)
-#define RADEON_CUR2_CLR0 0x036c
-#define RADEON_CUR2_CLR1 0x0370
-#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
-#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
-#define RADEON_CUR2_OFFSET 0x0360
-# define RADEON_CUR2_LOCK (1 << 31)
-
-#define RADEON_DAC_CNTL 0x0058
-# define RADEON_DAC_RANGE_CNTL (3 << 0)
-# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
-# define RADEON_DAC_RANGE_CNTL_MASK 0x03
-# define RADEON_DAC_BLANKING (1 << 2)
-# define RADEON_DAC_CMP_EN (1 << 3)
-# define RADEON_DAC_CMP_OUTPUT (1 << 7)
-# define RADEON_DAC_8BIT_EN (1 << 8)
-# define RADEON_DAC_TVO_EN (1 << 10)
-# define RADEON_DAC_VGA_ADR_EN (1 << 13)
-# define RADEON_DAC_PDWN (1 << 15)
-# define RADEON_DAC_MASK_ALL (0xff << 24)
-#define RADEON_DAC_CNTL2 0x007c
-# define RADEON_DAC2_TV_CLK_SEL (0 << 1)
-# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
-# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
-# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
-# define RADEON_DAC2_CMP_EN (1 << 7)
-# define RADEON_DAC2_CMP_OUT_R (1 << 8)
-# define RADEON_DAC2_CMP_OUT_G (1 << 9)
-# define RADEON_DAC2_CMP_OUT_B (1 << 10)
-# define RADEON_DAC2_CMP_OUTPUT (1 << 11)
-#define RADEON_DAC_EXT_CNTL 0x0280
-# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
-# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
-# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
-# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
-# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
-# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
-# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
-# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
-# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
-# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
-# define RADEON_DAC_FORCE_DATA_SHIFT 8
-#define RADEON_DAC_MACRO_CNTL 0x0d04
-# define RADEON_DAC_PDWN_R (1 << 16)
-# define RADEON_DAC_PDWN_G (1 << 17)
-# define RADEON_DAC_PDWN_B (1 << 18)
-#define RADEON_TV_DAC_CNTL 0x088c
-# define RADEON_TV_DAC_NBLANK (1 << 0)
-# define RADEON_TV_DAC_NHOLD (1 << 1)
-# define RADEON_TV_DAC_PEDESTAL (1 << 2)
-# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
-# define RADEON_TV_DAC_CMPOUT (1 << 5)
-# define RADEON_TV_DAC_STD_MASK (3 << 8)
-# define RADEON_TV_DAC_STD_PAL (0 << 8)
-# define RADEON_TV_DAC_STD_NTSC (1 << 8)
-# define RADEON_TV_DAC_STD_PS2 (2 << 8)
-# define RADEON_TV_DAC_STD_RS343 (3 << 8)
-# define RADEON_TV_DAC_BGSLEEP (1 << 6)
-# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
-# define RADEON_TV_DAC_BGADJ_SHIFT 16
-# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
-# define RADEON_TV_DAC_DACADJ_SHIFT 20
-# define RADEON_TV_DAC_RDACPD (1 << 24)
-# define RADEON_TV_DAC_GDACPD (1 << 25)
-# define RADEON_TV_DAC_BDACPD (1 << 26)
-# define RADEON_TV_DAC_RDACDET (1 << 29)
-# define RADEON_TV_DAC_GDACDET (1 << 30)
-# define RADEON_TV_DAC_BDACDET (1 << 31)
-# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
-# define R420_TV_DAC_RDACPD (1 << 25)
-# define R420_TV_DAC_GDACPD (1 << 26)
-# define R420_TV_DAC_BDACPD (1 << 27)
-# define R420_TV_DAC_TVENABLE (1 << 28)
-#define RADEON_DISP_HW_DEBUG 0x0d14
-# define RADEON_CRT2_DISP1_SEL (1 << 5)
-#define RADEON_DISP_OUTPUT_CNTL 0x0d64
-# define RADEON_DISP_DAC_SOURCE_MASK 0x03
-# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
-# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
-# define RADEON_DISP_DAC_SOURCE_RMX 0x02
-# define RADEON_DISP_DAC_SOURCE_LTU 0x03
-# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
-# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
-# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
-# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
-# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
-# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
-# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
-# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
-# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
-# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
-# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
-# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
-#define RADEON_DISP_TV_OUT_CNTL 0x0d6c
-# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
-# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
-#define RADEON_DAC_CRC_SIG 0x02cc
-#define RADEON_DAC_DATA 0x03c9 /* VGA */
-#define RADEON_DAC_MASK 0x03c6 /* VGA */
-#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
-#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
-#define RADEON_DDA_CONFIG 0x02e0
-#define RADEON_DDA_ON_OFF 0x02e4
-#define RADEON_DEFAULT_OFFSET 0x16e0
-#define RADEON_DEFAULT_PITCH 0x16e4
-#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
-# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
-# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
-#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
-#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
-#define RADEON_DEVICE_ID 0x0f02 /* PCI */
-#define RADEON_DISP_MISC_CNTL 0x0d00
-# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
-#define RADEON_DISP_MERGE_CNTL 0x0d60
-# define RADEON_DISP_ALPHA_MODE_MASK 0x03
-# define RADEON_DISP_ALPHA_MODE_KEY 0
-# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
-# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
-# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
-# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
-# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
-# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
-#define RADEON_DISP2_MERGE_CNTL 0x0d68
-# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
-#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
-#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
-#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
-#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
-#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
-#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
-#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
-#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
-#define RADEON_DP_CNTL 0x16c0
-# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
-# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
-# define RADEON_DP_DST_TILE_LINEAR (0 << 3)
-# define RADEON_DP_DST_TILE_MACRO (1 << 3)
-# define RADEON_DP_DST_TILE_MICRO (2 << 3)
-# define RADEON_DP_DST_TILE_BOTH (3 << 3)
-#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
-# define RADEON_DST_Y_MAJOR (1 << 2)
-# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
-# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
-#define RADEON_DP_DATATYPE 0x16c4
-# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
-#define RADEON_DP_GUI_MASTER_CNTL 0x146c
-# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
-# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
-# define RADEON_GMC_SRC_CLIPPING (1 << 2)
-# define RADEON_GMC_DST_CLIPPING (1 << 3)
-# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
-# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
-# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
-# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
-# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
-# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
-# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
-# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
-# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
-# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
-# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
-# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
-# define RADEON_GMC_BRUSH_NONE (15 << 4)
-# define RADEON_GMC_DST_8BPP_CI (2 << 8)
-# define RADEON_GMC_DST_15BPP (3 << 8)
-# define RADEON_GMC_DST_16BPP (4 << 8)
-# define RADEON_GMC_DST_24BPP (5 << 8)
-# define RADEON_GMC_DST_32BPP (6 << 8)
-# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
-# define RADEON_GMC_DST_Y8 (8 << 8)
-# define RADEON_GMC_DST_RGB8 (9 << 8)
-# define RADEON_GMC_DST_VYUY (11 << 8)
-# define RADEON_GMC_DST_YVYU (12 << 8)
-# define RADEON_GMC_DST_AYUV444 (14 << 8)
-# define RADEON_GMC_DST_ARGB4444 (15 << 8)
-# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
-# define RADEON_GMC_DST_DATATYPE_SHIFT 8
-# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
-# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
-# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
-# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
-# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
-# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
-# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
-# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
-# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
-# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
-# define RADEON_GMC_ROP3_MASK (0xff << 16)
-# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
-# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
-# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
-# define RADEON_GMC_3D_FCN_EN (1 << 27)
-# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
-# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
-# define RADEON_GMC_WR_MSK_DIS (1 << 30)
-# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
-# define RADEON_ROP3_ZERO 0x00000000
-# define RADEON_ROP3_DSa 0x00880000
-# define RADEON_ROP3_SDna 0x00440000
-# define RADEON_ROP3_S 0x00cc0000
-# define RADEON_ROP3_DSna 0x00220000
-# define RADEON_ROP3_D 0x00aa0000
-# define RADEON_ROP3_DSx 0x00660000
-# define RADEON_ROP3_DSo 0x00ee0000
-# define RADEON_ROP3_DSon 0x00110000
-# define RADEON_ROP3_DSxn 0x00990000
-# define RADEON_ROP3_Dn 0x00550000
-# define RADEON_ROP3_SDno 0x00dd0000
-# define RADEON_ROP3_Sn 0x00330000
-# define RADEON_ROP3_DSno 0x00bb0000
-# define RADEON_ROP3_DSan 0x00770000
-# define RADEON_ROP3_ONE 0x00ff0000
-# define RADEON_ROP3_DPa 0x00a00000
-# define RADEON_ROP3_PDna 0x00500000
-# define RADEON_ROP3_P 0x00f00000
-# define RADEON_ROP3_DPna 0x000a0000
-# define RADEON_ROP3_D 0x00aa0000
-# define RADEON_ROP3_DPx 0x005a0000
-# define RADEON_ROP3_DPo 0x00fa0000
-# define RADEON_ROP3_DPon 0x00050000
-# define RADEON_ROP3_PDxn 0x00a50000
-# define RADEON_ROP3_PDno 0x00f50000
-# define RADEON_ROP3_Pn 0x000f0000
-# define RADEON_ROP3_DPno 0x00af0000
-# define RADEON_ROP3_DPan 0x005f0000
-#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
-#define RADEON_DP_MIX 0x16c8
-#define RADEON_DP_SRC_BKGD_CLR 0x15dc
-#define RADEON_DP_SRC_FRGD_CLR 0x15d8
-#define RADEON_DP_WRITE_MASK 0x16cc
-#define RADEON_DST_BRES_DEC 0x1630
-#define RADEON_DST_BRES_ERR 0x1628
-#define RADEON_DST_BRES_INC 0x162c
-#define RADEON_DST_BRES_LNTH 0x1634
-#define RADEON_DST_BRES_LNTH_SUB 0x1638
-#define RADEON_DST_HEIGHT 0x1410
-#define RADEON_DST_HEIGHT_WIDTH 0x143c
-#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
-#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
-#define RADEON_DST_HEIGHT_Y 0x15a0
-#define RADEON_DST_LINE_START 0x1600
-#define RADEON_DST_LINE_END 0x1604
-#define RADEON_DST_LINE_PATCOUNT 0x1608
-# define RADEON_BRES_CNTL_SHIFT 8
-#define RADEON_DST_OFFSET 0x1404
-#define RADEON_DST_PITCH 0x1408
-#define RADEON_DST_PITCH_OFFSET 0x142c
-#define RADEON_DST_PITCH_OFFSET_C 0x1c80
-# define RADEON_PITCH_SHIFT 21
-# define RADEON_DST_TILE_LINEAR (0 << 30)
-# define RADEON_DST_TILE_MACRO (1 << 30)
-# define RADEON_DST_TILE_MICRO (2 << 30)
-# define RADEON_DST_TILE_BOTH (3 << 30)
-#define RADEON_DST_WIDTH 0x140c
-#define RADEON_DST_WIDTH_HEIGHT 0x1598
-#define RADEON_DST_WIDTH_X 0x1588
-#define RADEON_DST_WIDTH_X_INCY 0x159c
-#define RADEON_DST_X 0x141c
-#define RADEON_DST_X_SUB 0x15a4
-#define RADEON_DST_X_Y 0x1594
-#define RADEON_DST_Y 0x1420
-#define RADEON_DST_Y_SUB 0x15a8
-#define RADEON_DST_Y_X 0x1438
-
-#define RADEON_FCP_CNTL 0x0910
-# define RADEON_FCP0_SRC_PCICLK 0
-# define RADEON_FCP0_SRC_PCLK 1
-# define RADEON_FCP0_SRC_PCLKb 2
-# define RADEON_FCP0_SRC_HREF 3
-# define RADEON_FCP0_SRC_GND 4
-# define RADEON_FCP0_SRC_HREFb 5
-#define RADEON_FLUSH_1 0x1704
-#define RADEON_FLUSH_2 0x1708
-#define RADEON_FLUSH_3 0x170c
-#define RADEON_FLUSH_4 0x1710
-#define RADEON_FLUSH_5 0x1714
-#define RADEON_FLUSH_6 0x1718
-#define RADEON_FLUSH_7 0x171c
-#define RADEON_FOG_3D_TABLE_START 0x1810
-#define RADEON_FOG_3D_TABLE_END 0x1814
-#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
-#define RADEON_FOG_TABLE_INDEX 0x1a14
-#define RADEON_FOG_TABLE_DATA 0x1a18
-#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
-#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
-# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
-# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
-# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
-# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
-# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
-# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
-# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
-# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
-# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
-# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
-# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
-# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
-# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
-# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
-# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
-# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
-#define RADEON_FP_GEN_CNTL 0x0284
-# define RADEON_FP_FPON (1 << 0)
-# define RADEON_FP_BLANK_EN (1 << 1)
-# define RADEON_FP_TMDS_EN (1 << 2)
-# define RADEON_FP_PANEL_FORMAT (1 << 3)
-# define RADEON_FP_EN_TMDS (1 << 7)
-# define RADEON_FP_DETECT_SENSE (1 << 8)
-# define R200_FP_SOURCE_SEL_MASK (3 << 10)
-# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
-# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
-# define R200_FP_SOURCE_SEL_RMX (2 << 10)
-# define R200_FP_SOURCE_SEL_TRANS (3 << 10)
-# define RADEON_FP_SEL_CRTC1 (0 << 13)
-# define RADEON_FP_SEL_CRTC2 (1 << 13)
-# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
-# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
-# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
-# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
-# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
-# define RADEON_FP_DFP_SYNC_SEL (1 << 21)
-# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
-# define RADEON_FP_CRT_SYNC_SEL (1 << 23)
-# define RADEON_FP_USE_SHADOW_EN (1 << 24)
-# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
-#define RADEON_FP2_GEN_CNTL 0x0288
-# define RADEON_FP2_BLANK_EN (1 << 1)
-# define RADEON_FP2_ON (1 << 2)
-# define RADEON_FP2_PANEL_FORMAT (1 << 3)
-# define RADEON_FP2_DETECT_SENSE (1 << 8)
-# define R200_FP2_SOURCE_SEL_MASK (3 << 10)
-# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
-# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
-# define R200_FP2_SOURCE_SEL_RMX (2 << 10)
-# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
-# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
-# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
-# define RADEON_FP2_FP_POL (1 << 16)
-# define RADEON_FP2_LP_POL (1 << 17)
-# define RADEON_FP2_SCK_POL (1 << 18)
-# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
-# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
-# define RADEON_FP2_CRC_EN (1 << 23)
-# define RADEON_FP2_CRC_READ_EN (1 << 24)
-# define RADEON_FP2_DVO_EN (1 << 25)
-# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
-# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
-# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
-# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
-#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
-#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
-#define RADEON_FP_HORZ_STRETCH 0x028c
-#define RADEON_FP_HORZ2_STRETCH 0x038c
-# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
-# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
-# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
-# define RADEON_HORZ_PANEL_SHIFT 16
-# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
-# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
-# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
-# define RADEON_HORZ_AUTO_RATIO (1 << 27)
-# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
-# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
-#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
-#define RADEON_FP_V_SYNC_STRT_WID 0x02c8
-#define RADEON_FP_VERT_STRETCH 0x0290
-#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
-#define RADEON_FP_VERT2_STRETCH 0x0390
-# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
-# define RADEON_VERT_PANEL_SHIFT 12
-# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
-# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
-# define RADEON_VERT_STRETCH_RATIO_MAX 4096
-# define RADEON_VERT_STRETCH_ENABLE (1 << 25)
-# define RADEON_VERT_STRETCH_LINEREP (0 << 26)
-# define RADEON_VERT_STRETCH_BLEND (1 << 26)
-# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
-# define RADEON_VERT_STRETCH_RESERVED 0xf1000000
-
-#define RADEON_GEN_INT_CNTL 0x0040
-#define RADEON_GEN_INT_STATUS 0x0044
-# define RADEON_VSYNC_INT_AK (1 << 2)
-# define RADEON_VSYNC_INT (1 << 2)
-# define RADEON_VSYNC2_INT_AK (1 << 6)
-# define RADEON_VSYNC2_INT (1 << 6)
-#define RADEON_GENENB 0x03c3 /* VGA */
-#define RADEON_GENFC_RD 0x03ca /* VGA */
-#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
-#define RADEON_GENMO_RD 0x03cc /* VGA */
-#define RADEON_GENMO_WT 0x03c2 /* VGA */
-#define RADEON_GENS0 0x03c2 /* VGA */
-#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
-#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */
-#define RADEON_GPIO_MONIDB 0x006c
-#define RADEON_GPIO_CRT2_DDC 0x006c
-#define RADEON_GPIO_DVI_DDC 0x0064
-#define RADEON_GPIO_VGA_DDC 0x0060
-# define RADEON_GPIO_A_0 (1 << 0)
-# define RADEON_GPIO_A_1 (1 << 1)
-# define RADEON_GPIO_Y_0 (1 << 8)
-# define RADEON_GPIO_Y_1 (1 << 9)
-# define RADEON_GPIO_Y_SHIFT_0 8
-# define RADEON_GPIO_Y_SHIFT_1 9
-# define RADEON_GPIO_EN_0 (1 << 16)
-# define RADEON_GPIO_EN_1 (1 << 17)
-# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
-# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
-#define RADEON_GRPH8_DATA 0x03cf /* VGA */
-#define RADEON_GRPH8_IDX 0x03ce /* VGA */
-#define RADEON_GUI_SCRATCH_REG0 0x15e0
-#define RADEON_GUI_SCRATCH_REG1 0x15e4
-#define RADEON_GUI_SCRATCH_REG2 0x15e8
-#define RADEON_GUI_SCRATCH_REG3 0x15ec
-#define RADEON_GUI_SCRATCH_REG4 0x15f0
-#define RADEON_GUI_SCRATCH_REG5 0x15f4
-
-#define RADEON_HEADER 0x0f0e /* PCI */
-#define RADEON_HOST_DATA0 0x17c0
-#define RADEON_HOST_DATA1 0x17c4
-#define RADEON_HOST_DATA2 0x17c8
-#define RADEON_HOST_DATA3 0x17cc
-#define RADEON_HOST_DATA4 0x17d0
-#define RADEON_HOST_DATA5 0x17d4
-#define RADEON_HOST_DATA6 0x17d8
-#define RADEON_HOST_DATA7 0x17dc
-#define RADEON_HOST_DATA_LAST 0x17e0
-#define RADEON_HOST_PATH_CNTL 0x0130
-# define RADEON_HDP_SOFT_RESET (1 << 26)
-# define RADEON_HDP_APER_CNTL (1 << 23)
-#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
-# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
-#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
-
- /* Multimedia I2C bus */
-#define RADEON_I2C_CNTL_0 0x0090
-#define RADEON_I2C_DONE (1<<0)
-#define RADEON_I2C_NACK (1<<1)
-#define RADEON_I2C_HALT (1<<2)
-#define RADEON_I2C_SOFT_RST (1<<5)
-#define RADEON_I2C_DRIVE_EN (1<<6)
-#define RADEON_I2C_DRIVE_SEL (1<<7)
-#define RADEON_I2C_START (1<<8)
-#define RADEON_I2C_STOP (1<<9)
-#define RADEON_I2C_RECEIVE (1<<10)
-#define RADEON_I2C_ABORT (1<<11)
-#define RADEON_I2C_GO (1<<12)
-#define RADEON_I2C_CNTL_1 0x0094
-#define RADEON_I2C_SEL (1<<16)
-#define RADEON_I2C_EN (1<<17)
-#define RADEON_I2C_DATA 0x0098
-
-#define RADEON_DVI_I2C_CNTL_0 0x02e0
-#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */
-#define RADEON_DVI_I2C_DATA 0x02e8
-
-#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
-#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
-#define RADEON_IO_BASE 0x0f14 /* PCI */
-
-#define RADEON_LATENCY 0x0f0d /* PCI */
-#define RADEON_LEAD_BRES_DEC 0x1608
-#define RADEON_LEAD_BRES_LNTH 0x161c
-#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
-#define RADEON_LVDS_GEN_CNTL 0x02d0
-# define RADEON_LVDS_ON (1 << 0)
-# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
-# define RADEON_LVDS_PANEL_TYPE (1 << 2)
-# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
-# define RADEON_LVDS_RST_FM (1 << 6)
-# define RADEON_LVDS_EN (1 << 7)
-# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
-# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
-# define RADEON_LVDS_BL_MOD_EN (1 << 16)
-# define RADEON_LVDS_DIGON (1 << 18)
-# define RADEON_LVDS_BLON (1 << 19)
-# define RADEON_LVDS_SEL_CRTC2 (1 << 23)
-#define RADEON_LVDS_PLL_CNTL 0x02d4
-# define RADEON_HSYNC_DELAY_SHIFT 28
-# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
-# define RADEON_LVDS_PLL_EN (1 << 16)
-# define RADEON_LVDS_PLL_RESET (1 << 17)
-# define R300_LVDS_SRC_SEL_MASK (3 << 18)
-# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
-# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
-# define R300_LVDS_SRC_SEL_RMX (2 << 18)
-
-#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
-#define RADEON_MC_AGP_LOCATION 0x014c
-#define RADEON_MC_FB_LOCATION 0x0148
-#define RADEON_DISPLAY_BASE_ADDR 0x23c
-#define RADEON_DISPLAY2_BASE_ADDR 0x33c
-#define RADEON_OV0_BASE_ADDR 0x43c
-#define RADEON_NB_TOM 0x15c
-#define R300_MC_INIT_MISC_LAT_TIMER 0x180
-#define RADEON_MCLK_CNTL 0x0012 /* PLL */
-# define RADEON_FORCEON_MCLKA (1 << 16)
-# define RADEON_FORCEON_MCLKB (1 << 17)
-# define RADEON_FORCEON_YCLKA (1 << 18)
-# define RADEON_FORCEON_YCLKB (1 << 19)
-# define RADEON_FORCEON_MC (1 << 20)
-# define RADEON_FORCEON_AIC (1 << 21)
-# define R300_DISABLE_MC_MCLKA (1 << 21)
-# define R300_DISABLE_MC_MCLKB (1 << 21)
-#define RADEON_MCLK_MISC 0x001f /* PLL */
-# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
-# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
-# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
-# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
-#define RADEON_LCD_GPIO_MASK 0x01a0
-#define RADEON_LCD_GPIO_Y_REG 0x01a4
-#define RADEON_MDGPIO_A_REG 0x01ac
-#define RADEON_MDGPIO_EN_REG 0x01b0
-#define RADEON_MDGPIO_MASK 0x0198
-#define RADEON_GPIOPAD_A 0x019c
-#define RADEON_MDGPIO_Y_REG 0x01b4
-#define RADEON_MEM_ADDR_CONFIG 0x0148
-#define RADEON_MEM_BASE 0x0f10 /* PCI */
-#define RADEON_MEM_CNTL 0x0140
-# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
-# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
-# define RV100_HALF_MODE (1 << 3)
-# define R300_MEM_NUM_CHANNELS_MASK 0x03
-# define R300_MEM_USE_CD_CH_ONLY (1 << 2)
-#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
-#define RADEON_MEM_INIT_LAT_TIMER 0x0154
-#define RADEON_MEM_INTF_CNTL 0x014c
-#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-# define RADEON_SDRAM_MODE_MASK 0xffff0000
-# define RADEON_B3MEM_RESET_MASK 0x6fffffff
-#define RADEON_MEM_STR_CNTL 0x0150
-# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
-# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
-# define R300_MEM_PWRUP_COMPL_C (1 << 2)
-# define R300_MEM_PWRUP_COMPL_D (1 << 3)
-# define RADEON_MEM_PWRUP_COMPLETE 0x03
-# define R300_MEM_PWRUP_COMPLETE 0x0f
-#define RADEON_MC_STATUS 0x0150
-# define RADEON_MC_IDLE (1 << 2)
-# define R300_MC_IDLE (1 << 4)
-#define RADEON_MEM_VGA_RP_SEL 0x003c
-#define RADEON_MEM_VGA_WP_SEL 0x0038
-#define RADEON_MIN_GRANT 0x0f3e /* PCI */
-#define RADEON_MM_DATA 0x0004
-#define RADEON_MM_INDEX 0x0000
-#define RADEON_MPLL_CNTL 0x000e /* PLL */
-#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
-#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
-#define R300_MC_IND_INDEX 0x01f8
-# define R300_MC_IND_ADDR_MASK 0x3f
-# define R300_MC_IND_WR_EN (1 << 8)
-#define R300_MC_IND_DATA 0x01fc
-#define R300_MC_READ_CNTL_AB 0x017c
-# define R300_MEM_RBS_POSITION_A_MASK 0x03
-#define R300_MC_READ_CNTL_CD_mcind 0x24
-# define R300_MEM_RBS_POSITION_C_MASK 0x03
-
-#define RADEON_N_VIF_COUNT 0x0248
-
-#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
-# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
-# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
-# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
-# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
-# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
-# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
-# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
-# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
-# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
-# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
-
-#define RADEON_OV0_COLOUR_CNTL 0x04E0
-#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
-#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
-# define RADEON_EXCL_HORZ_START_MASK 0x000000ff
-# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
-# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
-# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
-#define RADEON_OV0_EXCLUSIVE_VERT 0x040C
-# define RADEON_EXCL_VERT_START_MASK 0x000003ff
-# define RADEON_EXCL_VERT_END_MASK 0x03ff0000
-#define RADEON_OV0_FILTER_CNTL 0x04A0
-# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
-# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
-# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
-# define RADEON_FILTER_HC_COEF_VERT_Y 0x4
-# define RADEON_FILTER_HC_COEF_VERT_UV 0x8
-# define RADEON_FILTER_HARDCODED_COEF 0xf
-# define RADEON_FILTER_COEF_MASK 0xf
-
-#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
-#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
-#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
-#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
-#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
-#define RADEON_OV0_FLAG_CNTL 0x04DC
-#define RADEON_OV0_GAMMA_000_00F 0x0d40
-#define RADEON_OV0_GAMMA_010_01F 0x0d44
-#define RADEON_OV0_GAMMA_020_03F 0x0d48
-#define RADEON_OV0_GAMMA_040_07F 0x0d4c
-#define RADEON_OV0_GAMMA_080_0BF 0x0e00
-#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
-#define RADEON_OV0_GAMMA_100_13F 0x0e08
-#define RADEON_OV0_GAMMA_140_17F 0x0e0c
-#define RADEON_OV0_GAMMA_180_1BF 0x0e10
-#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
-#define RADEON_OV0_GAMMA_200_23F 0x0e18
-#define RADEON_OV0_GAMMA_240_27F 0x0e1c
-#define RADEON_OV0_GAMMA_280_2BF 0x0e20
-#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
-#define RADEON_OV0_GAMMA_300_33F 0x0e28
-#define RADEON_OV0_GAMMA_340_37F 0x0e2c
-#define RADEON_OV0_GAMMA_380_3BF 0x0d50
-#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
-#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
-#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
-#define RADEON_OV0_H_INC 0x0480
-#define RADEON_OV0_KEY_CNTL 0x04F4
-# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
-# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
-# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
-# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
-# define RADEON_VIDEO_KEY_FN_NE 0x00000003L
-# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
-# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
-# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
-# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
-# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
-# define RADEON_CMP_MIX_MASK 0x00000100L
-# define RADEON_CMP_MIX_OR 0x00000000L
-# define RADEON_CMP_MIX_AND 0x00000100L
-#define RADEON_OV0_LIN_TRANS_A 0x0d20
-#define RADEON_OV0_LIN_TRANS_B 0x0d24
-#define RADEON_OV0_LIN_TRANS_C 0x0d28
-#define RADEON_OV0_LIN_TRANS_D 0x0d2c
-#define RADEON_OV0_LIN_TRANS_E 0x0d30
-#define RADEON_OV0_LIN_TRANS_F 0x0d34
-#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
-# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
-# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
-#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
-#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
-# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
-# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
-#define RADEON_OV0_P1_X_START_END 0x0494
-#define RADEON_OV0_P2_X_START_END 0x0498
-#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
-# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
-# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
-#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
-#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
-#define RADEON_OV0_P3_X_START_END 0x049C
-#define RADEON_OV0_REG_LOAD_CNTL 0x0410
-# define RADEON_REG_LD_CTL_LOCK 0x00000001L
-# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
-# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
-# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
-# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
-#define RADEON_OV0_SCALE_CNTL 0x0420
-# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
-# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
-# define RADEON_SCALER_SIGNED_UV 0x00000010L
-# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
-# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
-# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
-# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
-# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
-# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
-# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
-# define RADEON_SCALER_SOURCE_15BPP 0x00000300L
-# define RADEON_SCALER_SOURCE_16BPP 0x00000400L
-# define RADEON_SCALER_SOURCE_32BPP 0x00000600L
-# define RADEON_SCALER_SOURCE_YUV9 0x00000900L
-# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
-# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
-# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
-# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
-# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
-# define RADEON_SCALER_CRTC_SEL 0x00004000L
-# define RADEON_SCALER_SMART_SWITCH 0x00008000L
-# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
-# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
-# define RADEON_SCALER_DIS_LIMIT 0x08000000L
-# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
-# define RADEON_SCALER_INT_EMU 0x20000000L
-# define RADEON_SCALER_ENABLE 0x40000000L
-# define RADEON_SCALER_SOFT_RESET 0x80000000L
-#define RADEON_OV0_STEP_BY 0x0484
-#define RADEON_OV0_TEST 0x04F8
-#define RADEON_OV0_V_INC 0x0424
-#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
-#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
-#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
-# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
-# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
-# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
-# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
-#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
-# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
-# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
-# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
-# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
-#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
-# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
-# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
-# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
-# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
-#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
-#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
-#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
-#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
-#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
-#define RADEON_OV0_Y_X_START 0x0400
-#define RADEON_OV0_Y_X_END 0x0404
-#define RADEON_OV1_Y_X_START 0x0600
-#define RADEON_OV1_Y_X_END 0x0604
-#define RADEON_OVR_CLR 0x0230
-#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
-#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
-
-/* first capture unit */
-
-#define RADEON_CAP0_BUF0_OFFSET 0x0920
-#define RADEON_CAP0_BUF1_OFFSET 0x0924
-#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
-#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
-
-#define RADEON_CAP0_BUF_PITCH 0x0930
-#define RADEON_CAP0_V_WINDOW 0x0934
-#define RADEON_CAP0_H_WINDOW 0x0938
-#define RADEON_CAP0_VBI0_OFFSET 0x093C
-#define RADEON_CAP0_VBI1_OFFSET 0x0940
-#define RADEON_CAP0_VBI_V_WINDOW 0x0944
-#define RADEON_CAP0_VBI_H_WINDOW 0x0948
-#define RADEON_CAP0_PORT_MODE_CNTL 0x094C
-#define RADEON_CAP0_TRIG_CNTL 0x0950
-#define RADEON_CAP0_DEBUG 0x0954
-#define RADEON_CAP0_CONFIG 0x0958
-# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
-# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
-# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
-# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
-# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
-# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
-# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
-# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
-# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
-# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
-# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
-# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
-# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
-# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
-# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
-# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
-# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
-# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
-# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
-# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
-# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
-# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
-# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
-# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
-# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
-# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
-# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
-# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
-# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
-# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
-# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
-# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
-# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
-#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
-#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
-#define RADEON_CAP0_ANC_H_WINDOW 0x0964
-#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
-#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
-#define RADEON_CAP0_BUF_STATUS 0x0970
-/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
-/* #define RADEON_CAP0_XSHARPNESS 0x097C */
-#define RADEON_CAP0_VBI2_OFFSET 0x0980
-#define RADEON_CAP0_VBI3_OFFSET 0x0984
-#define RADEON_CAP0_ANC2_OFFSET 0x0988
-#define RADEON_CAP0_ANC3_OFFSET 0x098C
-#define RADEON_VID_BUFFER_CONTROL 0x0900
-
-/* second capture unit */
-
-#define RADEON_CAP1_BUF0_OFFSET 0x0990
-#define RADEON_CAP1_BUF1_OFFSET 0x0994
-#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
-#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
-
-#define RADEON_CAP1_BUF_PITCH 0x09A0
-#define RADEON_CAP1_V_WINDOW 0x09A4
-#define RADEON_CAP1_H_WINDOW 0x09A8
-#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
-#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
-#define RADEON_CAP1_VBI_V_WINDOW 0x09B4
-#define RADEON_CAP1_VBI_H_WINDOW 0x09B8
-#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
-#define RADEON_CAP1_TRIG_CNTL 0x09C0
-#define RADEON_CAP1_DEBUG 0x09C4
-#define RADEON_CAP1_CONFIG 0x09C8
-#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
-#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
-#define RADEON_CAP1_ANC_H_WINDOW 0x09D4
-#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
-#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
-#define RADEON_CAP1_BUF_STATUS 0x09E0
-#define RADEON_CAP1_DWNSC_XRATIO 0x09E8
-#define RADEON_CAP1_XSHARPNESS 0x09EC
-
-/* misc multimedia registers */
-
-#define RADEON_IDCT_RUNS 0x1F80
-#define RADEON_IDCT_LEVELS 0x1F84
-#define RADEON_IDCT_CONTROL 0x1FBC
-#define RADEON_IDCT_AUTH_CONTROL 0x1F88
-#define RADEON_IDCT_AUTH 0x1F8C
-
-#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
-# define RADEON_P2PLL_RESET (1 << 0)
-# define RADEON_P2PLL_SLEEP (1 << 1)
-# define RADEON_P2PLL_PVG_MASK (7 << 11)
-# define RADEON_P2PLL_PVG_SHIFT 11
-# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
-# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define RADEON_P2PLL_DIV_0 0x002c
-# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
-# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
-#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
-# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
-# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
-# define R300_PPLL_REF_DIV_ACC_SHIFT 18
-#define RADEON_PALETTE_DATA 0x00b4
-#define RADEON_PALETTE_30_DATA 0x00b8
-#define RADEON_PALETTE_INDEX 0x00b0
-#define RADEON_PCI_GART_PAGE 0x017c
-#define RADEON_PIXCLKS_CNTL 0x002d
-# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
-# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
-# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
-# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
-# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
-# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
-# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
-# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
-# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
-# define R300_DVOCLK_ALWAYS_ONb (1 << 10)
-# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
-# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
-# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
-# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
-# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
-# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
-# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
-# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
-# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
-# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
-# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
-#define RADEON_PLANE_3D_MASK_C 0x1d44
-#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
-# define RADEON_PLL_MASK_READ_B (1 << 9)
-#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
-#define RADEON_PMI_DATA 0x0f63 /* PCI */
-#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
-#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
-#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
-#define RADEON_PMI_REGISTER 0x0f5c /* PCI */
-#define RADEON_PPLL_CNTL 0x0002 /* PLL */
-# define RADEON_PPLL_RESET (1 << 0)
-# define RADEON_PPLL_SLEEP (1 << 1)
-# define RADEON_PPLL_PVG_MASK (7 << 11)
-# define RADEON_PPLL_PVG_SHIFT 11
-# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
-# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define RADEON_PPLL_DIV_0 0x0004 /* PLL */
-#define RADEON_PPLL_DIV_1 0x0005 /* PLL */
-#define RADEON_PPLL_DIV_2 0x0006 /* PLL */
-#define RADEON_PPLL_DIV_3 0x0007 /* PLL */
-# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
-# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
-#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
-# define RADEON_PPLL_REF_DIV_MASK 0x03ff
-# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
-
-#define RADEON_RBBM_GUICNTL 0x172c
-# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
-# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
-# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
-# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
-#define RADEON_RBBM_SOFT_RESET 0x00f0
-# define RADEON_SOFT_RESET_CP (1 << 0)
-# define RADEON_SOFT_RESET_HI (1 << 1)
-# define RADEON_SOFT_RESET_SE (1 << 2)
-# define RADEON_SOFT_RESET_RE (1 << 3)
-# define RADEON_SOFT_RESET_PP (1 << 4)
-# define RADEON_SOFT_RESET_E2 (1 << 5)
-# define RADEON_SOFT_RESET_RB (1 << 6)
-# define RADEON_SOFT_RESET_HDP (1 << 7)
-#define RADEON_RBBM_STATUS 0x0e40
-# define RADEON_RBBM_FIFOCNT_MASK 0x007f
-# define RADEON_RBBM_ACTIVE (1 << 31)
-#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
-# define RADEON_RB2D_DC_FLUSH (3 << 0)
-# define RADEON_RB2D_DC_FREE (3 << 2)
-# define RADEON_RB2D_DC_FLUSH_ALL 0xf
-# define RADEON_RB2D_DC_BUSY (1 << 31)
-#define RADEON_RB2D_DSTCACHE_MODE 0x3428
-
-#define RADEON_RB3D_ZCACHE_MODE 0x3250
-#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
-# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
-#define RADEON_RB3D_DSTCACHE_MODE 0x3258
-# define RADEON_RB3D_DC_CACHE_ENABLE (0)
-# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
-# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
-# define RADEON_RB3D_DC_CACHE_DISABLE (3)
-# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
-# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
-# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
-# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
-# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
-# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
-# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
-# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
-# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
-
-#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
-# define RADEON_RB3D_DC_FLUSH (3 << 0)
-# define RADEON_RB3D_DC_FREE (3 << 2)
-# define RADEON_RB3D_DC_FLUSH_ALL 0xf
-# define RADEON_RB3D_DC_BUSY (1 << 31)
-
-#define RADEON_REG_BASE 0x0f18 /* PCI */
-#define RADEON_REGPROG_INF 0x0f09 /* PCI */
-#define RADEON_REVISION_ID 0x0f08 /* PCI */
-
-#define RADEON_SC_BOTTOM 0x164c
-#define RADEON_SC_BOTTOM_RIGHT 0x16f0
-#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
-#define RADEON_SC_LEFT 0x1640
-#define RADEON_SC_RIGHT 0x1644
-#define RADEON_SC_TOP 0x1648
-#define RADEON_SC_TOP_LEFT 0x16ec
-#define RADEON_SC_TOP_LEFT_C 0x1c88
-# define RADEON_SC_SIGN_MASK_LO 0x8000
-# define RADEON_SC_SIGN_MASK_HI 0x80000000
-#define RADEON_SCLK_CNTL 0x000d /* PLL */
-# define RADEON_SCLK_SRC_SEL_MASK 0x0007
-# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
-# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
-# define RADEON_SCLK_FORCEON_MASK 0xffff8000
-# define RADEON_SCLK_FORCE_DISP2 (1<<15)
-# define RADEON_SCLK_FORCE_CP (1<<16)
-# define RADEON_SCLK_FORCE_HDP (1<<17)
-# define RADEON_SCLK_FORCE_DISP1 (1<<18)
-# define RADEON_SCLK_FORCE_TOP (1<<19)
-# define RADEON_SCLK_FORCE_E2 (1<<20)
-# define RADEON_SCLK_FORCE_SE (1<<21)
-# define RADEON_SCLK_FORCE_IDCT (1<<22)
-# define RADEON_SCLK_FORCE_VIP (1<<23)
-# define RADEON_SCLK_FORCE_RE (1<<24)
-# define RADEON_SCLK_FORCE_PB (1<<25)
-# define RADEON_SCLK_FORCE_TAM (1<<26)
-# define RADEON_SCLK_FORCE_TDM (1<<27)
-# define RADEON_SCLK_FORCE_RB (1<<28)
-# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
-# define RADEON_SCLK_FORCE_SUBPIC (1<<30)
-# define RADEON_SCLK_FORCE_OV0 (1<<31)
-# define R300_SCLK_FORCE_VAP (1<<21)
-# define R300_SCLK_FORCE_SR (1<<25)
-# define R300_SCLK_FORCE_PX (1<<26)
-# define R300_SCLK_FORCE_TX (1<<27)
-# define R300_SCLK_FORCE_US (1<<28)
-# define R300_SCLK_FORCE_SU (1<<30)
-#define R300_SCLK_CNTL2 0x1e /* PLL */
-# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
-# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
-# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
-# define R300_SCLK_FORCE_TCL (1<<13)
-# define R300_SCLK_FORCE_CBA (1<<14)
-# define R300_SCLK_FORCE_GA (1<<15)
-#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
-# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
-# define RADEON_SCLK_MORE_FORCEON 0x0700
-#define RADEON_SDRAM_MODE_REG 0x0158
-#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
-#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
-#define RADEON_SNAPSHOT_F_COUNT 0x0244
-#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
-#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
-#define RADEON_SRC_OFFSET 0x15ac
-#define RADEON_SRC_PITCH 0x15b0
-#define RADEON_SRC_PITCH_OFFSET 0x1428
-#define RADEON_SRC_SC_BOTTOM 0x165c
-#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
-#define RADEON_SRC_SC_RIGHT 0x1654
-#define RADEON_SRC_X 0x1414
-#define RADEON_SRC_X_Y 0x1590
-#define RADEON_SRC_Y 0x1418
-#define RADEON_SRC_Y_X 0x1434
-#define RADEON_STATUS 0x0f06 /* PCI */
-#define RADEON_SUBPIC_CNTL 0x0540 /* ? */
-#define RADEON_SUB_CLASS 0x0f0a /* PCI */
-#define RADEON_SURFACE_CNTL 0x0b00
-# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
-# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
-# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
-# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
-# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
-#define RADEON_SURFACE0_INFO 0x0b0c
-# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
-# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
-# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
-# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
-# define R200_SURF_TILE_NONE (0 << 16)
-# define R200_SURF_TILE_COLOR_MACRO (1 << 16)
-# define R200_SURF_TILE_COLOR_MICRO (2 << 16)
-# define R200_SURF_TILE_COLOR_BOTH (3 << 16)
-# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
-# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
-# define R300_SURF_TILE_NONE (0 << 16)
-# define R300_SURF_TILE_COLOR_MACRO (1 << 16)
-# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
-# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
-# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
-# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
-# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
-#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
-#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
-#define RADEON_SURFACE1_INFO 0x0b1c
-#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
-#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
-#define RADEON_SURFACE2_INFO 0x0b2c
-#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
-#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
-#define RADEON_SURFACE3_INFO 0x0b3c
-#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
-#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
-#define RADEON_SURFACE4_INFO 0x0b4c
-#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
-#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
-#define RADEON_SURFACE5_INFO 0x0b5c
-#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
-#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
-#define RADEON_SURFACE6_INFO 0x0b6c
-#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
-#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
-#define RADEON_SURFACE7_INFO 0x0b7c
-#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
-#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
-#define RADEON_SW_SEMAPHORE 0x013c
-
-#define RADEON_TEST_DEBUG_CNTL 0x0120
-#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
-
-#define RADEON_TEST_DEBUG_MUX 0x0124
-#define RADEON_TEST_DEBUG_OUT 0x012c
-#define RADEON_TMDS_PLL_CNTL 0x02a8
-#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
-# define RADEON_TMDS_TRANSMITTER_PLLEN 1
-# define RADEON_TMDS_TRANSMITTER_PLLRST 2
-#define RADEON_TRAIL_BRES_DEC 0x1614
-#define RADEON_TRAIL_BRES_ERR 0x160c
-#define RADEON_TRAIL_BRES_INC 0x1610
-#define RADEON_TRAIL_X 0x1618
-#define RADEON_TRAIL_X_SUB 0x1620
-
-#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
-# define RADEON_VCLK_SRC_SEL_MASK 0x03
-# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
-# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
-# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
-# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
-# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
-# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
-# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
-
-#define RADEON_VENDOR_ID 0x0f00 /* PCI */
-#define RADEON_VGA_DDA_CONFIG 0x02e8
-#define RADEON_VGA_DDA_ON_OFF 0x02ec
-#define RADEON_VID_BUFFER_CONTROL 0x0900
-#define RADEON_VIDEOMUX_CNTL 0x0190
-
- /* VIP bus */
-#define RADEON_VIPH_CH0_DATA 0x0c00
-#define RADEON_VIPH_CH1_DATA 0x0c04
-#define RADEON_VIPH_CH2_DATA 0x0c08
-#define RADEON_VIPH_CH3_DATA 0x0c0c
-#define RADEON_VIPH_CH0_ADDR 0x0c10
-#define RADEON_VIPH_CH1_ADDR 0x0c14
-#define RADEON_VIPH_CH2_ADDR 0x0c18
-#define RADEON_VIPH_CH3_ADDR 0x0c1c
-#define RADEON_VIPH_CH0_SBCNT 0x0c20
-#define RADEON_VIPH_CH1_SBCNT 0x0c24
-#define RADEON_VIPH_CH2_SBCNT 0x0c28
-#define RADEON_VIPH_CH3_SBCNT 0x0c2c
-#define RADEON_VIPH_CH0_ABCNT 0x0c30
-#define RADEON_VIPH_CH1_ABCNT 0x0c34
-#define RADEON_VIPH_CH2_ABCNT 0x0c38
-#define RADEON_VIPH_CH3_ABCNT 0x0c3c
-#define RADEON_VIPH_CONTROL 0x0c40
-# define RADEON_VIP_BUSY 0
-# define RADEON_VIP_IDLE 1
-# define RADEON_VIP_RESET 2
-#define RADEON_VIPH_DV_LAT 0x0c44
-#define RADEON_VIPH_BM_CHUNK 0x0c48
-#define RADEON_VIPH_DV_INT 0x0c4c
-#define RADEON_VIPH_TIMEOUT_STAT 0x0c50
-#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
-#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
-#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
-
-#define RADEON_VIPH_REG_DATA 0x0084
-#define RADEON_VIPH_REG_ADDR 0x0080
-
-
-#define RADEON_WAIT_UNTIL 0x1720
-# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
-# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
-# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
-# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-
-#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
-#define RADEON_XCLK_CNTL 0x000d /* PLL */
-#define RADEON_XDLL_CNTL 0x000c /* PLL */
-#define RADEON_XPLL_CNTL 0x000b /* PLL */
-
-
-
- /* Registers for 3D/TCL */
-#define RADEON_PP_BORDER_COLOR_0 0x1d40
-#define RADEON_PP_BORDER_COLOR_1 0x1d44
-#define RADEON_PP_BORDER_COLOR_2 0x1d48
-#define RADEON_PP_CNTL 0x1c38
-# define RADEON_STIPPLE_ENABLE (1 << 0)
-# define RADEON_SCISSOR_ENABLE (1 << 1)
-# define RADEON_PATTERN_ENABLE (1 << 2)
-# define RADEON_SHADOW_ENABLE (1 << 3)
-# define RADEON_TEX_ENABLE_MASK (0xf << 4)
-# define RADEON_TEX_0_ENABLE (1 << 4)
-# define RADEON_TEX_1_ENABLE (1 << 5)
-# define RADEON_TEX_2_ENABLE (1 << 6)
-# define RADEON_TEX_3_ENABLE (1 << 7)
-# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
-# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
-# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
-# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
-# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
-# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
-# define RADEON_SPECULAR_ENABLE (1 << 21)
-# define RADEON_FOG_ENABLE (1 << 22)
-# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
-# define RADEON_ANTI_ALIAS_NONE (0 << 24)
-# define RADEON_ANTI_ALIAS_LINE (1 << 24)
-# define RADEON_ANTI_ALIAS_POLY (2 << 24)
-# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
-# define RADEON_BUMP_MAP_ENABLE (1 << 26)
-# define RADEON_BUMPED_MAP_T0 (0 << 27)
-# define RADEON_BUMPED_MAP_T1 (1 << 27)
-# define RADEON_BUMPED_MAP_T2 (2 << 27)
-# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
-# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
-# define RADEON_MC_ENABLE (1 << 31)
-#define RADEON_PP_FOG_COLOR 0x1c18
-# define RADEON_FOG_COLOR_MASK 0x00ffffff
-# define RADEON_FOG_VERTEX (0 << 24)
-# define RADEON_FOG_TABLE (1 << 24)
-# define RADEON_FOG_USE_DEPTH (0 << 25)
-# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
-# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
-#define RADEON_PP_LUM_MATRIX 0x1d00
-#define RADEON_PP_MISC 0x1c14
-# define RADEON_REF_ALPHA_MASK 0x000000ff
-# define RADEON_ALPHA_TEST_FAIL (0 << 8)
-# define RADEON_ALPHA_TEST_LESS (1 << 8)
-# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
-# define RADEON_ALPHA_TEST_EQUAL (3 << 8)
-# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
-# define RADEON_ALPHA_TEST_GREATER (5 << 8)
-# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
-# define RADEON_ALPHA_TEST_PASS (7 << 8)
-# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
-# define RADEON_CHROMA_FUNC_FAIL (0 << 16)
-# define RADEON_CHROMA_FUNC_PASS (1 << 16)
-# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
-# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
-# define RADEON_CHROMA_KEY_NEAREST (0 << 18)
-# define RADEON_CHROMA_KEY_ZERO (1 << 18)
-# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
-# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
-# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
-# define RADEON_SHADOW_PASS_1 (0 << 22)
-# define RADEON_SHADOW_PASS_2 (1 << 22)
-# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
-# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
-#define RADEON_PP_ROT_MATRIX_0 0x1d58
-#define RADEON_PP_ROT_MATRIX_1 0x1d5c
-#define RADEON_PP_TXFILTER_0 0x1c54
-#define RADEON_PP_TXFILTER_1 0x1c6c
-#define RADEON_PP_TXFILTER_2 0x1c84
-# define RADEON_MAG_FILTER_NEAREST (0 << 0)
-# define RADEON_MAG_FILTER_LINEAR (1 << 0)
-# define RADEON_MAG_FILTER_MASK (1 << 0)
-# define RADEON_MIN_FILTER_NEAREST (0 << 1)
-# define RADEON_MIN_FILTER_LINEAR (1 << 1)
-# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
-# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
-# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
-# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
-# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
-# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
-# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
-# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
-# define RADEON_MIN_FILTER_MASK (15 << 1)
-# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
-# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
-# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
-# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
-# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
-# define RADEON_MAX_ANISO_MASK (7 << 5)
-# define RADEON_LOD_BIAS_MASK (0xff << 8)
-# define RADEON_LOD_BIAS_SHIFT 8
-# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
-# define RADEON_MAX_MIP_LEVEL_SHIFT 16
-# define RADEON_YUV_TO_RGB (1 << 20)
-# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
-# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
-# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
-# define RADEON_WRAPEN_S (1 << 22)
-# define RADEON_CLAMP_S_WRAP (0 << 23)
-# define RADEON_CLAMP_S_MIRROR (1 << 23)
-# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
-# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
-# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
-# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
-# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
-# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
-# define RADEON_CLAMP_S_MASK (7 << 23)
-# define RADEON_WRAPEN_T (1 << 26)
-# define RADEON_CLAMP_T_WRAP (0 << 27)
-# define RADEON_CLAMP_T_MIRROR (1 << 27)
-# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
-# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
-# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
-# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
-# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
-# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
-# define RADEON_CLAMP_T_MASK (7 << 27)
-# define RADEON_BORDER_MODE_OGL (0 << 31)
-# define RADEON_BORDER_MODE_D3D (1 << 31)
-#define RADEON_PP_TXFORMAT_0 0x1c58
-#define RADEON_PP_TXFORMAT_1 0x1c70
-#define RADEON_PP_TXFORMAT_2 0x1c88
-# define RADEON_TXFORMAT_I8 (0 << 0)
-# define RADEON_TXFORMAT_AI88 (1 << 0)
-# define RADEON_TXFORMAT_RGB332 (2 << 0)
-# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
-# define RADEON_TXFORMAT_RGB565 (4 << 0)
-# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
-# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
-# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
-# define RADEON_TXFORMAT_Y8 (8 << 0)
-# define RADEON_TXFORMAT_VYUY422 (10 << 0)
-# define RADEON_TXFORMAT_YVYU422 (11 << 0)
-# define RADEON_TXFORMAT_DXT1 (12 << 0)
-# define RADEON_TXFORMAT_DXT23 (14 << 0)
-# define RADEON_TXFORMAT_DXT45 (15 << 0)
-# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
-# define RADEON_TXFORMAT_FORMAT_SHIFT 0
-# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
-# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
-# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
-# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
-# define RADEON_TXFORMAT_WIDTH_SHIFT 8
-# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
-# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
-# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
-# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
-# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
-# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
-# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
-# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
-# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
-# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
-# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
-# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
-# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
-# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
-# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
-#define RADEON_PP_CUBIC_FACES_0 0x1d24
-#define RADEON_PP_CUBIC_FACES_1 0x1d28
-#define RADEON_PP_CUBIC_FACES_2 0x1d2c
-# define RADEON_FACE_WIDTH_1_SHIFT 0
-# define RADEON_FACE_HEIGHT_1_SHIFT 4
-# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
-# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
-# define RADEON_FACE_WIDTH_2_SHIFT 8
-# define RADEON_FACE_HEIGHT_2_SHIFT 12
-# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
-# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
-# define RADEON_FACE_WIDTH_3_SHIFT 16
-# define RADEON_FACE_HEIGHT_3_SHIFT 20
-# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
-# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
-# define RADEON_FACE_WIDTH_4_SHIFT 24
-# define RADEON_FACE_HEIGHT_4_SHIFT 28
-# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
-# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
-
-#define RADEON_PP_TXOFFSET_0 0x1c5c
-#define RADEON_PP_TXOFFSET_1 0x1c74
-#define RADEON_PP_TXOFFSET_2 0x1c8c
-# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
-# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
-# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
-# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
-# define RADEON_TXO_MACRO_LINEAR (0 << 2)
-# define RADEON_TXO_MACRO_TILE (1 << 2)
-# define RADEON_TXO_MICRO_LINEAR (0 << 3)
-# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
-# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
-# define RADEON_TXO_OFFSET_MASK 0xffffffe0
-# define RADEON_TXO_OFFSET_SHIFT 5
-
-#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
-#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
-#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
-#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
-#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
-#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
-#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
-#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
-#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
-#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
-#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
-#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
-#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
-#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
-#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
-
-#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
-#define RADEON_PP_TEX_SIZE_1 0x1d0c
-#define RADEON_PP_TEX_SIZE_2 0x1d14
-# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
-# define RADEON_TEX_USIZE_SHIFT 0
-# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
-# define RADEON_TEX_VSIZE_SHIFT 16
-# define RADEON_SIGNED_RGB_MASK (1 << 30)
-# define RADEON_SIGNED_RGB_SHIFT 30
-# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
-# define RADEON_SIGNED_ALPHA_SHIFT 31
-#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
-#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
-#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
-/* note: bits 13-5: 32 byte aligned stride of texture map */
-
-#define RADEON_PP_TXCBLEND_0 0x1c60
-#define RADEON_PP_TXCBLEND_1 0x1c78
-#define RADEON_PP_TXCBLEND_2 0x1c90
-# define RADEON_COLOR_ARG_A_SHIFT 0
-# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
-# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
-# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
-# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
-# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
-# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
-# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
-# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
-# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
-# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
-# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
-# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
-# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
-# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
-# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
-# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
-# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
-# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
-# define RADEON_COLOR_ARG_B_SHIFT 5
-# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
-# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
-# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
-# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
-# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
-# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
-# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
-# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
-# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
-# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
-# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
-# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
-# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
-# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
-# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
-# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
-# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
-# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
-# define RADEON_COLOR_ARG_C_SHIFT 10
-# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
-# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
-# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
-# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
-# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
-# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
-# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
-# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
-# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
-# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
-# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
-# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
-# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
-# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
-# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
-# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
-# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
-# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
-# define RADEON_COMP_ARG_A (1 << 15)
-# define RADEON_COMP_ARG_A_SHIFT 15
-# define RADEON_COMP_ARG_B (1 << 16)
-# define RADEON_COMP_ARG_B_SHIFT 16
-# define RADEON_COMP_ARG_C (1 << 17)
-# define RADEON_COMP_ARG_C_SHIFT 17
-# define RADEON_BLEND_CTL_MASK (7 << 18)
-# define RADEON_BLEND_CTL_ADD (0 << 18)
-# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
-# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
-# define RADEON_BLEND_CTL_BLEND (3 << 18)
-# define RADEON_BLEND_CTL_DOT3 (4 << 18)
-# define RADEON_SCALE_SHIFT 21
-# define RADEON_SCALE_MASK (3 << 21)
-# define RADEON_SCALE_1X (0 << 21)
-# define RADEON_SCALE_2X (1 << 21)
-# define RADEON_SCALE_4X (2 << 21)
-# define RADEON_CLAMP_TX (1 << 23)
-# define RADEON_T0_EQ_TCUR (1 << 24)
-# define RADEON_T1_EQ_TCUR (1 << 25)
-# define RADEON_T2_EQ_TCUR (1 << 26)
-# define RADEON_T3_EQ_TCUR (1 << 27)
-# define RADEON_COLOR_ARG_MASK 0x1f
-# define RADEON_COMP_ARG_SHIFT 15
-#define RADEON_PP_TXABLEND_0 0x1c64
-#define RADEON_PP_TXABLEND_1 0x1c7c
-#define RADEON_PP_TXABLEND_2 0x1c94
-# define RADEON_ALPHA_ARG_A_SHIFT 0
-# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
-# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
-# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
-# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
-# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
-# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
-# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
-# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
-# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
-# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
-# define RADEON_ALPHA_ARG_B_SHIFT 4
-# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
-# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
-# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
-# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
-# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
-# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
-# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
-# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
-# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
-# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
-# define RADEON_ALPHA_ARG_C_SHIFT 8
-# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
-# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
-# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
-# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
-# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
-# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
-# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
-# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
-# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
-# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
-# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
-# define RADEON_ALPHA_ARG_MASK 0xf
-
-#define RADEON_PP_TFACTOR_0 0x1c68
-#define RADEON_PP_TFACTOR_1 0x1c80
-#define RADEON_PP_TFACTOR_2 0x1c98
-
-#define RADEON_RB3D_BLENDCNTL 0x1c20
-# define RADEON_COMB_FCN_MASK (3 << 12)
-# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
-# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
-# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
-# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
-# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
-# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
-# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
-# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
-# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
-# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
-# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
-# define RADEON_SRC_BLEND_MASK (63 << 16)
-# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
-# define RADEON_DST_BLEND_GL_ONE (33 << 24)
-# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
-# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
-# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
-# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
-# define RADEON_DST_BLEND_MASK (63 << 24)
-#define RADEON_RB3D_CNTL 0x1c3c
-# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
-# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-# define RADEON_DITHER_ENABLE (1 << 2)
-# define RADEON_ROUND_ENABLE (1 << 3)
-# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
-# define RADEON_DITHER_INIT (1 << 5)
-# define RADEON_ROP_ENABLE (1 << 6)
-# define RADEON_STENCIL_ENABLE (1 << 7)
-# define RADEON_Z_ENABLE (1 << 8)
-# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
-# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
-# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
-# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
-# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
-# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
-# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
-# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
-# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
-# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
-# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
-# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
-#define RADEON_RB3D_COLOROFFSET 0x1c40
-# define RADEON_COLOROFFSET_MASK 0xfffffff0
-#define RADEON_RB3D_COLORPITCH 0x1c48
-# define RADEON_COLORPITCH_MASK 0x000001ff8
-# define RADEON_COLOR_TILE_ENABLE (1 << 16)
-# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
-# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
-# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
-# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
-#define RADEON_RB3D_DEPTHOFFSET 0x1c24
-#define RADEON_RB3D_DEPTHPITCH 0x1c28
-# define RADEON_DEPTHPITCH_MASK 0x00001ff8
-# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
-# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
-# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
-#define RADEON_RB3D_PLANEMASK 0x1d84
-#define RADEON_RB3D_ROPCNTL 0x1d80
-# define RADEON_ROP_MASK (15 << 8)
-# define RADEON_ROP_CLEAR (0 << 8)
-# define RADEON_ROP_NOR (1 << 8)
-# define RADEON_ROP_AND_INVERTED (2 << 8)
-# define RADEON_ROP_COPY_INVERTED (3 << 8)
-# define RADEON_ROP_AND_REVERSE (4 << 8)
-# define RADEON_ROP_INVERT (5 << 8)
-# define RADEON_ROP_XOR (6 << 8)
-# define RADEON_ROP_NAND (7 << 8)
-# define RADEON_ROP_AND (8 << 8)
-# define RADEON_ROP_EQUIV (9 << 8)
-# define RADEON_ROP_NOOP (10 << 8)
-# define RADEON_ROP_OR_INVERTED (11 << 8)
-# define RADEON_ROP_COPY (12 << 8)
-# define RADEON_ROP_OR_REVERSE (13 << 8)
-# define RADEON_ROP_OR (14 << 8)
-# define RADEON_ROP_SET (15 << 8)
-#define RADEON_RB3D_STENCILREFMASK 0x1d7c
-# define RADEON_STENCIL_REF_SHIFT 0
-# define RADEON_STENCIL_REF_MASK (0xff << 0)
-# define RADEON_STENCIL_MASK_SHIFT 16
-# define RADEON_STENCIL_VALUE_MASK (0xff << 16)
-# define RADEON_STENCIL_WRITEMASK_SHIFT 24
-# define RADEON_STENCIL_WRITE_MASK (0xff << 24)
-#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
-# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
-# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
-# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
-# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
-# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
-# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
-# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
-# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
-# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
-# define RADEON_Z_TEST_NEVER (0 << 4)
-# define RADEON_Z_TEST_LESS (1 << 4)
-# define RADEON_Z_TEST_LEQUAL (2 << 4)
-# define RADEON_Z_TEST_EQUAL (3 << 4)
-# define RADEON_Z_TEST_GEQUAL (4 << 4)
-# define RADEON_Z_TEST_GREATER (5 << 4)
-# define RADEON_Z_TEST_NEQUAL (6 << 4)
-# define RADEON_Z_TEST_ALWAYS (7 << 4)
-# define RADEON_Z_TEST_MASK (7 << 4)
-# define RADEON_STENCIL_TEST_NEVER (0 << 12)
-# define RADEON_STENCIL_TEST_LESS (1 << 12)
-# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
-# define RADEON_STENCIL_TEST_EQUAL (3 << 12)
-# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
-# define RADEON_STENCIL_TEST_GREATER (5 << 12)
-# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
-# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
-# define RADEON_STENCIL_TEST_MASK (0x7 << 12)
-# define RADEON_STENCIL_FAIL_KEEP (0 << 16)
-# define RADEON_STENCIL_FAIL_ZERO (1 << 16)
-# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
-# define RADEON_STENCIL_FAIL_INC (3 << 16)
-# define RADEON_STENCIL_FAIL_DEC (4 << 16)
-# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
-# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
-# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
-# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
-# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
-# define RADEON_STENCIL_ZPASS_INC (3 << 20)
-# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
-# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
-# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
-# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
-# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
-# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
-# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
-# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
-# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
-# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
-# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
-# define RADEON_FORCE_Z_DIRTY (1 << 29)
-# define RADEON_Z_WRITE_ENABLE (1 << 30)
-#define RADEON_RE_LINE_PATTERN 0x1cd0
-# define RADEON_LINE_PATTERN_MASK 0x0000ffff
-# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
-# define RADEON_LINE_PATTERN_START_SHIFT 24
-# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
-# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
-# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
-#define RADEON_RE_LINE_STATE 0x1cd4
-# define RADEON_LINE_CURRENT_PTR_SHIFT 0
-# define RADEON_LINE_CURRENT_COUNT_SHIFT 8
-#define RADEON_RE_MISC 0x26c4
-# define RADEON_STIPPLE_COORD_MASK 0x1f
-# define RADEON_STIPPLE_X_OFFSET_SHIFT 0
-# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
-# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
-# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
-# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
-# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
-#define RADEON_RE_SOLID_COLOR 0x1c1c
-#define RADEON_RE_TOP_LEFT 0x26c0
-# define RADEON_RE_LEFT_SHIFT 0
-# define RADEON_RE_TOP_SHIFT 16
-#define RADEON_RE_WIDTH_HEIGHT 0x1c44
-# define RADEON_RE_WIDTH_SHIFT 0
-# define RADEON_RE_HEIGHT_SHIFT 16
-
-#define RADEON_SE_CNTL 0x1c4c
-# define RADEON_FFACE_CULL_CW (0 << 0)
-# define RADEON_FFACE_CULL_CCW (1 << 0)
-# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
-# define RADEON_BFACE_CULL (0 << 1)
-# define RADEON_BFACE_SOLID (3 << 1)
-# define RADEON_FFACE_CULL (0 << 3)
-# define RADEON_FFACE_SOLID (3 << 3)
-# define RADEON_FFACE_CULL_MASK (3 << 3)
-# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
-# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
-# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
-# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
-# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
-# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
-# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
-# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
-# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
-# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
-# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
-# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
-# define RADEON_ALPHA_SHADE_MASK (3 << 10)
-# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
-# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
-# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
-# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
-# define RADEON_FOG_SHADE_SOLID (0 << 14)
-# define RADEON_FOG_SHADE_FLAT (1 << 14)
-# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
-# define RADEON_FOG_SHADE_MASK (3 << 14)
-# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
-# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
-# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
-# define RADEON_WIDELINE_ENABLE (1 << 20)
-# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
-# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
-# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
-# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
-# define RADEON_ROUND_MODE_TRUNC (0 << 28)
-# define RADEON_ROUND_MODE_ROUND (1 << 28)
-# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
-# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
-# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
-# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
-# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
-# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
-#define R200_RE_CNTL 0x1c50
-# define R200_STIPPLE_ENABLE 0x1
-# define R200_SCISSOR_ENABLE 0x2
-# define R200_PATTERN_ENABLE 0x4
-# define R200_PERSPECTIVE_ENABLE 0x8
-# define R200_POINT_SMOOTH 0x20
-# define R200_VTX_STQ0_D3D 0x00010000
-# define R200_VTX_STQ1_D3D 0x00040000
-# define R200_VTX_STQ2_D3D 0x00100000
-# define R200_VTX_STQ3_D3D 0x00400000
-# define R200_VTX_STQ4_D3D 0x01000000
-# define R200_VTX_STQ5_D3D 0x04000000
-#define RADEON_SE_CNTL_STATUS 0x2140
-# define RADEON_VC_NO_SWAP (0 << 0)
-# define RADEON_VC_16BIT_SWAP (1 << 0)
-# define RADEON_VC_32BIT_SWAP (2 << 0)
-# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
-# define RADEON_TCL_BYPASS (1 << 8)
-#define RADEON_SE_COORD_FMT 0x1c50
-# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
-# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
-# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
-# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
-# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
-# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
-# define RADEON_VTX_W0_NORMALIZE (1 << 12)
-# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
-# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
-# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
-# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
-# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
-# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
-# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
-#define RADEON_SE_LINE_WIDTH 0x1db8
-#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
-# define RADEON_LIGHTING_ENABLE (1 << 0)
-# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
-# define RADEON_LOCAL_VIEWER (1 << 2)
-# define RADEON_NORMALIZE_NORMALS (1 << 3)
-# define RADEON_RESCALE_NORMALS (1 << 4)
-# define RADEON_SPECULAR_LIGHTS (1 << 5)
-# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
-# define RADEON_LIGHT_ALPHA (1 << 7)
-# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
-# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
-# define RADEON_LM_SOURCE_STATE_PREMULT 0
-# define RADEON_LM_SOURCE_STATE_MULT 1
-# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
-# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
-# define RADEON_EMISSIVE_SOURCE_SHIFT 16
-# define RADEON_AMBIENT_SOURCE_SHIFT 18
-# define RADEON_DIFFUSE_SOURCE_SHIFT 20
-# define RADEON_SPECULAR_SOURCE_SHIFT 22
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
-#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
-# define RADEON_MODELVIEW_0_SHIFT 0
-# define RADEON_MODELVIEW_1_SHIFT 4
-# define RADEON_MODELVIEW_2_SHIFT 8
-# define RADEON_MODELVIEW_3_SHIFT 12
-# define RADEON_IT_MODELVIEW_0_SHIFT 16
-# define RADEON_IT_MODELVIEW_1_SHIFT 20
-# define RADEON_IT_MODELVIEW_2_SHIFT 24
-# define RADEON_IT_MODELVIEW_3_SHIFT 28
-#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
-# define RADEON_MODELPROJECT_0_SHIFT 0
-# define RADEON_MODELPROJECT_1_SHIFT 4
-# define RADEON_MODELPROJECT_2_SHIFT 8
-# define RADEON_MODELPROJECT_3_SHIFT 12
-# define RADEON_TEXMAT_0_SHIFT 16
-# define RADEON_TEXMAT_1_SHIFT 20
-# define RADEON_TEXMAT_2_SHIFT 24
-# define RADEON_TEXMAT_3_SHIFT 28
-
-
-#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
-# define RADEON_TCL_VTX_W0 (1 << 0)
-# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
-# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
-# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
-# define RADEON_TCL_VTX_FP_SPEC (1 << 4)
-# define RADEON_TCL_VTX_FP_FOG (1 << 5)
-# define RADEON_TCL_VTX_PK_SPEC (1 << 6)
-# define RADEON_TCL_VTX_ST0 (1 << 7)
-# define RADEON_TCL_VTX_ST1 (1 << 8)
-# define RADEON_TCL_VTX_Q1 (1 << 9)
-# define RADEON_TCL_VTX_ST2 (1 << 10)
-# define RADEON_TCL_VTX_Q2 (1 << 11)
-# define RADEON_TCL_VTX_ST3 (1 << 12)
-# define RADEON_TCL_VTX_Q3 (1 << 13)
-# define RADEON_TCL_VTX_Q0 (1 << 14)
-# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
-# define RADEON_TCL_VTX_NORM0 (1 << 18)
-# define RADEON_TCL_VTX_XY1 (1 << 27)
-# define RADEON_TCL_VTX_Z1 (1 << 28)
-# define RADEON_TCL_VTX_W1 (1 << 29)
-# define RADEON_TCL_VTX_NORM1 (1 << 30)
-# define RADEON_TCL_VTX_Z0 (1 << 31)
-
-#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
-# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
-# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
-# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
-# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
-# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
-# define RADEON_TCL_TEX_INPUT_TEX_0 0
-# define RADEON_TCL_TEX_INPUT_TEX_1 1
-# define RADEON_TCL_TEX_INPUT_TEX_2 2
-# define RADEON_TCL_TEX_INPUT_TEX_3 3
-# define RADEON_TCL_TEX_COMPUTED_TEX_0 8
-# define RADEON_TCL_TEX_COMPUTED_TEX_1 9
-# define RADEON_TCL_TEX_COMPUTED_TEX_2 10
-# define RADEON_TCL_TEX_COMPUTED_TEX_3 11
-# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
-# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
-# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
-# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
-
-#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
-# define RADEON_LIGHT_0_ENABLE (1 << 0)
-# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
-# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
-# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
-# define RADEON_LIGHT_0_IS_SPOT (1 << 4)
-# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
-# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
-# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
-# define RADEON_LIGHT_0_SHIFT 0
-# define RADEON_LIGHT_1_ENABLE (1 << 16)
-# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
-# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
-# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
-# define RADEON_LIGHT_1_IS_SPOT (1 << 20)
-# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
-# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
-# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
-# define RADEON_LIGHT_1_SHIFT 16
-#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
-# define RADEON_LIGHT_2_SHIFT 0
-# define RADEON_LIGHT_3_SHIFT 16
-#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
-# define RADEON_LIGHT_4_SHIFT 0
-# define RADEON_LIGHT_5_SHIFT 16
-#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
-# define RADEON_LIGHT_6_SHIFT 0
-# define RADEON_LIGHT_7_SHIFT 16
-
-#define RADEON_SE_TCL_SHININESS 0x2250
-
-#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
-# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
-# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
-# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
-# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
-# define RADEON_TEXMAT_0_ENABLE (1 << 4)
-# define RADEON_TEXMAT_1_ENABLE (1 << 5)
-# define RADEON_TEXMAT_2_ENABLE (1 << 6)
-# define RADEON_TEXMAT_3_ENABLE (1 << 7)
-# define RADEON_TEXGEN_INPUT_MASK 0xf
-# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
-# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
-# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
-# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
-# define RADEON_TEXGEN_INPUT_OBJ 4
-# define RADEON_TEXGEN_INPUT_EYE 5
-# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
-# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
-# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
-# define RADEON_TEXGEN_0_INPUT_SHIFT 16
-# define RADEON_TEXGEN_1_INPUT_SHIFT 20
-# define RADEON_TEXGEN_2_INPUT_SHIFT 24
-# define RADEON_TEXGEN_3_INPUT_SHIFT 28
-
-#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
-# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
-# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
-# define RADEON_UCP_ENABLE_0 (1 << 2)
-# define RADEON_UCP_ENABLE_1 (1 << 3)
-# define RADEON_UCP_ENABLE_2 (1 << 4)
-# define RADEON_UCP_ENABLE_3 (1 << 5)
-# define RADEON_UCP_ENABLE_4 (1 << 6)
-# define RADEON_UCP_ENABLE_5 (1 << 7)
-# define RADEON_TCL_FOG_MASK (3 << 8)
-# define RADEON_TCL_FOG_DISABLE (0 << 8)
-# define RADEON_TCL_FOG_EXP (1 << 8)
-# define RADEON_TCL_FOG_EXP2 (2 << 8)
-# define RADEON_TCL_FOG_LINEAR (3 << 8)
-# define RADEON_RNG_BASED_FOG (1 << 10)
-# define RADEON_LIGHT_TWOSIDE (1 << 11)
-# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
-# define RADEON_BLEND_OP_COUNT_SHIFT 12
-# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
-# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
-# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
-# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
-# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
-# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
-# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
-# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
-# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
-# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
-# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
-# define RADEON_CULL_FRONT_IS_CW (0 << 28)
-# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
-# define RADEON_CULL_FRONT (1 << 29)
-# define RADEON_CULL_BACK (1 << 30)
-# define RADEON_FORCE_W_TO_ONE (1 << 31)
-
-#define RADEON_SE_VPORT_XSCALE 0x1d98
-#define RADEON_SE_VPORT_XOFFSET 0x1d9c
-#define RADEON_SE_VPORT_YSCALE 0x1da0
-#define RADEON_SE_VPORT_YOFFSET 0x1da4
-#define RADEON_SE_VPORT_ZSCALE 0x1da8
-#define RADEON_SE_VPORT_ZOFFSET 0x1dac
-#define RADEON_SE_ZBIAS_FACTOR 0x1db0
-#define RADEON_SE_ZBIAS_CONSTANT 0x1db4
-
-#define RADEON_SE_VTX_FMT 0x2080
-# define RADEON_SE_VTX_FMT_XY 0x00000000
-# define RADEON_SE_VTX_FMT_W0 0x00000001
-# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
-# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
-# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
-# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
-# define RADEON_SE_VTX_FMT_FPFOG 0x00000020
-# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
-# define RADEON_SE_VTX_FMT_ST0 0x00000080
-# define RADEON_SE_VTX_FMT_ST1 0x00000100
-# define RADEON_SE_VTX_FMT_Q1 0x00000200
-# define RADEON_SE_VTX_FMT_ST2 0x00000400
-# define RADEON_SE_VTX_FMT_Q2 0x00000800
-# define RADEON_SE_VTX_FMT_ST3 0x00001000
-# define RADEON_SE_VTX_FMT_Q3 0x00002000
-# define RADEON_SE_VTX_FMT_Q0 0x00004000
-# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
-# define RADEON_SE_VTX_FMT_N0 0x00040000
-# define RADEON_SE_VTX_FMT_XY1 0x08000000
-# define RADEON_SE_VTX_FMT_Z1 0x10000000
-# define RADEON_SE_VTX_FMT_W1 0x20000000
-# define RADEON_SE_VTX_FMT_N1 0x40000000
-# define RADEON_SE_VTX_FMT_Z 0x80000000
-
-#define RADEON_SE_VF_CNTL 0x2084
-# define RADEON_VF_PRIM_TYPE_POINT_LIST 1
-# define RADEON_VF_PRIM_TYPE_LINE_LIST 2
-# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
-# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
-# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
-# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
-# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
-# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
-# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
-# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
-# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
-# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
-# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
-# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
-# define RADEON_VF_PRIM_TYPE_POLYGON 15
-# define RADEON_VF_PRIM_WALK_STATE (0<<4)
-# define RADEON_VF_PRIM_WALK_INDEX (1<<4)
-# define RADEON_VF_PRIM_WALK_LIST (2<<4)
-# define RADEON_VF_PRIM_WALK_DATA (3<<4)
-# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
-# define RADEON_VF_RADEON_MODE (1<<8)
-# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
-# define RADEON_VF_PROG_STREAM_ENA (1<<10)
-# define RADEON_VF_INDEX_SIZE_SHIFT 11
-# define RADEON_VF_NUM_VERTICES_SHIFT 16
-
-#define RADEON_SE_PORT_DATA0 0x2000
-
-#define R200_SE_VAP_CNTL 0x2080
-# define R200_VAP_TCL_ENABLE 0x00000001
-# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010
-# define R200_VAP_FORCE_W_TO_ONE 0x00010000
-# define R200_VAP_D3D_TEX_DEFAULT 0x00020000
-# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18
-# define R200_VAP_VF_MAX_VTX_NUM (9 << 18)
-# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000
-#define R200_VF_MAX_VTX_INDX 0x210c
-#define R200_VF_MIN_VTX_INDX 0x2110
-#define R200_SE_VTE_CNTL 0x20b0
-# define R200_VPORT_X_SCALE_ENA 0x00000001
-# define R200_VPORT_X_OFFSET_ENA 0x00000002
-# define R200_VPORT_Y_SCALE_ENA 0x00000004
-# define R200_VPORT_Y_OFFSET_ENA 0x00000008
-# define R200_VPORT_Z_SCALE_ENA 0x00000010
-# define R200_VPORT_Z_OFFSET_ENA 0x00000020
-# define R200_VTX_XY_FMT 0x00000100
-# define R200_VTX_Z_FMT 0x00000200
-# define R200_VTX_W0_FMT 0x00000400
-# define R200_VTX_W0_NORMALIZE 0x00000800
-# define R200_VTX_ST_DENORMALIZED 0x00001000
-#define R200_SE_VAP_CNTL_STATUS 0x2140
-# define R200_VC_NO_SWAP (0 << 0)
-# define R200_VC_16BIT_SWAP (1 << 0)
-# define R200_VC_32BIT_SWAP (2 << 0)
-#define R200_PP_TXFILTER_0 0x2c00
-#define R200_PP_TXFILTER_1 0x2c20
-#define R200_PP_TXFILTER_2 0x2c40
-#define R200_PP_TXFILTER_3 0x2c60
-#define R200_PP_TXFILTER_4 0x2c80
-#define R200_PP_TXFILTER_5 0x2ca0
-# define R200_MAG_FILTER_NEAREST (0 << 0)
-# define R200_MAG_FILTER_LINEAR (1 << 0)
-# define R200_MAG_FILTER_MASK (1 << 0)
-# define R200_MIN_FILTER_NEAREST (0 << 1)
-# define R200_MIN_FILTER_LINEAR (1 << 1)
-# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
-# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
-# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
-# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
-# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)
-# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)
-# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
-# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
-# define R200_MIN_FILTER_MASK (15 << 1)
-# define R200_MAX_ANISO_1_TO_1 (0 << 5)
-# define R200_MAX_ANISO_2_TO_1 (1 << 5)
-# define R200_MAX_ANISO_4_TO_1 (2 << 5)
-# define R200_MAX_ANISO_8_TO_1 (3 << 5)
-# define R200_MAX_ANISO_16_TO_1 (4 << 5)
-# define R200_MAX_ANISO_MASK (7 << 5)
-# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)
-# define R200_MAX_MIP_LEVEL_SHIFT 16
-# define R200_YUV_TO_RGB (1 << 20)
-# define R200_YUV_TEMPERATURE_COOL (0 << 21)
-# define R200_YUV_TEMPERATURE_HOT (1 << 21)
-# define R200_YUV_TEMPERATURE_MASK (1 << 21)
-# define R200_WRAPEN_S (1 << 22)
-# define R200_CLAMP_S_WRAP (0 << 23)
-# define R200_CLAMP_S_MIRROR (1 << 23)
-# define R200_CLAMP_S_CLAMP_LAST (2 << 23)
-# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
-# define R200_CLAMP_S_CLAMP_BORDER (4 << 23)
-# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
-# define R200_CLAMP_S_CLAMP_GL (6 << 23)
-# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
-# define R200_CLAMP_S_MASK (7 << 23)
-# define R200_WRAPEN_T (1 << 26)
-# define R200_CLAMP_T_WRAP (0 << 27)
-# define R200_CLAMP_T_MIRROR (1 << 27)
-# define R200_CLAMP_T_CLAMP_LAST (2 << 27)
-# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
-# define R200_CLAMP_T_CLAMP_BORDER (4 << 27)
-# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
-# define R200_CLAMP_T_CLAMP_GL (6 << 27)
-# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
-# define R200_CLAMP_T_MASK (7 << 27)
-# define R200_KILL_LT_ZERO (1 << 30)
-# define R200_BORDER_MODE_OGL (0 << 31)
-# define R200_BORDER_MODE_D3D (1 << 31)
-#define R200_PP_TXFORMAT_0 0x2c04
-#define R200_PP_TXFORMAT_1 0x2c24
-#define R200_PP_TXFORMAT_2 0x2c44
-#define R200_PP_TXFORMAT_3 0x2c64
-#define R200_PP_TXFORMAT_4 0x2c84
-#define R200_PP_TXFORMAT_5 0x2ca4
-# define R200_TXFORMAT_I8 (0 << 0)
-# define R200_TXFORMAT_AI88 (1 << 0)
-# define R200_TXFORMAT_RGB332 (2 << 0)
-# define R200_TXFORMAT_ARGB1555 (3 << 0)
-# define R200_TXFORMAT_RGB565 (4 << 0)
-# define R200_TXFORMAT_ARGB4444 (5 << 0)
-# define R200_TXFORMAT_ARGB8888 (6 << 0)
-# define R200_TXFORMAT_RGBA8888 (7 << 0)
-# define R200_TXFORMAT_Y8 (8 << 0)
-# define R200_TXFORMAT_AVYU4444 (9 << 0)
-# define R200_TXFORMAT_VYUY422 (10 << 0)
-# define R200_TXFORMAT_YVYU422 (11 << 0)
-# define R200_TXFORMAT_DXT1 (12 << 0)
-# define R200_TXFORMAT_DXT23 (14 << 0)
-# define R200_TXFORMAT_DXT45 (15 << 0)
-# define R200_TXFORMAT_ABGR8888 (22 << 0)
-# define R200_TXFORMAT_FORMAT_MASK (31 << 0)
-# define R200_TXFORMAT_FORMAT_SHIFT 0
-# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
-# define R200_TXFORMAT_NON_POWER2 (1 << 7)
-# define R200_TXFORMAT_WIDTH_MASK (15 << 8)
-# define R200_TXFORMAT_WIDTH_SHIFT 8
-# define R200_TXFORMAT_HEIGHT_MASK (15 << 12)
-# define R200_TXFORMAT_HEIGHT_SHIFT 12
-# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */
-# define R200_TXFORMAT_F5_WIDTH_SHIFT 16
-# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
-# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20
-# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
-# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
-# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
-# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)
-# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)
-# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)
-# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)
-# define R200_TXFORMAT_ST_ROUTE_SHIFT 24
-# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
-# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
-# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
-#define R200_PP_TXFORMAT_X_0 0x2c08
-#define R200_PP_TXFORMAT_X_1 0x2c28
-#define R200_PP_TXFORMAT_X_2 0x2c48
-#define R200_PP_TXFORMAT_X_3 0x2c68
-#define R200_PP_TXFORMAT_X_4 0x2c88
-#define R200_PP_TXFORMAT_X_5 0x2ca8
-
-#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */
-#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */
-#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */
-#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */
-#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */
-#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */
-
-#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
-#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */
-#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */
-#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */
-#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
-#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
-
-#define R200_PP_TXOFFSET_0 0x2d00
-# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
-# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
-# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)
-# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
-# define R200_TXO_MACRO_LINEAR (0 << 2)
-# define R200_TXO_MACRO_TILE (1 << 2)
-# define R200_TXO_MICRO_LINEAR (0 << 3)
-# define R200_TXO_MICRO_TILE (1 << 3)
-# define R200_TXO_OFFSET_MASK 0xffffffe0
-# define R200_TXO_OFFSET_SHIFT 5
-#define R200_PP_TXOFFSET_1 0x2d18
-#define R200_PP_TXOFFSET_2 0x2d30
-#define R200_PP_TXOFFSET_3 0x2d48
-#define R200_PP_TXOFFSET_4 0x2d60
-#define R200_PP_TXOFFSET_5 0x2d78
-
-#define R200_PP_TFACTOR_0 0x2ee0
-#define R200_PP_TFACTOR_1 0x2ee4
-#define R200_PP_TFACTOR_2 0x2ee8
-#define R200_PP_TFACTOR_3 0x2eec
-#define R200_PP_TFACTOR_4 0x2ef0
-#define R200_PP_TFACTOR_5 0x2ef4
-
-#define R200_PP_TXCBLEND_0 0x2f00
-# define R200_TXC_ARG_A_ZERO (0)
-# define R200_TXC_ARG_A_CURRENT_COLOR (2)
-# define R200_TXC_ARG_A_CURRENT_ALPHA (3)
-# define R200_TXC_ARG_A_DIFFUSE_COLOR (4)
-# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)
-# define R200_TXC_ARG_A_SPECULAR_COLOR (6)
-# define R200_TXC_ARG_A_SPECULAR_ALPHA (7)
-# define R200_TXC_ARG_A_TFACTOR_COLOR (8)
-# define R200_TXC_ARG_A_TFACTOR_ALPHA (9)
-# define R200_TXC_ARG_A_R0_COLOR (10)
-# define R200_TXC_ARG_A_R0_ALPHA (11)
-# define R200_TXC_ARG_A_R1_COLOR (12)
-# define R200_TXC_ARG_A_R1_ALPHA (13)
-# define R200_TXC_ARG_A_R2_COLOR (14)
-# define R200_TXC_ARG_A_R2_ALPHA (15)
-# define R200_TXC_ARG_A_R3_COLOR (16)
-# define R200_TXC_ARG_A_R3_ALPHA (17)
-# define R200_TXC_ARG_A_R4_COLOR (18)
-# define R200_TXC_ARG_A_R4_ALPHA (19)
-# define R200_TXC_ARG_A_R5_COLOR (20)
-# define R200_TXC_ARG_A_R5_ALPHA (21)
-# define R200_TXC_ARG_A_TFACTOR1_COLOR (26)
-# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)
-# define R200_TXC_ARG_A_MASK (31 << 0)
-# define R200_TXC_ARG_A_SHIFT 0
-# define R200_TXC_ARG_B_ZERO (0 << 5)
-# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)
-# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)
-# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)
-# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)
-# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)
-# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)
-# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)
-# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)
-# define R200_TXC_ARG_B_R0_COLOR (10 << 5)
-# define R200_TXC_ARG_B_R0_ALPHA (11 << 5)
-# define R200_TXC_ARG_B_R1_COLOR (12 << 5)
-# define R200_TXC_ARG_B_R1_ALPHA (13 << 5)
-# define R200_TXC_ARG_B_R2_COLOR (14 << 5)
-# define R200_TXC_ARG_B_R2_ALPHA (15 << 5)
-# define R200_TXC_ARG_B_R3_COLOR (16 << 5)
-# define R200_TXC_ARG_B_R3_ALPHA (17 << 5)
-# define R200_TXC_ARG_B_R4_COLOR (18 << 5)
-# define R200_TXC_ARG_B_R4_ALPHA (19 << 5)
-# define R200_TXC_ARG_B_R5_COLOR (20 << 5)
-# define R200_TXC_ARG_B_R5_ALPHA (21 << 5)
-# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)
-# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)
-# define R200_TXC_ARG_B_MASK (31 << 5)
-# define R200_TXC_ARG_B_SHIFT 5
-# define R200_TXC_ARG_C_ZERO (0 << 10)
-# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)
-# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)
-# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)
-# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)
-# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)
-# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)
-# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)
-# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)
-# define R200_TXC_ARG_C_R0_COLOR (10 << 10)
-# define R200_TXC_ARG_C_R0_ALPHA (11 << 10)
-# define R200_TXC_ARG_C_R1_COLOR (12 << 10)
-# define R200_TXC_ARG_C_R1_ALPHA (13 << 10)
-# define R200_TXC_ARG_C_R2_COLOR (14 << 10)
-# define R200_TXC_ARG_C_R2_ALPHA (15 << 10)
-# define R200_TXC_ARG_C_R3_COLOR (16 << 10)
-# define R200_TXC_ARG_C_R3_ALPHA (17 << 10)
-# define R200_TXC_ARG_C_R4_COLOR (18 << 10)
-# define R200_TXC_ARG_C_R4_ALPHA (19 << 10)
-# define R200_TXC_ARG_C_R5_COLOR (20 << 10)
-# define R200_TXC_ARG_C_R5_ALPHA (21 << 10)
-# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)
-# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)
-# define R200_TXC_ARG_C_MASK (31 << 10)
-# define R200_TXC_ARG_C_SHIFT 10
-# define R200_TXC_COMP_ARG_A (1 << 16)
-# define R200_TXC_COMP_ARG_A_SHIFT (16)
-# define R200_TXC_BIAS_ARG_A (1 << 17)
-# define R200_TXC_SCALE_ARG_A (1 << 18)
-# define R200_TXC_NEG_ARG_A (1 << 19)
-# define R200_TXC_COMP_ARG_B (1 << 20)
-# define R200_TXC_COMP_ARG_B_SHIFT (20)
-# define R200_TXC_BIAS_ARG_B (1 << 21)
-# define R200_TXC_SCALE_ARG_B (1 << 22)
-# define R200_TXC_NEG_ARG_B (1 << 23)
-# define R200_TXC_COMP_ARG_C (1 << 24)
-# define R200_TXC_COMP_ARG_C_SHIFT (24)
-# define R200_TXC_BIAS_ARG_C (1 << 25)
-# define R200_TXC_SCALE_ARG_C (1 << 26)
-# define R200_TXC_NEG_ARG_C (1 << 27)
-# define R200_TXC_OP_MADD (0 << 28)
-# define R200_TXC_OP_CND0 (2 << 28)
-# define R200_TXC_OP_LERP (3 << 28)
-# define R200_TXC_OP_DOT3 (4 << 28)
-# define R200_TXC_OP_DOT4 (5 << 28)
-# define R200_TXC_OP_CONDITIONAL (6 << 28)
-# define R200_TXC_OP_DOT2_ADD (7 << 28)
-# define R200_TXC_OP_MASK (7 << 28)
-#define R200_PP_TXCBLEND2_0 0x2f04
-# define R200_TXC_TFACTOR_SEL_SHIFT 0
-# define R200_TXC_TFACTOR_SEL_MASK 0x7
-# define R200_TXC_TFACTOR1_SEL_SHIFT 4
-# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)
-# define R200_TXC_SCALE_SHIFT 8
-# define R200_TXC_SCALE_MASK (7 << 8)
-# define R200_TXC_SCALE_1X (0 << 8)
-# define R200_TXC_SCALE_2X (1 << 8)
-# define R200_TXC_SCALE_4X (2 << 8)
-# define R200_TXC_SCALE_8X (3 << 8)
-# define R200_TXC_SCALE_INV2 (5 << 8)
-# define R200_TXC_SCALE_INV4 (6 << 8)
-# define R200_TXC_SCALE_INV8 (7 << 8)
-# define R200_TXC_CLAMP_SHIFT 12
-# define R200_TXC_CLAMP_MASK (3 << 12)
-# define R200_TXC_CLAMP_WRAP (0 << 12)
-# define R200_TXC_CLAMP_0_1 (1 << 12)
-# define R200_TXC_CLAMP_8_8 (2 << 12)
-# define R200_TXC_OUTPUT_REG_MASK (7 << 16)
-# define R200_TXC_OUTPUT_REG_NONE (0 << 16)
-# define R200_TXC_OUTPUT_REG_R0 (1 << 16)
-# define R200_TXC_OUTPUT_REG_R1 (2 << 16)
-# define R200_TXC_OUTPUT_REG_R2 (3 << 16)
-# define R200_TXC_OUTPUT_REG_R3 (4 << 16)
-# define R200_TXC_OUTPUT_REG_R4 (5 << 16)
-# define R200_TXC_OUTPUT_REG_R5 (6 << 16)
-# define R200_TXC_OUTPUT_MASK_MASK (7 << 20)
-# define R200_TXC_OUTPUT_MASK_RGB (0 << 20)
-# define R200_TXC_OUTPUT_MASK_RG (1 << 20)
-# define R200_TXC_OUTPUT_MASK_RB (2 << 20)
-# define R200_TXC_OUTPUT_MASK_R (3 << 20)
-# define R200_TXC_OUTPUT_MASK_GB (4 << 20)
-# define R200_TXC_OUTPUT_MASK_G (5 << 20)
-# define R200_TXC_OUTPUT_MASK_B (6 << 20)
-# define R200_TXC_OUTPUT_MASK_NONE (7 << 20)
-# define R200_TXC_REPL_NORMAL 0
-# define R200_TXC_REPL_RED 1
-# define R200_TXC_REPL_GREEN 2
-# define R200_TXC_REPL_BLUE 3
-# define R200_TXC_REPL_ARG_A_SHIFT 26
-# define R200_TXC_REPL_ARG_A_MASK (3 << 26)
-# define R200_TXC_REPL_ARG_B_SHIFT 28
-# define R200_TXC_REPL_ARG_B_MASK (3 << 28)
-# define R200_TXC_REPL_ARG_C_SHIFT 30
-# define R200_TXC_REPL_ARG_C_MASK (3 << 30)
-#define R200_PP_TXABLEND_0 0x2f08
-# define R200_TXA_ARG_A_ZERO (0)
-# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */
-# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */
-# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)
-# define R200_TXA_ARG_A_DIFFUSE_BLUE (5)
-# define R200_TXA_ARG_A_SPECULAR_ALPHA (6)
-# define R200_TXA_ARG_A_SPECULAR_BLUE (7)
-# define R200_TXA_ARG_A_TFACTOR_ALPHA (8)
-# define R200_TXA_ARG_A_TFACTOR_BLUE (9)
-# define R200_TXA_ARG_A_R0_ALPHA (10)
-# define R200_TXA_ARG_A_R0_BLUE (11)
-# define R200_TXA_ARG_A_R1_ALPHA (12)
-# define R200_TXA_ARG_A_R1_BLUE (13)
-# define R200_TXA_ARG_A_R2_ALPHA (14)
-# define R200_TXA_ARG_A_R2_BLUE (15)
-# define R200_TXA_ARG_A_R3_ALPHA (16)
-# define R200_TXA_ARG_A_R3_BLUE (17)
-# define R200_TXA_ARG_A_R4_ALPHA (18)
-# define R200_TXA_ARG_A_R4_BLUE (19)
-# define R200_TXA_ARG_A_R5_ALPHA (20)
-# define R200_TXA_ARG_A_R5_BLUE (21)
-# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)
-# define R200_TXA_ARG_A_TFACTOR1_BLUE (27)
-# define R200_TXA_ARG_A_MASK (31 << 0)
-# define R200_TXA_ARG_A_SHIFT 0
-# define R200_TXA_ARG_B_ZERO (0 << 5)
-# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */
-# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */
-# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)
-# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)
-# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)
-# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)
-# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)
-# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)
-# define R200_TXA_ARG_B_R0_ALPHA (10 << 5)
-# define R200_TXA_ARG_B_R0_BLUE (11 << 5)
-# define R200_TXA_ARG_B_R1_ALPHA (12 << 5)
-# define R200_TXA_ARG_B_R1_BLUE (13 << 5)
-# define R200_TXA_ARG_B_R2_ALPHA (14 << 5)
-# define R200_TXA_ARG_B_R2_BLUE (15 << 5)
-# define R200_TXA_ARG_B_R3_ALPHA (16 << 5)
-# define R200_TXA_ARG_B_R3_BLUE (17 << 5)
-# define R200_TXA_ARG_B_R4_ALPHA (18 << 5)
-# define R200_TXA_ARG_B_R4_BLUE (19 << 5)
-# define R200_TXA_ARG_B_R5_ALPHA (20 << 5)
-# define R200_TXA_ARG_B_R5_BLUE (21 << 5)
-# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)
-# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)
-# define R200_TXA_ARG_B_MASK (31 << 5)
-# define R200_TXA_ARG_B_SHIFT 5
-# define R200_TXA_ARG_C_ZERO (0 << 10)
-# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */
-# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */
-# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)
-# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)
-# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)
-# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)
-# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)
-# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)
-# define R200_TXA_ARG_C_R0_ALPHA (10 << 10)
-# define R200_TXA_ARG_C_R0_BLUE (11 << 10)
-# define R200_TXA_ARG_C_R1_ALPHA (12 << 10)
-# define R200_TXA_ARG_C_R1_BLUE (13 << 10)
-# define R200_TXA_ARG_C_R2_ALPHA (14 << 10)
-# define R200_TXA_ARG_C_R2_BLUE (15 << 10)
-# define R200_TXA_ARG_C_R3_ALPHA (16 << 10)
-# define R200_TXA_ARG_C_R3_BLUE (17 << 10)
-# define R200_TXA_ARG_C_R4_ALPHA (18 << 10)
-# define R200_TXA_ARG_C_R4_BLUE (19 << 10)
-# define R200_TXA_ARG_C_R5_ALPHA (20 << 10)
-# define R200_TXA_ARG_C_R5_BLUE (21 << 10)
-# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)
-# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)
-# define R200_TXA_ARG_C_MASK (31 << 10)
-# define R200_TXA_ARG_C_SHIFT 10
-# define R200_TXA_COMP_ARG_A (1 << 16)
-# define R200_TXA_COMP_ARG_A_SHIFT (16)
-# define R200_TXA_BIAS_ARG_A (1 << 17)
-# define R200_TXA_SCALE_ARG_A (1 << 18)
-# define R200_TXA_NEG_ARG_A (1 << 19)
-# define R200_TXA_COMP_ARG_B (1 << 20)
-# define R200_TXA_COMP_ARG_B_SHIFT (20)
-# define R200_TXA_BIAS_ARG_B (1 << 21)
-# define R200_TXA_SCALE_ARG_B (1 << 22)
-# define R200_TXA_NEG_ARG_B (1 << 23)
-# define R200_TXA_COMP_ARG_C (1 << 24)
-# define R200_TXA_COMP_ARG_C_SHIFT (24)
-# define R200_TXA_BIAS_ARG_C (1 << 25)
-# define R200_TXA_SCALE_ARG_C (1 << 26)
-# define R200_TXA_NEG_ARG_C (1 << 27)
-# define R200_TXA_OP_MADD (0 << 28)
-# define R200_TXA_OP_CND0 (2 << 28)
-# define R200_TXA_OP_LERP (3 << 28)
-# define R200_TXA_OP_CONDITIONAL (6 << 28)
-# define R200_TXA_OP_MASK (7 << 28)
-#define R200_PP_TXABLEND2_0 0x2f0c
-# define R200_TXA_TFACTOR_SEL_SHIFT 0
-# define R200_TXA_TFACTOR_SEL_MASK 0x7
-# define R200_TXA_TFACTOR1_SEL_SHIFT 4
-# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)
-# define R200_TXA_SCALE_SHIFT 8
-# define R200_TXA_SCALE_MASK (7 << 8)
-# define R200_TXA_SCALE_1X (0 << 8)
-# define R200_TXA_SCALE_2X (1 << 8)
-# define R200_TXA_SCALE_4X (2 << 8)
-# define R200_TXA_SCALE_8X (3 << 8)
-# define R200_TXA_SCALE_INV2 (5 << 8)
-# define R200_TXA_SCALE_INV4 (6 << 8)
-# define R200_TXA_SCALE_INV8 (7 << 8)
-# define R200_TXA_CLAMP_SHIFT 12
-# define R200_TXA_CLAMP_MASK (3 << 12)
-# define R200_TXA_CLAMP_WRAP (0 << 12)
-# define R200_TXA_CLAMP_0_1 (1 << 12)
-# define R200_TXA_CLAMP_8_8 (2 << 12)
-# define R200_TXA_OUTPUT_REG_MASK (7 << 16)
-# define R200_TXA_OUTPUT_REG_NONE (0 << 16)
-# define R200_TXA_OUTPUT_REG_R0 (1 << 16)
-# define R200_TXA_OUTPUT_REG_R1 (2 << 16)
-# define R200_TXA_OUTPUT_REG_R2 (3 << 16)
-# define R200_TXA_OUTPUT_REG_R3 (4 << 16)
-# define R200_TXA_OUTPUT_REG_R4 (5 << 16)
-# define R200_TXA_OUTPUT_REG_R5 (6 << 16)
-# define R200_TXA_DOT_ALPHA (1 << 20)
-# define R200_TXA_REPL_NORMAL 0
-# define R200_TXA_REPL_RED 1
-# define R200_TXA_REPL_GREEN 2
-# define R200_TXA_REPL_ARG_A_SHIFT 26
-# define R200_TXA_REPL_ARG_A_MASK (3 << 26)
-# define R200_TXA_REPL_ARG_B_SHIFT 28
-# define R200_TXA_REPL_ARG_B_MASK (3 << 28)
-# define R200_TXA_REPL_ARG_C_SHIFT 30
-# define R200_TXA_REPL_ARG_C_MASK (3 << 30)
-
-#define R200_SE_VTX_FMT_0 0x2088
-# define R200_VTX_XY 0 /* always have xy */
-# define R200_VTX_Z0 (1<<0)
-# define R200_VTX_W0 (1<<1)
-# define R200_VTX_WEIGHT_COUNT_SHIFT (2)
-# define R200_VTX_PV_MATRIX_SEL (1<<5)
-# define R200_VTX_N0 (1<<6)
-# define R200_VTX_POINT_SIZE (1<<7)
-# define R200_VTX_DISCRETE_FOG (1<<8)
-# define R200_VTX_SHININESS_0 (1<<9)
-# define R200_VTX_SHININESS_1 (1<<10)
-# define R200_VTX_COLOR_NOT_PRESENT 0
-# define R200_VTX_PK_RGBA 1
-# define R200_VTX_FP_RGB 2
-# define R200_VTX_FP_RGBA 3
-# define R200_VTX_COLOR_MASK 3
-# define R200_VTX_COLOR_0_SHIFT 11
-# define R200_VTX_COLOR_1_SHIFT 13
-# define R200_VTX_COLOR_2_SHIFT 15
-# define R200_VTX_COLOR_3_SHIFT 17
-# define R200_VTX_COLOR_4_SHIFT 19
-# define R200_VTX_COLOR_5_SHIFT 21
-# define R200_VTX_COLOR_6_SHIFT 23
-# define R200_VTX_COLOR_7_SHIFT 25
-# define R200_VTX_XY1 (1<<28)
-# define R200_VTX_Z1 (1<<29)
-# define R200_VTX_W1 (1<<30)
-# define R200_VTX_N1 (1<<31)
-#define R200_SE_VTX_FMT_1 0x208c
-# define R200_VTX_TEX0_COMP_CNT_SHIFT 0
-# define R200_VTX_TEX1_COMP_CNT_SHIFT 3
-# define R200_VTX_TEX2_COMP_CNT_SHIFT 6
-# define R200_VTX_TEX3_COMP_CNT_SHIFT 9
-# define R200_VTX_TEX4_COMP_CNT_SHIFT 12
-# define R200_VTX_TEX5_COMP_CNT_SHIFT 15
-
-#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090
-#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094
-#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
-# define R200_OUTPUT_XYZW (1<<0)
-# define R200_OUTPUT_COLOR_0 (1<<8)
-# define R200_OUTPUT_COLOR_1 (1<<9)
-# define R200_OUTPUT_TEX_0 (1<<16)
-# define R200_OUTPUT_TEX_1 (1<<17)
-# define R200_OUTPUT_TEX_2 (1<<18)
-# define R200_OUTPUT_TEX_3 (1<<19)
-# define R200_OUTPUT_TEX_4 (1<<20)
-# define R200_OUTPUT_TEX_5 (1<<21)
-# define R200_OUTPUT_TEX_MASK (0x3f<<16)
-# define R200_OUTPUT_DISCRETE_FOG (1<<24)
-# define R200_OUTPUT_PT_SIZE (1<<25)
-# define R200_FORCE_INORDER_PROC (1<<31)
-#define R200_PP_CNTL_X 0x2cc4
-#define R200_PP_TXMULTI_CTL_0 0x2c1c
-#define R200_SE_VTX_STATE_CNTL 0x2180
-# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
-
- /* Registers for CP and Microcode Engine */
-#define RADEON_CP_ME_RAM_ADDR 0x07d4
-#define RADEON_CP_ME_RAM_RADDR 0x07d8
-#define RADEON_CP_ME_RAM_DATAH 0x07dc
-#define RADEON_CP_ME_RAM_DATAL 0x07e0
-
-#define RADEON_CP_RB_BASE 0x0700
-#define RADEON_CP_RB_CNTL 0x0704
-#define RADEON_CP_RB_RPTR_ADDR 0x070c
-#define RADEON_CP_RB_RPTR 0x0710
-#define RADEON_CP_RB_WPTR 0x0714
-
-#define RADEON_CP_IB_BASE 0x0738
-#define RADEON_CP_IB_BUFSZ 0x073c
-
-#define RADEON_CP_CSQ_CNTL 0x0740
-# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
-# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
-# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
-# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
-# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
-# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
-# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
-#define RADEON_CP_CSQ_STAT 0x07f8
-# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
-# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
-# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
-# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
-#define RADEON_CP_CSQ_ADDR 0x07f0
-#define RADEON_CP_CSQ_DATA 0x07f4
-#define RADEON_CP_CSQ_APER_PRIMARY 0x1000
-#define RADEON_CP_CSQ_APER_INDIRECT 0x1300
-
-#define RADEON_CP_RB_WPTR_DELAY 0x0718
-# define RADEON_PRE_WRITE_TIMER_SHIFT 0
-# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
-
-#define RADEON_AIC_CNTL 0x01d0
-# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
-#define RADEON_AIC_LO_ADDR 0x01dc
-
-
-
- /* Constants */
-#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
-#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
-
-
-
- /* CP packet types */
-#define RADEON_CP_PACKET0 0x00000000
-#define RADEON_CP_PACKET1 0x40000000
-#define RADEON_CP_PACKET2 0x80000000
-#define RADEON_CP_PACKET3 0xC0000000
-# define RADEON_CP_PACKET_MASK 0xC0000000
-# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
-# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
-# define RADEON_CP_PACKET0_REG_MASK 0x000007ff
-# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
-# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
-
-#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
-
-#define RADEON_CP_PACKET3_NOP 0xC0001000
-#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
-#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
-#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
-#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
-#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
-#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
-#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
-#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
-#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
-#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
-#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
-#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
-#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
-#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
-#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
-#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
-#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
-#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
-#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
-#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
-#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
-
-
-#define RADEON_CP_VC_FRMT_XY 0x00000000
-#define RADEON_CP_VC_FRMT_W0 0x00000001
-#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
-#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
-#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
-#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
-#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
-#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
-#define RADEON_CP_VC_FRMT_ST0 0x00000080
-#define RADEON_CP_VC_FRMT_ST1 0x00000100
-#define RADEON_CP_VC_FRMT_Q1 0x00000200
-#define RADEON_CP_VC_FRMT_ST2 0x00000400
-#define RADEON_CP_VC_FRMT_Q2 0x00000800
-#define RADEON_CP_VC_FRMT_ST3 0x00001000
-#define RADEON_CP_VC_FRMT_Q3 0x00002000
-#define RADEON_CP_VC_FRMT_Q0 0x00004000
-#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
-#define RADEON_CP_VC_FRMT_N0 0x00040000
-#define RADEON_CP_VC_FRMT_XY1 0x08000000
-#define RADEON_CP_VC_FRMT_Z1 0x10000000
-#define RADEON_CP_VC_FRMT_W1 0x20000000
-#define RADEON_CP_VC_FRMT_N1 0x40000000
-#define RADEON_CP_VC_FRMT_Z 0x80000000
-
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
-#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
-#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
-#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
-#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
-#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
-#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
-#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
-#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
-#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
-#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
-#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
-
-#define RADEON_VS_MATRIX_0_ADDR 0
-#define RADEON_VS_MATRIX_1_ADDR 4
-#define RADEON_VS_MATRIX_2_ADDR 8
-#define RADEON_VS_MATRIX_3_ADDR 12
-#define RADEON_VS_MATRIX_4_ADDR 16
-#define RADEON_VS_MATRIX_5_ADDR 20
-#define RADEON_VS_MATRIX_6_ADDR 24
-#define RADEON_VS_MATRIX_7_ADDR 28
-#define RADEON_VS_MATRIX_8_ADDR 32
-#define RADEON_VS_MATRIX_9_ADDR 36
-#define RADEON_VS_MATRIX_10_ADDR 40
-#define RADEON_VS_MATRIX_11_ADDR 44
-#define RADEON_VS_MATRIX_12_ADDR 48
-#define RADEON_VS_MATRIX_13_ADDR 52
-#define RADEON_VS_MATRIX_14_ADDR 56
-#define RADEON_VS_MATRIX_15_ADDR 60
-#define RADEON_VS_LIGHT_AMBIENT_ADDR 64
-#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
-#define RADEON_VS_LIGHT_SPECULAR_ADDR 80
-#define RADEON_VS_LIGHT_DIRPOS_ADDR 88
-#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
-#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
-#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
-#define RADEON_VS_UCP_ADDR 116
-#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
-#define RADEON_VS_FOG_PARAM_ADDR 123
-#define RADEON_VS_EYE_VECTOR_ADDR 124
-
-#define RADEON_SS_LIGHT_DCD_ADDR 0
-#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
-#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
-#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
-#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
-#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
-#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
-#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
-#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
-#define RADEON_SS_SHININESS 60
-
-#define RADEON_TV_MASTER_CNTL 0x0800
-# define RADEON_TV_ASYNC_RST (1 << 0)
-# define RADEON_CRT_ASYNC_RST (1 << 1)
-# define RADEON_RESTART_PHASE_FIX (1 << 3)
-# define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
-# define RADEON_VIN_ASYNC_RST (1 << 5)
-# define RADEON_AUD_ASYNC_RST (1 << 6)
-# define RADEON_DVS_ASYNC_RST (1 << 7)
-# define RADEON_CRT_FIFO_CE_EN (1 << 9)
-# define RADEON_TV_FIFO_CE_EN (1 << 10)
-# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
-# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
-# define RADEON_TV_ON (1 << 31)
-#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
-# define RADEON_Y_RED_EN (1 << 0)
-# define RADEON_C_GRN_EN (1 << 1)
-# define RADEON_CMP_BLU_EN (1 << 2)
-# define RADEON_DAC_DITHER_EN (1 << 3)
-# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
-# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
-# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
-# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
-#define RADEON_TV_RGB_CNTL 0x0804
-# define RADEON_SWITCH_TO_BLUE (1 << 4)
-# define RADEON_RGB_DITHER_EN (1 << 5)
-# define RADEON_RGB_SRC_SEL_MASK (3 << 8)
-# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
-# define RADEON_RGB_SRC_SEL_RMX (1 << 8)
-# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
-# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
-# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
-# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
-# define RADEON_TVOUT_SCALE_EN (1 << 26)
-#define RADEON_TV_SYNC_CNTL 0x0808
-# define RADEON_SYNC_OE (1 << 0)
-# define RADEON_SYNC_OUT (1 << 1)
-# define RADEON_SYNC_IN (1 << 2)
-# define RADEON_SYNC_PUB (1 << 3)
-# define RADEON_SYNC_PD (1 << 4)
-# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
-#define RADEON_TV_HTOTAL 0x080c
-#define RADEON_TV_HDISP 0x0810
-#define RADEON_TV_HSTART 0x0818
-#define RADEON_TV_HCOUNT 0x081C
-#define RADEON_TV_VTOTAL 0x0820
-#define RADEON_TV_VDISP 0x0824
-#define RADEON_TV_VCOUNT 0x0828
-#define RADEON_TV_FTOTAL 0x082c
-#define RADEON_TV_FCOUNT 0x0830
-#define RADEON_TV_FRESTART 0x0834
-#define RADEON_TV_HRESTART 0x0838
-#define RADEON_TV_VRESTART 0x083c
-#define RADEON_TV_HOST_READ_DATA 0x0840
-#define RADEON_TV_HOST_WRITE_DATA 0x0844
-#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
-# define RADEON_HOST_FIFO_RD (1 << 12)
-# define RADEON_HOST_FIFO_RD_ACK (1 << 13)
-# define RADEON_HOST_FIFO_WT (1 << 14)
-# define RADEON_HOST_FIFO_WT_ACK (1 << 15)
-#define RADEON_TV_VSCALER_CNTL1 0x084c
-# define RADEON_UV_INC_MASK 0xffff
-# define RADEON_UV_INC_SHIFT 0
-# define RADEON_Y_W_EN (1 << 24)
-# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
-# define RADEON_Y_DEL_W_SIG_SHIFT 26
-#define RADEON_TV_TIMING_CNTL 0x0850
-# define RADEON_H_INC_MASK 0xfff
-# define RADEON_H_INC_SHIFT 0
-# define RADEON_REQ_Y_FIRST (1 << 19)
-# define RADEON_FORCE_BURST_ALWAYS (1 << 21)
-# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
-# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
-#define RADEON_TV_VSCALER_CNTL2 0x0854
-# define RADEON_DITHER_MODE (1 << 0)
-# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
-# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
-# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
-#define RADEON_TV_Y_FALL_CNTL 0x0858
-# define RADEON_Y_FALL_PING_PONG (1 << 16)
-# define RADEON_Y_COEF_EN (1 << 17)
-#define RADEON_TV_Y_RISE_CNTL 0x085c
-# define RADEON_Y_RISE_PING_PONG (1 << 16)
-#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
-#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
-# define RADEON_YUPSAMP_EN (1 << 0)
-# define RADEON_UVUPSAMP_EN (1 << 2)
-#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
-# define RADEON_Y_GAIN_LIMIT_SHIFT 0
-# define RADEON_UV_GAIN_LIMIT_SHIFT 16
-#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
-# define RADEON_Y_GAIN_SHIFT 0
-# define RADEON_UV_GAIN_SHIFT 16
-#define RADEON_TV_MODULATOR_CNTL1 0x0870
-# define RADEON_YFLT_EN (1 << 2)
-# define RADEON_UVFLT_EN (1 << 3)
-# define RADEON_ALT_PHASE_EN (1 << 6)
-# define RADEON_SYNC_TIP_LEVEL (1 << 7)
-# define RADEON_BLANK_LEVEL_SHIFT 8
-# define RADEON_SET_UP_LEVEL_SHIFT 16
-# define RADEON_SLEW_RATE_LIMIT (1 << 23)
-# define RADEON_CY_FILT_BLEND_SHIFT 28
-#define RADEON_TV_MODULATOR_CNTL2 0x0874
-# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
-# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
-# define RADEON_TV_V_BURST_LEVEL_SHIFT 16
-#define RADEON_TV_CRC_CNTL 0x0890
-#define RADEON_TV_UV_ADR 0x08ac
-# define RADEON_MAX_UV_ADR_MASK 0x000000ff
-# define RADEON_MAX_UV_ADR_SHIFT 0
-# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
-# define RADEON_TABLE1_BOT_ADR_SHIFT 8
-# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
-# define RADEON_TABLE3_TOP_ADR_SHIFT 16
-# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
-# define RADEON_HCODE_TABLE_SEL_SHIFT 25
-# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
-# define RADEON_VCODE_TABLE_SEL_SHIFT 27
-# define RADEON_TV_MAX_FIFO_ADDR 0x1a7
-# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
-#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */
-#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */
-# define RADEON_TV_M0LO_MASK 0xff
-# define RADEON_TV_M0HI_MASK 0x7
-# define RADEON_TV_M0HI_SHIFT 18
-# define RADEON_TV_N0LO_MASK 0x1ff
-# define RADEON_TV_N0LO_SHIFT 8
-# define RADEON_TV_N0HI_MASK 0x3
-# define RADEON_TV_N0HI_SHIFT 21
-# define RADEON_TV_P_MASK 0xf
-# define RADEON_TV_P_SHIFT 24
-# define RADEON_TV_SLIP_EN (1 << 23)
-# define RADEON_TV_DTO_EN (1 << 28)
-#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */
-# define RADEON_TVPLL_RESET (1 << 1)
-# define RADEON_TVPLL_SLEEP (1 << 3)
-# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
-# define RADEON_TVPCP_SHIFT 8
-# define RADEON_TVPCP_MASK (7 << 8)
-# define RADEON_TVPVG_SHIFT 11
-# define RADEON_TVPVG_MASK (7 << 11)
-# define RADEON_TVPDC_SHIFT 14
-# define RADEON_TVPDC_MASK (3 << 14)
-# define RADEON_TVPLL_TEST_DIS (1 << 31)
-# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
-
-#define RADEON_RS480_UNK_e30 0xe30
-#define RADEON_RS480_UNK_e34 0xe34
-#define RADEON_RS480_UNK_e38 0xe38
-#define RADEON_RS480_UNK_e3c 0xe3c
-
-#define RS690_MC_INDEX 0x78
-# define RS690_MC_INDEX_MASK 0x1ff
-# define RS690_MC_INDEX_WR_EN (1 << 9)
-# define RS690_MC_INDEX_WR_ACK 0x7f
-#define RS690_MC_DATA 0x7c
-
-#define RS690_MC_FB_LOCATION 0x100
-#define RS690_MC_AGP_LOCATION 0x101
-#define RS690_MC_AGP_BASE 0x102
-#define RS690_MC_STATUS 0x90
-#define RS690_MC_STATUS_IDLE (1 << 0)
-
-#define AVIVO_MC_INDEX 0x0070
-#define R520_MC_STATUS 0x00
-#define R520_MC_STATUS_IDLE (1<<1)
-#define RV515_MC_STATUS 0x08
-#define RV515_MC_STATUS_IDLE (1<<4)
-#define AVIVO_MC_DATA 0x0074
-
-#define RV515_MC_FB_LOCATION 0x1
-#define RV515_MC_AGP_LOCATION 0x2
-#define R520_MC_FB_LOCATION 0x4
-#define R520_MC_AGP_LOCATION 0x5
-
-#define AVIVO_HDP_FB_LOCATION 0x134
-
-#define AVIVO_D1VGA_CONTROL 0x0330
-# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
-# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
-# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
-# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
-# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
-# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
-#define AVIVO_D2VGA_CONTROL 0x0338
-
-#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
-#define AVIVO_EXT1_PPLL_REF_DIV 0x404
-#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
-#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
-
-#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
-#define AVIVO_EXT2_PPLL_REF_DIV 0x414
-#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
-#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
-
-#define AVIVO_EXT1_PPLL_FB_DIV 0x430
-#define AVIVO_EXT2_PPLL_FB_DIV 0x434
-
-#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
-#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
-
-#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
-#define AVIVO_EXT2_PPLL_POST_DIV 0x444
-
-#define AVIVO_EXT1_PPLL_CNTL 0x448
-#define AVIVO_EXT2_PPLL_CNTL 0x44c
-
-#define AVIVO_P1PLL_CNTL 0x450
-#define AVIVO_P2PLL_CNTL 0x454
-#define AVIVO_P1PLL_INT_SS_CNTL 0x458
-#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
-#define AVIVO_P1PLL_TMDSA_CNTL 0x460
-#define AVIVO_P2PLL_LVTMA_CNTL 0x464
-
-#define AVIVO_PCLK_CRTC1_CNTL 0x480
-#define AVIVO_PCLK_CRTC2_CNTL 0x484
-
-#define AVIVO_D1CRTC_H_TOTAL 0x6000
-#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
-#define AVIVO_D1CRTC_H_SYNC_A 0x6008
-#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
-#define AVIVO_D1CRTC_H_SYNC_B 0x6010
-#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
-
-#define AVIVO_D1CRTC_V_TOTAL 0x6020
-#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
-#define AVIVO_D1CRTC_V_SYNC_A 0x6028
-#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
-#define AVIVO_D1CRTC_V_SYNC_B 0x6030
-#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
-
-#define AVIVO_D1CRTC_CONTROL 0x6080
-# define AVIVO_CRTC_EN (1<<0)
-#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
-#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
-#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
-#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
-
-/* master controls */
-#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
-#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
-
-#define AVIVO_D1GRPH_ENABLE 0x6100
-#define AVIVO_D1GRPH_CONTROL 0x6104
-# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
-# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
-# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
-# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
-
-# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
-
-# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
-# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
-
-# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
-# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
-# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
-# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
-
-
-# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
-
-# define AVIVO_D1GRPH_SWAP_RB (1<<16)
-# define AVIVO_D1GRPH_TILED (1<<20)
-# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
-
-#define AVIVO_D1GRPH_LUT_SEL 0x6108
-#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
-#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
-#define AVIVO_D1GRPH_PITCH 0x6120
-#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
-#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
-#define AVIVO_D1GRPH_X_START 0x612c
-#define AVIVO_D1GRPH_Y_START 0x6130
-#define AVIVO_D1GRPH_X_END 0x6134
-#define AVIVO_D1GRPH_Y_END 0x6138
-#define AVIVO_D1GRPH_UPDATE 0x6144
-# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)
-#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
-
-#define AVIVO_D1CUR_CONTROL 0x6400
-# define AVIVO_D1CURSOR_EN (1<<0)
-# define AVIVO_D1CURSOR_MODE_SHIFT 8
-# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)
-# define AVIVO_D1CURSOR_MODE_24BPP (0x2)
-#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
-#define AVIVO_D1CUR_SIZE 0x6410
-#define AVIVO_D1CUR_POSITION 0x6414
-#define AVIVO_D1CUR_HOT_SPOT 0x6418
-
-#define AVIVO_DC_LUT_RW_SELECT 0x6480
-#define AVIVO_DC_LUT_RW_MODE 0x6484
-#define AVIVO_DC_LUT_RW_INDEX 0x6488
-#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
-#define AVIVO_DC_LUT_PWL_DATA 0x6490
-#define AVIVO_DC_LUT_30_COLOR 0x6494
-#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
-#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
-#define AVIVO_DC_LUT_AUTOFILL 0x64a0
-
-#define AVIVO_DC_LUTA_CONTROL 0x64c0
-#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
-#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
-#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
-#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
-#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
-#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
-
-
-#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
-#define AVIVO_D1MODE_VIEWPORT_START 0x6580
-#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
-#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
-#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
-
-#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
-#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
-#define AVIVO_D1SCL_UPDATE 0x65cc
-# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
-
-/* second crtc */
-#define AVIVO_D2CRTC_H_TOTAL 0x6800
-#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
-#define AVIVO_D2CRTC_H_SYNC_A 0x6808
-#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
-#define AVIVO_D2CRTC_H_SYNC_B 0x6810
-#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
-
-#define AVIVO_D2CRTC_V_TOTAL 0x6820
-#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
-#define AVIVO_D2CRTC_V_SYNC_A 0x6828
-#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
-#define AVIVO_D2CRTC_V_SYNC_B 0x6830
-#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
-
-#define AVIVO_D2CRTC_CONTROL 0x6880
-#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
-#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
-#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
-#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
-
-#define AVIVO_D2GRPH_ENABLE 0x6900
-#define AVIVO_D2GRPH_CONTROL 0x6904
-#define AVIVO_D2GRPH_LUT_SEL 0x6908
-#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
-#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
-#define AVIVO_D2GRPH_PITCH 0x6920
-#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
-#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
-#define AVIVO_D2GRPH_X_START 0x692c
-#define AVIVO_D2GRPH_Y_START 0x6930
-#define AVIVO_D2GRPH_X_END 0x6934
-#define AVIVO_D2GRPH_Y_END 0x6938
-#define AVIVO_D2GRPH_UPDATE 0x6944
-#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
-
-#define AVIVO_D2CUR_CONTROL 0x6c00
-#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
-#define AVIVO_D2CUR_SIZE 0x6c10
-#define AVIVO_D2CUR_POSITION 0x6c14
-
-#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
-#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
-#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
-#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
-
-#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
-#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
-
-#define AVIVO_DACA_ENABLE 0x7800
-# define AVIVO_DAC_ENABLE (1 << 0)
-#define AVIVO_DACA_SOURCE_SELECT 0x7804
-# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
-# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
-# define AVIVO_DAC_SOURCE_TV (2 << 0)
-
-#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
-# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
-#define AVIVO_DACA_POWERDOWN 0x7850
-# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
-# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
-# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
-# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
-
-#define AVIVO_DACB_ENABLE 0x7a00
-#define AVIVO_DACB_SOURCE_SELECT 0x7a04
-#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
-# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
-#define AVIVO_DACB_POWERDOWN 0x7a50
-# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
-# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
-# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
-# define AVIVO_DACB_POWERDOWN_RED
-
-#define AVIVO_TMDSA_CNTL 0x7880
-# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
-# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
-# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
-# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
-# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
-# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
-# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
-#define AVIVO_TMDSA_SOURCE_SELECT 0x7884
-/* 78a8 appears to be some kind of (reasonably tolerant) clock?
- * 78d0 definitely hits the transmitter, definitely clock. */
-/* MYSTERY1 This appears to control dithering? */
-#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
-# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
-#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
-# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
-#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
-# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
-# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
-#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
-# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-
-#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
-
-#define AVIVO_LVTMA_CNTL 0x7a80
-# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
-# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
-# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
-# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
-# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
-# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
-# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
-#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
-#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
-#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
-# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
-
-
-
-#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
-# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
-
-#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
-# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
-# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
-#define R500_LVTMA_CLOCK_ENABLE 0x7b00
-#define R600_LVTMA_CLOCK_ENABLE 0x7b04
-
-#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
-#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
-# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
-
-#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
-#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
-# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
-
-#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
-#define R600_LVTMA_PWRSEQ_CNTL 0x7af4
-# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
-# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
-# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
-# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
-# define AVIVO_LVTMA_SYNCEN (1 << 8)
-# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
-# define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
-# define AVIVO_LVTMA_DIGON (1 << 16)
-# define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
-# define AVIVO_LVTMA_DIGON_POL (1 << 18)
-# define AVIVO_LVTMA_BLON (1 << 24)
-# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
-# define AVIVO_LVTMA_BLON_POL (1 << 26)
-
-#define R500_LVTMA_PWRSEQ_STATE 0x7af4
-#define R600_LVTMA_PWRSEQ_STATE 0x7af8
-# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
-# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
-# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
-# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
-# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
-# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
-
-#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
-# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
-# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
-# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
-
-#define AVIVO_GPIO_0 0x7e30
-#define AVIVO_GPIO_1 0x7e40
-#define AVIVO_GPIO_2 0x7e50
-#define AVIVO_GPIO_3 0x7e60
-
-#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
-
-#define AVIVO_I2C_STATUS 0x7d30
-# define AVIVO_I2C_STATUS_DONE (1 << 0)
-# define AVIVO_I2C_STATUS_NACK (1 << 1)
-# define AVIVO_I2C_STATUS_HALT (1 << 2)
-# define AVIVO_I2C_STATUS_GO (1 << 3)
-# define AVIVO_I2C_STATUS_MASK 0x7
-/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
- * DONE? */
-# define AVIVO_I2C_STATUS_CMD_RESET 0x7
-# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
-#define AVIVO_I2C_STOP 0x7d34
-#define AVIVO_I2C_START_CNTL 0x7d38
-# define AVIVO_I2C_START (1 << 8)
-# define AVIVO_I2C_CONNECTOR0 (0 << 16)
-# define AVIVO_I2C_CONNECTOR1 (1 << 16)
-#define R520_I2C_START (1<<0)
-#define R520_I2C_STOP (1<<1)
-#define R520_I2C_RX (1<<2)
-#define R520_I2C_EN (1<<8)
-#define R520_I2C_DDC1 (0<<16)
-#define R520_I2C_DDC2 (1<<16)
-#define R520_I2C_DDC3 (2<<16)
-#define R520_I2C_DDC_MASK (3<<16)
-#define AVIVO_I2C_CONTROL2 0x7d3c
-# define AVIVO_I2C_7D3C_SIZE_SHIFT 8
-# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
-#define AVIVO_I2C_CONTROL3 0x7d40
-/* Reading is done 4 bytes at a time: read the bottom 8 bits from
- * 7d44, four times in a row.
- * Writing is a little more complex. First write DATA with
- * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
- * magic number, zz is, I think, the slave address, and yy is the byte
- * you want to write. */
-#define AVIVO_I2C_DATA 0x7d44
-#define R520_I2C_ADDR_COUNT_MASK (0x7)
-#define R520_I2C_DATA_COUNT_SHIFT (8)
-#define R520_I2C_DATA_COUNT_MASK (0xF00)
-#define AVIVO_I2C_CNTL 0x7d50
-# define AVIVO_I2C_EN (1 << 0)
-# define AVIVO_I2C_RESET (1 << 8)
-
-#define R600_MC_VM_FB_LOCATION 0x2180
-#define R600_MC_VM_AGP_TOP 0x2184
-#define R600_MC_VM_AGP_BOT 0x2188
-#define R600_MC_VM_AGP_BASE 0x218c
-#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
-#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
-#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
-
-#define R600_HDP_NONSURFACE_BASE 0x2c04
-
-#define R600_BUS_CNTL 0x5420
-#define R600_CONFIG_CNTL 0x5424
-#define R600_CONFIG_MEMSIZE 0x5428
-#define R600_CONFIG_F0_BASE 0x542C
-#define R600_CONFIG_APER_SIZE 0x5430
-
-#define R600_BIOS_0_SCRATCH 0x1724
-#define R600_BIOS_1_SCRATCH 0x1728
-#define R600_BIOS_2_SCRATCH 0x172c
-#define R600_BIOS_3_SCRATCH 0x1730
-#define R600_BIOS_4_SCRATCH 0x1734
-#define R600_BIOS_5_SCRATCH 0x1738
-#define R600_BIOS_6_SCRATCH 0x173c
-#define R600_BIOS_7_SCRATCH 0x1740
-
-#define R300_GB_TILE_CONFIG 0x4018
-# define R300_ENABLE_TILING (1 << 0)
-# define R300_PIPE_COUNT_RV350 (0 << 1)
-# define R300_PIPE_COUNT_R300 (3 << 1)
-# define R300_PIPE_COUNT_R420_3P (6 << 1)
-# define R300_PIPE_COUNT_R420 (7 << 1)
-# define R300_TILE_SIZE_8 (0 << 4)
-# define R300_TILE_SIZE_16 (1 << 4)
-# define R300_TILE_SIZE_32 (2 << 4)
-# define R300_SUBPIXEL_1_12 (0 << 16)
-# define R300_SUBPIXEL_1_16 (1 << 16)
-#define R300_GB_SELECT 0x401c
-#define R300_GB_ENABLE 0x4008
-#define R300_GB_AA_CONFIG 0x4020
-#define R300_GB_MSPOS0 0x4010
-# define R300_MS_X0_SHIFT 0
-# define R300_MS_Y0_SHIFT 4
-# define R300_MS_X1_SHIFT 8
-# define R300_MS_Y1_SHIFT 12
-# define R300_MS_X2_SHIFT 16
-# define R300_MS_Y2_SHIFT 20
-# define R300_MSBD0_Y_SHIFT 24
-# define R300_MSBD0_X_SHIFT 28
-#define R300_GB_MSPOS1 0x4014
-# define R300_MS_X3_SHIFT 0
-# define R300_MS_Y3_SHIFT 4
-# define R300_MS_X4_SHIFT 8
-# define R300_MS_Y4_SHIFT 12
-# define R300_MS_X5_SHIFT 16
-# define R300_MS_Y5_SHIFT 20
-# define R300_MSBD1_SHIFT 24
-
-#define R300_GA_POLY_MODE 0x4288
-# define R300_FRONT_PTYPE_POINT (0 << 4)
-# define R300_FRONT_PTYPE_LINE (1 << 4)
-# define R300_FRONT_PTYPE_TRIANGE (2 << 4)
-# define R300_BACK_PTYPE_POINT (0 << 7)
-# define R300_BACK_PTYPE_LINE (1 << 7)
-# define R300_BACK_PTYPE_TRIANGE (2 << 7)
-#define R300_GA_ROUND_MODE 0x428c
-# define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
-# define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
-# define R300_COLOR_ROUND_TRUNC (0 << 2)
-# define R300_COLOR_ROUND_NEAREST (1 << 2)
-#define R300_GA_COLOR_CONTROL 0x4278
-# define R300_RGB0_SHADING_SOLID (0 << 0)
-# define R300_RGB0_SHADING_FLAT (1 << 0)
-# define R300_RGB0_SHADING_GOURAUD (2 << 0)
-# define R300_ALPHA0_SHADING_SOLID (0 << 2)
-# define R300_ALPHA0_SHADING_FLAT (1 << 2)
-# define R300_ALPHA0_SHADING_GOURAUD (2 << 2)
-# define R300_RGB1_SHADING_SOLID (0 << 4)
-# define R300_RGB1_SHADING_FLAT (1 << 4)
-# define R300_RGB1_SHADING_GOURAUD (2 << 4)
-# define R300_ALPHA1_SHADING_SOLID (0 << 6)
-# define R300_ALPHA1_SHADING_FLAT (1 << 6)
-# define R300_ALPHA1_SHADING_GOURAUD (2 << 6)
-# define R300_RGB2_SHADING_SOLID (0 << 8)
-# define R300_RGB2_SHADING_FLAT (1 << 8)
-# define R300_RGB2_SHADING_GOURAUD (2 << 8)
-# define R300_ALPHA2_SHADING_SOLID (0 << 10)
-# define R300_ALPHA2_SHADING_FLAT (1 << 10)
-# define R300_ALPHA2_SHADING_GOURAUD (2 << 10)
-# define R300_RGB3_SHADING_SOLID (0 << 12)
-# define R300_RGB3_SHADING_FLAT (1 << 12)
-# define R300_RGB3_SHADING_GOURAUD (2 << 12)
-# define R300_ALPHA3_SHADING_SOLID (0 << 14)
-# define R300_ALPHA3_SHADING_FLAT (1 << 14)
-# define R300_ALPHA3_SHADING_GOURAUD (2 << 14)
-#define R300_GA_OFFSET 0x4290
-
-#define R300_VAP_CNTL_STATUS 0x2140
-# define R300_PVS_BYPASS (1 << 8)
-#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
-#define R300_VAP_CNTL 0x2080
-# define R300_PVS_NUM_SLOTS_SHIFT 0
-# define R300_PVS_NUM_CNTLRS_SHIFT 4
-# define R300_PVS_NUM_FPUS_SHIFT 8
-# define R300_VF_MAX_VTX_NUM_SHIFT 18
-# define R300_GL_CLIP_SPACE_DEF (0 << 22)
-# define R300_DX_CLIP_SPACE_DEF (1 << 22)
-#define R300_VAP_VTE_CNTL 0x20B0
-# define R300_VPORT_X_SCALE_ENA (1 << 0)
-# define R300_VPORT_X_OFFSET_ENA (1 << 1)
-# define R300_VPORT_Y_SCALE_ENA (1 << 2)
-# define R300_VPORT_Y_OFFSET_ENA (1 << 3)
-# define R300_VPORT_Z_SCALE_ENA (1 << 4)
-# define R300_VPORT_Z_OFFSET_ENA (1 << 5)
-# define R300_VTX_XY_FMT (1 << 8)
-# define R300_VTX_Z_FMT (1 << 9)
-# define R300_VTX_W0_FMT (1 << 10)
-#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC
-#define R300_VAP_PROG_STREAM_CNTL_0 0x2150
-# define R300_DATA_TYPE_0_SHIFT 0
-# define R300_DATA_TYPE_FLOAT_1 0
-# define R300_DATA_TYPE_FLOAT_2 1
-# define R300_DATA_TYPE_FLOAT_3 2
-# define R300_DATA_TYPE_FLOAT_4 3
-# define R300_DATA_TYPE_BYTE 4
-# define R300_DATA_TYPE_D3DCOLOR 5
-# define R300_DATA_TYPE_SHORT_2 6
-# define R300_DATA_TYPE_SHORT_4 7
-# define R300_DATA_TYPE_VECTOR_3_TTT 8
-# define R300_DATA_TYPE_VECTOR_3_EET 9
-# define R300_SKIP_DWORDS_0_SHIFT 4
-# define R300_DST_VEC_LOC_0_SHIFT 8
-# define R300_LAST_VEC_0 (1 << 13)
-# define R300_SIGNED_0 (1 << 14)
-# define R300_NORMALIZE_0 (1 << 15)
-# define R300_DATA_TYPE_1_SHIFT 16
-# define R300_SKIP_DWORDS_1_SHIFT 20
-# define R300_DST_VEC_LOC_1_SHIFT 24
-# define R300_LAST_VEC_1 (1 << 29)
-# define R300_SIGNED_1 (1 << 30)
-# define R300_NORMALIZE_1 (1 << 31)
-#define R300_VAP_PROG_STREAM_CNTL_1 0x2154
-# define R300_DATA_TYPE_2_SHIFT 0
-# define R300_SKIP_DWORDS_2_SHIFT 4
-# define R300_DST_VEC_LOC_2_SHIFT 8
-# define R300_LAST_VEC_2 (1 << 13)
-# define R300_SIGNED_2 (1 << 14)
-# define R300_NORMALIZE_2 (1 << 15)
-# define R300_DATA_TYPE_3_SHIFT 16
-# define R300_SKIP_DWORDS_3_SHIFT 20
-# define R300_DST_VEC_LOC_3_SHIFT 24
-# define R300_LAST_VEC_3 (1 << 29)
-# define R300_SIGNED_3 (1 << 30)
-# define R300_NORMALIZE_3 (1 << 31)
-#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
-# define R300_SWIZZLE_SELECT_X_0_SHIFT 0
-# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3
-# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6
-# define R300_SWIZZLE_SELECT_W_0_SHIFT 9
-# define R300_SWIZZLE_SELECT_X 0
-# define R300_SWIZZLE_SELECT_Y 1
-# define R300_SWIZZLE_SELECT_Z 2
-# define R300_SWIZZLE_SELECT_W 3
-# define R300_SWIZZLE_SELECT_FP_ZERO 4
-# define R300_SWIZZLE_SELECT_FP_ONE 5
-# define R300_WRITE_ENA_0_SHIFT 12
-# define R300_WRITE_ENA_X 1
-# define R300_WRITE_ENA_Y 2
-# define R300_WRITE_ENA_Z 4
-# define R300_WRITE_ENA_W 8
-# define R300_SWIZZLE_SELECT_X_1_SHIFT 16
-# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19
-# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22
-# define R300_SWIZZLE_SELECT_W_1_SHIFT 25
-# define R300_WRITE_ENA_1_SHIFT 28
-#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
-# define R300_SWIZZLE_SELECT_X_2_SHIFT 0
-# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3
-# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6
-# define R300_SWIZZLE_SELECT_W_2_SHIFT 9
-# define R300_WRITE_ENA_2_SHIFT 12
-# define R300_SWIZZLE_SELECT_X_3_SHIFT 16
-# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19
-# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22
-# define R300_SWIZZLE_SELECT_W_3_SHIFT 25
-# define R300_WRITE_ENA_3_SHIFT 28
-#define R300_VAP_PVS_CODE_CNTL_0 0x22D0
-# define R300_PVS_FIRST_INST_SHIFT 0
-# define R300_PVS_XYZW_VALID_INST_SHIFT 10
-# define R300_PVS_LAST_INST_SHIFT 20
-#define R300_VAP_PVS_CODE_CNTL_1 0x22D8
-# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
-#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
-#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
-#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
-#define R300_VAP_OUT_VTX_FMT_0 0x2090
-# define R300_VTX_POS_PRESENT (1 << 0)
-# define R300_VTX_COLOR_0_PRESENT (1 << 1)
-# define R300_VTX_COLOR_1_PRESENT (1 << 2)
-# define R300_VTX_COLOR_2_PRESENT (1 << 3)
-# define R300_VTX_COLOR_3_PRESENT (1 << 4)
-# define R300_VTX_PT_SIZE_PRESENT (1 << 16)
-#define R300_VAP_OUT_VTX_FMT_1 0x2094
-# define R300_TEX_0_COMP_CNT_SHIFT 0
-# define R300_TEX_1_COMP_CNT_SHIFT 3
-# define R300_TEX_2_COMP_CNT_SHIFT 6
-# define R300_TEX_3_COMP_CNT_SHIFT 9
-# define R300_TEX_4_COMP_CNT_SHIFT 12
-# define R300_TEX_5_COMP_CNT_SHIFT 15
-# define R300_TEX_6_COMP_CNT_SHIFT 18
-# define R300_TEX_7_COMP_CNT_SHIFT 21
-#define R300_VAP_VTX_SIZE 0x20b4
-#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
-#define R300_VAP_GB_VERT_DISC_ADJ 0x2224
-#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
-#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
-#define R300_VAP_CLIP_CNTL 0x221c
-# define R300_UCP_ENA_0 (1 << 0)
-# define R300_UCP_ENA_1 (1 << 1)
-# define R300_UCP_ENA_2 (1 << 2)
-# define R300_UCP_ENA_3 (1 << 3)
-# define R300_UCP_ENA_4 (1 << 4)
-# define R300_UCP_ENA_5 (1 << 5)
-# define R300_PS_UCP_MODE_SHIFT 14
-# define R300_CLIP_DISABLE (1 << 16)
-# define R300_UCP_CULL_ONLY_ENA (1 << 17)
-# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)
-
-#define R300_SU_TEX_WRAP 0x42a0
-#define R300_SU_POLY_OFFSET_ENABLE 0x42b4
-#define R300_SU_CULL_MODE 0x42b8
-# define R300_CULL_FRONT (1 << 0)
-# define R300_CULL_BACK (1 << 1)
-# define R300_FACE_POS (0 << 2)
-# define R300_FACE_NEG (1 << 2)
-#define R300_SU_DEPTH_SCALE 0x42c0
-#define R300_SU_DEPTH_OFFSET 0x42c4
-
-#define R300_RS_COUNT 0x4300
-# define R300_RS_COUNT_IT_COUNT_SHIFT 0
-# define R300_RS_COUNT_IC_COUNT_SHIFT 7
-# define R300_RS_COUNT_HIRES_EN (1 << 18)
-
-#define R300_RS_IP_0 0x4310
-# define R300_RS_TEX_PTR(x) (x << 0)
-# define R300_RS_COL_PTR(x) (x << 6)
-# define R300_RS_COL_FMT(x) (x << 9)
-# define R300_RS_COL_FMT_RGBA 0
-# define R300_RS_COL_FMT_RGB0 2
-# define R300_RS_COL_FMT_RGB1 3
-# define R300_RS_COL_FMT_000A 4
-# define R300_RS_COL_FMT_0000 5
-# define R300_RS_COL_FMT_0001 6
-# define R300_RS_COL_FMT_111A 8
-# define R300_RS_COL_FMT_1110 9
-# define R300_RS_COL_FMT_1111 10
-# define R300_RS_SEL_S(x) (x << 13)
-# define R300_RS_SEL_T(x) (x << 16)
-# define R300_RS_SEL_R(x) (x << 19)
-# define R300_RS_SEL_Q(x) (x << 22)
-# define R300_RS_SEL_C0 0
-# define R300_RS_SEL_C1 1
-# define R300_RS_SEL_C2 2
-# define R300_RS_SEL_C3 3
-# define R300_RS_SEL_K0 4
-# define R300_RS_SEL_K1 5
-#define R300_RS_INST_COUNT 0x4304
-# define R300_INST_COUNT_RS(x) (x << 0)
-# define R300_RS_W_EN (1 << 4)
-# define R300_TX_OFFSET_RS(x) (x << 5)
-#define R300_RS_INST_0 0x4330
-# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
-
-#define R300_TX_INVALTAGS 0x4100
-#define R300_TX_FILTER0_0 0x4400
-# define R300_TX_CLAMP_S(x) (x << 0)
-# define R300_TX_CLAMP_T(x) (x << 3)
-# define R300_TX_CLAMP_R(x) (x << 6)
-# define R300_TX_CLAMP_WRAP 0
-# define R300_TX_CLAMP_MIRROR 1
-# define R300_TX_CLAMP_CLAMP_LAST 2
-# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3
-# define R300_TX_CLAMP_CLAMP_BORDER 4
-# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5
-# define R300_TX_CLAMP_CLAMP_GL 6
-# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7
-# define R300_TX_MAG_FILTER_NEAREST (1 << 9)
-# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
-# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
-# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
-#define R300_TX_FILTER1_0 0x4440
-#define R300_TX_FORMAT0_0 0x4480
-# define R300_TXWIDTH_SHIFT 0
-# define R300_TXHEIGHT_SHIFT 11
-# define R300_NUM_LEVELS_SHIFT 26
-# define R300_NUM_LEVELS_MASK 0x
-# define R300_TXPROJECTED (1 << 30)
-# define R300_TXPITCH_EN (1 << 31)
-#define R300_TX_FORMAT1_0 0x44c0
-# define R300_TX_FORMAT_X8 0x0
-# define R300_TX_FORMAT_X16 0x1
-# define R300_TX_FORMAT_Y4X4 0x2
-# define R300_TX_FORMAT_Y8X8 0x3
-# define R300_TX_FORMAT_Y16X16 0x4
-# define R300_TX_FORMAT_Z3Y3X2 0x5
-# define R300_TX_FORMAT_Z5Y6X5 0x6
-# define R300_TX_FORMAT_Z6Y5X5 0x7
-# define R300_TX_FORMAT_Z11Y11X10 0x8
-# define R300_TX_FORMAT_Z10Y11X11 0x9
-# define R300_TX_FORMAT_W4Z4Y4X4 0xA
-# define R300_TX_FORMAT_W1Z5Y5X5 0xB
-# define R300_TX_FORMAT_W8Z8Y8X8 0xC
-# define R300_TX_FORMAT_W2Z10Y10X10 0xD
-# define R300_TX_FORMAT_W16Z16Y16X16 0xE
-# define R300_TX_FORMAT_DXT1 0xF
-# define R300_TX_FORMAT_DXT3 0x10
-# define R300_TX_FORMAT_DXT5 0x11
-# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
-# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
-# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
-# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
-# define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */
-# define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */
-# define R300_TX_FORMAT_X24_Y8 0x1e
-# define R300_TX_FORMAT_X32 0x1e
- /* Floating point formats */
- /* Note - hardware supports both 16 and 32 bit floating point */
-# define R300_TX_FORMAT_FL_I16 0x18
-# define R300_TX_FORMAT_FL_I16A16 0x19
-# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
-# define R300_TX_FORMAT_FL_I32 0x1B
-# define R300_TX_FORMAT_FL_I32A32 0x1C
-# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
- /* alpha modes, convenience mostly */
- /* if you have alpha, pick constant appropriate to the
- number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
-# define R300_TX_FORMAT_ALPHA_1CH 0x000
-# define R300_TX_FORMAT_ALPHA_2CH 0x200
-# define R300_TX_FORMAT_ALPHA_4CH 0x600
-# define R300_TX_FORMAT_ALPHA_NONE 0xA00
- /* Swizzling */
- /* constants */
-# define R300_TX_FORMAT_X 0
-# define R300_TX_FORMAT_Y 1
-# define R300_TX_FORMAT_Z 2
-# define R300_TX_FORMAT_W 3
-# define R300_TX_FORMAT_ZERO 4
-# define R300_TX_FORMAT_ONE 5
- /* 2.0*Z, everything above 1.0 is set to 0.0 */
-# define R300_TX_FORMAT_CUT_Z 6
- /* 2.0*W, everything above 1.0 is set to 0.0 */
-# define R300_TX_FORMAT_CUT_W 7
-
-# define R300_TX_FORMAT_B_SHIFT 18
-# define R300_TX_FORMAT_G_SHIFT 15
-# define R300_TX_FORMAT_R_SHIFT 12
-# define R300_TX_FORMAT_A_SHIFT 9
-
- /* Convenience macro to take care of layout and swizzling */
-# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
- ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
- | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
- | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
- | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
- | (R300_TX_FORMAT_##FMT) \
- )
-
-# define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22)
-# define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22)
-# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
-
-#define R300_TX_FORMAT2_0 0x4500
-#define R300_TX_OFFSET_0 0x4540
-# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
-# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
-# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
-# define R300_MACRO_TILE (1 << 2);
-
-#define R300_TX_ENABLE 0x4104
-# define R300_TEX_0_ENABLE (1 << 0)
-# define R300_TEX_1_ENABLE (1 << 1)
-
-#define R300_US_W_FMT 0x46b4
-#define R300_US_OUT_FMT_1 0x46a8
-#define R300_US_OUT_FMT_2 0x46ac
-#define R300_US_OUT_FMT_3 0x46b0
-#define R300_US_OUT_FMT_0 0x46a4
-# define R300_OUT_FMT_C4_8 (0 << 0)
-# define R300_OUT_FMT_C4_10 (1 << 0)
-# define R300_OUT_FMT_C4_10_GAMMA (2 << 0)
-# define R300_OUT_FMT_C_16 (3 << 0)
-# define R300_OUT_FMT_C2_16 (4 << 0)
-# define R300_OUT_FMT_C4_16 (5 << 0)
-# define R300_OUT_FMT_C_16_MPEG (6 << 0)
-# define R300_OUT_FMT_C2_16_MPEG (7 << 0)
-# define R300_OUT_FMT_C2_4 (8 << 0)
-# define R300_OUT_FMT_C_3_3_2 (9 << 0)
-# define R300_OUT_FMT_C_6_5_6 (10 << 0)
-# define R300_OUT_FMT_C_11_11_10 (11 << 0)
-# define R300_OUT_FMT_C_10_11_11 (12 << 0)
-# define R300_OUT_FMT_C_2_10_10_10 (13 << 0)
-# define R300_OUT_FMT_UNUSED (15 << 0)
-# define R300_OUT_FMT_C_16_FP (16 << 0)
-# define R300_OUT_FMT_C2_16_FP (17 << 0)
-# define R300_OUT_FMT_C4_16_FP (18 << 0)
-# define R300_OUT_FMT_C_32_FP (19 << 0)
-# define R300_OUT_FMT_C2_32_FP (20 << 0)
-# define R300_OUT_FMT_C4_32_FP (21 << 0)
-# define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8)
-# define R300_OUT_FMT_C0_SEL_RED (1 << 8)
-# define R300_OUT_FMT_C0_SEL_GREEN (2 << 8)
-# define R300_OUT_FMT_C0_SEL_BLUE (3 << 8)
-# define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10)
-# define R300_OUT_FMT_C1_SEL_RED (1 << 10)
-# define R300_OUT_FMT_C1_SEL_GREEN (2 << 10)
-# define R300_OUT_FMT_C1_SEL_BLUE (3 << 10)
-# define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12)
-# define R300_OUT_FMT_C2_SEL_RED (1 << 12)
-# define R300_OUT_FMT_C2_SEL_GREEN (2 << 12)
-# define R300_OUT_FMT_C2_SEL_BLUE (3 << 12)
-# define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14)
-# define R300_OUT_FMT_C3_SEL_RED (1 << 14)
-# define R300_OUT_FMT_C3_SEL_GREEN (2 << 14)
-# define R300_OUT_FMT_C3_SEL_BLUE (3 << 14)
-#define R300_US_CONFIG 0x4600
-# define R300_NLEVEL_SHIFT 0
-# define R300_FIRST_TEX (1 << 3)
-# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
-#define R300_US_PIXSIZE 0x4604
-#define R300_US_CODE_OFFSET 0x4608
-# define R300_ALU_CODE_OFFSET(x) (x << 0)
-# define R300_ALU_CODE_SIZE(x) (x << 6)
-# define R300_TEX_CODE_OFFSET(x) (x << 13)
-# define R300_TEX_CODE_SIZE(x) (x << 18)
-#define R300_US_CODE_ADDR_0 0x4610
-#define R300_US_CODE_ADDR_1 0x4614
-#define R300_US_CODE_ADDR_2 0x4618
-#define R300_US_CODE_ADDR_3 0x461c
-#define R300_US_TEX_INST_0 0x4620
-#define R300_US_ALU_RGB_ADDR_0 0x46c0
-#define R300_US_ALU_RGB_INST_0 0x48c0
-#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
-#define R300_US_ALU_ALPHA_INST_0 0x49c0
-
-#define R300_FG_DEPTH_SRC 0x4bd8
-#define R300_FG_FOG_BLEND 0x4bc0
-#define R300_FG_ALPHA_FUNC 0x4bd4
-
-#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
-# define R300_DC_FLUSH_3D (2 << 0)
-# define R300_DC_FREE_3D (2 << 2)
-#define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
-# define R300_ZC_FLUSH (1 << 0)
-# define R300_ZC_FREE (1 << 1)
-#define R300_WAIT_UNTIL 0x1720
-# define R300_WAIT_2D_IDLECLEAN (1 << 16)
-# define R300_WAIT_3D_IDLECLEAN (1 << 17)
-#define R300_RB3D_ZSTENCILCNTL 0x4f04
-#define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
-#define R300_RB3D_BW_CNTL 0x4f1c
-#define R300_RB3D_ZCNTL 0x4f00
-#define R300_RB3D_ZTOP 0x4f14
-#define R300_RB3D_ROPCNTL 0x4e18
-#define R300_RB3D_BLENDCNTL 0x4e04
-#define R300_RB3D_ABLENDCNTL 0x4e08
-#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
-#define R300_RB3D_COLOROFFSET0 0x4e28
-#define R300_RB3D_COLORPITCH0 0x4e38
-# define R300_COLORTILE (1 << 16)
-# define R300_COLORENDIAN_WORD (1 << 19)
-# define R300_COLORENDIAN_DWORD (2 << 19)
-# define R300_COLORENDIAN_HALF_DWORD (3 << 19)
-# define R300_COLORFORMAT_ARGB1555 (3 << 21)
-# define R300_COLORFORMAT_RGB565 (4 << 21)
-# define R300_COLORFORMAT_ARGB8888 (6 << 21)
-# define R300_COLORFORMAT_ARGB32323232 (7 << 21)
-# define R300_COLORFORMAT_I8 (9 << 21)
-# define R300_COLORFORMAT_ARGB16161616 (10 << 21)
-# define R300_COLORFORMAT_VYUY (11 << 21)
-# define R300_COLORFORMAT_YVYU (12 << 21)
-# define R300_COLORFORMAT_UV88 (13 << 21)
-# define R300_COLORFORMAT_ARGB4444 (15 << 21)
-
-#define R300_RB3D_AARESOLVE_CTL 0x4e88
-#define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c
-# define R300_BLUE_MASK_EN (1 << 0)
-# define R300_GREEN_MASK_EN (1 << 1)
-# define R300_RED_MASK_EN (1 << 2)
-# define R300_ALPHA_MASK_EN (1 << 3)
-#define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14
-#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
-#define R300_RB3D_CCTL 0x4e00
-#define R300_RB3D_DITHER_CTL 0x4e50
-
-#define R300_SC_EDGERULE 0x43a8
-#define R300_SC_SCISSOR0 0x43e0
-#define R300_SC_SCISSOR1 0x43e4
-# define R300_SCISSOR_X_SHIFT 0
-# define R300_SCISSOR_Y_SHIFT 13
-#define R300_SC_CLIP_0_A 0x43b0
-#define R300_SC_CLIP_0_B 0x43b4
-# define R300_CLIP_X_SHIFT 0
-# define R300_CLIP_Y_SHIFT 13
-#define R300_SC_CLIP_RULE 0x43d0
-#define R300_SC_SCREENDOOR 0x43e8
-
-/* R500 US has to be loaded through an index/data pair */
-#define R500_GA_US_VECTOR_INDEX 0x4250
-# define R500_US_VECTOR_INDEX(x) (x << 0)
-# define R500_US_VECTOR_TYPE_INST (0 << 16)
-# define R500_US_VECTOR_TYPE_CONST (1 << 16)
-# define R500_US_VECTOR_CLAMP (1 << 17)
-#define R500_GA_US_VECTOR_DATA 0x4254
-
-/*
- * The R500 unified shader (US) registers come in banks of 512 each, one
- * for each instruction slot in the shader. You can't touch them directly.
- * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
- * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
- * instruction is fully specified.
- */
-#define R500_US_ALU_ALPHA_INST_0 0xa800
-# define R500_ALPHA_OP_MAD 0
-# define R500_ALPHA_OP_DP 1
-# define R500_ALPHA_OP_MIN 2
-# define R500_ALPHA_OP_MAX 3
-/* #define R500_ALPHA_OP_RESERVED 4 */
-# define R500_ALPHA_OP_CND 5
-# define R500_ALPHA_OP_CMP 6
-# define R500_ALPHA_OP_FRC 7
-# define R500_ALPHA_OP_EX2 8
-# define R500_ALPHA_OP_LN2 9
-# define R500_ALPHA_OP_RCP 10
-# define R500_ALPHA_OP_RSQ 11
-# define R500_ALPHA_OP_SIN 12
-# define R500_ALPHA_OP_COS 13
-# define R500_ALPHA_OP_MDH 14
-# define R500_ALPHA_OP_MDV 15
-# define R500_ALPHA_ADDRD(x) (x << 4)
-# define R500_ALPHA_ADDRD_REL (1 << 11)
-# define R500_ALPHA_SEL_A_SRC0 (0 << 12)
-# define R500_ALPHA_SEL_A_SRC1 (1 << 12)
-# define R500_ALPHA_SEL_A_SRC2 (2 << 12)
-# define R500_ALPHA_SEL_A_SRCP (3 << 12)
-# define R500_ALPHA_SWIZ_A_R (0 << 14)
-# define R500_ALPHA_SWIZ_A_G (1 << 14)
-# define R500_ALPHA_SWIZ_A_B (2 << 14)
-# define R500_ALPHA_SWIZ_A_A (3 << 14)
-# define R500_ALPHA_SWIZ_A_0 (4 << 14)
-# define R500_ALPHA_SWIZ_A_HALF (5 << 14)
-# define R500_ALPHA_SWIZ_A_1 (6 << 14)
-/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
-# define R500_ALPHA_MOD_A_NOP (0 << 17)
-# define R500_ALPHA_MOD_A_NEG (1 << 17)
-# define R500_ALPHA_MOD_A_ABS (2 << 17)
-# define R500_ALPHA_MOD_A_NAB (3 << 17)
-# define R500_ALPHA_SEL_B_SRC0 (0 << 19)
-# define R500_ALPHA_SEL_B_SRC1 (1 << 19)
-# define R500_ALPHA_SEL_B_SRC2 (2 << 19)
-# define R500_ALPHA_SEL_B_SRCP (3 << 19)
-# define R500_ALPHA_SWIZ_B_R (0 << 21)
-# define R500_ALPHA_SWIZ_B_G (1 << 21)
-# define R500_ALPHA_SWIZ_B_B (2 << 21)
-# define R500_ALPHA_SWIZ_B_A (3 << 21)
-# define R500_ALPHA_SWIZ_B_0 (4 << 21)
-# define R500_ALPHA_SWIZ_B_HALF (5 << 21)
-# define R500_ALPHA_SWIZ_B_1 (6 << 21)
-/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
-# define R500_ALPHA_MOD_B_NOP (0 << 24)
-# define R500_ALPHA_MOD_B_NEG (1 << 24)
-# define R500_ALPHA_MOD_B_ABS (2 << 24)
-# define R500_ALPHA_MOD_B_NAB (3 << 24)
-# define R500_ALPHA_OMOD_IDENTITY (0 << 26)
-# define R500_ALPHA_OMOD_MUL_2 (1 << 26)
-# define R500_ALPHA_OMOD_MUL_4 (2 << 26)
-# define R500_ALPHA_OMOD_MUL_8 (3 << 26)
-# define R500_ALPHA_OMOD_DIV_2 (4 << 26)
-# define R500_ALPHA_OMOD_DIV_4 (5 << 26)
-# define R500_ALPHA_OMOD_DIV_8 (6 << 26)
-# define R500_ALPHA_OMOD_DISABLE (7 << 26)
-# define R500_ALPHA_TARGET(x) (x << 29)
-# define R500_ALPHA_W_OMASK (1 << 31)
-#define R500_US_ALU_ALPHA_ADDR_0 0x9800
-# define R500_ALPHA_ADDR0(x) (x << 0)
-# define R500_ALPHA_ADDR0_CONST (1 << 8)
-# define R500_ALPHA_ADDR0_REL (1 << 9)
-# define R500_ALPHA_ADDR1(x) (x << 10)
-# define R500_ALPHA_ADDR1_CONST (1 << 18)
-# define R500_ALPHA_ADDR1_REL (1 << 19)
-# define R500_ALPHA_ADDR2(x) (x << 20)
-# define R500_ALPHA_ADDR2_CONST (1 << 28)
-# define R500_ALPHA_ADDR2_REL (1 << 29)
-# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
-# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
-# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
-# define R500_ALPHA_SRCP_OP_1_PLUS_A0 (3 << 30)
-#define R500_US_ALU_RGBA_INST_0 0xb000
-# define R500_ALU_RGBA_OP_MAD (0 << 0)
-# define R500_ALU_RGBA_OP_DP3 (1 << 0)
-# define R500_ALU_RGBA_OP_DP4 (2 << 0)
-# define R500_ALU_RGBA_OP_D2A (3 << 0)
-# define R500_ALU_RGBA_OP_MIN (4 << 0)
-# define R500_ALU_RGBA_OP_MAX (5 << 0)
-/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
-# define R500_ALU_RGBA_OP_CND (7 << 0)
-# define R500_ALU_RGBA_OP_CMP (8 << 0)
-# define R500_ALU_RGBA_OP_FRC (9 << 0)
-# define R500_ALU_RGBA_OP_SOP (10 << 0)
-# define R500_ALU_RGBA_OP_MDH (11 << 0)
-# define R500_ALU_RGBA_OP_MDV (12 << 0)
-# define R500_ALU_RGBA_ADDRD(x) (x << 4)
-# define R500_ALU_RGBA_ADDRD_REL (1 << 11)
-# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
-# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
-# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
-# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
-# define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
-# define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
-# define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
-# define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
-# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
-# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
-# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
-/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
-# define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
-# define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
-# define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
-# define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
-# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
-# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
-# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
-/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
-# define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
-# define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
-# define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
-# define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
-# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
-# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
-# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
-/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
-# define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
-# define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
-# define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
-# define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
-# define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
-# define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
-# define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
-# define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
-# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
-# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
-# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
-/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
-# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
-# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
-# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
-# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
-#define R500_US_ALU_RGB_INST_0 0xa000
-# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
-# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
-# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
-# define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
-# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
-/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
-# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
-/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
-# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
-/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
-# define R500_ALU_RGB_MOD_A_NOP (0 << 11)
-# define R500_ALU_RGB_MOD_A_NEG (1 << 11)
-# define R500_ALU_RGB_MOD_A_ABS (2 << 11)
-# define R500_ALU_RGB_MOD_A_NAB (3 << 11)
-# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
-# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
-# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
-# define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
-# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
-/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
-# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
-/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
-# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
-/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
-# define R500_ALU_RGB_MOD_B_NOP (0 << 24)
-# define R500_ALU_RGB_MOD_B_NEG (1 << 24)
-# define R500_ALU_RGB_MOD_B_ABS (2 << 24)
-# define R500_ALU_RGB_MOD_B_NAB (3 << 24)
-# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
-# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
-# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
-# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
-# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
-# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
-# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
-# define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
-# define R500_ALU_RGB_TARGET(x) (x << 29)
-# define R500_ALU_RGB_WMASK (1 << 31)
-#define R500_US_ALU_RGB_ADDR_0 0x9000
-# define R500_RGB_ADDR0(x) (x << 0)
-# define R500_RGB_ADDR0_CONST (1 << 8)
-# define R500_RGB_ADDR0_REL (1 << 9)
-# define R500_RGB_ADDR1(x) (x << 10)
-# define R500_RGB_ADDR1_CONST (1 << 18)
-# define R500_RGB_ADDR1_REL (1 << 19)
-# define R500_RGB_ADDR2(x) (x << 20)
-# define R500_RGB_ADDR2_CONST (1 << 28)
-# define R500_RGB_ADDR2_REL (1 << 29)
-# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
-# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
-# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
-# define R500_RGB_SRCP_OP_1_PLUS_RGB0 (3 << 30)
-#define R500_US_CMN_INST_0 0xb800
-# define R500_INST_TYPE_ALU (0 << 0)
-# define R500_INST_TYPE_OUT (1 << 0)
-# define R500_INST_TYPE_FC (2 << 0)
-# define R500_INST_TYPE_TEX (3 << 0)
-# define R500_INST_TEX_SEM_WAIT (1 << 2)
-# define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
-# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
-# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
-# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
-# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
-# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
-# define R500_INST_RGB_PRED_INV (1 << 6)
-# define R500_INST_WRITE_INACTIVE (1 << 7)
-# define R500_INST_LAST (1 << 8)
-# define R500_INST_NOP (1 << 9)
-# define R500_INST_ALU_WAIT (1 << 10)
-# define R500_INST_RGB_WMASK_R (1 << 11)
-# define R500_INST_RGB_WMASK_G (1 << 12)
-# define R500_INST_RGB_WMASK_B (1 << 13)
-# define R500_INST_ALPHA_WMASK (1 << 14)
-# define R500_INST_RGB_OMASK_R (1 << 15)
-# define R500_INST_RGB_OMASK_G (1 << 16)
-# define R500_INST_RGB_OMASK_B (1 << 17)
-# define R500_INST_ALPHA_OMASK (1 << 18)
-# define R500_INST_RGB_CLAMP (1 << 19)
-# define R500_INST_ALPHA_CLAMP (1 << 20)
-# define R500_INST_ALU_RESULT_SEL (1 << 21)
-# define R500_INST_ALPHA_PRED_INV (1 << 22)
-# define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
-# define R500_INST_ALU_RESULT_OP_LT (1 << 23)
-# define R500_INST_ALU_RESULT_OP_GE (2 << 23)
-# define R500_INST_ALU_RESULT_OP_NE (3 << 23)
-# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
-# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
-# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
-# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
-# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
-# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
-/* XXX next four are kind of guessed */
-# define R500_INST_STAT_WE_R (1 << 28)
-# define R500_INST_STAT_WE_G (1 << 29)
-# define R500_INST_STAT_WE_B (1 << 30)
-# define R500_INST_STAT_WE_A (1 << 31)
-/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
-#define R500_US_CODE_ADDR 0x4630
-# define R500_US_CODE_START_ADDR(x) (x << 0)
-# define R500_US_CODE_END_ADDR(x) (x << 16)
-#define R500_US_CODE_OFFSET 0x4638
-# define R500_US_CODE_OFFSET_ADDR(x) (x << 0)
-#define R500_US_CODE_RANGE 0x4634
-# define R500_US_CODE_RANGE_ADDR(x) (x << 0)
-# define R500_US_CODE_RANGE_SIZE(x) (x << 16)
-#define R500_US_CONFIG 0x4600
-# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
-#define R500_US_FC_ADDR_0 0xa000
-# define R500_FC_BOOL_ADDR(x) (x << 0)
-# define R500_FC_INT_ADDR(x) (x << 8)
-# define R500_FC_JUMP_ADDR(x) (x << 16)
-# define R500_FC_JUMP_GLOBAL (1 << 31)
-#define R500_US_FC_BOOL_CONST 0x4620
-# define R500_FC_KBOOL(x) (x)
-#define R500_US_FC_CTRL 0x4624
-# define R500_FC_TEST_EN (1 << 30)
-# define R500_FC_FULL_FC_EN (1 << 31)
-#define R500_US_FC_INST_0 0x9800
-# define R500_FC_OP_JUMP (0 << 0)
-# define R500_FC_OP_LOOP (1 << 0)
-# define R500_FC_OP_ENDLOOP (2 << 0)
-# define R500_FC_OP_REP (3 << 0)
-# define R500_FC_OP_ENDREP (4 << 0)
-# define R500_FC_OP_BREAKLOOP (5 << 0)
-# define R500_FC_OP_BREAKREP (6 << 0)
-# define R500_FC_OP_CONTINUE (7 << 0)
-# define R500_FC_B_ELSE (1 << 4)
-# define R500_FC_JUMP_ANY (1 << 5)
-# define R500_FC_A_OP_NONE (0 << 6)
-# define R500_FC_A_OP_POP (1 << 6)
-# define R500_FC_A_OP_PUSH (2 << 6)
-# define R500_FC_JUMP_FUNC(x) (x << 8)
-# define R500_FC_B_POP_CNT(x) (x << 16)
-# define R500_FC_B_OP0_NONE (0 << 24)
-# define R500_FC_B_OP0_DECR (1 << 24)
-# define R500_FC_B_OP0_INCR (2 << 24)
-# define R500_FC_B_OP1_DECR (0 << 26)
-# define R500_FC_B_OP1_NONE (1 << 26)
-# define R500_FC_B_OP1_INCR (2 << 26)
-# define R500_FC_IGNORE_UNCOVERED (1 << 28)
-#define R500_US_FC_INT_CONST_0 0x4c00
-# define R500_FC_INT_CONST_KR(x) (x << 0)
-# define R500_FC_INT_CONST_KG(x) (x << 8)
-# define R500_FC_INT_CONST_KB(x) (x << 16)
-/* _0 through _15 */
-#define R500_US_FORMAT0_0 0x4640
-# define R500_FORMAT_TXWIDTH(x) (x << 0)
-# define R500_FORMAT_TXHEIGHT(x) (x << 11)
-# define R500_FORMAT_TXDEPTH(x) (x << 22)
-/* _0 through _3 */
-#define R500_US_OUT_FMT_0 0x46a4
-# define R500_OUT_FMT_C4_8 (0 << 0)
-# define R500_OUT_FMT_C4_10 (1 << 0)
-# define R500_OUT_FMT_C4_10_GAMMA (2 << 0)
-# define R500_OUT_FMT_C_16 (3 << 0)
-# define R500_OUT_FMT_C2_16 (4 << 0)
-# define R500_OUT_FMT_C4_16 (5 << 0)
-# define R500_OUT_FMT_C_16_MPEG (6 << 0)
-# define R500_OUT_FMT_C2_16_MPEG (7 << 0)
-# define R500_OUT_FMT_C2_4 (8 << 0)
-# define R500_OUT_FMT_C_3_3_2 (9 << 0)
-# define R500_OUT_FMT_C_6_5_6 (10 << 0)
-# define R500_OUT_FMT_C_11_11_10 (11 << 0)
-# define R500_OUT_FMT_C_10_11_11 (12 << 0)
-# define R500_OUT_FMT_C_2_10_10_10 (13 << 0)
-/* #define R500_OUT_FMT_RESERVED (14 << 0) */
-# define R500_OUT_FMT_UNUSED (15 << 0)
-# define R500_OUT_FMT_C_16_FP (16 << 0)
-# define R500_OUT_FMT_C2_16_FP (17 << 0)
-# define R500_OUT_FMT_C4_16_FP (18 << 0)
-# define R500_OUT_FMT_C_32_FP (19 << 0)
-# define R500_OUT_FMT_C2_32_FP (20 << 0)
-# define R500_OUT_FMT_C4_32_FP (21 << 0)
-# define R500_C0_SEL_A (0 << 8)
-# define R500_C0_SEL_R (1 << 8)
-# define R500_C0_SEL_G (2 << 8)
-# define R500_C0_SEL_B (3 << 8)
-# define R500_C1_SEL_A (0 << 10)
-# define R500_C1_SEL_R (1 << 10)
-# define R500_C1_SEL_G (2 << 10)
-# define R500_C1_SEL_B (3 << 10)
-# define R500_C2_SEL_A (0 << 12)
-# define R500_C2_SEL_R (1 << 12)
-# define R500_C2_SEL_G (2 << 12)
-# define R500_C2_SEL_B (3 << 12)
-# define R500_C3_SEL_A (0 << 14)
-# define R500_C3_SEL_R (1 << 14)
-# define R500_C3_SEL_G (2 << 14)
-# define R500_C3_SEL_B (3 << 14)
-# define R500_OUT_SIGN(x) (x << 16)
-# define R500_ROUND_ADJ (1 << 20)
-#define R500_US_PIXSIZE 0x4604
-# define R500_PIX_SIZE(x) (x)
-#define R500_US_TEX_ADDR_0 0x9800
-# define R500_TEX_SRC_ADDR(x) (x << 0)
-# define R500_TEX_SRC_ADDR_REL (1 << 7)
-# define R500_TEX_SRC_S_SWIZ_R (0 << 8)
-# define R500_TEX_SRC_S_SWIZ_G (1 << 8)
-# define R500_TEX_SRC_S_SWIZ_B (2 << 8)
-# define R500_TEX_SRC_S_SWIZ_A (3 << 8)
-# define R500_TEX_SRC_T_SWIZ_R (0 << 10)
-# define R500_TEX_SRC_T_SWIZ_G (1 << 10)
-# define R500_TEX_SRC_T_SWIZ_B (2 << 10)
-# define R500_TEX_SRC_T_SWIZ_A (3 << 10)
-# define R500_TEX_SRC_R_SWIZ_R (0 << 12)
-# define R500_TEX_SRC_R_SWIZ_G (1 << 12)
-# define R500_TEX_SRC_R_SWIZ_B (2 << 12)
-# define R500_TEX_SRC_R_SWIZ_A (3 << 12)
-# define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
-# define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
-# define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
-# define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
-# define R500_TEX_DST_ADDR(x) (x << 16)
-# define R500_TEX_DST_ADDR_REL (1 << 23)
-# define R500_TEX_DST_R_SWIZ_R (0 << 24)
-# define R500_TEX_DST_R_SWIZ_G (1 << 24)
-# define R500_TEX_DST_R_SWIZ_B (2 << 24)
-# define R500_TEX_DST_R_SWIZ_A (3 << 24)
-# define R500_TEX_DST_G_SWIZ_R (0 << 26)
-# define R500_TEX_DST_G_SWIZ_G (1 << 26)
-# define R500_TEX_DST_G_SWIZ_B (2 << 26)
-# define R500_TEX_DST_G_SWIZ_A (3 << 26)
-# define R500_TEX_DST_B_SWIZ_R (0 << 28)
-# define R500_TEX_DST_B_SWIZ_G (1 << 28)
-# define R500_TEX_DST_B_SWIZ_B (2 << 28)
-# define R500_TEX_DST_B_SWIZ_A (3 << 28)
-# define R500_TEX_DST_A_SWIZ_R (0 << 30)
-# define R500_TEX_DST_A_SWIZ_G (1 << 30)
-# define R500_TEX_DST_A_SWIZ_B (2 << 30)
-# define R500_TEX_DST_A_SWIZ_A (3 << 30)
-#define R500_US_TEX_ADDR_DXDY_0 0xa000
-# define R500_DX_ADDR(x) (x << 0)
-# define R500_DX_ADDR_REL (1 << 7)
-# define R500_DX_S_SWIZ_R (0 << 8)
-# define R500_DX_S_SWIZ_G (1 << 8)
-# define R500_DX_S_SWIZ_B (2 << 8)
-# define R500_DX_S_SWIZ_A (3 << 8)
-# define R500_DX_T_SWIZ_R (0 << 10)
-# define R500_DX_T_SWIZ_G (1 << 10)
-# define R500_DX_T_SWIZ_B (2 << 10)
-# define R500_DX_T_SWIZ_A (3 << 10)
-# define R500_DX_R_SWIZ_R (0 << 12)
-# define R500_DX_R_SWIZ_G (1 << 12)
-# define R500_DX_R_SWIZ_B (2 << 12)
-# define R500_DX_R_SWIZ_A (3 << 12)
-# define R500_DX_Q_SWIZ_R (0 << 14)
-# define R500_DX_Q_SWIZ_G (1 << 14)
-# define R500_DX_Q_SWIZ_B (2 << 14)
-# define R500_DX_Q_SWIZ_A (3 << 14)
-# define R500_DY_ADDR(x) (x << 16)
-# define R500_DY_ADDR_REL (1 << 17)
-# define R500_DY_S_SWIZ_R (0 << 24)
-# define R500_DY_S_SWIZ_G (1 << 24)
-# define R500_DY_S_SWIZ_B (2 << 24)
-# define R500_DY_S_SWIZ_A (3 << 24)
-# define R500_DY_T_SWIZ_R (0 << 26)
-# define R500_DY_T_SWIZ_G (1 << 26)
-# define R500_DY_T_SWIZ_B (2 << 26)
-# define R500_DY_T_SWIZ_A (3 << 26)
-# define R500_DY_R_SWIZ_R (0 << 28)
-# define R500_DY_R_SWIZ_G (1 << 28)
-# define R500_DY_R_SWIZ_B (2 << 28)
-# define R500_DY_R_SWIZ_A (3 << 28)
-# define R500_DY_Q_SWIZ_R (0 << 30)
-# define R500_DY_Q_SWIZ_G (1 << 30)
-# define R500_DY_Q_SWIZ_B (2 << 30)
-# define R500_DY_Q_SWIZ_A (3 << 30)
-#define R500_US_TEX_INST_0 0x9000
-# define R500_TEX_ID(x) (x << 16)
-# define R500_TEX_INST_NOP (0 << 22)
-# define R500_TEX_INST_LD (1 << 22)
-# define R500_TEX_INST_TEXKILL (2 << 22)
-# define R500_TEX_INST_PROJ (3 << 22)
-# define R500_TEX_INST_LODBIAS (4 << 22)
-# define R500_TEX_INST_LOD (5 << 22)
-# define R500_TEX_INST_DXDY (6 << 22)
-# define R500_TEX_SEM_ACQUIRE (1 << 25)
-# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
-# define R500_TEX_UNSCALED (1 << 27)
-#define R500_US_W_FMT 0x46b4
-# define R500_W_FMT_W0 (0 << 0)
-# define R500_W_FMT_W24 (1 << 0)
-# define R500_W_FMT_W24FP (2 << 0)
-# define R500_W_SRC_US (0 << 2)
-# define R500_W_SRC_RAS (1 << 2)
-
-#define R500_GA_US_VECTOR_INDEX 0x4250
-#define R500_GA_US_VECTOR_DATA 0x4254
-
-#define R500_RS_INST_0 0x4320
-#define R500_RS_INST_TEX_ID_SHIFT 0
-#define R500_RS_INST_TEX_CN_WRITE (1 << 4)
-#define R500_RS_INST_TEX_ADDR_SHIFT 5
-#define R500_RS_INST_COL_ID_SHIFT 12
-#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
-#define R500_RS_INST_COL_CN_WRITE (1 << 16)
-#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
-#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
-#define R500_RS_INST_COL_COL_ADDR_SHIFT 18
-#define R500_RS_INST_TEX_ADJ (1 << 25)
-#define R500_RS_INST_W_CN (1 << 26)
-
-#define R500_US_FC_CTRL 0x4624
-#define R500_US_CODE_ADDR 0x4630
-#define R500_US_CODE_RANGE 0x4634
-#define R500_US_CODE_OFFSET 0x4638
-
-#define R500_RS_IP_0 0x4074
-#define R500_RS_IP_PTR_K0 62
-#define R500_RS_IP_PTR_K1 63
-#define R500_RS_IP_TEX_PTR_S_SHIFT 0
-#define R500_RS_IP_TEX_PTR_T_SHIFT 6
-#define R500_RS_IP_TEX_PTR_R_SHIFT 12
-#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
-#define R500_RS_IP_COL_PTR_SHIFT 24
-#define R500_RS_IP_COL_FMT_SHIFT 27
-#define R500_RS_IP_COL_FMT_RGBA (0<<27)
-#define R500_RS_IP_OFFSET_EN (1 << 31)
-
-
-#endif
diff --git a/src/radeon_render.c b/src/radeon_render.c
deleted file mode 100644
index a80d136..0000000
--- a/src/radeon_render.c
+++ /dev/null
@@ -1,1052 +0,0 @@
-/*
- * Copyright 2004 Eric Anholt
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- * Authors:
- * Eric Anholt <anholt at FreeBSD.org>
- * Hui Yu <hyu at ati.com>
- *
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
-#ifdef USE_XAA
-
-#include "dixstruct.h"
-
-#include "xaa.h"
-#include "xaalocal.h"
-
-#ifndef RENDER_GENERIC_HELPER
-#define RENDER_GENERIC_HELPER
-
-struct blendinfo {
- Bool dst_alpha;
- Bool src_alpha;
- CARD32 blend_cntl;
-};
-
-/* The first part of blend_cntl corresponds to Fa from the render "protocol"
- * document, and the second part to Fb.
- */
-static const struct blendinfo RadeonBlendOp[] = {
- /* Clear */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ZERO},
- /* Src */
- {0, 0, RADEON_SRC_BLEND_GL_ONE |
- RADEON_DST_BLEND_GL_ZERO},
- /* Dst */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ONE},
- /* Over */
- {0, 1, RADEON_SRC_BLEND_GL_ONE |
- RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* OverReverse */
- {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
- RADEON_DST_BLEND_GL_ONE},
- /* In */
- {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA |
- RADEON_DST_BLEND_GL_ZERO},
- /* InReverse */
- {0, 1, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_SRC_ALPHA},
- /* Out */
- {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
- RADEON_DST_BLEND_GL_ZERO},
- /* OutReverse */
- {0, 1, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* Atop */
- {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA |
- RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* AtopReverse */
- {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
- RADEON_DST_BLEND_GL_SRC_ALPHA},
- /* Xor */
- {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA |
- RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
- /* Add */
- {0, 0, RADEON_SRC_BLEND_GL_ONE |
- RADEON_DST_BLEND_GL_ONE},
- /* Saturate */
- {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
- RADEON_DST_BLEND_GL_ONE},
- {0, 0, 0},
- {0, 0, 0},
- /* DisjointClear */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ZERO},
- /* DisjointSrc */
- {0, 0, RADEON_SRC_BLEND_GL_ONE |
- RADEON_DST_BLEND_GL_ZERO},
- /* DisjointDst */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ONE},
- /* DisjointOver unsupported */
- {0, 0, 0},
- /* DisjointOverReverse */
- {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
- RADEON_DST_BLEND_GL_ONE},
- /* DisjointIn unsupported */
- {0, 0, 0},
- /* DisjointInReverse unsupported */
- {0, 0, 0},
- /* DisjointOut unsupported */
- {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
- RADEON_DST_BLEND_GL_ZERO},
- /* DisjointOutReverse unsupported */
- {0, 0, 0},
- /* DisjointAtop unsupported */
- {0, 0, 0},
- /* DisjointAtopReverse unsupported */
- {0, 0, 0},
- /* DisjointXor unsupported */
- {0, 0, 0},
- {0, 0, 0},
- {0, 0, 0},
- {0, 0, 0},
- {0, 0, 0},
- /* ConjointClear */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ZERO},
- /* ConjointSrc */
- {0, 0, RADEON_SRC_BLEND_GL_ONE |
- RADEON_DST_BLEND_GL_ZERO},
- /* ConjointDst */
- {0, 0, RADEON_SRC_BLEND_GL_ZERO |
- RADEON_DST_BLEND_GL_ONE},
-};
-#define RadeonOpMax (sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
-
-/* Note on texture formats:
- * TXFORMAT_Y8 expands to (Y,Y,Y,1). TXFORMAT_I8 expands to (I,I,I,I)
- * The RADEON and R200 TXFORMATS we use are the same on r100/r200.
- */
-
-static CARD32 RADEONTextureFormats[] = {
- PICT_a8r8g8b8,
- PICT_a8,
- PICT_x8r8g8b8,
- PICT_r5g6b5,
- PICT_a1r5g5b5,
- PICT_x1r5g5b5,
- 0
-};
-
-static CARD32 RADEONDstFormats[] = {
- PICT_a8r8g8b8,
- PICT_x8r8g8b8,
- PICT_r5g6b5,
- PICT_a1r5g5b5,
- PICT_x1r5g5b5,
- 0
-};
-
-static CARD32
-RadeonGetTextureFormat(CARD32 format)
-{
- switch (format) {
- case PICT_a8r8g8b8:
- return RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
- case PICT_a8:
- return RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
- case PICT_x8r8g8b8:
- return RADEON_TXFORMAT_ARGB8888;
- case PICT_r5g6b5:
- return RADEON_TXFORMAT_RGB565;
- case PICT_a1r5g5b5:
- return RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP;
- case PICT_x1r5g5b5:
- return RADEON_TXFORMAT_ARGB1555;
- default:
- return 0;
- }
-}
-
-static CARD32
-RadeonGetColorFormat(CARD32 format)
-{
- switch (format) {
- case PICT_a8r8g8b8:
- case PICT_x8r8g8b8:
- return RADEON_COLOR_FORMAT_ARGB8888;
- case PICT_r5g6b5:
- return RADEON_COLOR_FORMAT_RGB565;
- case PICT_a1r5g5b5:
- case PICT_x1r5g5b5:
- return RADEON_COLOR_FORMAT_ARGB1555;
- default:
- return 0;
- }
-}
-
-/* Returns a RADEON_RB3D_BLENDCNTL value, or 0 if the operation is not
- * supported
- */
-static CARD32
-RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat)
-{
- CARD32 blend_cntl;
-
- if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
- return 0;
-
- blend_cntl = RadeonBlendOp[op].blend_cntl;
-
- if (RadeonBlendOp[op].dst_alpha && !PICT_FORMAT_A(dstFormat)) {
- CARD32 srcblend = blend_cntl & RADEON_SRC_BLEND_MASK;
-
- /* If there's no destination alpha channel, we need to wire the blending
- * to treat the alpha channel as always 1.
- */
- if (srcblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA ||
- srcblend == RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE)
- blend_cntl = (blend_cntl & ~RADEON_SRC_BLEND_MASK) |
- RADEON_SRC_BLEND_GL_ZERO;
- else if (srcblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
- blend_cntl = (blend_cntl & ~RADEON_SRC_BLEND_MASK) |
- RADEON_SRC_BLEND_GL_ONE;
- }
-
- return blend_cntl;
-}
-
-static __inline__ CARD32 F_TO_DW(float val)
-{
- union {
- float f;
- CARD32 l;
- } tmp;
- tmp.f = val;
- return tmp.l;
-}
-
-/* Compute log base 2 of val. */
-static __inline__ int
-ATILog2(int val)
-{
- int bits;
-
- for (bits = 0; val != 0; val >>= 1, ++bits)
- ;
- return bits - 1;
-}
-
-static void
-RemoveLinear (FBLinearPtr linear)
-{
- RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr);
-
- info->RenderTex = NULL;
-}
-
-static void
-RenderCallback (ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if ((currentTime.milliseconds > info->RenderTimeout) && info->RenderTex) {
- xf86FreeOffscreenLinear(info->RenderTex);
- info->RenderTex = NULL;
- }
-
- if (!info->RenderTex)
- info->RenderCallback = NULL;
-}
-
-static Bool
-AllocateLinear (
- ScrnInfoPtr pScrn,
- int sizeNeeded
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int cpp = info->CurrentLayout.bitsPerPixel / 8;
-
- info->RenderTimeout = currentTime.milliseconds + 30000;
- info->RenderCallback = RenderCallback;
-
- /* XAA allocates in units of pixels at the screen bpp, so adjust size
- * appropriately.
- */
- sizeNeeded = (sizeNeeded + cpp - 1) / cpp;
-
- if (info->RenderTex) {
- if (info->RenderTex->size >= sizeNeeded)
- return TRUE;
- else {
- if (xf86ResizeOffscreenLinear(info->RenderTex, sizeNeeded))
- return TRUE;
-
- xf86FreeOffscreenLinear(info->RenderTex);
- info->RenderTex = NULL;
- }
- }
-
- info->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32,
- NULL, RemoveLinear, info);
-
- return (info->RenderTex != NULL);
-}
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 swapper = info->ModeReg->surface_cntl;
-
- swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP |
- RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP);
-
- /* Set up byte swapping for the framebuffer aperture as needed */
- switch (tex_bytepp) {
- case 1:
- break;
- case 2:
- swapper |= RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP;
- break;
- case 4:
- swapper |= RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: Don't know what to do for "
- "tex_bytepp == %d!\n", __func__, tex_bytepp);
- return FALSE;
- }
- OUTREG(RADEON_SURFACE_CNTL, swapper);
- return TRUE;
-}
-
-static void RADEONRestoreByteswap(RADEONInfoPtr info)
-{
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-}
-#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */
-
-#endif /* RENDER_GENERIC_HELPER */
-
-#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
-#error Cannot define both MMIO and CP acceleration!
-#endif
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#ifdef ACCEL_MMIO
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
-#else
-#ifdef ACCEL_CP
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-#else
-#error No accel type defined!
-#endif
-#endif
-
-static Bool FUNC_NAME(R100SetupTexture)(
- ScrnInfoPtr pScrn,
- CARD32 format,
- CARD8 *src,
- int src_pitch,
- unsigned int width,
- unsigned int height,
- int flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD8 *dst;
- CARD32 tex_size = 0, txformat;
- int dst_pitch, offset, size, tex_bytepp;
-#ifdef ACCEL_CP
- CARD32 buf_pitch, dst_pitch_off;
- int x, y;
- unsigned int hpass;
- CARD8 *tmp_dst;
-#endif
- ACCEL_PREAMBLE();
-
- if ((width > 2047) || (height > 2047))
- return FALSE;
-
- txformat = RadeonGetTextureFormat(format);
- tex_bytepp = PICT_FORMAT_BPP(format) >> 3;
-
- dst_pitch = (width * tex_bytepp + 63) & ~63;
- size = dst_pitch * height;
-
- if ((flags & XAA_RENDER_REPEAT) && (height != 1) &&
- (((width * tex_bytepp + 31) & ~31) != dst_pitch))
- return FALSE;
-
-#ifndef ACCEL_CP
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- if (!RADEONSetupRenderByteswap(pScrn, tex_bytepp)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: RADEONSetupRenderByteswap() "
- "failed!\n", __func__);
- return FALSE;
- }
-#endif
-
-#endif
-
- if (!AllocateLinear(pScrn, size))
- return FALSE;
-
- if (flags & XAA_RENDER_REPEAT) {
- txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT;
- txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT;
- } else {
- tex_size = (height << 16) | width;
- txformat |= RADEON_TXFORMAT_NON_POWER2;
- }
-
- offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
- dst = (CARD8*)(info->FB + offset);
-
- /* Upload texture to card. */
-
-#ifdef ACCEL_CP
-
- RADEONHostDataParams( pScrn, dst, dst_pitch, tex_bytepp, &dst_pitch_off, &x, &y );
-
- while ( height )
- {
- tmp_dst = RADEONHostDataBlit( pScrn, tex_bytepp, width,
- dst_pitch_off, &buf_pitch,
- x, &y, &height, &hpass );
- RADEONHostDataBlitCopyPass( pScrn, tex_bytepp, tmp_dst, src,
- hpass, buf_pitch, src_pitch );
- src += hpass * src_pitch;
- }
-
- RADEON_PURGE_CACHE();
- RADEON_WAIT_UNTIL_IDLE();
-
-#else
-
- if (info->accel->NeedToSync)
- info->accel->Sync(pScrn);
-
- while (height--) {
- memcpy(dst, src, width * tex_bytepp);
- src += src_pitch;
- dst += dst_pitch;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- RADEONRestoreByteswap(info);
-#endif
-
-#endif /* ACCEL_CP */
-
- BEGIN_ACCEL(5);
- OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size);
- OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, dst_pitch - 32);
- OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation +
- pScrn->fbOffset);
- OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR |
- RADEON_MIN_FILTER_LINEAR |
- RADEON_CLAMP_S_WRAP |
- RADEON_CLAMP_T_WRAP);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-static Bool
-FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
- ScrnInfoPtr pScrn,
- int op,
- CARD16 red,
- CARD16 green,
- CARD16 blue,
- CARD16 alpha,
- CARD32 maskFormat,
- CARD32 dstFormat,
- CARD8 *alphaPtr,
- int alphaPitch,
- int width,
- int height,
- int flags
-)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 colorformat, srccolor, blend_cntl;
- ACCEL_PREAMBLE();
-
- blend_cntl = RadeonGetBlendCntl(op, dstFormat);
- if (blend_cntl == 0)
- return FALSE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- if (!FUNC_NAME(R100SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
- width, height, flags))
- return FALSE;
-
- colorformat = RadeonGetColorFormat(dstFormat);
-
- srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) |
- (green & 0xff00);
-
- BEGIN_ACCEL(7);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
- OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
- RADEON_TEX_BLEND_0_ENABLE);
- OUT_ACCEL_REG(RADEON_PP_TFACTOR_0, srccolor);
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_TFACTOR_COLOR |
- RADEON_COLOR_ARG_B_T0_ALPHA);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_TFACTOR_ALPHA |
- RADEON_ALPHA_ARG_B_T0_ALPHA);
- OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
- RADEON_SE_VTX_FMT_ST0);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-
-static Bool
-FUNC_NAME(R100SetupForCPUToScreenTexture) (
- ScrnInfoPtr pScrn,
- int op,
- CARD32 srcFormat,
- CARD32 dstFormat,
- CARD8 *texPtr,
- int texPitch,
- int width,
- int height,
- int flags
-)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 colorformat, blend_cntl;
- ACCEL_PREAMBLE();
-
- blend_cntl = RadeonGetBlendCntl(op, dstFormat);
- if (blend_cntl == 0)
- return FALSE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- if (!FUNC_NAME(R100SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width,
- height, flags))
- return FALSE;
-
- colorformat = RadeonGetColorFormat(dstFormat);
-
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
- OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
- RADEON_TEX_BLEND_0_ENABLE);
- if (srcFormat != PICT_a8)
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR);
- else
- OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_ZERO);
- OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA);
- OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
- RADEON_SE_VTX_FMT_ST0);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-
-static void
-FUNC_NAME(R100SubsequentCPUToScreenTexture) (
- ScrnInfoPtr pScrn,
- int dstx,
- int dsty,
- int srcx,
- int srcy,
- int width,
- int height
-)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int byteshift;
- CARD32 fboffset;
- float l, t, r, b, fl, fr, ft, fb;
-
- ACCEL_PREAMBLE();
-
- /* Note: we can't simply set up the 3D surface at the same location as the
- * front buffer, because the 2048x2048 limit on coordinates may be smaller
- * than the (MergedFB) screen.
- * Can't use arbitrary offsets for color tiling
- */
- if (info->tilingEnabled) {
- /* can't play tricks with x coordinate, or could we - tiling is disabled anyway in that case */
- fboffset = info->fbLocation + pScrn->fbOffset +
- (pScrn->displayWidth * (dsty & ~15) * (pScrn->bitsPerPixel >> 3));
- l = dstx;
- t = (dsty % 16);
- }
- else {
- byteshift = (pScrn->bitsPerPixel >> 4);
- fboffset = (info->fbLocation + pScrn->fbOffset +
- ((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15;
- l = ((dstx << byteshift) % 16) >> byteshift;
- t = 0.0;
- }
-
- r = width + l;
- b = height + t;
- fl = srcx;
- fr = srcx + width;
- ft = srcy;
- fb = srcy + height;
-
-#ifdef ACCEL_CP
- BEGIN_RING(25);
-
- OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
- ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
- OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
- OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 17));
- /* RADEON_SE_VTX_FMT */
- OUT_RING(RADEON_CP_VC_FRMT_XY |
- RADEON_CP_VC_FRMT_ST0);
- /* SE_VF_CNTL */
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
- RADEON_CP_VC_CNTL_PRIM_WALK_RING |
- RADEON_CP_VC_CNTL_MAOS_ENABLE |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
-
- OUT_RING(F_TO_DW(l));
- OUT_RING(F_TO_DW(t));
- OUT_RING(F_TO_DW(fl));
- OUT_RING(F_TO_DW(ft));
-
- OUT_RING(F_TO_DW(r));
- OUT_RING(F_TO_DW(t));
- OUT_RING(F_TO_DW(fr));
- OUT_RING(F_TO_DW(ft));
-
- OUT_RING(F_TO_DW(r));
- OUT_RING(F_TO_DW(b));
- OUT_RING(F_TO_DW(fr));
- OUT_RING(F_TO_DW(fb));
-
- OUT_RING(F_TO_DW(l));
- OUT_RING(F_TO_DW(b));
- OUT_RING(F_TO_DW(fl));
- OUT_RING(F_TO_DW(fb));
-
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
-
- ADVANCE_RING();
-#else
- BEGIN_ACCEL(20);
-
- OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
- ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
- OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
-
- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
- RADEON_VF_PRIM_WALK_DATA |
- RADEON_VF_RADEON_MODE |
- (4 << RADEON_VF_NUM_VERTICES_SHIFT));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
-
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- FINISH_ACCEL();
-#endif
-
-}
-
-static Bool FUNC_NAME(R200SetupTexture)(
- ScrnInfoPtr pScrn,
- CARD32 format,
- CARD8 *src,
- int src_pitch,
- unsigned int width,
- unsigned int height,
- int flags)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD8 *dst;
- CARD32 tex_size = 0, txformat;
- int dst_pitch, offset, size, tex_bytepp;
-#ifdef ACCEL_CP
- CARD32 buf_pitch, dst_pitch_off;
- int x, y;
- unsigned int hpass;
- CARD8 *tmp_dst;
-#endif
- ACCEL_PREAMBLE();
-
- if ((width > 2048) || (height > 2048))
- return FALSE;
-
- txformat = RadeonGetTextureFormat(format);
- tex_bytepp = PICT_FORMAT_BPP(format) >> 3;
-
- dst_pitch = (width * tex_bytepp + 63) & ~63;
- size = dst_pitch * height;
-
- if ((flags & XAA_RENDER_REPEAT) && (height != 1) &&
- (((width * tex_bytepp + 31) & ~31) != dst_pitch))
- return FALSE;
-
-#ifndef ACCEL_CP
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- if (!RADEONSetupRenderByteswap(pScrn, tex_bytepp)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: RADEONSetupRenderByteswap() "
- "failed!\n", __func__);
- return FALSE;
- }
-#endif
-
-#endif
-
- if (!AllocateLinear(pScrn, size))
- return FALSE;
-
- if (flags & XAA_RENDER_REPEAT) {
- txformat |= ATILog2(width) << R200_TXFORMAT_WIDTH_SHIFT;
- txformat |= ATILog2(height) << R200_TXFORMAT_HEIGHT_SHIFT;
- } else {
- tex_size = ((height - 1) << 16) | (width - 1);
- txformat |= RADEON_TXFORMAT_NON_POWER2;
- }
-
- info->texW[0] = width;
- info->texH[0] = height;
-
- offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
- dst = (CARD8*)(info->FB + offset);
-
- /* Upload texture to card. */
-
-#ifdef ACCEL_CP
-
- RADEONHostDataParams( pScrn, dst, dst_pitch, tex_bytepp, &dst_pitch_off, &x, &y );
-
- while ( height )
- {
- tmp_dst = RADEONHostDataBlit( pScrn, tex_bytepp, width,
- dst_pitch_off, &buf_pitch,
- x, &y, &height, &hpass );
- RADEONHostDataBlitCopyPass( pScrn, tex_bytepp, tmp_dst, src,
- hpass, buf_pitch, src_pitch );
- src += hpass * src_pitch;
- }
-
- RADEON_PURGE_CACHE();
- RADEON_WAIT_UNTIL_IDLE();
-
-#else
-
- if (info->accel->NeedToSync)
- info->accel->Sync(pScrn);
-
- while (height--) {
- memcpy(dst, src, width * tex_bytepp);
- src += src_pitch;
- dst += dst_pitch;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- RADEONRestoreByteswap(info);
-#endif
-
-#endif /* ACCEL_CP */
-
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
- OUT_ACCEL_REG(R200_PP_TXSIZE_0, tex_size);
- OUT_ACCEL_REG(R200_PP_TXPITCH_0, dst_pitch - 32);
- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation +
- pScrn->fbOffset);
- OUT_ACCEL_REG(R200_PP_TXFILTER_0, R200_MAG_FILTER_NEAREST |
- R200_MIN_FILTER_NEAREST |
- R200_CLAMP_S_WRAP |
- R200_CLAMP_T_WRAP);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-static Bool
-FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) (
- ScrnInfoPtr pScrn,
- int op,
- CARD16 red,
- CARD16 green,
- CARD16 blue,
- CARD16 alpha,
- CARD32 maskFormat,
- CARD32 dstFormat,
- CARD8 *alphaPtr,
- int alphaPitch,
- int width,
- int height,
- int flags
-)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 colorformat, srccolor, blend_cntl;
- ACCEL_PREAMBLE();
-
- blend_cntl = RadeonGetBlendCntl(op, dstFormat);
- if (blend_cntl == 0)
- return FALSE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- if (!FUNC_NAME(R200SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
- width, height, flags))
- return FALSE;
-
- colorformat = RadeonGetColorFormat(dstFormat);
-
- srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) |
- (green & 0xff00);
-
- BEGIN_ACCEL(10);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
- OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
- RADEON_TEX_BLEND_0_ENABLE);
- OUT_ACCEL_REG(R200_PP_TFACTOR_0, srccolor);
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR |
- R200_TXC_ARG_B_R0_ALPHA);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_TFACTOR_ALPHA |
- R200_TXA_ARG_B_R0_ALPHA);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-static Bool
-FUNC_NAME(R200SetupForCPUToScreenTexture) (
- ScrnInfoPtr pScrn,
- int op,
- CARD32 srcFormat,
- CARD32 dstFormat,
- CARD8 *texPtr,
- int texPitch,
- int width,
- int height,
- int flags
-)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 colorformat, blend_cntl;
- ACCEL_PREAMBLE();
-
- blend_cntl = RadeonGetBlendCntl(op, dstFormat);
- if (blend_cntl == 0)
- return FALSE;
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- if (!FUNC_NAME(R200SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width,
- height, flags))
- return FALSE;
-
- colorformat = RadeonGetColorFormat(dstFormat);
-
- BEGIN_ACCEL(9);
- OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
- OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
- RADEON_TEX_BLEND_0_ENABLE);
- if (srcFormat != PICT_a8)
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_R0_COLOR);
- else
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_ZERO);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_C_R0_ALPHA);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
- OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
- FINISH_ACCEL();
-
- return TRUE;
-}
-
-static void
-FUNC_NAME(R200SubsequentCPUToScreenTexture) (
- ScrnInfoPtr pScrn,
- int dstx,
- int dsty,
- int srcx,
- int srcy,
- int width,
- int height
-)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int byteshift;
- CARD32 fboffset;
- float l, t, r, b, fl, fr, ft, fb;
- ACCEL_PREAMBLE();
-
- /* Note: we can't simply set up the 3D surface at the same location as the
- * front buffer, because the 2048x2048 limit on coordinates may be smaller
- * than the (MergedFB) screen.
- * Can't use arbitrary offsets for color tiling
- */
- if (info->tilingEnabled) {
- /* can't play tricks with x coordinate, or could we - tiling is disabled anyway in that case */
- fboffset = info->fbLocation + pScrn->fbOffset +
- (pScrn->displayWidth * (dsty & ~15) * (pScrn->bitsPerPixel >> 3));
- l = dstx;
- t = (dsty % 16);
- }
- else {
- byteshift = (pScrn->bitsPerPixel >> 4);
- fboffset = (info->fbLocation + pScrn->fbOffset +
- ((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15;
- l = ((dstx << byteshift) % 16) >> byteshift;
- t = 0.0;
- }
-
- r = width + l;
- b = height + t;
- fl = (float)srcx / info->texW[0];
- fr = (float)(srcx + width) / info->texW[0];
- ft = (float)srcy / info->texH[0];
- fb = (float)(srcy + height) / info->texH[0];
-
-#ifdef ACCEL_CP
- BEGIN_RING(24);
-
- OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
- ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
- OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
-
- OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 16));
- /* RADEON_SE_VF_CNTL */
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
- RADEON_CP_VC_CNTL_PRIM_WALK_RING |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
-
- OUT_RING(F_TO_DW(l));
- OUT_RING(F_TO_DW(t));
- OUT_RING(F_TO_DW(fl));
- OUT_RING(F_TO_DW(ft));
-
- OUT_RING(F_TO_DW(r));
- OUT_RING(F_TO_DW(t));
- OUT_RING(F_TO_DW(fr));
- OUT_RING(F_TO_DW(ft));
-
- OUT_RING(F_TO_DW(r));
- OUT_RING(F_TO_DW(b));
- OUT_RING(F_TO_DW(fr));
- OUT_RING(F_TO_DW(fb));
-
- OUT_RING(F_TO_DW(l));
- OUT_RING(F_TO_DW(b));
- OUT_RING(F_TO_DW(fl));
- OUT_RING(F_TO_DW(fb));
-
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
-
- ADVANCE_RING();
-#else
- BEGIN_ACCEL(20);
-
- /* Note: we can't simply setup 3D surface at the same location as the front buffer,
- some apps may draw offscreen pictures out of the limitation of radeon 3D surface.
- */
- OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
- ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
- OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
-
- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
- RADEON_VF_PRIM_WALK_DATA |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
-
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl));
- OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb));
-
- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
-
- FINISH_ACCEL();
-#endif
-}
-
-#undef FUNC_NAME
-#endif /* USE_XAA */
diff --git a/src/radeon_sarea.h b/src/radeon_sarea.h
deleted file mode 100644
index 80333a4..0000000
--- a/src/radeon_sarea.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin at xfree86.org>
- * Gareth Hughes <gareth at valinux.com>
- *
- */
-
-#ifndef _RADEON_SAREA_H_
-#define _RADEON_SAREA_H_
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the kernel file (radeon_drm.h)
- */
-#ifndef __RADEON_SAREA_DEFINES__
-#define __RADEON_SAREA_DEFINES__
-
-/* What needs to be changed for the current vertex buffer? */
-#define RADEON_UPLOAD_CONTEXT 0x00000001
-#define RADEON_UPLOAD_VERTFMT 0x00000002
-#define RADEON_UPLOAD_LINE 0x00000004
-#define RADEON_UPLOAD_BUMPMAP 0x00000008
-#define RADEON_UPLOAD_MASKS 0x00000010
-#define RADEON_UPLOAD_VIEWPORT 0x00000020
-#define RADEON_UPLOAD_SETUP 0x00000040
-#define RADEON_UPLOAD_TCL 0x00000080
-#define RADEON_UPLOAD_MISC 0x00000100
-#define RADEON_UPLOAD_TEX0 0x00000200
-#define RADEON_UPLOAD_TEX1 0x00000400
-#define RADEON_UPLOAD_TEX2 0x00000800
-#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
-#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
-#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
-#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
-#define RADEON_REQUIRE_QUIESCENCE 0x00010000
-#define RADEON_UPLOAD_ZBIAS 0x00020000
-#define RADEON_UPLOAD_ALL 0x0002ffff
-#define RADEON_UPLOAD_CONTEXT_ALL 0x000201ff
-
-#define RADEON_FRONT 0x1
-#define RADEON_BACK 0x2
-#define RADEON_DEPTH 0x4
-#define RADEON_STENCIL 0x8
-
-/* Primitive types */
-#define RADEON_POINTS 0x1
-#define RADEON_LINES 0x2
-#define RADEON_LINE_STRIP 0x3
-#define RADEON_TRIANGLES 0x4
-#define RADEON_TRIANGLE_FAN 0x5
-#define RADEON_TRIANGLE_STRIP 0x6
-#define RADEON_3VTX_POINTS 0x9
-#define RADEON_3VTX_LINES 0xa
-
-/* Vertex/indirect buffer size */
-#define RADEON_BUFFER_SIZE 65536
-
-/* Byte offsets for indirect buffer data */
-#define RADEON_INDEX_PRIM_OFFSET 20
-#define RADEON_HOSTDATA_BLIT_OFFSET 32
-
-#define RADEON_SCRATCH_REG_OFFSET 32
-
-/* Keep these small for testing */
-#define RADEON_NR_SAREA_CLIPRECTS 12
-
-/* There are 2 heaps (local/GART). Each region within a heap is a
- * minimum of 64k, and there are at most 64 of them per heap.
- */
-#define RADEON_CARD_HEAP 0
-#define RADEON_GART_HEAP 1
-#define RADEON_NR_TEX_HEAPS 2
-#define RADEON_NR_TEX_REGIONS 64
-#define RADEON_LOG_TEX_GRANULARITY 16
-
-#define RADEON_MAX_TEXTURE_LEVELS 12
-#define RADEON_MAX_TEXTURE_UNITS 3
-
-/* Blits have strict offset rules. All blit offset must be aligned on
- * a 1K-byte boundary.
- */
-#define RADEON_OFFSET_SHIFT 10
-#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
-#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
-
-#endif /* __RADEON_SAREA_DEFINES__ */
-
-typedef struct {
- unsigned int red;
- unsigned int green;
- unsigned int blue;
- unsigned int alpha;
-} radeon_color_regs_t;
-
-typedef struct {
- /* Context state */
- unsigned int pp_misc;
- unsigned int pp_fog_color;
- unsigned int re_solid_color;
- unsigned int rb3d_blendcntl;
- unsigned int rb3d_depthoffset;
- unsigned int rb3d_depthpitch;
- unsigned int rb3d_zstencilcntl;
-
- unsigned int pp_cntl;
- unsigned int rb3d_cntl;
- unsigned int rb3d_coloroffset;
- unsigned int re_width_height;
- unsigned int rb3d_colorpitch;
- unsigned int se_cntl;
-
- /* Vertex format state */
- unsigned int se_coord_fmt;
-
- /* Line state */
- unsigned int re_line_pattern;
- unsigned int re_line_state;
-
- unsigned int se_line_width;
-
- /* Bumpmap state */
- unsigned int pp_lum_matrix;
-
- unsigned int pp_rot_matrix_0;
- unsigned int pp_rot_matrix_1;
-
- /* Mask state */
- unsigned int rb3d_stencilrefmask;
- unsigned int rb3d_ropcntl;
- unsigned int rb3d_planemask;
-
- /* Viewport state */
- unsigned int se_vport_xscale;
- unsigned int se_vport_xoffset;
- unsigned int se_vport_yscale;
- unsigned int se_vport_yoffset;
- unsigned int se_vport_zscale;
- unsigned int se_vport_zoffset;
-
- /* Setup state */
- unsigned int se_cntl_status;
-
- /* Misc state */
- unsigned int re_top_left;
- unsigned int re_misc;
-} radeon_context_regs_t;
-
-/* Setup registers for each texture unit */
-typedef struct {
- unsigned int pp_txfilter;
- unsigned int pp_txformat;
- unsigned int pp_txoffset;
- unsigned int pp_txcblend;
- unsigned int pp_txablend;
- unsigned int pp_tfactor;
- unsigned int pp_border_color;
-} radeon_texture_regs_t;
-
-typedef struct {
- /* The channel for communication of state information to the kernel
- * on firing a vertex buffer.
- */
- radeon_context_regs_t ContextState;
- radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
- unsigned int dirty;
- unsigned int vertsize;
- unsigned int vc_format;
-
- /* The current cliprects, or a subset thereof */
- drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
- unsigned int nbox;
-
- /* Counters for throttling of rendering clients */
- unsigned int last_frame;
- unsigned int last_dispatch;
- unsigned int last_clear;
-
- /* Maintain an LRU of contiguous regions of texture space. If you
- * think you own a region of texture memory, and it has an age
- * different to the one you set, then you are mistaken and it has
- * been stolen by another client. If global texAge hasn't changed,
- * there is no need to walk the list.
- *
- * These regions can be used as a proxy for the fine-grained texture
- * information of other clients - by maintaining them in the same
- * lru which is used to age their own textures, clients have an
- * approximate lru for the whole of global texture space, and can
- * make informed decisions as to which areas to kick out. There is
- * no need to choose whether to kick out your own texture or someone
- * else's - simply eject them all in LRU order.
- */
- /* Last elt is sentinal */
- drmTextureRegion texList[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
- /* last time texture was uploaded */
- unsigned int texAge[RADEON_NR_TEX_HEAPS];
-
- int ctxOwner; /* last context to upload state */
- int pfAllowPageFlip; /* set by the 2d driver, read by the client */
- int pfCurrentPage; /* set by kernel, read by others */
- int crtc2_base; /* for pageflipping with CloneMode */
- int tiling_enabled; /* set by drm, read by 2d + 3d clients */
- } RADEONSAREAPriv, *RADEONSAREAPrivPtr;
-
-#endif
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
deleted file mode 100644
index 329a834..0000000
--- a/src/radeon_textured_video.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * Copyright 2008 Alex Deucher
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- *
- * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al.
- *
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-#include <math.h>
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_video.h"
-
-#include <X11/extensions/Xv.h>
-#include "fourcc.h"
-
-#define IMAGE_MAX_WIDTH 2048
-#define IMAGE_MAX_HEIGHT 2048
-
-static Bool
-RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef USE_EXA
- if (info->useEXA) {
- if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0)
- return TRUE;
- else
- return FALSE;
- } else
-#endif
- {
- if (info->tilingEnabled)
- return TRUE;
- else
- return FALSE;
- }
-}
-
-static __inline__ CARD32 F_TO_DW(float val)
-{
- union {
- float f;
- CARD32 l;
- } tmp;
- tmp.f = val;
- return tmp.l;
-}
-
-#define ACCEL_MMIO
-#define VIDEO_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO
-#define BEGIN_VIDEO(n) RADEONWaitForFifo(pScrn, (n))
-#define OUT_VIDEO_REG(reg, val) OUTREG(reg, val)
-#define OUT_VIDEO_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
-#define FINISH_VIDEO()
-
-#include "radeon_textured_videofuncs.c"
-
-#undef ACCEL_MMIO
-#undef VIDEO_PREAMBLE
-#undef BEGIN_VIDEO
-#undef OUT_VIDEO_REG
-#undef FINISH_VIDEO
-
-#ifdef XF86DRI
-
-#define ACCEL_CP
-#define VIDEO_PREAMBLE() \
- RING_LOCALS; \
- RADEONCP_REFRESH(pScrn, info)
-#define BEGIN_VIDEO(n) BEGIN_RING(2*(n))
-#define OUT_VIDEO_REG(reg, val) OUT_RING_REG(reg, val)
-#define FINISH_VIDEO() ADVANCE_RING()
-#define OUT_VIDEO_RING_F(x) OUT_RING(F_TO_DW(x))
-
-#include "radeon_textured_videofuncs.c"
-
-#endif /* XF86DRI */
-
-static int
-RADEONPutImageTextured(ScrnInfoPtr pScrn,
- short src_x, short src_y,
- short drw_x, short drw_y,
- short src_w, short src_h,
- short drw_w, short drw_h,
- int id,
- unsigned char *buf,
- short width,
- short height,
- Bool sync,
- RegionPtr clipBoxes,
- pointer data,
- DrawablePtr pDraw)
-{
- ScreenPtr pScreen = pScrn->pScreen;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- INT32 x1, x2, y1, y2;
- int srcPitch, srcPitch2, dstPitch;
- int s2offset, s3offset, tmp;
- int top, left, npixels, nlines, size;
- BoxRec dstBox;
- int dst_width = width, dst_height = height;
-
- /* make the compiler happy */
- s2offset = s3offset = srcPitch2 = 0;
-
- /* Clip */
- x1 = src_x;
- x2 = src_x + src_w;
- y1 = src_y;
- y2 = src_y + src_h;
-
- dstBox.x1 = drw_x;
- dstBox.x2 = drw_x + drw_w;
- dstBox.y1 = drw_y;
- dstBox.y2 = drw_y + drw_h;
-
- if (!xf86XVClipVideoHelper(&dstBox, &x1, &x2, &y1, &y2, clipBoxes, width, height))
- return Success;
-
- src_w = (x2 - x1) >> 16;
- src_h = (y2 - y1) >> 16;
- drw_w = dstBox.x2 - dstBox.x1;
- drw_h = dstBox.y2 - dstBox.y1;
-
- if ((x1 >= x2) || (y1 >= y2))
- return Success;
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- dstPitch = ((dst_width << 1) + 15) & ~15;
- srcPitch = (width + 3) & ~3;
- srcPitch2 = ((width >> 1) + 3) & ~3;
- size = dstPitch * dst_height;
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- dstPitch = ((dst_width << 1) + 15) & ~15;
- srcPitch = (width << 1);
- srcPitch2 = 0;
- size = dstPitch * dst_height;
- break;
- }
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled && info->DMAForXv)
- /* The upload blit only supports multiples of 64 bytes */
- dstPitch = (dstPitch + 63) & ~63;
- else
-#endif
- dstPitch = (dstPitch + 15) & ~15;
-
- if (pPriv->video_memory != NULL && size != pPriv->size) {
- RADEONFreeMemory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
- }
-
- if (pPriv->video_memory == NULL) {
- pPriv->video_offset = RADEONAllocateMemory(pScrn,
- &pPriv->video_memory,
- size * 2);
- if (pPriv->video_offset == 0)
- return BadAlloc;
- }
-
- if (pDraw->type == DRAWABLE_WINDOW)
- pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw);
- else
- pPriv->pPixmap = (PixmapPtr)pDraw;
-
-#ifdef USE_EXA
- if (info->useEXA) {
- /* Force the pixmap into framebuffer so we can draw to it. */
- exaMoveInPixmap(pPriv->pPixmap);
- }
-#endif
-
- if (!info->useEXA &&
- (((char *)pPriv->pPixmap->devPrivate.ptr < (char *)info->FB) ||
- ((char *)pPriv->pPixmap->devPrivate.ptr >= (char *)info->FB +
- info->FbMapSize))) {
- /* If the pixmap wasn't in framebuffer, then we have no way in XAA to
- * force it there. So, we simply refuse to draw and fail.
- */
- return BadAlloc;
- }
-
- /* copy data */
- top = y1 >> 16;
- left = (x1 >> 16) & ~1;
- npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left;
-
- pPriv->src_offset = pPriv->video_offset + info->fbLocation;
- pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch));
- pPriv->src_pitch = dstPitch;
- pPriv->size = size;
- pPriv->pDraw = pDraw;
-
-#if 0
- ErrorF("src_offset: 0x%x\n", pPriv->src_offset);
- ErrorF("src_addr: 0x%x\n", pPriv->src_addr);
- ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch);
-#endif
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- top &= ~1;
- nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top;
- s2offset = srcPitch * height;
- s3offset = (srcPitch2 * (height >> 1)) + s2offset;
- top &= ~1;
- pPriv->src_addr += left << 1;
- tmp = ((top >> 1) * srcPitch2) + (left >> 1);
- s2offset += tmp;
- s3offset += tmp;
- if (id == FOURCC_I420) {
- tmp = s2offset;
- s2offset = s3offset;
- s3offset = tmp;
- }
- RADEONCopyMungedData(pScrn, buf + (top * srcPitch) + left,
- buf + s2offset, buf + s3offset, pPriv->src_addr,
- srcPitch, srcPitch2, dstPitch, nlines, npixels);
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- nlines = ((y2 + 0xffff) >> 16) - top;
- RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2);
- break;
- }
-
- /* update cliplist */
- if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
- REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes);
- }
-
- pPriv->id = id;
- pPriv->src_w = src_w;
- pPriv->src_h = src_h;
- pPriv->drw_x = drw_x;
- pPriv->drw_y = drw_y;
- pPriv->dst_w = drw_w;
- pPriv->dst_h = drw_h;
- pPriv->w = width;
- pPriv->h = height;
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled)
- RADEONDisplayTexturedVideoCP(pScrn, pPriv);
- else
-#endif
- RADEONDisplayTexturedVideoMMIO(pScrn, pPriv);
-
- return Success;
-}
-
-/* client libraries expect an encoding */
-static XF86VideoEncodingRec DummyEncoding[1] =
-{
- {
- 0,
- "XV_IMAGE",
- IMAGE_MAX_WIDTH, IMAGE_MAX_HEIGHT,
- {1, 1}
- }
-};
-
-#define NUM_FORMATS 3
-
-static XF86VideoFormatRec Formats[NUM_FORMATS] =
-{
- {15, TrueColor}, {16, TrueColor}, {24, TrueColor}
-};
-
-#define NUM_ATTRIBUTES 0
-
-static XF86AttributeRec Attributes[NUM_ATTRIBUTES] =
-{
-};
-
-#define NUM_IMAGES 4
-
-static XF86ImageRec Images[NUM_IMAGES] =
-{
- XVIMAGE_YUY2,
- XVIMAGE_YV12,
- XVIMAGE_I420,
- XVIMAGE_UYVY
-};
-
-XF86VideoAdaptorPtr
-RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
-{
- RADEONPortPrivPtr pPortPriv;
- XF86VideoAdaptorPtr adapt;
- int i;
- int num_texture_ports = 16;
-
- adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports *
- (sizeof(RADEONPortPrivRec) + sizeof(DevUnion)));
- if (adapt == NULL)
- return NULL;
-
- adapt->type = XvWindowMask | XvInputMask | XvImageMask;
- adapt->flags = 0;
- adapt->name = "Radeon Textured Video";
- adapt->nEncodings = 1;
- adapt->pEncodings = DummyEncoding;
- adapt->nFormats = NUM_FORMATS;
- adapt->pFormats = Formats;
- adapt->nPorts = num_texture_ports;
- adapt->pPortPrivates = (DevUnion*)(&adapt[1]);
-
- pPortPriv =
- (RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]);
-
- adapt->nAttributes = NUM_ATTRIBUTES;
- adapt->pAttributes = Attributes;
- adapt->pImages = Images;
- adapt->nImages = NUM_IMAGES;
- adapt->PutVideo = NULL;
- adapt->PutStill = NULL;
- adapt->GetVideo = NULL;
- adapt->GetStill = NULL;
- adapt->StopVideo = RADEONStopVideo;
- adapt->SetPortAttribute = RADEONSetPortAttribute;
- adapt->GetPortAttribute = RADEONGetPortAttribute;
- adapt->QueryBestSize = RADEONQueryBestSize;
- adapt->PutImage = RADEONPutImageTextured;
- adapt->ReputImage = NULL;
- adapt->QueryImageAttributes = RADEONQueryImageAttributes;
-
- for (i = 0; i < num_texture_ports; i++) {
- RADEONPortPrivPtr pPriv = &pPortPriv[i];
-
- pPriv->textured = TRUE;
- pPriv->videoStatus = 0;
- pPriv->currentBuffer = 0;
- pPriv->doubleBuffer = 0;
-
- /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */
- REGION_NULL(pScreen, &pPriv->clip);
- adapt->pPortPrivates[i].ptr = (pointer) (pPriv);
- }
-
- return adapt;
-}
-
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
deleted file mode 100644
index e0f3bba..0000000
--- a/src/radeon_textured_videofuncs.c
+++ /dev/null
@@ -1,596 +0,0 @@
-/*
- * Copyright 2008 Alex Deucher
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- *
- * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al.
- *
- */
-
-#if defined(ACCEL_MMIO) && defined(ACCEL_CP)
-#error Cannot define both MMIO and CP acceleration!
-#endif
-
-#if !defined(UNIXCPP) || defined(ANSICPP)
-#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix
-#else
-#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix
-#endif
-
-#ifdef ACCEL_MMIO
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO)
-#else
-#ifdef ACCEL_CP
-#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP)
-#else
-#error No accel type defined!
-#endif
-#endif
-
-#define VTX_DWORD_COUNT 4
-
-#ifdef ACCEL_CP
-
-#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
-do { \
- OUT_VIDEO_RING_F(_dstX); \
- OUT_VIDEO_RING_F(_dstY); \
- OUT_VIDEO_RING_F(_srcX); \
- OUT_VIDEO_RING_F(_srcY); \
-} while (0)
-
-#else /* ACCEL_CP */
-
-#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
-do { \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstY); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcX); \
- OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcY); \
-} while (0)
-
-#endif /* !ACCEL_CP */
-
-static void
-FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- PixmapPtr pPixmap = pPriv->pPixmap;
- CARD32 txformat;
- CARD32 txfilter, txformat0, txformat1, txoffset, txpitch;
- CARD32 dst_offset, dst_pitch, dst_format;
- CARD32 txenable, colorpitch;
- CARD32 blendcntl;
- int dstxoff, dstyoff, pixel_shift;
- VIDEO_PREAMBLE();
-
- BoxPtr pBox = REGION_RECTS(&pPriv->clip);
- int nBox = REGION_NUM_RECTS(&pPriv->clip);
-
- pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
-
-#ifdef USE_EXA
- if (info->useEXA) {
- dst_offset = exaGetPixmapOffset(pPixmap) + info->fbLocation;
- dst_pitch = exaGetPixmapPitch(pPixmap);
- } else
-#endif
- {
- dst_offset = (pPixmap->devPrivate.ptr - info->FB) +
- info->fbLocation + pScrn->fbOffset;
- dst_pitch = pPixmap->devKind;
- }
-
-#ifdef COMPOSITE
- dstxoff = -pPixmap->screen_x + pPixmap->drawable.x;
- dstyoff = -pPixmap->screen_y + pPixmap->drawable.y;
-#else
- dstxoff = 0;
- dstyoff = 0;
-#endif
-
-#if 0
- ErrorF("dst_offset: 0x%x\n", dst_offset);
- ErrorF("dst_pitch: 0x%x\n", dst_pitch);
- ErrorF("dstxoff: 0x%x\n", dstxoff);
- ErrorF("dstyoff: 0x%x\n", dstyoff);
- ErrorF("src_offset: 0x%x\n", pPriv->src_offset);
- ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch);
-#endif
-
- if (!info->XInited3D)
- RADEONInit3DEngine(pScrn);
-
- /* we can probably improve this */
- BEGIN_VIDEO(2);
- OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
- /* We must wait for 3d to idle, in case source was just written as a dest. */
- OUT_VIDEO_REG(RADEON_WAIT_UNTIL,
- RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
- FINISH_VIDEO();
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
-
- switch (pPixmap->drawable.bitsPerPixel) {
- case 16:
- if (pPixmap->drawable.depth == 15)
- dst_format = R300_COLORFORMAT_ARGB1555;
- else
- dst_format = R300_COLORFORMAT_RGB565;
- break;
- case 32:
- dst_format = R300_COLORFORMAT_ARGB8888;
- break;
- default:
- return;
- }
-
- colorpitch = dst_pitch >> pixel_shift;
- colorpitch |= dst_format;
-
- if (RADEONTilingEnabled(pScrn, pPixmap))
- colorpitch |= R300_COLORTILE;
-
- if (pPriv->id == FOURCC_UYVY)
- txformat1 = R300_TX_FORMAT_YVYU422;
- else
- txformat1 = R300_TX_FORMAT_VYUY422;
-
- txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP;
-
- txformat0 = (((pPriv->w - 1) << R300_TXWIDTH_SHIFT) |
- ((pPriv->h - 1) << R300_TXHEIGHT_SHIFT));
-
- txformat0 |= R300_TXPITCH_EN;
-
- info->texW[0] = pPriv->w;
- info->texH[0] = pPriv->h;
-
- txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) |
- R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
-
- /* pitch is in pixels */
- txpitch = pPriv->src_pitch / 2;
- txpitch -= 1;
-
- txoffset = pPriv->src_offset;
-
- BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_FILTER0_0, txfilter);
- OUT_VIDEO_REG(R300_TX_FILTER1_0, 0);
- OUT_VIDEO_REG(R300_TX_FORMAT0_0, txformat0);
- OUT_VIDEO_REG(R300_TX_FORMAT1_0, txformat1);
- OUT_VIDEO_REG(R300_TX_FORMAT2_0, txpitch);
- OUT_VIDEO_REG(R300_TX_OFFSET_0, txoffset);
- FINISH_VIDEO();
-
- txenable = R300_TEX_0_ENABLE;
-
- /* setup the VAP */
- if (has_tcl) {
- BEGIN_VIDEO(26);
- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0);
- OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
- } else {
- BEGIN_VIDEO(8);
- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
- OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (4 << R300_PVS_NUM_FPUS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
- }
-
- OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
- if (has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (10 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_LAST_VEC_1 |
- R300_SIGNED_1));
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- } else {
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_LAST_VEC_1 |
- R300_SIGNED_1));
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_1_SHIFT)));
- }
-
- /* setup vertex shader */
- if (has_tcl) {
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT)));
- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
-
-
- OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
- }
-
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
- FINISH_VIDEO();
-
- /* setup pixel shader */
- if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
- BEGIN_VIDEO(16);
- OUT_VIDEO_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_VIDEO_REG(R300_RS_IP_0,
- (R300_RS_TEX_PTR(0) |
- R300_RS_COL_PTR(0) |
- R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
- OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
- OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
- OUT_VIDEO_REG(R300_US_CODE_OFFSET,
- (R300_ALU_CODE_OFFSET(0) |
- R300_ALU_CODE_SIZE(1) |
- R300_TEX_CODE_OFFSET(0) |
- R300_TEX_CODE_SIZE(1)));
- OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0);
- OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0);
- OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0);
- OUT_VIDEO_REG(R300_US_CODE_ADDR_3, 0x400000);
- OUT_VIDEO_REG(R300_US_TEX_INST_0, 0x8000);
- OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
- OUT_VIDEO_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
- OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
- OUT_VIDEO_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
- FINISH_VIDEO();
- } else {
- BEGIN_VIDEO(22);
- OUT_VIDEO_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_VIDEO_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
-
- OUT_VIDEO_REG(R300_RS_INST_COUNT, 0);
- OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
- OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
- OUT_VIDEO_REG(R500_US_FC_CTRL, 0);
- OUT_VIDEO_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
- OUT_VIDEO_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
- OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00007807);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x06400000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0xe4000400);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00078105);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00db0220);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00c0c000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x20490000);
- FINISH_VIDEO();
- }
-
- BEGIN_VIDEO(6);
- OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
- OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
-
- OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
- OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch);
-
- blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
- OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
- OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0);
- FINISH_VIDEO();
-
- BEGIN_VIDEO(1);
- OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT);
- FINISH_VIDEO();
-
- } else {
-
- /* Same for R100/R200 */
- switch (pPixmap->drawable.bitsPerPixel) {
- case 16:
- if (pPixmap->drawable.depth == 15)
- dst_format = RADEON_COLOR_FORMAT_ARGB1555;
- else
- dst_format = RADEON_COLOR_FORMAT_RGB565;
- break;
- case 32:
- dst_format = RADEON_COLOR_FORMAT_ARGB8888;
- break;
- default:
- return;
- }
-
- if (pPriv->id == FOURCC_UYVY)
- txformat = RADEON_TXFORMAT_YVYU422;
- else
- txformat = RADEON_TXFORMAT_VYUY422;
-
- txformat |= RADEON_TXFORMAT_NON_POWER2;
-
- colorpitch = dst_pitch >> pixel_shift;
-
- if (RADEONTilingEnabled(pScrn, pPixmap))
- colorpitch |= RADEON_COLOR_TILE_ENABLE;
-
- BEGIN_VIDEO(5);
-
- OUT_VIDEO_REG(RADEON_PP_CNTL,
- RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
- OUT_VIDEO_REG(RADEON_RB3D_CNTL,
- dst_format | RADEON_ALPHA_BLEND_ENABLE);
- OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
-
- OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch);
-
- OUT_VIDEO_REG(RADEON_RB3D_BLENDCNTL,
- RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
-
- FINISH_VIDEO();
-
-
- if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) ||
- (info->ChipFamily == CHIP_FAMILY_RS300) ||
- (info->ChipFamily == CHIP_FAMILY_R200)) {
-
- info->texW[0] = pPriv->w;
- info->texH[0] = pPriv->h;
-
- BEGIN_VIDEO(12);
-
- OUT_VIDEO_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
- OUT_VIDEO_REG(R200_SE_VTX_FMT_1,
- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
-
- OUT_VIDEO_REG(R200_PP_TXFILTER_0,
- R200_MAG_FILTER_LINEAR |
- R200_MIN_FILTER_LINEAR |
- R200_YUV_TO_RGB);
- OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat);
- OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0);
- OUT_VIDEO_REG(R200_PP_TXSIZE_0,
- (pPriv->w - 1) |
- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
-
- OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
-
- OUT_VIDEO_REG(R200_PP_TXCBLEND_0,
- R200_TXC_ARG_A_ZERO |
- R200_TXC_ARG_B_ZERO |
- R200_TXC_ARG_C_R0_COLOR |
- R200_TXC_OP_MADD);
- OUT_VIDEO_REG(R200_PP_TXCBLEND2_0,
- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_VIDEO_REG(R200_PP_TXABLEND_0,
- R200_TXA_ARG_A_ZERO |
- R200_TXA_ARG_B_ZERO |
- R200_TXA_ARG_C_R0_ALPHA |
- R200_TXA_OP_MADD);
- OUT_VIDEO_REG(R200_PP_TXABLEND2_0,
- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
- FINISH_VIDEO();
- } else {
-
- info->texW[0] = 1;
- info->texH[0] = 1;
-
- BEGIN_VIDEO(8);
-
- OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
- RADEON_SE_VTX_FMT_ST0);
-
- OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR |
- RADEON_MIN_FILTER_LINEAR |
- RADEON_YUV_TO_RGB);
- OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat);
- OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
- OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0,
- RADEON_COLOR_ARG_A_ZERO |
- RADEON_COLOR_ARG_B_ZERO |
- RADEON_COLOR_ARG_C_T0_COLOR |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- OUT_VIDEO_REG(RADEON_PP_TXABLEND_0,
- RADEON_ALPHA_ARG_A_ZERO |
- RADEON_ALPHA_ARG_B_ZERO |
- RADEON_ALPHA_ARG_C_T0_ALPHA |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
-
- OUT_VIDEO_REG(RADEON_PP_TEX_SIZE_0,
- (pPriv->w - 1) |
- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- OUT_VIDEO_REG(RADEON_PP_TEX_PITCH_0,
- pPriv->src_pitch - 32);
- FINISH_VIDEO();
- }
- }
-
- while (nBox--) {
- int srcX, srcY, srcw, srch;
- int dstX, dstY, dstw, dsth;
- xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
- dstX = pBox->x1 + dstxoff;
- dstY = pBox->y1 + dstyoff;
- dstw = pBox->x2 - pBox->x1;
- dsth = pBox->y2 - pBox->y1;
-
- srcX = ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
- srcY = ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
-
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
-
- srcTopLeft.x = IntToxFixed(srcX);
- srcTopLeft.y = IntToxFixed(srcY);
- srcTopRight.x = IntToxFixed(srcX + srcw);
- srcTopRight.y = IntToxFixed(srcY);
- srcBottomLeft.x = IntToxFixed(srcX);
- srcBottomLeft.y = IntToxFixed(srcY + srch);
- srcBottomRight.x = IntToxFixed(srcX + srcw);
- srcBottomRight.y = IntToxFixed(srcY + srch);
-
-
-#if 0
- ErrorF("dst: %d, %d, %d, %d\n", dstX, dstY, dstw, dsth);
- ErrorF("src: %d, %d, %d, %d\n", srcX, srcY, srcw, srch);
-#endif
-
-#ifdef ACCEL_CP
- if (info->ChipFamily < CHIP_FAMILY_R200) {
- BEGIN_RING(4 * VTX_DWORD_COUNT + 3);
- OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
- 4 * VTX_DWORD_COUNT + 1));
- OUT_RING(RADEON_CP_VC_FRMT_XY |
- RADEON_CP_VC_FRMT_ST0);
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
- RADEON_CP_VC_CNTL_PRIM_WALK_RING |
- RADEON_CP_VC_CNTL_MAOS_ENABLE |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
- } else {
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- BEGIN_RING(4 * VTX_DWORD_COUNT + 6);
- else
- BEGIN_RING(4 * VTX_DWORD_COUNT + 2);
- OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
- 4 * VTX_DWORD_COUNT));
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
- RADEON_CP_VC_CNTL_PRIM_WALK_RING |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
- }
-#else /* ACCEL_CP */
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
- BEGIN_VIDEO(3 + VTX_DWORD_COUNT * 4);
- else
- BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4);
-
- if (info->ChipFamily < CHIP_FAMILY_R200) {
- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
- RADEON_VF_PRIM_WALK_DATA |
- RADEON_VF_RADEON_MODE |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
- } else {
- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
- RADEON_VF_PRIM_WALK_DATA |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
- }
-#endif
-
- VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
- VTX_OUT((float)dstX, (float)(dstY + dsth),
- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
- VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth),
- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]);
- VTX_OUT((float)(dstX + dstw), (float)dstY,
- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
-
- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
- OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
- OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
- }
-
-#ifdef ACCEL_CP
- ADVANCE_RING();
-#else
- FINISH_VIDEO();
-#endif /* !ACCEL_CP */
-
- pBox++;
- }
-
- DamageDamageRegion(pPriv->pDraw, &pPriv->clip);
-}
-
-#undef VTX_OUT
-#undef FUNC_NAME
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
deleted file mode 100644
index d5d1e9e..0000000
--- a/src/radeon_tv.c
+++ /dev/null
@@ -1,1164 +0,0 @@
-/*
- * Integrated TV out support based on the GATOS code by
- * Federico Ulivi <fulivi at lycos.com>
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include <stdio.h>
-
-/* X and server generic header files */
-#include "xf86.h"
-#include "xf86_OSproc.h"
-#include "vgaHW.h"
-#include "xf86Modes.h"
-
-/* Driver data structures */
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_version.h"
-#include "radeon_tv.h"
-
-/**********************************************************************
- *
- * ModeConstants
- *
- * Storage of constants related to a single video mode
- *
- **********************************************************************/
-
-typedef struct
-{
- CARD16 horResolution;
- CARD16 verResolution;
- TVStd standard;
- CARD16 horTotal;
- CARD16 verTotal;
- CARD16 horStart;
- CARD16 horSyncStart;
- CARD16 verSyncStart;
- unsigned defRestart;
- CARD16 crtcPLL_N;
- CARD8 crtcPLL_M;
- CARD8 crtcPLL_postDiv;
- unsigned pixToTV;
-} TVModeConstants;
-
-static const CARD16 hor_timing_NTSC[] =
-{
- 0x0007,
- 0x003f,
- 0x0263,
- 0x0a24,
- 0x2a6b,
- 0x0a36,
- 0x126d, /* H_TABLE_POS1 */
- 0x1bfe,
- 0x1a8f, /* H_TABLE_POS2 */
- 0x1ec7,
- 0x3863,
- 0x1bfe,
- 0x1bfe,
- 0x1a2a,
- 0x1e95,
- 0x0e31,
- 0x201b,
- 0
-};
-
-static const CARD16 vert_timing_NTSC[] =
-{
- 0x2001,
- 0x200d,
- 0x1006,
- 0x0c06,
- 0x1006,
- 0x1818,
- 0x21e3,
- 0x1006,
- 0x0c06,
- 0x1006,
- 0x1817,
- 0x21d4,
- 0x0002,
- 0
-};
-
-static const CARD16 hor_timing_PAL[] =
-{
- 0x0007,
- 0x0058,
- 0x027c,
- 0x0a31,
- 0x2a77,
- 0x0a95,
- 0x124f, /* H_TABLE_POS1 */
- 0x1bfe,
- 0x1b22, /* H_TABLE_POS2 */
- 0x1ef9,
- 0x387c,
- 0x1bfe,
- 0x1bfe,
- 0x1b31,
- 0x1eb5,
- 0x0e43,
- 0x201b,
- 0
-};
-
-static const CARD16 vert_timing_PAL[] =
-{
- 0x2001,
- 0x200c,
- 0x1005,
- 0x0c05,
- 0x1005,
- 0x1401,
- 0x1821,
- 0x2240,
- 0x1005,
- 0x0c05,
- 0x1005,
- 0x1401,
- 0x1822,
- 0x2230,
- 0x0002,
- 0
-};
-
-/**********************************************************************
- *
- * availableModes
- *
- * Table of all allowed modes for tv output
- *
- **********************************************************************/
-static const TVModeConstants availableTVModes[] =
-{
- {
- 800, /* horResolution */
- 600, /* verResolution */
- TV_STD_NTSC, /* standard */
- 990, /* horTotal */
- 740, /* verTotal */
- 813, /* horStart */
- 824, /* horSyncStart */
- 632, /* verSyncStart */
- 625592, /* defRestart */
- 592, /* crtcPLL_N */
- 91, /* crtcPLL_M */
- 4, /* crtcPLL_postDiv */
- 1022, /* pixToTV */
- },
- {
- 800, /* horResolution */
- 600, /* verResolution */
- TV_STD_PAL, /* standard */
- 1144, /* horTotal */
- 706, /* verTotal */
- 812, /* horStart */
- 824, /* horSyncStart */
- 669, /* verSyncStart */
- 696700, /* defRestart */
- 1382, /* crtcPLL_N */
- 231, /* crtcPLL_M */
- 4, /* crtcPLL_postDiv */
- 759, /* pixToTV */
- }
-};
-
-#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ]))
-
-static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
-static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
-static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
-static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
-
-
-static void
-RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests,
- unsigned nWaitLoops, unsigned cntThreshold)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 savePLLTest;
- unsigned i;
- unsigned j;
-
- OUTREG(RADEON_TEST_DEBUG_MUX, (INREG(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
-
- savePLLTest = INPLL(pScrn, RADEON_PLL_TEST_CNTL);
-
- OUTPLL(pScrn, RADEON_PLL_TEST_CNTL, savePLLTest & ~RADEON_PLL_MASK_READ_B);
-
- /* XXX: these should probably be OUTPLL to avoid various PLL errata */
-
- OUTREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
-
- for (i = 0; i < nTests; i++) {
- OUTREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
-
- for (j = 0; j < nWaitLoops; j++)
- if (INREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cntThreshold)
- break;
- }
-
- OUTPLL(pScrn, RADEON_PLL_TEST_CNTL, savePLLTest);
-
- OUTREG(RADEON_TEST_DEBUG_MUX, INREG(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
-}
-
-/* Write to TV FIFO RAM */
-static void
-RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr,
- CARD32 value)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp;
- int i = 0;
-
- OUTREG(RADEON_TV_HOST_WRITE_DATA, value);
-
- OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr);
- OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
-
- do {
- tmp = INREG(RADEON_TV_HOST_RD_WT_CNTL);
- if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
- break;
- i++;
- }
- while (i < 10000);
- /*while ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0);*/
-
- OUTREG(RADEON_TV_HOST_RD_WT_CNTL, 0);
-}
-
-/* Read from TV FIFO RAM */
-static CARD32
-RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp;
- int i = 0;
-
- OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr);
- OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
-
- do {
- tmp = INREG(RADEON_TV_HOST_RD_WT_CNTL);
- if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
- break;
- i++;
- }
- while (i < 10000);
- /*while ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0);*/
-
- OUTREG(RADEON_TV_HOST_RD_WT_CNTL, 0);
-
- return INREG(RADEON_TV_HOST_READ_DATA);
-}
-
-/* Get FIFO addresses of horizontal & vertical code timing tables from
- * settings of uv_adr register.
- */
-static CARD16
-RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr)
-{
- CARD16 hTable;
-
- switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
- case 0:
- hTable = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
- break;
- case 1:
- hTable = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
- break;
- case 2:
- hTable = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
- break;
- default:
- /* Of course, this should never happen */
- hTable = 0;
- break;
- }
- return hTable;
-}
-
-static CARD16
-RADEONGetVTimingTablesAddr(CARD32 tv_uv_adr)
-{
- CARD16 vTable;
-
- switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
- case 0:
- vTable = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
- break;
- case 1:
- vTable = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
- break;
- case 2:
- vTable = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
- break;
- default:
- /* Of course, this should never happen */
- vTable = 0;
- break;
- }
- return vTable;
-}
-
-/* Restore horizontal/vertical timing code tables */
-static void
-RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD16 hTable;
- CARD16 vTable;
- CARD32 tmp;
- unsigned i;
-
- OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr);
- hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr);
- vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr);
-
- for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) {
- tmp = ((CARD32)restore->h_code_timing[ i ] << 14) | ((CARD32)restore->h_code_timing[ i + 1 ]);
- RADEONWriteTVFIFO(pScrn, hTable, tmp);
- if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0)
- break;
- }
-
- for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, vTable++) {
- tmp = ((CARD32)restore->v_code_timing[ i + 1 ] << 14) | ((CARD32)restore->v_code_timing[ i ]);
- RADEONWriteTVFIFO(pScrn, vTable, tmp);
- if (restore->v_code_timing[ i ] == 0 || restore->v_code_timing[ i + 1 ] == 0)
- break;
- }
-}
-
-/* restore TV PLLs */
-static void
-RADEONRestoreTVPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
-
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
- OUTPLL(pScrn, RADEON_TV_PLL_CNTL, restore->tv_pll_cntl);
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
-
- RADEONWaitPLLLock(pScrn, 200, 800, 135);
-
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
-
- RADEONWaitPLLLock(pScrn, 300, 160, 27);
- RADEONWaitPLLLock(pScrn, 200, 800, 135);
-
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~0xf);
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
-
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
- OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
-}
-
-/* Restore TV horizontal/vertical settings */
-static void
-RADEONRestoreTVHVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_TV_RGB_CNTL, restore->tv_rgb_cntl);
-
- OUTREG(RADEON_TV_HTOTAL, restore->tv_htotal);
- OUTREG(RADEON_TV_HDISP, restore->tv_hdisp);
- OUTREG(RADEON_TV_HSTART, restore->tv_hstart);
-
- OUTREG(RADEON_TV_VTOTAL, restore->tv_vtotal);
- OUTREG(RADEON_TV_VDISP, restore->tv_vdisp);
-
- OUTREG(RADEON_TV_FTOTAL, restore->tv_ftotal);
-
- OUTREG(RADEON_TV_VSCALER_CNTL1, restore->tv_vscaler_cntl1);
- OUTREG(RADEON_TV_VSCALER_CNTL2, restore->tv_vscaler_cntl2);
-
- OUTREG(RADEON_TV_Y_FALL_CNTL, restore->tv_y_fall_cntl);
- OUTREG(RADEON_TV_Y_RISE_CNTL, restore->tv_y_rise_cntl);
- OUTREG(RADEON_TV_Y_SAW_TOOTH_CNTL, restore->tv_y_saw_tooth_cntl);
-}
-
-/* restore TV RESTART registers */
-static void
-RADEONRestoreTVRestarts(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_TV_FRESTART, restore->tv_frestart);
- OUTREG(RADEON_TV_HRESTART, restore->tv_hrestart);
- OUTREG(RADEON_TV_VRESTART, restore->tv_vrestart);
-}
-
-/* restore tv standard & output muxes */
-static void
-RADEONRestoreTVOutputStd(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- OUTREG(RADEON_TV_SYNC_CNTL, restore->tv_sync_cntl);
-
- OUTREG(RADEON_TV_TIMING_CNTL, restore->tv_timing_cntl);
-
- OUTREG(RADEON_TV_MODULATOR_CNTL1, restore->tv_modulator_cntl1);
- OUTREG(RADEON_TV_MODULATOR_CNTL2, restore->tv_modulator_cntl2);
-
- OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, restore->tv_pre_dac_mux_cntl);
-
- OUTREG(RADEON_TV_CRC_CNTL, restore->tv_crc_cntl);
-}
-
-/* Restore TV out regs */
-void
-RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- ErrorF("Entering Restore TV\n");
-
- OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
- | RADEON_TV_ASYNC_RST
- | RADEON_CRT_ASYNC_RST
- | RADEON_TV_FIFO_ASYNC_RST));
-
- /* Temporarily turn the TV DAC off */
- OUTREG(RADEON_TV_DAC_CNTL, ((restore->tv_dac_cntl & ~RADEON_TV_DAC_NBLANK)
- | RADEON_TV_DAC_BGSLEEP
- | RADEON_TV_DAC_RDACPD
- | RADEON_TV_DAC_GDACPD
- | RADEON_TV_DAC_BDACPD));
-
- ErrorF("Restore TV PLL\n");
- RADEONRestoreTVPLLRegisters(pScrn, restore);
-
- ErrorF("Restore TVHV\n");
- RADEONRestoreTVHVRegisters(pScrn, restore);
-
- OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
- | RADEON_TV_ASYNC_RST
- | RADEON_CRT_ASYNC_RST));
-
- ErrorF("Restore TV Restarts\n");
- RADEONRestoreTVRestarts(pScrn, restore);
-
- ErrorF("Restore Timing Tables\n");
- RADEONRestoreTVTimingTables(pScrn, restore);
-
-
- OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl
- | RADEON_TV_ASYNC_RST));
-
- ErrorF("Restore TV standard\n");
- RADEONRestoreTVOutputStd(pScrn, restore);
-
- OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl);
-
- OUTREG(RADEON_TV_GAIN_LIMIT_SETTINGS, restore->tv_gain_limit_settings);
- OUTREG(RADEON_TV_LINEAR_GAIN_SETTINGS, restore->tv_linear_gain_settings);
-
- OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
-
- ErrorF("Leaving Restore TV\n");
-}
-
-/* Save horizontal/vertical timing code tables */
-static void
-RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD16 hTable;
- CARD16 vTable;
- CARD32 tmp;
- unsigned i;
-
- save->tv_uv_adr = INREG(RADEON_TV_UV_ADR);
- hTable = RADEONGetHTimingTablesAddr(save->tv_uv_adr);
- vTable = RADEONGetVTimingTablesAddr(save->tv_uv_adr);
-
- /*
- * Reset FIFO arbiter in order to be able to access FIFO RAM
- */
-
- OUTREG(RADEON_TV_MASTER_CNTL, (RADEON_TV_ASYNC_RST
- | RADEON_CRT_ASYNC_RST
- | RADEON_RESTART_PHASE_FIX
- | RADEON_CRT_FIFO_CE_EN
- | RADEON_TV_FIFO_CE_EN
- | RADEON_TV_ON));
-
- /*OUTREG(RADEON_TV_MASTER_CNTL, save->tv_master_cntl | RADEON_TV_ON);*/
-
- ErrorF("saveTimingTables: reading timing tables\n");
-
- for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2) {
- tmp = RADEONReadTVFIFO(pScrn, hTable--);
- save->h_code_timing[ i ] = (CARD16)((tmp >> 14) & 0x3fff);
- save->h_code_timing[ i + 1 ] = (CARD16)(tmp & 0x3fff);
-
- if (save->h_code_timing[ i ] == 0 || save->h_code_timing[ i + 1 ] == 0)
- break;
- }
-
- for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2) {
- tmp = RADEONReadTVFIFO(pScrn, vTable++);
- save->v_code_timing[ i ] = (CARD16)(tmp & 0x3fff);
- save->v_code_timing[ i + 1 ] = (CARD16)((tmp >> 14) & 0x3fff);
-
- if (save->v_code_timing[ i ] == 0 || save->v_code_timing[ i + 1 ] == 0)
- break;
- }
-}
-
-/* read TV regs */
-void
-RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- ErrorF("Entering TV Save\n");
-
- save->tv_crc_cntl = INREG(RADEON_TV_CRC_CNTL);
- save->tv_frestart = INREG(RADEON_TV_FRESTART);
- save->tv_hrestart = INREG(RADEON_TV_HRESTART);
- save->tv_vrestart = INREG(RADEON_TV_VRESTART);
- save->tv_gain_limit_settings = INREG(RADEON_TV_GAIN_LIMIT_SETTINGS);
- save->tv_hdisp = INREG(RADEON_TV_HDISP);
- save->tv_hstart = INREG(RADEON_TV_HSTART);
- save->tv_htotal = INREG(RADEON_TV_HTOTAL);
- save->tv_linear_gain_settings = INREG(RADEON_TV_LINEAR_GAIN_SETTINGS);
- save->tv_master_cntl = INREG(RADEON_TV_MASTER_CNTL);
- save->tv_rgb_cntl = INREG(RADEON_TV_RGB_CNTL);
- save->tv_modulator_cntl1 = INREG(RADEON_TV_MODULATOR_CNTL1);
- save->tv_modulator_cntl2 = INREG(RADEON_TV_MODULATOR_CNTL2);
- save->tv_pre_dac_mux_cntl = INREG(RADEON_TV_PRE_DAC_MUX_CNTL);
- save->tv_sync_cntl = INREG(RADEON_TV_SYNC_CNTL);
- save->tv_timing_cntl = INREG(RADEON_TV_TIMING_CNTL);
- save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
- save->tv_upsamp_and_gain_cntl = INREG(RADEON_TV_UPSAMP_AND_GAIN_CNTL);
- save->tv_vdisp = INREG(RADEON_TV_VDISP);
- save->tv_ftotal = INREG(RADEON_TV_FTOTAL);
- save->tv_vscaler_cntl1 = INREG(RADEON_TV_VSCALER_CNTL1);
- save->tv_vscaler_cntl2 = INREG(RADEON_TV_VSCALER_CNTL2);
- save->tv_vtotal = INREG(RADEON_TV_VTOTAL);
- save->tv_y_fall_cntl = INREG(RADEON_TV_Y_FALL_CNTL);
- save->tv_y_rise_cntl = INREG(RADEON_TV_Y_RISE_CNTL);
- save->tv_y_saw_tooth_cntl = INREG(RADEON_TV_Y_SAW_TOOTH_CNTL);
-
- save->tv_pll_cntl = INPLL(pScrn, RADEON_TV_PLL_CNTL);
- save->tv_pll_cntl1 = INPLL(pScrn, RADEON_TV_PLL_CNTL1);
-
- ErrorF("Save TV timing tables\n");
-
- RADEONSaveTVTimingTables(pScrn, save);
-
- ErrorF("TV Save done\n");
-}
-
-
-/* Compute F,V,H restarts from default restart position and hPos & vPos
- * Return TRUE when code timing table was changed
- */
-static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode)
-{
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int restart;
- unsigned hTotal;
- unsigned vTotal;
- unsigned fTotal;
- int vOffset;
- int hOffset;
- CARD16 p1;
- CARD16 p2;
- Bool hChanged;
- CARD16 hInc;
- const TVModeConstants *constPtr;
-
- /* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
-
- hTotal = constPtr->horTotal;
- vTotal = constPtr->verTotal;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- fTotal = NTSC_TV_VFTOTAL + 1;
- else
- fTotal = PAL_TV_VFTOTAL + 1;
-
- /* Adjust positions 1&2 in hor. code timing table */
- hOffset = radeon_output->hPos * H_POS_UNIT;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M) {
- /* improve image centering */
- hOffset -= 50;
- p1 = hor_timing_NTSC[ H_TABLE_POS1 ];
- p2 = hor_timing_NTSC[ H_TABLE_POS2 ];
- } else {
- p1 = hor_timing_PAL[ H_TABLE_POS1 ];
- p2 = hor_timing_PAL[ H_TABLE_POS2 ];
- }
-
-
- p1 = (CARD16)((int)p1 + hOffset);
- p2 = (CARD16)((int)p2 - hOffset);
-
- hChanged = (p1 != save->h_code_timing[ H_TABLE_POS1 ] ||
- p2 != save->h_code_timing[ H_TABLE_POS2 ]);
-
- save->h_code_timing[ H_TABLE_POS1 ] = p1;
- save->h_code_timing[ H_TABLE_POS2 ] = p2;
-
- /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
- hOffset = (hOffset * (int)(constPtr->pixToTV)) / 1000;
-
- /* Adjust restart */
- restart = constPtr->defRestart;
-
- /*
- * Convert vPos TV lines to n. of CRTC pixels
- * Be verrrrry careful when mixing signed & unsigned values in C..
- */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- vOffset = ((int)(vTotal * hTotal) * 2 * radeon_output->vPos) / (int)(NTSC_TV_LINES_PER_FRAME);
- else
- vOffset = ((int)(vTotal * hTotal) * 2 * radeon_output->vPos) / (int)(PAL_TV_LINES_PER_FRAME);
-
- restart -= vOffset + hOffset;
-
- ErrorF("computeRestarts: def = %u, h = %d, v = %d, p1=%04x, p2=%04x, restart = %d\n",
- constPtr->defRestart , radeon_output->hPos , radeon_output->vPos , p1 , p2 , restart);
-
- save->tv_hrestart = restart % hTotal;
- restart /= hTotal;
- save->tv_vrestart = restart % vTotal;
- restart /= vTotal;
- save->tv_frestart = restart % fTotal;
-
- ErrorF("computeRestarts: F/H/V=%u,%u,%u\n",
- (unsigned)save->tv_frestart, (unsigned)save->tv_vrestart,
- (unsigned)save->tv_hrestart);
-
- /* Compute H_INC from hSize */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- hInc = (CARD16)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) /
- (radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
- else
- hInc = (CARD16)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) /
- (radeon_output->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
-
- save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) |
- ((CARD32)hInc << RADEON_H_INC_SHIFT);
-
- ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , radeon_output->hSize , hInc);
-
- return hChanged;
-}
-
-/* intit TV-out regs */
-void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
- DisplayModePtr mode, BOOL IsPrimary)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned i;
- unsigned long vert_space, flicker_removal;
- CARD32 tmp;
- const TVModeConstants *constPtr;
- const CARD16 *hor_timing;
- const CARD16 *vert_timing;
-
-
- /* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
-
- save->tv_crc_cntl = 0;
-
- save->tv_gain_limit_settings = (0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
- (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT);
-
- save->tv_hdisp = constPtr->horResolution - 1;
- save->tv_hstart = constPtr->horStart;
- save->tv_htotal = constPtr->horTotal - 1;
-
- save->tv_linear_gain_settings = (0x100 << RADEON_UV_GAIN_SHIFT) |
- (0x100 << RADEON_Y_GAIN_SHIFT);
-
- save->tv_master_cntl = (RADEON_VIN_ASYNC_RST
- | RADEON_CRT_FIFO_CE_EN
- | RADEON_TV_FIFO_CE_EN
- | RADEON_TV_ON);
-
- if (!IS_R300_VARIANT)
- save->tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
- save->tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
-
- save->tv_modulator_cntl1 = RADEON_SLEW_RATE_LIMIT
- | RADEON_SYNC_TIP_LEVEL
- | RADEON_YFLT_EN
- | RADEON_UVFLT_EN
- | (6 << RADEON_CY_FILT_BLEND_SHIFT);
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J) {
- save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT)
- | (0x3b << RADEON_BLANK_LEVEL_SHIFT);
- save->tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
- ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
- } else if (radeon_output->tvStd == TV_STD_SCART_PAL) {
- save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
- save->tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
- ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
- } else {
- save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN
- | (0x3b << RADEON_SET_UP_LEVEL_SHIFT)
- | (0x3b << RADEON_BLANK_LEVEL_SHIFT);
- save->tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
- ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
- }
-
- save->pll_test_cntl = 0;
-
- save->tv_pre_dac_mux_cntl = (RADEON_Y_RED_EN
- | RADEON_C_GRN_EN
- | RADEON_CMP_BLU_EN
- | RADEON_DAC_DITHER_EN);
-
- save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN
- | RADEON_TVOUT_SCALE_EN
- | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
- | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT));
-
- if (IsPrimary) {
- if (radeon_output->Flags & RADEON_USE_RMX)
- save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
- else
- save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
- } else {
- save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
- }
-
- save->tv_sync_cntl = RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE;
-
- save->tv_sync_size = constPtr->horResolution + 8;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- vert_space = constPtr->verTotal * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
- else
- vert_space = constPtr->verTotal * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
-
- save->tv_vscaler_cntl1 = RADEON_Y_W_EN;
- save->tv_vscaler_cntl1 =
- (save->tv_vscaler_cntl1 & 0xe3ff0000) | (vert_space * (1 << FRAC_BITS) / 10000);
- save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
- if (constPtr->horResolution == 1024)
- save->tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
- else
- save->tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- flicker_removal =
- (float) constPtr->verTotal * 2.0 / NTSC_TV_LINES_PER_FRAME + 0.5;
- else
- flicker_removal =
- (float) constPtr->verTotal * 2.0 / PAL_TV_LINES_PER_FRAME + 0.5;
-
- if (flicker_removal < 3)
- flicker_removal = 3;
- for (i = 0; i < 6; ++i) {
- if (flicker_removal == SLOPE_limit[i])
- break;
- }
- save->tv_y_saw_tooth_cntl =
- (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 5001) / 10000 / 8
- | ((SLOPE_value[i] * (1 << (FRAC_BITS - 1)) / 8) << 16);
- save->tv_y_fall_cntl =
- (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
- RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
- 1024;
- save->tv_y_rise_cntl =
- RADEON_Y_RISE_PING_PONG
- | (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
-
- save->tv_vscaler_cntl2 = ((save->tv_vscaler_cntl2 & 0x00fffff0)
- | (0x10 << 24)
- | RADEON_DITHER_MODE
- | RADEON_Y_OUTPUT_DITHER_EN
- | RADEON_UV_OUTPUT_DITHER_EN
- | RADEON_UV_TO_BUF_DITHER_EN);
-
- tmp = (save->tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
- tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
- tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
- save->tv_timing_cntl = tmp;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- save->tv_dac_cntl = radeon_output->ntsc_tvdac_adj;
- else
- save->tv_dac_cntl = radeon_output->pal_tvdac_adj;
-
- save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD);
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
- save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
- else
- save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
-
-#if 0
- /* needs fixes for r4xx */
- save->tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | RADEON_TV_DAC_GDACPD
- | RADEON_TV_DAC_BDACPD);
-
- if (radeon_output->MonType == MT_CTV) {
- save->tv_dac_cntl &= ~RADEON_TV_DAC_BDACPD;
- }
-
- if (radeon_output->MonType == MT_STV) {
- save->tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
- RADEON_TV_DAC_GDACPD);
- }
-#endif
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
- save->tv_pll_cntl = (NTSC_TV_PLL_M & RADEON_TV_M0LO_MASK) |
- (((NTSC_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
- ((NTSC_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
- (((NTSC_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
- ((NTSC_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
- else
- save->tv_pll_cntl = (PAL_TV_PLL_M & RADEON_TV_M0LO_MASK) |
- (((PAL_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
- ((PAL_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
- (((PAL_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
- ((PAL_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
-
- save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) |
- ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
- ((1 & RADEON_TVPDC_MASK)<< RADEON_TVPDC_SHIFT) |
- RADEON_TVCLK_SRC_SEL_TVPLL |
- RADEON_TVPLL_TEST_DIS);
-
- save->tv_upsamp_and_gain_cntl = RADEON_YUPSAMP_EN | RADEON_UVUPSAMP_EN;
-
- save->tv_uv_adr = 0xc8;
-
- save->tv_vdisp = constPtr->verResolution - 1;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- save->tv_ftotal = NTSC_TV_VFTOTAL;
- else
- save->tv_ftotal = PAL_TV_VFTOTAL;
-
- save->tv_vtotal = constPtr->verTotal - 1;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M) {
- hor_timing = hor_timing_NTSC;
- } else {
- hor_timing = hor_timing_PAL;
- }
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60) {
- vert_timing = vert_timing_NTSC;
- } else {
- vert_timing = vert_timing_PAL;
- }
-
- for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
- if ((save->h_code_timing[ i ] = hor_timing[ i ]) == 0)
- break;
- }
-
- for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
- if ((save->v_code_timing[ i ] = vert_timing[ i ]) == 0)
- break;
- }
-
- /*
- * This must be called AFTER loading timing tables as they are modified by this function
- */
- RADEONInitTVRestarts(output, save, mode);
-
- save->dac_cntl &= ~RADEON_DAC_TVO_EN;
-
- if (IS_R300_VARIANT)
- save->gpiopad_a = info->SavedReg->gpiopad_a & ~1;
-
- if (IsPrimary) {
- save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
- save->disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC
- | RADEON_DISP_TV_SOURCE_CRTC);
- if (info->ChipFamily >= CHIP_FAMILY_R200) {
- save->disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
- } else {
- save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
- }
- } else {
- save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
- save->disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
-
- if (info->ChipFamily >= CHIP_FAMILY_R200) {
- save->disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
- } else {
- save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
- }
- }
-}
-
-
-/* Set hw registers for a new h/v position & h size */
-void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode)
-{
- ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- Bool reloadTable;
- RADEONSavePtr restore = info->ModeReg;
-
- reloadTable = RADEONInitTVRestarts(output, restore, mode);
-
- RADEONRestoreTVRestarts(pScrn, restore);
-
- OUTREG(RADEON_TV_TIMING_CNTL, restore->tv_timing_cntl);
-
- if (reloadTable) {
- OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl
- | RADEON_TV_ASYNC_RST
- | RADEON_CRT_ASYNC_RST
- | RADEON_RESTART_PHASE_FIX);
-
- RADEONRestoreTVTimingTables(pScrn, restore);
-
- OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl);
- }
-}
-
-void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output)
-{
- const TVModeConstants *constPtr;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- /* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
-
- save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
- (((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
-
- save->crtc_h_sync_strt_wid = (save->crtc_h_sync_strt_wid
- & ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR)) |
- (((constPtr->horSyncStart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
- (constPtr->horSyncStart & 7);
-
- save->crtc_v_total_disp = ((constPtr->verResolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
- ((constPtr->verTotal - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
-
- save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) |
- ((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
-
-}
-
-void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output)
-{
- unsigned postDiv;
- const TVModeConstants *constPtr;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- /* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
-
- save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
-
- save->ppll_ref_div = constPtr->crtcPLL_M;
-
- switch (constPtr->crtcPLL_postDiv) {
- case 1:
- postDiv = 0;
- break;
- case 2:
- postDiv = 1;
- break;
- case 3:
- postDiv = 4;
- break;
- case 4:
- postDiv = 2;
- break;
- case 6:
- postDiv = 6;
- break;
- case 8:
- postDiv = 3;
- break;
- case 12:
- postDiv = 7;
- break;
- case 16:
- default:
- postDiv = 5;
- break;
- }
-
- save->ppll_div_3 = (constPtr->crtcPLL_N & 0x7ff) | (postDiv << 16);
-
- save->pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
- save->pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
-
-}
-
-void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output)
-{
- const TVModeConstants *constPtr;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- /* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
-
- save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
- (((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
-
- save->crtc2_h_sync_strt_wid = (save->crtc2_h_sync_strt_wid
- & ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR)) |
- (((constPtr->horSyncStart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
- (constPtr->horSyncStart & 7);
-
- save->crtc2_v_total_disp = ((constPtr->verResolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
- ((constPtr->verTotal - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
-
- save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) |
- ((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
-
-}
-
-void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
- DisplayModePtr mode, xf86OutputPtr output)
-{
- unsigned postDiv;
- const TVModeConstants *constPtr;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
- /* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
-
- save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
-
- save->p2pll_ref_div = constPtr->crtcPLL_M;
-
- switch (constPtr->crtcPLL_postDiv) {
- case 1:
- postDiv = 0;
- break;
- case 2:
- postDiv = 1;
- break;
- case 3:
- postDiv = 4;
- break;
- case 4:
- postDiv = 2;
- break;
- case 6:
- postDiv = 6;
- break;
- case 8:
- postDiv = 3;
- break;
- case 12:
- postDiv = 7;
- break;
- case 16:
- default:
- postDiv = 5;
- break;
- }
-
- save->p2pll_div_0 = (constPtr->crtcPLL_N & 0x7ff) | (postDiv << 16);
-
- save->pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
- save->pixclks_cntl |= (RADEON_PIX2CLK_SRC_SEL_P2PLLCLK
- | RADEON_PIXCLK_TV_SRC_SEL);
-
-}
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
deleted file mode 100644
index c4b7838..0000000
--- a/src/radeon_tv.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Integrated TV out support based on the GATOS code by
- * Federico Ulivi <fulivi at lycos.com>
- */
-
-
-/*
- * Limits of h/v positions (hPos & vPos)
- */
-#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
-#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
-
-/*
- * Unit for hPos (in TV clock periods)
- */
-#define H_POS_UNIT 10
-
-/*
- * Indexes in h. code timing table for horizontal line position adjustment
- */
-#define H_TABLE_POS1 6
-#define H_TABLE_POS2 8
-
-/*
- * Limits of hor. size (hSize)
- */
-#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
-
-/* tv standard constants */
-#define NTSC_TV_PLL_M 22
-#define NTSC_TV_PLL_N 175
-#define NTSC_TV_PLL_P 5
-#define NTSC_TV_CLOCK_T 233
-#define NTSC_TV_VFTOTAL 1
-#define NTSC_TV_LINES_PER_FRAME 525
-#define NTSC_TV_ZERO_H_SIZE 479166
-#define NTSC_TV_H_SIZE_UNIT 9478
-
-#define PAL_TV_PLL_M 113
-#define PAL_TV_PLL_N 668
-#define PAL_TV_PLL_P 3
-#define PAL_TV_CLOCK_T 188
-#define PAL_TV_VFTOTAL 3
-#define PAL_TV_LINES_PER_FRAME 625
-#define PAL_TV_ZERO_H_SIZE 473200
-#define PAL_TV_H_SIZE_UNIT 9360
-
-
-#define VERT_LEAD_IN_LINES 2
-#define FRAC_BITS 0xe
-#define FRAC_MASK 0x3fff
diff --git a/src/radeon_version.h b/src/radeon_version.h
deleted file mode 100644
index ccc1367..0000000
--- a/src/radeon_version.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2000 through 2004 by Marc Aurele La France (TSI @ UQV), tsi at xfree86.org
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that copyright
- * notice and this permission notice appear in supporting documentation, and
- * that the name of Marc Aurele La France not be used in advertising or
- * publicity pertaining to distribution of the software without specific,
- * written prior permission. Marc Aurele La France makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as-is" without express or implied warranty.
- *
- * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _RADEON_VERSION_H_
-#define _RADEON_VERSION_H_ 1
-
-#undef RADEON_NAME
-#undef RADEON_DRIVER_NAME
-#undef R200_DRIVER_NAME
-#undef RADEON_VERSION_MAJOR
-#undef RADEON_VERSION_MINOR
-#undef RADEON_VERSION_PATCH
-#undef RADEON_VERSION_CURRENT
-#undef RADEON_VERSION_EVALUATE
-#undef RADEON_VERSION_STRINGIFY
-#undef RADEON_VERSION_NAME
-
-#define RADEON_NAME "RADEON"
-#define RADEON_DRIVER_NAME "radeon"
-#define R200_DRIVER_NAME "r200"
-#define R300_DRIVER_NAME "r300"
-
-#define RADEON_VERSION_MAJOR 4
-#define RADEON_VERSION_MAJOR_TILED 5
-#define RADEON_VERSION_MINOR 3
-#define RADEON_VERSION_PATCH 0
-
-#ifndef RADEON_VERSION_EXTRA
-#define RADEON_VERSION_EXTRA ""
-#endif
-
-#define RADEON_VERSION_CURRENT \
- ((RADEON_VERSION_MAJOR << 20) | \
- (RADEON_VERSION_MINOR << 10) | \
- (RADEON_VERSION_PATCH))
-
-#define RADEON_VERSION_EVALUATE(__x) #__x
-#define RADEON_VERSION_STRINGIFY(_x) RADEON_VERSION_EVALUATE(_x)
-#define RADEON_VERSION_NAME \
- RADEON_VERSION_STRINGIFY(RADEON_VERSION_MAJOR) "." \
- RADEON_VERSION_STRINGIFY(RADEON_VERSION_MINOR) "." \
- RADEON_VERSION_STRINGIFY(RADEON_VERSION_PATCH) RADEON_VERSION_EXTRA
-
-#endif /* _RADEON_VERSION_H_ */
diff --git a/src/radeon_video.c b/src/radeon_video.c
deleted file mode 100644
index 7502e1e..0000000
--- a/src/radeon_video.c
+++ /dev/null
@@ -1,3985 +0,0 @@
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-#include <math.h>
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include "radeon_video.h"
-
-#include "xf86.h"
-#include "dixstruct.h"
-#include "atipciids.h"
-#include "xf86fbman.h"
-
-#include <X11/extensions/Xv.h>
-#include "fourcc.h"
-
-#include "theatre_detect.h"
-#include "theatre_reg.h"
-#include "fi1236.h"
-#include "msp3430.h"
-#include "tda9885.h"
-
-#define OFF_DELAY 250 /* milliseconds */
-#define FREE_DELAY 15000
-
-#define OFF_TIMER 0x01
-#define FREE_TIMER 0x02
-#define CLIENT_VIDEO_ON 0x04
-
-#define TIMER_MASK (OFF_TIMER | FREE_TIMER)
-
-/* capture config constants */
-#define BUF_TYPE_FIELD 0
-#define BUF_TYPE_ALTERNATING 1
-#define BUF_TYPE_FRAME 2
-
-
-#define BUF_MODE_SINGLE 0
-#define BUF_MODE_DOUBLE 1
-#define BUF_MODE_TRIPLE 2
-/* CAP0_CONFIG values */
-
-#define FORMAT_BROOKTREE 0
-#define FORMAT_CCIR656 1
-#define FORMAT_ZV 2
-#define FORMAT_VIP16 3
-#define FORMAT_TRANSPORT 4
-
-#define ENABLE_RADEON_CAPTURE_WEAVE (RADEON_CAP0_CONFIG_CONTINUOS \
- | (BUF_MODE_DOUBLE <<7) \
- | (BUF_TYPE_FRAME << 4) \
- | ( (pPriv->theatre !=NULL)?(FORMAT_CCIR656<<23):(FORMAT_BROOKTREE<<23)) \
- | RADEON_CAP0_CONFIG_HORZ_DECIMATOR \
- | (pPriv->capture_vbi_data ? RADEON_CAP0_CONFIG_VBI_EN : 0) \
- | RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422)
-
-#define ENABLE_RADEON_CAPTURE_BOB (RADEON_CAP0_CONFIG_CONTINUOS \
- | (BUF_MODE_SINGLE <<7) \
- | (BUF_TYPE_ALTERNATING << 4) \
- | ( (pPriv->theatre !=NULL)?(FORMAT_CCIR656<<23):(FORMAT_BROOKTREE<<23)) \
- | RADEON_CAP0_CONFIG_HORZ_DECIMATOR \
- | (pPriv->capture_vbi_data ? RADEON_CAP0_CONFIG_VBI_EN : 0) \
- | RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422)
-
-
-static void RADEONInitOffscreenImages(ScreenPtr);
-
-static XF86VideoAdaptorPtr RADEONSetupImageVideo(ScreenPtr);
-static int RADEONPutImage(ScrnInfoPtr, short, short, short, short, short,
- short, short, short, int, unsigned char*, short,
- short, Bool, RegionPtr, pointer,
- DrawablePtr);
-static void RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now);
-static int RADEONPutVideo(ScrnInfoPtr pScrn, short src_x, short src_y, short drw_x, short drw_y,
- short src_w, short src_h, short drw_w, short drw_h,
- RegionPtr clipBoxes, pointer data, DrawablePtr pDraw);
-
-static void RADEON_board_setmisc(RADEONPortPrivPtr pPriv);
-static void RADEON_RT_SetEncoding(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
-static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv);
-static void RADEON_TDA9885_SetEncoding(RADEONPortPrivPtr pPriv);
-static void RADEON_FI1236_SetEncoding(RADEONPortPrivPtr pPriv);
-
-
-
-#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v))
-
-static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer;
-static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity;
-static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults;
-static Atom xvGamma, xvColorspace;
-static Atom xvCRTC;
-static Atom xvEncoding, xvFrequency, xvVolume, xvMute,
- xvDecBrightness, xvDecContrast, xvDecHue, xvDecColor, xvDecSaturation,
- xvTunerStatus, xvSAP, xvOverlayDeinterlacingMethod,
- xvLocationID, xvDeviceID, xvInstanceID, xvDumpStatus,
- xvAdjustment;
-
-static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode;
-
-
-#define GET_PORT_PRIVATE(pScrn) \
- (RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr)
-
-#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER
-static void
-radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b)
-{
- dest->x1 = a->x1 > b->x1 ? a->x1 : b->x1;
- dest->x2 = a->x2 < b->x2 ? a->x2 : b->x2;
- dest->y1 = a->y1 > b->y1 ? a->y1 : b->y1;
- dest->y2 = a->y2 < b->y2 ? a->y2 : b->y2;
-
- if (dest->x1 >= dest->x2 || dest->y1 >= dest->y2)
- dest->x1 = dest->x2 = dest->y1 = dest->y2 = 0;
-}
-
-static void
-radeon_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box)
-{
- if (crtc->enabled) {
- crtc_box->x1 = crtc->x;
- crtc_box->x2 = crtc->x + xf86ModeWidth(&crtc->mode, crtc->rotation);
- crtc_box->y1 = crtc->y;
- crtc_box->y2 = crtc->y + xf86ModeHeight(&crtc->mode, crtc->rotation);
- } else
- crtc_box->x1 = crtc_box->x2 = crtc_box->y1 = crtc_box->y2 = 0;
-}
-
-static int
-radeon_box_area(BoxPtr box)
-{
- return (int) (box->x2 - box->x1) * (int) (box->y2 - box->y1);
-}
-
-static xf86CrtcPtr
-radeon_covering_crtc(ScrnInfoPtr pScrn,
- BoxPtr box,
- xf86CrtcPtr desired,
- BoxPtr crtc_box_ret)
-{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- xf86CrtcPtr crtc, best_crtc;
- int coverage, best_coverage;
- int c;
- BoxRec crtc_box, cover_box;
-
- best_crtc = NULL;
- best_coverage = 0;
- crtc_box_ret->x1 = 0;
- crtc_box_ret->x2 = 0;
- crtc_box_ret->y1 = 0;
- crtc_box_ret->y2 = 0;
- for (c = 0; c < xf86_config->num_crtc; c++) {
- crtc = xf86_config->crtc[c];
- radeon_crtc_box(crtc, &crtc_box);
- radeon_box_intersect(&cover_box, &crtc_box, box);
- coverage = radeon_box_area(&cover_box);
- if (coverage && crtc == desired) {
- *crtc_box_ret = crtc_box;
- return crtc;
- } else if (coverage > best_coverage) {
- *crtc_box_ret = crtc_box;
- best_crtc = crtc;
- best_coverage = coverage;
- }
- }
- return best_crtc;
-}
-
-static Bool
-radeon_crtc_clip_video_helper(ScrnInfoPtr pScrn,
- xf86CrtcPtr *crtc_ret,
- xf86CrtcPtr desired_crtc,
- BoxPtr dst,
- INT32 *xa,
- INT32 *xb,
- INT32 *ya,
- INT32 *yb,
- RegionPtr reg,
- INT32 width,
- INT32 height)
-{
- Bool ret;
- RegionRec crtc_region_local;
- RegionPtr crtc_region = reg;
-
- /*
- * For overlay video, compute the relevant CRTC and
- * clip video to that
- */
- if (crtc_ret) {
- BoxRec crtc_box;
- xf86CrtcPtr crtc = radeon_covering_crtc(pScrn, dst,
- desired_crtc,
- &crtc_box);
-
- if (crtc) {
- REGION_INIT (pScreen, &crtc_region_local, &crtc_box, 1);
- crtc_region = &crtc_region_local;
- REGION_INTERSECT (pScreen, crtc_region, crtc_region, reg);
- }
- *crtc_ret = crtc;
- }
-
- ret = xf86XVClipVideoHelper(dst, xa, xb, ya, yb,
- crtc_region, width, height);
-
- if (crtc_region != reg)
- REGION_UNINIT (pScreen, &crtc_region_local);
-
- return ret;
-}
-#endif
-
-static Bool
-radeon_crtc_clip_video(ScrnInfoPtr pScrn,
- xf86CrtcPtr *crtc_ret,
- xf86CrtcPtr desired_crtc,
- BoxPtr dst,
- INT32 *xa,
- INT32 *xb,
- INT32 *ya,
- INT32 *yb,
- RegionPtr reg,
- INT32 width,
- INT32 height)
-{
-#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER
- return radeon_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc,
- dst, xa, xb, ya, yb,
- reg, width, height);
-#else
- return xf86_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc,
- dst, xa, xb, ya, yb,
- reg, width, height);
-#endif
-}
-
-#ifdef USE_EXA
-static void
-ATIVideoSave(ScreenPtr pScreen, ExaOffscreenArea *area)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
-
- if (pPriv->video_memory == area)
- pPriv->video_memory = NULL;
-}
-#endif /* USE_EXA */
-
-void RADEONInitVideo(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL;
- XF86VideoAdaptorPtr overlayAdaptor = NULL, texturedAdaptor = NULL;
- int num_adaptors;
-
-
- num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors);
- newAdaptors = xalloc((num_adaptors + 2) * sizeof(XF86VideoAdaptorPtr *));
- if (newAdaptors == NULL)
- return;
-
- memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr));
- adaptors = newAdaptors;
-
- if (!IS_AVIVO_VARIANT) {
- overlayAdaptor = RADEONSetupImageVideo(pScreen);
- if (overlayAdaptor != NULL) {
- adaptors[num_adaptors++] = overlayAdaptor;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up overlay video\n");
- } else
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up overlay video\n");
- RADEONInitOffscreenImages(pScreen);
- }
-
- if (info->ChipFamily != CHIP_FAMILY_RS400) {
- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
- if (texturedAdaptor != NULL) {
- adaptors[num_adaptors++] = texturedAdaptor;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
- } else
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
- }
-
- if(num_adaptors)
- xf86XVScreenInit(pScreen, adaptors, num_adaptors);
-
- if(newAdaptors)
- xfree(newAdaptors);
-
-}
-
-/* client libraries expect an encoding */
-static XF86VideoEncodingRec DummyEncoding =
-{
- 0,
- "XV_IMAGE",
- 2048, 2048,
- {1, 1}
-};
-
- /* the picture is interlaced - hence the half-heights */
-
-static XF86VideoEncodingRec
-InputVideoEncodings[] =
-{
- { 0, "XV_IMAGE", 2048,2048,{1,1}},
- { 1, "pal-composite", 720, 288, { 1, 50 }},
- { 2, "pal-tuner", 720, 288, { 1, 50 }},
- { 3, "pal-svideo", 720, 288, { 1, 50 }},
- { 4, "ntsc-composite", 640, 240, { 1001, 60000 }},
- { 5, "ntsc-tuner", 640, 240, { 1001, 60000 }},
- { 6, "ntsc-svideo", 640, 240, { 1001, 60000 }},
- { 7, "secam-composite", 720, 288, { 1, 50 }},
- { 8, "secam-tuner", 720, 288, { 1, 50 }},
- { 9, "secam-svideo", 720, 288, { 1, 50 }},
- { 10,"pal_60-composite", 768, 288, { 1, 50 }},
- { 11,"pal_60-tuner", 768, 288, { 1, 50 }},
- { 12,"pal_60-svideo", 768, 288, { 1, 50 }}
-};
-
-
-#define NUM_FORMATS 12
-
-static XF86VideoFormatRec Formats[NUM_FORMATS] =
-{
- {8, TrueColor}, {8, DirectColor}, {8, PseudoColor},
- {8, GrayScale}, {8, StaticGray}, {8, StaticColor},
- {15, TrueColor}, {16, TrueColor}, {24, TrueColor},
- {15, DirectColor}, {16, DirectColor}, {24, DirectColor}
-};
-
-
-#if 0
-#define NUM_ATTRIBUTES 9+6
-
-static XF86AttributeRec Attributes[NUM_ATTRIBUTES] =
-{
- {XvSettable , 0, 1, "XV_SET_DEFAULTS"},
- {XvSettable | XvGettable, 0, 1, "XV_AUTOPAINT_COLORKEY"},
- {XvSettable | XvGettable, 0, ~0, "XV_COLORKEY"},
- {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"},
- {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
- {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
- {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
- {XvSettable | XvGettable, -1000, 1000, "XV_COLOR"},
- {XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
- {XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"},
- {XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"},
- {XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"},
- {XvSettable | XvGettable, -1, 1, "XV_CRTC"},
- {XvSettable | XvGettable, 100, 10000, "XV_GAMMA"},
- {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
-};
-
-#endif
-
-#define NUM_ATTRIBUTES 22
-#define NUM_DEC_ATTRIBUTES (NUM_ATTRIBUTES+12)
-
-static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] =
-{
- { XvGettable, 0, ~0, "XV_DEVICE_ID"},
- { XvGettable, 0, ~0, "XV_LOCATION_ID"},
- { XvGettable, 0, ~0, "XV_INSTANCE_ID"},
- {XvSettable , 0, 1, "XV_DUMP_STATUS"},
- {XvSettable , 0, 1, "XV_SET_DEFAULTS"},
- {XvSettable | XvGettable, 0, 1, "XV_AUTOPAINT_COLORKEY"},
- {XvSettable | XvGettable, 0, ~0,"XV_COLORKEY"},
- {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"},
- {XvSettable | XvGettable, 0, 255, "XV_OVERLAY_ALPHA"},
- {XvSettable | XvGettable, 0, 255, "XV_GRAPHICS_ALPHA"},
- {XvSettable | XvGettable, 0, 1, "XV_ALPHA_MODE"},
- {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"},
- {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"},
- {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"},
- {XvSettable | XvGettable, -1000, 1000, "XV_COLOR"},
- {XvSettable | XvGettable, -1000, 1000, "XV_HUE"},
- {XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"},
- {XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"},
- {XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"},
- {XvSettable | XvGettable, -1, 1, "XV_CRTC"},
- {XvSettable | XvGettable, 100, 10000, "XV_GAMMA"},
- {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"},
-
- {XvSettable | XvGettable, -1000, 1000, "XV_DEC_BRIGHTNESS"},
- {XvSettable | XvGettable, -1000, 1000, "XV_DEC_CONTRAST"},
- {XvSettable | XvGettable, -1000, 1000, "XV_DEC_SATURATION"},
- {XvSettable | XvGettable, -1000, 1000, "XV_DEC_HUE"},
- {XvSettable | XvGettable, 0, 2, "XV_OVERLAY_DEINTERLACING_METHOD"},
- {XvSettable | XvGettable, 0, 12, "XV_ENCODING"},
- {XvSettable | XvGettable, 0, -1, "XV_FREQ"},
- { XvGettable, -1000, 1000, "XV_TUNER_STATUS"},
- {XvSettable | XvGettable, -1000, 1000, "XV_VOLUME"},
- {XvSettable | XvGettable, 0, 1, "XV_MUTE"},
- {XvSettable | XvGettable, 0, 1, "XV_SAP"},
- {XvSettable | XvGettable, 0, 0x1F, "XV_DEBUG_ADJUSTMENT"},
- { 0, 0, 0, NULL} /* just a place holder so I don't have to be fancy with commas */
-};
-
-
-#define INCLUDE_RGB_FORMATS 1
-
-#if INCLUDE_RGB_FORMATS
-
-#define NUM_IMAGES 8
-
-/* Note: GUIDs are bogus... - but nothing uses them anyway */
-
-#define FOURCC_RGBA32 0x41424752
-
-#define XVIMAGE_RGBA32(byte_order) \
- { \
- FOURCC_RGBA32, \
- XvRGB, \
- byte_order, \
- { 'R', 'G', 'B', 'A', \
- 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
- 32, \
- XvPacked, \
- 1, \
- 32, 0x00FF0000, 0x0000FF00, 0x000000FF, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- {'A', 'R', 'G', 'B', \
- 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \
- XvTopToBottom \
- }
-
-#define FOURCC_RGB24 0x00000000
-
-#define XVIMAGE_RGB24 \
- { \
- FOURCC_RGB24, \
- XvRGB, \
- LSBFirst, \
- { 'R', 'G', 'B', 0, \
- 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
- 24, \
- XvPacked, \
- 1, \
- 24, 0x00FF0000, 0x0000FF00, 0x000000FF, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- { 'R', 'G', 'B', \
- 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \
- XvTopToBottom \
- }
-
-#define FOURCC_RGBT16 0x54424752
-
-#define XVIMAGE_RGBT16(byte_order) \
- { \
- FOURCC_RGBT16, \
- XvRGB, \
- byte_order, \
- { 'R', 'G', 'B', 'T', \
- 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
- 16, \
- XvPacked, \
- 1, \
- 16, 0x00007C00, 0x000003E0, 0x0000001F, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- {'A', 'R', 'G', 'B', \
- 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \
- XvTopToBottom \
- }
-
-#define FOURCC_RGB16 0x32424752
-
-#define XVIMAGE_RGB16(byte_order) \
- { \
- FOURCC_RGB16, \
- XvRGB, \
- byte_order, \
- { 'R', 'G', 'B', 0x00, \
- 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
- 16, \
- XvPacked, \
- 1, \
- 16, 0x0000F800, 0x000007E0, 0x0000001F, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- {'R', 'G', 'B', \
- 0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \
- XvTopToBottom \
- }
-
-static XF86ImageRec Images[NUM_IMAGES] =
-{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- XVIMAGE_RGBA32(MSBFirst),
- XVIMAGE_RGBT16(MSBFirst),
- XVIMAGE_RGB16(MSBFirst),
-#else
- XVIMAGE_RGBA32(LSBFirst),
- XVIMAGE_RGBT16(LSBFirst),
- XVIMAGE_RGB16(LSBFirst),
-#endif
- XVIMAGE_RGB24,
- XVIMAGE_YUY2,
- XVIMAGE_UYVY,
- XVIMAGE_YV12,
- XVIMAGE_I420
-};
-
-#else
-
-#define NUM_IMAGES 4
-
-static XF86ImageRec Images[NUM_IMAGES] =
-{
- XVIMAGE_YUY2,
- XVIMAGE_UYVY,
- XVIMAGE_YV12,
- XVIMAGE_I420
-};
-
-#endif
-
-/* Reference color space transform data */
-typedef struct tagREF_TRANSFORM
-{
- float RefLuma;
- float RefRCb;
- float RefRCr;
- float RefGCb;
- float RefGCr;
- float RefBCb;
- float RefBCr;
-} REF_TRANSFORM;
-
-/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */
-static REF_TRANSFORM trans[2] =
-{
- {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */
- {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */
-};
-
-
-/* Gamma curve definition for preset gammas */
-typedef struct tagGAMMA_CURVE_R100
-{
- CARD32 GAMMA_0_F_SLOPE;
- CARD32 GAMMA_0_F_OFFSET;
- CARD32 GAMMA_10_1F_SLOPE;
- CARD32 GAMMA_10_1F_OFFSET;
- CARD32 GAMMA_20_3F_SLOPE;
- CARD32 GAMMA_20_3F_OFFSET;
- CARD32 GAMMA_40_7F_SLOPE;
- CARD32 GAMMA_40_7F_OFFSET;
- CARD32 GAMMA_380_3BF_SLOPE;
- CARD32 GAMMA_380_3BF_OFFSET;
- CARD32 GAMMA_3C0_3FF_SLOPE;
- CARD32 GAMMA_3C0_3FF_OFFSET;
- float OvGammaCont;
-} GAMMA_CURVE_R100;
-
-typedef struct tagGAMMA_CURVE_R200
-{
- CARD32 GAMMA_0_F_SLOPE;
- CARD32 GAMMA_0_F_OFFSET;
- CARD32 GAMMA_10_1F_SLOPE;
- CARD32 GAMMA_10_1F_OFFSET;
- CARD32 GAMMA_20_3F_SLOPE;
- CARD32 GAMMA_20_3F_OFFSET;
- CARD32 GAMMA_40_7F_SLOPE;
- CARD32 GAMMA_40_7F_OFFSET;
- CARD32 GAMMA_80_BF_SLOPE;
- CARD32 GAMMA_80_BF_OFFSET;
- CARD32 GAMMA_C0_FF_SLOPE;
- CARD32 GAMMA_C0_FF_OFFSET;
- CARD32 GAMMA_100_13F_SLOPE;
- CARD32 GAMMA_100_13F_OFFSET;
- CARD32 GAMMA_140_17F_SLOPE;
- CARD32 GAMMA_140_17F_OFFSET;
- CARD32 GAMMA_180_1BF_SLOPE;
- CARD32 GAMMA_180_1BF_OFFSET;
- CARD32 GAMMA_1C0_1FF_SLOPE;
- CARD32 GAMMA_1C0_1FF_OFFSET;
- CARD32 GAMMA_200_23F_SLOPE;
- CARD32 GAMMA_200_23F_OFFSET;
- CARD32 GAMMA_240_27F_SLOPE;
- CARD32 GAMMA_240_27F_OFFSET;
- CARD32 GAMMA_280_2BF_SLOPE;
- CARD32 GAMMA_280_2BF_OFFSET;
- CARD32 GAMMA_2C0_2FF_SLOPE;
- CARD32 GAMMA_2C0_2FF_OFFSET;
- CARD32 GAMMA_300_33F_SLOPE;
- CARD32 GAMMA_300_33F_OFFSET;
- CARD32 GAMMA_340_37F_SLOPE;
- CARD32 GAMMA_340_37F_OFFSET;
- CARD32 GAMMA_380_3BF_SLOPE;
- CARD32 GAMMA_380_3BF_OFFSET;
- CARD32 GAMMA_3C0_3FF_SLOPE;
- CARD32 GAMMA_3C0_3FF_OFFSET;
- float OvGammaCont;
-} GAMMA_CURVE_R200;
-
-
-/* Preset gammas */
-static GAMMA_CURVE_R100 gamma_curve_r100[8] =
-{
- /* Gamma 1.0 */
- {0x100, 0x0,
- 0x100, 0x20,
- 0x100, 0x40,
- 0x100, 0x80,
- 0x100, 0x100,
- 0x100, 0x100,
- 1.0},
- /* Gamma 0.85 */
- {0x75, 0x0,
- 0xA2, 0xF,
- 0xAC, 0x23,
- 0xC6, 0x4E,
- 0x129, 0xD6,
- 0x12B, 0xD5,
- 1.0},
- /* Gamma 1.1 */
- {0x180, 0x0,
- 0x13C, 0x30,
- 0x13C, 0x57,
- 0x123, 0xA5,
- 0xEA, 0x116,
- 0xEA, 0x116,
- 0.9913},
- /* Gamma 1.2 */
- {0x21B, 0x0,
- 0x16D, 0x43,
- 0x172, 0x71,
- 0x13D, 0xCD,
- 0xD9, 0x128,
- 0xD6, 0x12A,
- 0.9827},
- /* Gamma 1.45 */
- {0x404, 0x0,
- 0x1B9, 0x81,
- 0x1EE, 0xB8,
- 0x16A, 0x133,
- 0xB7, 0x14B,
- 0xB2, 0x14E,
- 0.9567},
- /* Gamma 1.7 */
- {0x658, 0x0,
- 0x1B5, 0xCB,
- 0x25F, 0x102,
- 0x181, 0x199,
- 0x9C, 0x165,
- 0x98, 0x167,
- 0.9394},
- /* Gamma 2.2 */
- {0x7FF, 0x0,
- 0x625, 0x100,
- 0x1E4, 0x1C4,
- 0x1BD, 0x23D,
- 0x79, 0x187,
- 0x76, 0x188,
- 0.9135},
- /* Gamma 2.5 */
- {0x7FF, 0x0,
- 0x7FF, 0x100,
- 0x2AD, 0x200,
- 0x1A2, 0x2AB,
- 0x6E, 0x194,
- 0x67, 0x197,
- 0.9135}
-};
-
-static GAMMA_CURVE_R200 gamma_curve_r200[8] =
- {
- /* Gamma 1.0 */
- {0x00000040, 0x00000000,
- 0x00000040, 0x00000020,
- 0x00000080, 0x00000040,
- 0x00000100, 0x00000080,
- 0x00000100, 0x00000100,
- 0x00000100, 0x00000100,
- 0x00000100, 0x00000200,
- 0x00000100, 0x00000200,
- 0x00000100, 0x00000300,
- 0x00000100, 0x00000300,
- 0x00000100, 0x00000400,
- 0x00000100, 0x00000400,
- 0x00000100, 0x00000500,
- 0x00000100, 0x00000500,
- 0x00000100, 0x00000600,
- 0x00000100, 0x00000600,
- 0x00000100, 0x00000700,
- 0x00000100, 0x00000700,
- 1.0},
- /* Gamma 0.85 */
- {0x0000001D, 0x00000000,
- 0x00000028, 0x0000000F,
- 0x00000056, 0x00000023,
- 0x000000C5, 0x0000004E,
- 0x000000DA, 0x000000B0,
- 0x000000E6, 0x000000AA,
- 0x000000F1, 0x00000190,
- 0x000000F9, 0x0000018C,
- 0x00000101, 0x00000286,
- 0x00000108, 0x00000282,
- 0x0000010D, 0x0000038A,
- 0x00000113, 0x00000387,
- 0x00000118, 0x0000049A,
- 0x0000011C, 0x00000498,
- 0x00000120, 0x000005B4,
- 0x00000124, 0x000005B2,
- 0x00000128, 0x000006D6,
- 0x0000012C, 0x000006D5,
- 1.0},
- /* Gamma 1.1 */
- {0x00000060, 0x00000000,
- 0x0000004F, 0x00000030,
- 0x0000009C, 0x00000057,
- 0x00000121, 0x000000A5,
- 0x00000113, 0x00000136,
- 0x0000010B, 0x0000013A,
- 0x00000105, 0x00000245,
- 0x00000100, 0x00000247,
- 0x000000FD, 0x00000348,
- 0x000000F9, 0x00000349,
- 0x000000F6, 0x00000443,
- 0x000000F4, 0x00000444,
- 0x000000F2, 0x00000538,
- 0x000000F0, 0x00000539,
- 0x000000EE, 0x00000629,
- 0x000000EC, 0x00000629,
- 0x000000EB, 0x00000716,
- 0x000000E9, 0x00000717,
- 0.9913},
- /* Gamma 1.2 */
- {0x00000087, 0x00000000,
- 0x0000005B, 0x00000043,
- 0x000000B7, 0x00000071,
- 0x0000013D, 0x000000CD,
- 0x00000121, 0x0000016B,
- 0x00000113, 0x00000172,
- 0x00000107, 0x00000286,
- 0x000000FF, 0x0000028A,
- 0x000000F8, 0x00000389,
- 0x000000F2, 0x0000038B,
- 0x000000ED, 0x0000047D,
- 0x000000E9, 0x00000480,
- 0x000000E5, 0x00000568,
- 0x000000E1, 0x0000056A,
- 0x000000DE, 0x0000064B,
- 0x000000DB, 0x0000064D,
- 0x000000D9, 0x00000728,
- 0x000000D6, 0x00000729,
- 0.9827},
- /* Gamma 1.45 */
- {0x00000101, 0x00000000,
- 0x0000006E, 0x00000081,
- 0x000000F7, 0x000000B8,
- 0x0000016E, 0x00000133,
- 0x00000139, 0x000001EA,
- 0x0000011B, 0x000001F9,
- 0x00000105, 0x00000314,
- 0x000000F6, 0x0000031C,
- 0x000000E9, 0x00000411,
- 0x000000DF, 0x00000417,
- 0x000000D7, 0x000004F6,
- 0x000000CF, 0x000004F9,
- 0x000000C9, 0x000005C9,
- 0x000000C4, 0x000005CC,
- 0x000000BF, 0x0000068F,
- 0x000000BA, 0x00000691,
- 0x000000B6, 0x0000074B,
- 0x000000B2, 0x0000074D,
- 0.9567},
- /* Gamma 1.7 */
- {0x00000196, 0x00000000,
- 0x0000006D, 0x000000CB,
- 0x0000012F, 0x00000102,
- 0x00000187, 0x00000199,
- 0x00000144, 0x0000025b,
- 0x00000118, 0x00000273,
- 0x000000FE, 0x0000038B,
- 0x000000E9, 0x00000395,
- 0x000000DA, 0x0000047E,
- 0x000000CE, 0x00000485,
- 0x000000C3, 0x00000552,
- 0x000000BB, 0x00000556,
- 0x000000B3, 0x00000611,
- 0x000000AC, 0x00000614,
- 0x000000A7, 0x000006C1,
- 0x000000A1, 0x000006C3,
- 0x0000009D, 0x00000765,
- 0x00000098, 0x00000767,
- 0.9394},
- /* Gamma 2.2 */
- {0x000001FF, 0x00000000,
- 0x0000018A, 0x00000100,
- 0x000000F1, 0x000001C5,
- 0x000001D6, 0x0000023D,
- 0x00000124, 0x00000328,
- 0x00000116, 0x0000032F,
- 0x000000E2, 0x00000446,
- 0x000000D3, 0x0000044D,
- 0x000000BC, 0x00000520,
- 0x000000B0, 0x00000526,
- 0x000000A4, 0x000005D6,
- 0x0000009B, 0x000005DB,
- 0x00000092, 0x00000676,
- 0x0000008B, 0x00000679,
- 0x00000085, 0x00000704,
- 0x00000080, 0x00000707,
- 0x0000007B, 0x00000787,
- 0x00000076, 0x00000789,
- 0.9135},
- /* Gamma 2.5 */
- {0x000001FF, 0x00000000,
- 0x000001FF, 0x00000100,
- 0x00000159, 0x000001FF,
- 0x000001AC, 0x000002AB,
- 0x0000012F, 0x00000381,
- 0x00000101, 0x00000399,
- 0x000000D9, 0x0000049A,
- 0x000000C3, 0x000004A5,
- 0x000000AF, 0x00000567,
- 0x000000A1, 0x0000056E,
- 0x00000095, 0x00000610,
- 0x0000008C, 0x00000614,
- 0x00000084, 0x000006A0,
- 0x0000007D, 0x000006A4,
- 0x00000077, 0x00000721,
- 0x00000071, 0x00000723,
- 0x0000006D, 0x00000795,
- 0x00000068, 0x00000797,
- 0.9135}
-};
-
-static void
-RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 gamma)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 ov0_scale_cntl;
-
- /* Set gamma */
- RADEONWaitForIdleMMIO(pScrn);
- ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK;
- OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 0x00000005));
-
- /* Load gamma curve adjustments */
- if (info->ChipFamily >= CHIP_FAMILY_R200) {
- OUTREG(RADEON_OV0_GAMMA_000_00F,
- (gamma_curve_r200[gamma].GAMMA_0_F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_0_F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_010_01F,
- (gamma_curve_r200[gamma].GAMMA_10_1F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_10_1F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_020_03F,
- (gamma_curve_r200[gamma].GAMMA_20_3F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_20_3F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_040_07F,
- (gamma_curve_r200[gamma].GAMMA_40_7F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_40_7F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_080_0BF,
- (gamma_curve_r200[gamma].GAMMA_80_BF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_80_BF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_0C0_0FF,
- (gamma_curve_r200[gamma].GAMMA_C0_FF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_C0_FF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_100_13F,
- (gamma_curve_r200[gamma].GAMMA_100_13F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_100_13F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_140_17F,
- (gamma_curve_r200[gamma].GAMMA_140_17F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_140_17F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_180_1BF,
- (gamma_curve_r200[gamma].GAMMA_180_1BF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_180_1BF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_1C0_1FF,
- (gamma_curve_r200[gamma].GAMMA_1C0_1FF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_1C0_1FF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_200_23F,
- (gamma_curve_r200[gamma].GAMMA_200_23F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_200_23F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_240_27F,
- (gamma_curve_r200[gamma].GAMMA_240_27F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_240_27F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_280_2BF,
- (gamma_curve_r200[gamma].GAMMA_280_2BF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_280_2BF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_2C0_2FF,
- (gamma_curve_r200[gamma].GAMMA_2C0_2FF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_2C0_2FF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_300_33F,
- (gamma_curve_r200[gamma].GAMMA_300_33F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_300_33F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_340_37F,
- (gamma_curve_r200[gamma].GAMMA_340_37F_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_340_37F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_380_3BF,
- (gamma_curve_r200[gamma].GAMMA_380_3BF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_380_3BF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_3C0_3FF,
- (gamma_curve_r200[gamma].GAMMA_3C0_3FF_OFFSET << 0x00000000) |
- (gamma_curve_r200[gamma].GAMMA_3C0_3FF_SLOPE << 0x00000010));
- } else {
- OUTREG(RADEON_OV0_GAMMA_000_00F,
- (gamma_curve_r100[gamma].GAMMA_0_F_OFFSET << 0x00000000) |
- (gamma_curve_r100[gamma].GAMMA_0_F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_010_01F,
- (gamma_curve_r100[gamma].GAMMA_10_1F_OFFSET << 0x00000000) |
- (gamma_curve_r100[gamma].GAMMA_10_1F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_020_03F,
- (gamma_curve_r100[gamma].GAMMA_20_3F_OFFSET << 0x00000000) |
- (gamma_curve_r100[gamma].GAMMA_20_3F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_040_07F,
- (gamma_curve_r100[gamma].GAMMA_40_7F_OFFSET << 0x00000000) |
- (gamma_curve_r100[gamma].GAMMA_40_7F_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_380_3BF,
- (gamma_curve_r100[gamma].GAMMA_380_3BF_OFFSET << 0x00000000) |
- (gamma_curve_r100[gamma].GAMMA_380_3BF_SLOPE << 0x00000010));
- OUTREG(RADEON_OV0_GAMMA_3C0_3FF,
- (gamma_curve_r100[gamma].GAMMA_3C0_3FF_OFFSET << 0x00000000) |
- (gamma_curve_r100[gamma].GAMMA_3C0_3FF_SLOPE << 0x00000010));
- }
-
-}
-
-
-/****************************************************************************
- * SetTransform *
- * Function: Calculates and sets color space transform from supplied *
- * reference transform, gamma, brightness, contrast, hue and *
- * saturation. *
- * Inputs: bright - brightness *
- * cont - contrast *
- * sat - saturation *
- * hue - hue *
- * red_intensity - intensity of red component *
- * green_intensity - intensity of green component *
- * blue_intensity - intensity of blue component *
- * ref - index to the table of refernce transforms *
- * user_gamma - gamma value x 1000 (e.g., 1200 = gamma of 1.2) *
- * Outputs: NONE *
- ****************************************************************************/
-
-static void RADEONSetTransform (ScrnInfoPtr pScrn,
- float bright,
- float cont,
- float sat,
- float hue,
- float red_intensity,
- float green_intensity,
- float blue_intensity,
- CARD32 ref,
- CARD32 user_gamma)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- float OvHueSin, OvHueCos;
- float CAdjLuma, CAdjOff;
- float CAdjRCb, CAdjRCr;
- float CAdjGCb, CAdjGCr;
- float CAdjBCb, CAdjBCr;
- float RedAdj,GreenAdj,BlueAdj;
- float OvLuma, OvROff, OvGOff, OvBOff;
- float OvRCb, OvRCr;
- float OvGCb, OvGCr;
- float OvBCb, OvBCr;
- float Loff = 64.0;
- float Coff = 512.0f;
-
- CARD32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff;
- CARD32 dwOvRCb, dwOvRCr;
- CARD32 dwOvGCb, dwOvGCr;
- CARD32 dwOvBCb, dwOvBCr;
- CARD32 gamma = 0;
-
- if (ref >= 2)
- return;
-
- /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */
- if (user_gamma <= 925) /* 0.85 */
- gamma = 1;
- else if (user_gamma <= 1050) /* 1.0 */
- gamma = 0;
- else if (user_gamma <= 1150) /* 1.1 */
- gamma = 2;
- else if (user_gamma <= 1325) /* 1.2 */
- gamma = 3;
- else if (user_gamma <= 1575) /* 1.45 */
- gamma = 4;
- else if (user_gamma <= 1950) /* 1.7 */
- gamma = 5;
- else if (user_gamma <= 2350) /* 2.2 */
- gamma = 6;
- else if (user_gamma > 2350) /* 2.5 */
- gamma = 7;
-
- if (gamma >= 8)
- return;
-
- OvHueSin = sin(hue);
- OvHueCos = cos(hue);
-
- CAdjLuma = cont * trans[ref].RefLuma;
- CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0;
- RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0;
- GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0;
- BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0;
-
- CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr;
- CAdjRCr = sat * OvHueCos * trans[ref].RefRCr;
- CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr);
- CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr);
- CAdjBCb = sat * OvHueCos * trans[ref].RefBCb;
- CAdjBCr = sat * OvHueSin * trans[ref].RefBCb;
-
-#if 0 /* default constants */
- CAdjLuma = 1.16455078125;
-
- CAdjRCb = 0.0;
- CAdjRCr = 1.59619140625;
- CAdjGCb = -0.39111328125;
- CAdjGCr = -0.8125;
- CAdjBCb = 2.01708984375;
- CAdjBCr = 0;
-#endif
-
- OvLuma = CAdjLuma * gamma_curve_r100[gamma].OvGammaCont;
- OvRCb = CAdjRCb * gamma_curve_r100[gamma].OvGammaCont;
- OvRCr = CAdjRCr * gamma_curve_r100[gamma].OvGammaCont;
- OvGCb = CAdjGCb * gamma_curve_r100[gamma].OvGammaCont;
- OvGCr = CAdjGCr * gamma_curve_r100[gamma].OvGammaCont;
- OvBCb = CAdjBCb * gamma_curve_r100[gamma].OvGammaCont;
- OvBCr = CAdjBCr * gamma_curve_r100[gamma].OvGammaCont;
- OvROff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
- OvLuma * Loff - (OvRCb + OvRCr) * Coff;
- OvGOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
- OvLuma * Loff - (OvGCb + OvGCr) * Coff;
- OvBOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont -
- OvLuma * Loff - (OvBCb + OvBCr) * Coff;
-#if 0 /* default constants */
- OvROff = -888.5;
- OvGOff = 545;
- OvBOff = -1104;
-#endif
-
- OvROff = ClipValue(OvROff, -2048.0, 2047.5);
- OvGOff = ClipValue(OvGOff, -2048.0, 2047.5);
- OvBOff = ClipValue(OvBOff, -2048.0, 2047.5);
- dwOvROff = ((INT32)(OvROff * 2.0)) & 0x1fff;
- dwOvGOff = ((INT32)(OvGOff * 2.0)) & 0x1fff;
- dwOvBOff = ((INT32)(OvBOff * 2.0)) & 0x1fff;
-
- if(info->ChipFamily == CHIP_FAMILY_RADEON)
- {
- dwOvLuma =(((INT32)(OvLuma * 2048.0))&0x7fff)<<17;
- dwOvRCb = (((INT32)(OvRCb * 2048.0))&0x7fff)<<1;
- dwOvRCr = (((INT32)(OvRCr * 2048.0))&0x7fff)<<17;
- dwOvGCb = (((INT32)(OvGCb * 2048.0))&0x7fff)<<1;
- dwOvGCr = (((INT32)(OvGCr * 2048.0))&0x7fff)<<17;
- dwOvBCb = (((INT32)(OvBCb * 2048.0))&0x7fff)<<1;
- dwOvBCr = (((INT32)(OvBCr * 2048.0))&0x7fff)<<17;
- }
- else
- {
- dwOvLuma = (((INT32)(OvLuma * 256.0))&0xfff)<<20;
- dwOvRCb = (((INT32)(OvRCb * 256.0))&0xfff)<<4;
- dwOvRCr = (((INT32)(OvRCr * 256.0))&0xfff)<<20;
- dwOvGCb = (((INT32)(OvGCb * 256.0))&0xfff)<<4;
- dwOvGCr = (((INT32)(OvGCr * 256.0))&0xfff)<<20;
- dwOvBCb = (((INT32)(OvBCb * 256.0))&0xfff)<<4;
- dwOvBCr = (((INT32)(OvBCr * 256.0))&0xfff)<<20;
- }
-
- /* set gamma */
- RADEONSetOverlayGamma(pScrn, gamma);
-
- /* color transforms */
- OUTREG(RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma);
- OUTREG(RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr);
- OUTREG(RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma);
- OUTREG(RADEON_OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr);
- OUTREG(RADEON_OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma);
- OUTREG(RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr);
-}
-
-static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, int alpha_mode)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (alpha_mode == 0) { /* key mode */
- OUTREG(RADEON_OV0_KEY_CNTL,
- RADEON_GRAPHIC_KEY_FN_EQ | /* what does this do? */
- RADEON_VIDEO_KEY_FN_FALSE | /* what does this do? */
- RADEON_CMP_MIX_OR);
- /* crtc 1 */
- OUTREG(RADEON_DISP_MERGE_CNTL,
- (RADEON_DISP_ALPHA_MODE_KEY &
- RADEON_DISP_ALPHA_MODE_MASK) |
- ((gr_alpha << 0x00000010) &
- RADEON_DISP_GRPH_ALPHA_MASK) |
- ((ov_alpha << 0x00000018) &
- RADEON_DISP_OV0_ALPHA_MASK));
- /* crtc 2 */
- OUTREG(RADEON_DISP2_MERGE_CNTL,
- (RADEON_DISP_ALPHA_MODE_KEY &
- RADEON_DISP_ALPHA_MODE_MASK) |
- ((gr_alpha << 0x00000010) &
- RADEON_DISP_GRPH_ALPHA_MASK) |
- ((ov_alpha << 0x00000018) &
- RADEON_DISP_OV0_ALPHA_MASK));
- } else { /* global mode */
- OUTREG(RADEON_OV0_KEY_CNTL,
- RADEON_GRAPHIC_KEY_FN_FALSE | /* what does this do? */
- RADEON_VIDEO_KEY_FN_FALSE | /* what does this do? */
- RADEON_CMP_MIX_AND);
- /* crtc 2 */
- OUTREG(RADEON_DISP2_MERGE_CNTL,
- (RADEON_DISP_ALPHA_MODE_GLOBAL &
- RADEON_DISP_ALPHA_MODE_MASK) |
- ((gr_alpha << 0x00000010) &
- RADEON_DISP_GRPH_ALPHA_MASK) |
- ((ov_alpha << 0x00000018) &
- RADEON_DISP_OV0_ALPHA_MASK));
- /* crtc 1 */
- OUTREG(RADEON_DISP_MERGE_CNTL,
- (RADEON_DISP_ALPHA_MODE_GLOBAL &
- RADEON_DISP_ALPHA_MODE_MASK) |
- ((gr_alpha << 0x00000010) &
- RADEON_DISP_GRPH_ALPHA_MASK) |
- ((ov_alpha << 0x00000018) &
- RADEON_DISP_OV0_ALPHA_MASK));
- }
- /* per-pixel mode - RADEON_DISP_ALPHA_MODE_PER_PIXEL */
- /* not yet supported */
-}
-
-static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 min, max;
- CARD8 r, g, b;
-
- if (info->CurrentLayout.depth > 8)
- {
- CARD32 rbits, gbits, bbits;
-
- rbits = (colorKey & pScrn->mask.red) >> pScrn->offset.red;
- gbits = (colorKey & pScrn->mask.green) >> pScrn->offset.green;
- bbits = (colorKey & pScrn->mask.blue) >> pScrn->offset.blue;
-
- r = rbits << (8 - pScrn->weight.red);
- g = gbits << (8 - pScrn->weight.green);
- b = bbits << (8 - pScrn->weight.blue);
- }
- else
- {
- CARD32 bits;
-
- bits = colorKey & ((1 << info->CurrentLayout.depth) - 1);
- r = bits;
- g = bits;
- b = bits;
- }
- min = (r << 16) | (g << 8) | (b);
- max = (0xff << 24) | (r << 16) | (g << 8) | (b);
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_OV0_GRAPHICS_KEY_CLR_HIGH, max);
- OUTREG(RADEON_OV0_GRAPHICS_KEY_CLR_LOW, min);
-}
-
-void
-RADEONResetVideo(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
- char tmp[200];
-
- /* this function is called from ScreenInit. pScreen is used
- by XAA internally, but not valid until ScreenInit finishs.
- */
- if (info->accelOn && pScrn->pScreen)
- RADEON_SYNC(info, pScrn);
-
- /* this is done here because each time the server is reset these
- could change.. Otherwise they remain constant */
- xvInstanceID = MAKE_ATOM("XV_INSTANCE_ID");
- xvDeviceID = MAKE_ATOM("XV_DEVICE_ID");
- xvLocationID = MAKE_ATOM("XV_LOCATION_ID");
- xvDumpStatus = MAKE_ATOM("XV_DUMP_STATUS");
-
- xvBrightness = MAKE_ATOM("XV_BRIGHTNESS");
- xvSaturation = MAKE_ATOM("XV_SATURATION");
- xvColor = MAKE_ATOM("XV_COLOR");
- xvContrast = MAKE_ATOM("XV_CONTRAST");
- xvColorKey = MAKE_ATOM("XV_COLORKEY");
- xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER");
- xvHue = MAKE_ATOM("XV_HUE");
- xvRedIntensity = MAKE_ATOM("XV_RED_INTENSITY");
- xvGreenIntensity = MAKE_ATOM("XV_GREEN_INTENSITY");
- xvBlueIntensity = MAKE_ATOM("XV_BLUE_INTENSITY");
- xvGamma = MAKE_ATOM("XV_GAMMA");
- xvColorspace = MAKE_ATOM("XV_COLORSPACE");
-
- xvAutopaintColorkey = MAKE_ATOM("XV_AUTOPAINT_COLORKEY");
- xvSetDefaults = MAKE_ATOM("XV_SET_DEFAULTS");
- xvCRTC = MAKE_ATOM("XV_CRTC");
-
- xvOvAlpha = MAKE_ATOM("XV_OVERLAY_ALPHA");
- xvGrAlpha = MAKE_ATOM("XV_GRAPHICS_ALPHA");
- xvAlphaMode = MAKE_ATOM("XV_ALPHA_MODE");
-
- xvOverlayDeinterlacingMethod = MAKE_ATOM("XV_OVERLAY_DEINTERLACING_METHOD");
-
- xvDecBrightness = MAKE_ATOM("XV_DEC_BRIGHTNESS");
- xvDecSaturation = MAKE_ATOM("XV_DEC_SATURATION");
- xvDecColor = MAKE_ATOM("XV_DEC_COLOR");
- xvDecContrast = MAKE_ATOM("XV_DEC_CONTRAST");
- xvDecHue = MAKE_ATOM("XV_DEC_HUE");
-
- xvEncoding = MAKE_ATOM("XV_ENCODING");
- xvFrequency = MAKE_ATOM("XV_FREQ");
- xvTunerStatus = MAKE_ATOM("XV_TUNER_STATUS");
- xvVolume = MAKE_ATOM("XV_VOLUME");
- xvMute = MAKE_ATOM("XV_MUTE");
- xvSAP = MAKE_ATOM("XV_SAP");
-
- xvAdjustment = MAKE_ATOM("XV_DEBUG_ADJUSTMENT");
-
- sprintf(tmp, "RXXX:%d.%d.%d", PCI_DEV_VENDOR_ID(info->PciInfo),
- PCI_DEV_DEVICE_ID(info->PciInfo), PCI_DEV_REVISION(info->PciInfo));
- pPriv->device_id = MAKE_ATOM(tmp);
- sprintf(tmp, "PCI:%02d:%02d.%d", PCI_DEV_BUS(info->PciInfo),
- PCI_DEV_DEV(info->PciInfo), PCI_DEV_FUNC(info->PciInfo));
- pPriv->location_id = MAKE_ATOM(tmp);
- sprintf(tmp, "INSTANCE:%d", pScrn->scrnIndex);
- pPriv->instance_id = MAKE_ATOM(tmp);
-
- OUTREG(RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET);
- OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, 0); /* maybe */
- OUTREG(RADEON_OV0_EXCLUSIVE_HORZ, 0);
- OUTREG(RADEON_OV0_FILTER_CNTL, RADEON_FILTER_PROGRAMMABLE_COEF);
- OUTREG(RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |
- RADEON_VIDEO_KEY_FN_FALSE |
- RADEON_CMP_MIX_OR);
- OUTREG(RADEON_OV0_TEST, 0);
- OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
- OUTREG(RADEON_CAP0_TRIG_CNTL, 0);
- RADEONSetColorKey(pScrn, pPriv->colorKey);
-
- if (info->ChipFamily == CHIP_FAMILY_RADEON) {
-
- OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a00000);
- OUTREG(RADEON_OV0_LIN_TRANS_B, 0x1990190e);
- OUTREG(RADEON_OV0_LIN_TRANS_C, 0x12a0f9c0);
- OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf3000442);
- OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a02040);
- OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f);
-
- } else {
-
- OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a20000);
- OUTREG(RADEON_OV0_LIN_TRANS_B, 0x198a190e);
- OUTREG(RADEON_OV0_LIN_TRANS_C, 0x12a2f9da);
- OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf2fe0442);
- OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a22046);
- OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f);
- }
- /*
- * Set default Gamma ramp:
- *
- * Of 18 segments for gamma curve, all segments in R200 (and
- * newer) are programmable, while only lower 4 and upper 2
- * segments are programmable in the older Radeons.
- */
-
- RADEONSetOverlayGamma(pScrn, 0); /* gamma = 1.0 */
-
- if(pPriv->VIP!=NULL){
- RADEONVIP_reset(pScrn,pPriv);
- }
-
- if(pPriv->theatre != NULL) {
- xf86_InitTheatre(pPriv->theatre);
-/* xf86_ResetTheatreRegsForNoTVout(pPriv->theatre); */
- }
-
- if(pPriv->i2c != NULL){
- RADEONResetI2C(pScrn, pPriv);
- }
-}
-
-static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPLLPtr pll = &(info->pll);
- TheatrePtr t;
-
- CARD8 a;
- int i;
-
- pPriv->theatre = NULL;
-
- if(!info->MM_TABLE_valid &&
- !((info->RageTheatreCrystal>=0) &&
- (info->RageTheatreTunerPort>=0) && (info->RageTheatreCompositePort>=0) &&
- (info->RageTheatreSVideoPort>=0)))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "no multimedia table present, disabling Rage Theatre.\n");
- return;
- }
-
- /* Go and find Rage Theatre, if it exists */
-
- if (info->IsMobility)
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility, not scanning for Rage Theatre\n");
- else
- pPriv->theatre=xf86_DetectTheatre(pPriv->VIP);
-
- if(pPriv->theatre==NULL)return;
-
- /* just a matter of convenience */
- t=pPriv->theatre;
-
- t->video_decoder_type=info->video_decoder_type;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "video decoder type is 0x%04x (BIOS value) versus 0x%04x (current PLL setting)\n",
- t->video_decoder_type, pll->xclk);
-
- if(info->MM_TABLE_valid){
- for(i=0;i<5;i++){
- a=info->MM_TABLE.input[i];
-
- switch(a & 0x3){
- case 1:
- t->wTunerConnector=i;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Tuner is on port %d\n",i);
- break;
- case 2: if(a & 0x4){
- t->wComp0Connector=RT_COMP2;
- } else {
- t->wComp0Connector=RT_COMP1;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Composite connector is port %u\n", (unsigned)t->wComp0Connector);
- break;
- case 3: if(a & 0x4){
- t->wSVideo0Connector=RT_YCR_COMP4;
- } else {
- t->wSVideo0Connector=RT_YCF_COMP4;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SVideo connector is port %u\n", (unsigned)t->wSVideo0Connector);
- break;
- default:
- break;
- }
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rage Theatre: Connectors (detected): tuner=%u, composite=%u, svideo=%u\n",
- (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector);
-
- }
-
- if(info->RageTheatreTunerPort>=0)t->wTunerConnector=info->RageTheatreTunerPort;
- if(info->RageTheatreCompositePort>=0)t->wComp0Connector=info->RageTheatreCompositePort;
- if(info->RageTheatreSVideoPort>=0)t->wSVideo0Connector=info->RageTheatreSVideoPort;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RageTheatre: Connectors (using): tuner=%u, composite=%u, svideo=%u\n",
- (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector);
-
- switch((info->RageTheatreCrystal>=0)?info->RageTheatreCrystal:pll->reference_freq){
- case 2700:
- t->video_decoder_type=RT_FREF_2700;
- break;
- case 2950:
- t->video_decoder_type=RT_FREF_2950;
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Unsupported reference clock frequency, Rage Theatre disabled\n");
- t->theatre_num=-1;
- xfree(pPriv->theatre);
- pPriv->theatre = NULL;
- return;
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "video decoder type used: 0x%04x\n", t->video_decoder_type);
-}
-
-static XF86VideoAdaptorPtr
-RADEONAllocAdaptor(ScrnInfoPtr pScrn)
-{
- XF86VideoAdaptorPtr adapt;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv;
- CARD32 dot_clock;
- int ecp;
-
- if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn)))
- return NULL;
-
- if(!(pPriv = xcalloc(1, sizeof(RADEONPortPrivRec) + sizeof(DevUnion))))
- {
- xfree(adapt);
- return NULL;
- }
-
- adapt->pPortPrivates = (DevUnion*)(&pPriv[1]);
- adapt->pPortPrivates[0].ptr = (pointer)pPriv;
-
- pPriv->colorKey = info->videoKey;
- pPriv->doubleBuffer = TRUE;
- pPriv->videoStatus = 0;
- pPriv->brightness = 0;
- pPriv->transform_index = 0;
- pPriv->saturation = 0;
- pPriv->contrast = 0;
- pPriv->red_intensity = 0;
- pPriv->green_intensity = 0;
- pPriv->blue_intensity = 0;
- pPriv->hue = 0;
- pPriv->currentBuffer = 0;
- pPriv->autopaint_colorkey = TRUE;
- pPriv->gamma = 1000;
- pPriv->desired_crtc = NULL;
-
- pPriv->ov_alpha = 255;
- pPriv->gr_alpha = 255;
- pPriv->alpha_mode = 0;
-
- /* TV-in stuff */
- pPriv->video_stream_active = FALSE;
- pPriv->encoding = 4;
- pPriv->frequency = 1000;
- pPriv->volume = -1000;
- pPriv->mute = TRUE;
- pPriv->v = 0;
- pPriv->overlay_deinterlacing_method = METHOD_BOB;
- pPriv->capture_vbi_data = 0;
- pPriv->dec_brightness = 0;
- pPriv->dec_saturation = 0;
- pPriv->dec_contrast = 0;
- pPriv->dec_hue = 0;
-
-
- /*
- * Unlike older Mach64 chips, RADEON has only two ECP settings:
- * 0 for PIXCLK < 175Mhz, and 1 (divide by 2)
- * for higher clocks, sure makes life nicer
- */
- dot_clock = info->ModeReg->dot_clock_freq;
-
- if (dot_clock < 17500)
- info->ecp_div = 0;
- else
- info->ecp_div = 1;
- ecp = (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (info->ecp_div << 8);
-
- if (info->IsIGP) {
- /* Force the overlay clock on for integrated chips
- */
- ecp |= (1<<18);
- }
-
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, ecp);
-
-
- /* Decide on tuner type */
- if((info->tunerType<0) && (info->MM_TABLE_valid)) {
- pPriv->tuner_type = info->MM_TABLE.tuner_type;
- } else
- pPriv->tuner_type = info->tunerType;
-
- /* Initialize I2C bus */
- RADEONInitI2C(pScrn, pPriv);
- if(pPriv->i2c != NULL)RADEON_board_setmisc(pPriv);
-
-
- #if 0 /* this is just here for easy debugging - normally off */
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Scanning I2C Bus\n");
- for(i=0;i<255;i+=2)
- if(RADEONProbeAddress(pPriv->i2c, i))
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, " found device at address 0x%02x\n", i);
- #endif
-
- /* resetting the VIP bus causes problems with some mobility chips.
- * we don't support video in on any mobility chips at the moment anyway
- */
- /* Initialize VIP bus */
- if (!info->IsMobility)
- RADEONVIP_init(pScrn, pPriv);
-
- info->adaptor = adapt;
-
- if(!xf86LoadSubModule(pScrn,"theatre_detect"))
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre detect module\n");
- goto skip_theatre;
- }
- RADEONSetupTheatre(pScrn, pPriv);
-
- /*
- * Now load the correspondind theatre chip based on what has been detected.
- */
- if (pPriv->theatre)
- {
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Going to load the corresponding theatre module\n");
- switch (pPriv->theatre->theatre_id)
- {
- case RT100_ATI_ID:
- {
- if(!xf86LoadSubModule(pScrn,"theatre"))
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre module\n");
- xfree(pPriv->theatre);
- goto skip_theatre;
- }
- break;
- }
- case RT200_ATI_ID:
- {
- if(!xf86LoadSubModule(pScrn,"theatre200"))
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre module\n");
- xfree(pPriv->theatre);
- goto skip_theatre;
- }
- pPriv->theatre->microc_path = info->RageTheatreMicrocPath;
- pPriv->theatre->microc_type = info->RageTheatreMicrocType;
- break;
- }
- default:
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unknown Theatre chip\n");
- xfree(pPriv->theatre);
- goto skip_theatre;
- }
- }
- }
-
- if(pPriv->theatre!=NULL)
- {
- xf86_InitTheatre(pPriv->theatre);
- if(pPriv->theatre->mode == MODE_UNINITIALIZED)
- {
- Xfree(pPriv->theatre);
- pPriv->theatre = NULL;
- xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Rage Theatre disabled\n");
- /* Here the modules must be unloaded */
- goto skip_theatre;
- }
- }
-
- if(pPriv->theatre!=NULL){
- xf86_ResetTheatreRegsForNoTVout(pPriv->theatre);
- xf86_RT_SetTint(pPriv->theatre, pPriv->dec_hue);
- xf86_RT_SetSaturation(pPriv->theatre, pPriv->dec_saturation);
- xf86_RT_SetSharpness(pPriv->theatre, RT_NORM_SHARPNESS);
- xf86_RT_SetContrast(pPriv->theatre, pPriv->dec_contrast);
- xf86_RT_SetBrightness(pPriv->theatre, pPriv->dec_brightness);
-
- RADEON_RT_SetEncoding(pScrn, pPriv);
- }
-
-skip_theatre:
-
- return adapt;
-}
-
-static XF86VideoAdaptorPtr
-RADEONSetupImageVideo(ScreenPtr pScreen)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONPortPrivPtr pPriv;
- XF86VideoAdaptorPtr adapt;
-
- if(!(adapt = RADEONAllocAdaptor(pScrn)))
- return NULL;
-
- adapt->type = XvWindowMask | XvInputMask | XvImageMask;
- adapt->flags = VIDEO_OVERLAID_IMAGES /*| VIDEO_CLIP_TO_VIEWPORT*/;
- adapt->name = "ATI Radeon Video Overlay";
- adapt->nEncodings = 1;
- adapt->pEncodings = &DummyEncoding;
- adapt->nFormats = NUM_FORMATS;
- adapt->pFormats = Formats;
- adapt->nPorts = 1;
- adapt->nAttributes = NUM_ATTRIBUTES;
- adapt->pAttributes = Attributes;
- adapt->nImages = NUM_IMAGES;
- adapt->pImages = Images;
- adapt->PutVideo = NULL;
- adapt->PutStill = NULL;
- adapt->GetVideo = NULL;
- adapt->GetStill = NULL;
- adapt->StopVideo = RADEONStopVideo;
- adapt->SetPortAttribute = RADEONSetPortAttribute;
- adapt->GetPortAttribute = RADEONGetPortAttribute;
- adapt->QueryBestSize = RADEONQueryBestSize;
- adapt->PutImage = RADEONPutImage;
- adapt->QueryImageAttributes = RADEONQueryImageAttributes;
-
- pPriv = (RADEONPortPrivPtr)(adapt->pPortPrivates[0].ptr);
- REGION_NULL(pScreen, &(pPriv->clip));
-
- pPriv->textured = FALSE;
-
- if(pPriv->theatre != NULL)
- {
- /* video decoder is present, extend capabilities */
- adapt->nEncodings = 13;
- adapt->pEncodings = InputVideoEncodings;
- adapt->type |= XvVideoMask;
- adapt->nAttributes = NUM_DEC_ATTRIBUTES;
- adapt->PutVideo = RADEONPutVideo;
- }
-
- RADEONResetVideo(pScrn);
-
- return adapt;
-}
-
-void
-RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
-
- if (pPriv->textured)
- return;
-
- REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
-
- if(cleanup) {
- if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_OV0_SCALE_CNTL, 0);
- }
- if(pPriv->video_stream_active){
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
- OUTREG(RADEON_CAP0_TRIG_CNTL, 0);
- RADEONResetVideo(pScrn);
- pPriv->video_stream_active = FALSE;
- if(pPriv->msp3430 != NULL) xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_FAST_MUTE);
- if(pPriv->uda1380 != NULL) xf86_uda1380_mute(pPriv->uda1380, TRUE);
- if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv);
- }
- if (pPriv->video_memory != NULL) {
- RADEONFreeMemory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
- }
- pPriv->videoStatus = 0;
- } else {
- if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
- pPriv->videoStatus |= OFF_TIMER;
- pPriv->offTime = currentTime.milliseconds + OFF_DELAY;
- }
- }
-}
-
-int
-RADEONSetPortAttribute(ScrnInfoPtr pScrn,
- Atom attribute,
- INT32 value,
- pointer data)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- Bool setTransform = FALSE;
- Bool setAlpha = FALSE;
- unsigned char *RADEONMMIO = info->MMIO;
-
- if (pPriv->textured)
- return BadMatch;
-
- RADEON_SYNC(info, pScrn);
-
-#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0)
-#define RTFBrightness(a) (((a)*1.0)/2000.0)
-#define RTFIntensity(a) (((a)*1.0)/2000.0)
-#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0)
-#define RTFHue(a) (((a)*3.1416)/1000.0)
-
- if(attribute == xvAutopaintColorkey)
- {
- pPriv->autopaint_colorkey = ClipValue (value, 0, 1);
- }
- else if(attribute == xvSetDefaults)
- {
- pPriv->autopaint_colorkey = TRUE;
- pPriv->brightness = 0;
- pPriv->saturation = 0;
- pPriv->contrast = 0;
- pPriv->hue = 0;
- pPriv->red_intensity = 0;
- pPriv->green_intensity = 0;
- pPriv->blue_intensity = 0;
- pPriv->gamma = 1000;
- pPriv->transform_index = 0;
- pPriv->doubleBuffer = FALSE;
- pPriv->ov_alpha = 255;
- pPriv->gr_alpha = 255;
- pPriv->alpha_mode = 0;
-
- /* It is simpler to call itself */
- RADEONSetPortAttribute(pScrn, xvDecBrightness, 0, data);
- RADEONSetPortAttribute(pScrn, xvDecSaturation, 0, data);
- RADEONSetPortAttribute(pScrn, xvDecContrast, 0, data);
- RADEONSetPortAttribute(pScrn, xvDecHue, 0, data);
-
- RADEONSetPortAttribute(pScrn, xvVolume, -1000, data);
- RADEONSetPortAttribute(pScrn, xvMute, 1, data);
- RADEONSetPortAttribute(pScrn, xvSAP, 0, data);
- RADEONSetPortAttribute(pScrn, xvDoubleBuffer, 1, data);
-
- setTransform = TRUE;
- setAlpha = TRUE;
- }
- else if(attribute == xvBrightness)
- {
- pPriv->brightness = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if((attribute == xvSaturation) || (attribute == xvColor))
- {
- pPriv->saturation = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if(attribute == xvContrast)
- {
- pPriv->contrast = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if(attribute == xvHue)
- {
- pPriv->hue = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if(attribute == xvRedIntensity)
- {
- pPriv->red_intensity = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if(attribute == xvGreenIntensity)
- {
- pPriv->green_intensity = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if(attribute == xvBlueIntensity)
- {
- pPriv->blue_intensity = ClipValue (value, -1000, 1000);
- setTransform = TRUE;
- }
- else if(attribute == xvGamma)
- {
- pPriv->gamma = ClipValue (value, 100, 10000);
- setTransform = TRUE;
- }
- else if(attribute == xvColorspace)
- {
- pPriv->transform_index = ClipValue (value, 0, 1);
- setTransform = TRUE;
- }
- else if(attribute == xvDoubleBuffer)
- {
- pPriv->doubleBuffer = ClipValue (value, 0, 1);
- }
- else if(attribute == xvColorKey)
- {
- pPriv->colorKey = value;
- RADEONSetColorKey (pScrn, pPriv->colorKey);
- REGION_EMPTY(pScrn->pScreen, &pPriv->clip);
- }
- else if(attribute == xvCRTC)
- {
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- if ((value < -1) || (value > xf86_config->num_crtc))
- return BadValue;
- if (value < 0)
- pPriv->desired_crtc = NULL;
- else
- pPriv->desired_crtc = xf86_config->crtc[value];
- }
- else if(attribute == xvOvAlpha)
- {
- pPriv->ov_alpha = ClipValue (value, 0, 255);
- setAlpha = TRUE;
- }
- else if(attribute == xvGrAlpha)
- {
- pPriv->gr_alpha = ClipValue (value, 0, 255);
- setAlpha = TRUE;
- }
- else if(attribute == xvAlphaMode)
- {
- pPriv->alpha_mode = ClipValue (value, 0, 1);
- setAlpha = TRUE;
- }
- else if(attribute == xvDecBrightness)
- {
- pPriv->dec_brightness = value;
- if(pPriv->theatre!=NULL) xf86_RT_SetBrightness(pPriv->theatre, pPriv->dec_brightness);
- }
- else if((attribute == xvDecSaturation) || (attribute == xvDecColor))
- {
- if(value<-1000)value = -1000;
- if(value>1000)value = 1000;
- pPriv->dec_saturation = value;
- if(pPriv->theatre != NULL)xf86_RT_SetSaturation(pPriv->theatre, value);
- }
- else if(attribute == xvDecContrast)
- {
- pPriv->dec_contrast = value;
- if(pPriv->theatre != NULL)xf86_RT_SetContrast(pPriv->theatre, value);
- }
- else if(attribute == xvDecHue)
- {
- pPriv->dec_hue = value;
- if(pPriv->theatre != NULL)xf86_RT_SetTint(pPriv->theatre, value);
- }
- else if(attribute == xvEncoding)
- {
- pPriv->encoding = value;
- if(pPriv->video_stream_active)
- {
- if(pPriv->theatre != NULL) RADEON_RT_SetEncoding(pScrn, pPriv);
- if(pPriv->msp3430 != NULL) RADEON_MSP_SetEncoding(pPriv);
- if(pPriv->tda9885 != NULL) RADEON_TDA9885_SetEncoding(pPriv);
- if(pPriv->fi1236 != NULL) RADEON_FI1236_SetEncoding(pPriv);
- if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv);
- /* put more here to actually change it */
- }
- }
- else if(attribute == xvFrequency)
- {
- pPriv->frequency = value;
- /* mute volume if it was not muted before */
- if((pPriv->msp3430!=NULL)&& !pPriv->mute)xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_FAST_MUTE);
- if((pPriv->uda1380!=NULL)&& !pPriv->mute)xf86_uda1380_mute(pPriv->uda1380, TRUE);
- if(pPriv->fi1236 != NULL) xf86_TUNER_set_frequency(pPriv->fi1236, value);
-/* if(pPriv->theatre != NULL) RADEON_RT_SetEncoding(pScrn, pPriv); */
- if((pPriv->msp3430 != NULL) && (pPriv->msp3430->recheck))
- xf86_InitMSP3430(pPriv->msp3430);
- if((pPriv->msp3430 != NULL)&& !pPriv->mute) xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_VOLUME(pPriv->volume));
- if((pPriv->uda1380 != NULL)&& !pPriv->mute) xf86_uda1380_setvolume(pPriv->uda1380, pPriv->volume);
- }
- else if(attribute == xvMute)
- {
- pPriv->mute = value;
- if(pPriv->msp3430 != NULL) xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume));
- if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv);
- if(pPriv->uda1380 != NULL) xf86_uda1380_mute(pPriv->uda1380, pPriv->mute);
- }
- else if(attribute == xvSAP)
- {
- pPriv->sap_channel = value;
- if(pPriv->msp3430 != NULL) xf86_MSP3430SetSAP(pPriv->msp3430, pPriv->sap_channel?4:3);
- }
- else if(attribute == xvVolume)
- {
- if(value<-1000)value = -1000;
- if(value>1000)value = 1000;
- pPriv->volume = value;
- pPriv->mute = FALSE;
- if(pPriv->msp3430 != NULL) xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_VOLUME(value));
- if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv);
- if(pPriv->uda1380 != NULL) xf86_uda1380_setvolume(pPriv->uda1380, value);
- }
- else if(attribute == xvOverlayDeinterlacingMethod)
- {
- if(value<0)value = 0;
- if(value>2)value = 2;
- pPriv->overlay_deinterlacing_method = value;
- switch(pPriv->overlay_deinterlacing_method){
- case METHOD_BOB:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA);
- break;
- case METHOD_SINGLE:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xEEEEE | (9<<28));
- break;
- case METHOD_WEAVE:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0x0);
- break;
- default:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA);
- }
- }
- else if(attribute == xvDumpStatus)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Current mode flags 0x%08x: %s%s\n",
- pScrn->currentMode->Flags,
- pScrn->currentMode->Flags & V_INTERLACE ? " interlaced" : "" ,
- pScrn->currentMode->Flags & V_DBLSCAN ? " doublescan" : ""
- );
- if(pPriv->tda9885 != NULL){
- xf86_tda9885_getstatus(pPriv->tda9885);
- xf86_tda9885_dumpstatus(pPriv->tda9885);
- }
- if(pPriv->fi1236!=NULL){
- xf86_fi1236_dump_status(pPriv->fi1236);
- }
- }
- else if(attribute == xvAdjustment)
- {
- pPriv->adjustment=value;
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Setting pPriv->adjustment to %u\n",
- (unsigned)pPriv->adjustment);
- if(pPriv->tda9885!=0){
- pPriv->tda9885->top_adjustment=value;
- RADEON_TDA9885_SetEncoding(pPriv);
- }
- }
- else
- return BadMatch;
-
- if (setTransform)
- {
- RADEONSetTransform(pScrn,
- RTFBrightness(pPriv->brightness),
- RTFContrast(pPriv->contrast),
- RTFSaturation(pPriv->saturation),
- RTFHue(pPriv->hue),
- RTFIntensity(pPriv->red_intensity),
- RTFIntensity(pPriv->green_intensity),
- RTFIntensity(pPriv->blue_intensity),
- pPriv->transform_index,
- pPriv->gamma);
- }
-
- if (setAlpha)
- {
- RADEONSetOverlayAlpha(pScrn, pPriv->ov_alpha, pPriv->gr_alpha, pPriv->alpha_mode);
- }
-
- return Success;
-}
-
-int
-RADEONGetPortAttribute(ScrnInfoPtr pScrn,
- Atom attribute,
- INT32 *value,
- pointer data)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
-
- if (pPriv->textured)
- return BadMatch;
-
- if (info->accelOn) RADEON_SYNC(info, pScrn);
-
- if(attribute == xvAutopaintColorkey)
- *value = pPriv->autopaint_colorkey;
- else if(attribute == xvBrightness)
- *value = pPriv->brightness;
- else if((attribute == xvSaturation) || (attribute == xvColor))
- *value = pPriv->saturation;
- else if(attribute == xvContrast)
- *value = pPriv->contrast;
- else if(attribute == xvHue)
- *value = pPriv->hue;
- else if(attribute == xvRedIntensity)
- *value = pPriv->red_intensity;
- else if(attribute == xvGreenIntensity)
- *value = pPriv->green_intensity;
- else if(attribute == xvBlueIntensity)
- *value = pPriv->blue_intensity;
- else if(attribute == xvGamma)
- *value = pPriv->gamma;
- else if(attribute == xvColorspace)
- *value = pPriv->transform_index;
- else if(attribute == xvDoubleBuffer)
- *value = pPriv->doubleBuffer ? 1 : 0;
- else if(attribute == xvColorKey)
- *value = pPriv->colorKey;
- else if(attribute == xvCRTC) {
- int c;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- for (c = 0; c < xf86_config->num_crtc; c++)
- if (xf86_config->crtc[c] == pPriv->desired_crtc)
- break;
- if (c == xf86_config->num_crtc)
- c = -1;
- *value = c;
- }
- else if(attribute == xvOvAlpha)
- *value = pPriv->ov_alpha;
- else if(attribute == xvGrAlpha)
- *value = pPriv->gr_alpha;
- else if(attribute == xvAlphaMode)
- *value = pPriv->alpha_mode;
- else if(attribute == xvDecBrightness)
- *value = pPriv->dec_brightness;
- else if((attribute == xvDecSaturation) || (attribute == xvDecColor))
- *value = pPriv->dec_saturation;
- else if(attribute == xvDecContrast)
- *value = pPriv->dec_contrast;
- else if(attribute == xvDecHue)
- *value = pPriv->dec_hue;
- else if(attribute == xvEncoding)
- *value = pPriv->encoding;
- else if(attribute == xvFrequency)
- *value = pPriv->frequency;
- else
- if(attribute == xvTunerStatus) {
- if(pPriv->fi1236==NULL){
- *value=TUNER_OFF;
- } else
- {
- *value = xf86_TUNER_get_afc_hint(pPriv->fi1236);
- }
- }
- else if(attribute == xvMute)
- *value = pPriv->mute;
- else if(attribute == xvSAP)
- *value = pPriv->sap_channel;
- else if(attribute == xvVolume)
- *value = pPriv->volume;
- else if(attribute == xvOverlayDeinterlacingMethod)
- *value = pPriv->overlay_deinterlacing_method;
- else if(attribute == xvDeviceID)
- *value = pPriv->device_id;
- else if(attribute == xvLocationID)
- *value = pPriv->location_id;
- else if(attribute == xvInstanceID)
- *value = pPriv->instance_id;
- else if(attribute == xvAdjustment)
- *value = pPriv->adjustment;
- else
- return BadMatch;
-
- return Success;
-}
-
-void
-RADEONQueryBestSize(
- ScrnInfoPtr pScrn,
- Bool motion,
- short vid_w, short vid_h,
- short drw_w, short drw_h,
- unsigned int *p_w, unsigned int *p_h,
- pointer data
-){
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
-
- if (!pPriv->textured) {
- if (vid_w > (drw_w << 4))
- drw_w = vid_w >> 4;
- if (vid_h > (drw_h << 4))
- drw_h = vid_h >> 4;
- }
-
- *p_w = drw_w;
- *p_h = drw_h;
-}
-
-static struct {
- double range;
- signed char coeff[5][4];
- } TapCoeffs[]=
- {
- {0.25, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.26, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.27, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.28, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.29, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.30, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.31, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.32, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.33, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.34, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.35, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.36, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.37, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.38, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.39, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.40, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.41, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.42, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.43, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.44, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.45, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.46, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.47, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.48, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.49, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.50, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }},
- {0.51, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 2, 14, 14, 2}, }},
- {0.52, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }},
- {0.53, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }},
- {0.54, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }},
- {0.55, {{ 7, 18, 7, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 1, 15, 15, 1}, }},
- {0.56, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.57, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.58, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.59, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.60, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.61, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.62, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.63, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.64, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }},
- {0.65, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }},
- {0.66, {{ 7, 18, 8, -1}, { 6, 18, 10, -2}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }},
- {0.67, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 18, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }},
- {0.68, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }},
- {0.69, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }},
- {0.70, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }},
- {0.71, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }},
- {0.72, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }},
- {0.73, {{ 7, 20, 7, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }},
- {0.74, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }},
- {0.75, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }},
- {0.76, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }},
- {0.77, {{ 6, 22, 6, -2}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }},
- {0.78, {{ 6, 21, 6, -1}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }},
- {0.79, {{ 5, 23, 5, -1}, { 3, 22, 9, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }},
- {0.80, {{ 5, 23, 5, -1}, { 3, 23, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }},
- {0.81, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }},
- {0.82, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-3, 19, 19, -3}, }},
- {0.83, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }},
- {0.84, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }},
- {0.85, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }},
- {0.86, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }},
- {0.87, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }},
- {0.88, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.89, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.90, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.91, {{ 3, 26, 3, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.92, {{ 2, 28, 2, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.93, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.94, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }},
- {0.95, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }},
- {0.96, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }},
- {0.97, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }},
- {0.98, {{ 1, 30, 1, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }},
- {0.99, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }},
- {1.00, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }}
- };
-
-void
-RADEONCopyData(
- ScrnInfoPtr pScrn,
- unsigned char *src,
- unsigned char *dst,
- unsigned int srcPitch,
- unsigned int dstPitch,
- unsigned int h,
- unsigned int w,
- unsigned int bpp
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#ifdef XF86DRI
-
- if ( info->directRenderingEnabled && info->DMAForXv )
- {
- CARD8 *buf;
- CARD32 bufPitch, dstPitchOff;
- int x, y;
- unsigned int hpass;
-
- /* Get the byte-swapping right for big endian systems */
- if ( bpp == 2 )
- {
- w *= 2;
- bpp = 1;
- }
-
- RADEONHostDataParams( pScrn, dst, dstPitch, bpp, &dstPitchOff, &x, &y );
-
- while ( (buf = RADEONHostDataBlit( pScrn, bpp, w, dstPitchOff, &bufPitch,
- x, &y, &h, &hpass )) )
- {
- RADEONHostDataBlitCopyPass( pScrn, bpp, buf, src, hpass, bufPitch,
- srcPitch );
- src += hpass * srcPitch;
- }
-
- FLUSH_RING();
-
- return;
- }
- else
-#endif /* XF86DRI */
- {
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int swapper = info->ModeReg->surface_cntl &
- ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP |
- RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP);
-
- switch(bpp) {
- case 2:
- swapper |= RADEON_NONSURF_AP0_SWP_16BPP
- | RADEON_NONSURF_AP1_SWP_16BPP;
- break;
- case 4:
- swapper |= RADEON_NONSURF_AP0_SWP_32BPP
- | RADEON_NONSURF_AP1_SWP_32BPP;
- break;
- }
- OUTREG(RADEON_SURFACE_CNTL, swapper);
-#endif
- w *= bpp;
-
- while (h--) {
- memcpy(dst, src, w);
- src += srcPitch;
- dst += dstPitch;
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-#endif
- }
-}
-
-static void
-RADEONCopyRGB24Data(
- ScrnInfoPtr pScrn,
- unsigned char *src,
- unsigned char *dst,
- unsigned int srcPitch,
- unsigned int dstPitch,
- unsigned int h,
- unsigned int w
-){
- CARD32 *dptr;
- CARD8 *sptr;
- int i,j;
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#ifdef XF86DRI
-
- if ( info->directRenderingEnabled && info->DMAForXv )
- {
- CARD32 bufPitch, dstPitchOff;
- int x, y;
- unsigned int hpass;
-
- RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y );
-
- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff,
- &bufPitch, x, &y, &h,
- &hpass )) )
- {
- for( j = 0; j < hpass; j++ )
- {
- sptr = src;
-
- for ( i = 0 ; i < w; i++, sptr += 3 )
- {
- dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
- }
-
- src += srcPitch;
- dptr += bufPitch / 4;
- }
- }
-
- FLUSH_RING();
-
- return;
- }
- else
-#endif /* XF86DRI */
- {
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
- | RADEON_NONSURF_AP0_SWP_32BPP)
- & ~RADEON_NONSURF_AP0_SWP_16BPP);
-#endif
-
- for (j = 0; j < h; j++) {
- dptr = (CARD32 *)(dst + j * dstPitch);
- sptr = src + j * srcPitch;
-
- for (i = 0; i < w; i++, sptr += 3) {
- dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
- }
- }
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-#endif
- }
-}
-
-
-#ifdef XF86DRI
-static void RADEON_420_422(
- unsigned int *d,
- unsigned char *s1,
- unsigned char *s2,
- unsigned char *s3,
- unsigned int n
-)
-{
- while ( n ) {
- *(d++) = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24);
- s1+=2; s2++; s3++;
- n--;
- }
-}
-#endif
-
-void
-RADEONCopyMungedData(
- ScrnInfoPtr pScrn,
- unsigned char *src1,
- unsigned char *src2,
- unsigned char *src3,
- unsigned char *dst1,
- unsigned int srcPitch,
- unsigned int srcPitch2,
- unsigned int dstPitch,
- unsigned int h,
- unsigned int w
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
-#ifdef XF86DRI
-
- if ( info->directRenderingEnabled && info->DMAForXv )
- {
- CARD8 *buf;
- CARD32 y = 0, bufPitch, dstPitchOff;
- int blitX, blitY;
- unsigned int hpass;
-
- /* XXX Fix endian flip on R300 */
-
- RADEONHostDataParams( pScrn, dst1, dstPitch, 4, &dstPitchOff, &blitX, &blitY );
-
- while ( (buf = RADEONHostDataBlit( pScrn, 4, w/2, dstPitchOff, &bufPitch,
- blitX, &blitY, &h, &hpass )) )
- {
- while ( hpass-- )
- {
- RADEON_420_422( (unsigned int *) buf, src1, src2, src3,
- bufPitch / 4 );
- src1 += srcPitch;
- if ( y & 1 )
- {
- src2 += srcPitch2;
- src3 += srcPitch2;
- }
- buf += bufPitch;
- y++;
- }
- }
-
- FLUSH_RING();
- }
- else
-#endif /* XF86DRI */
- {
- CARD32 *dst;
- CARD8 *s1, *s2, *s3;
- int i, j;
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl
- | RADEON_NONSURF_AP0_SWP_32BPP)
- & ~RADEON_NONSURF_AP0_SWP_16BPP);
-#endif
-
- w /= 2;
-
- for( j = 0; j < h; j++ )
- {
- dst = (pointer)dst1;
- s1 = src1; s2 = src2; s3 = src3;
- i = w;
- while( i > 4 )
- {
- dst[0] = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24);
- dst[1] = s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24);
- dst[2] = s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24);
- dst[3] = s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24);
- dst += 4; s2 += 4; s3 += 4; s1 += 8;
- i -= 4;
- }
- while( i-- )
- {
- dst[0] = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24);
- dst++; s2++; s3++;
- s1 += 2;
- }
-
- dst1 += dstPitch;
- src1 += srcPitch;
- if( j & 1 )
- {
- src2 += srcPitch2;
- src3 += srcPitch2;
- }
- }
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* restore byte swapping */
- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl);
-#endif
- }
-}
-
-
-/* Allocates memory, either by resizing the allocation pointed to by mem_struct,
- * or by freeing mem_struct (if non-NULL) and allocating a new space. The size
- * is measured in bytes, and the offset from the beginning of card space is
- * returned.
- */
-CARD32
-RADEONAllocateMemory(
- ScrnInfoPtr pScrn,
- void **mem_struct,
- int size
-){
- ScreenPtr pScreen;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- int offset = 0;
-
- pScreen = screenInfo.screens[pScrn->scrnIndex];
-#ifdef USE_EXA
- if (info->useEXA) {
- ExaOffscreenArea *area = *mem_struct;
-
- if (area != NULL) {
- if (area->size >= size)
- return area->offset;
-
- exaOffscreenFree(pScrn->pScreen, area);
- }
-
- area = exaOffscreenAlloc(pScrn->pScreen, size, 64, TRUE, ATIVideoSave,
- NULL);
- *mem_struct = area;
- if (area == NULL)
- return 0;
- offset = area->offset;
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- FBLinearPtr linear = *mem_struct;
- int cpp = info->CurrentLayout.bitsPerPixel / 8;
-
- /* XAA allocates in units of pixels at the screen bpp, so adjust size
- * appropriately.
- */
- size = (size + cpp - 1) / cpp;
-
- if (linear) {
- if(linear->size >= size)
- return linear->offset * cpp;
-
- if(xf86ResizeOffscreenLinear(linear, size))
- return linear->offset * cpp;
-
- xf86FreeOffscreenLinear(linear);
- }
-
- linear = xf86AllocateOffscreenLinear(pScreen, size, 16,
- NULL, NULL, NULL);
- *mem_struct = linear;
-
- if (!linear) {
- int max_size;
-
- xf86QueryLargestOffscreenLinear(pScreen, &max_size, 16,
- PRIORITY_EXTREME);
-
- if(max_size < size)
- return 0;
-
- xf86PurgeUnlockedOffscreenAreas(pScreen);
- linear = xf86AllocateOffscreenLinear(pScreen, size, 16,
- NULL, NULL, NULL);
- *mem_struct = linear;
- if (!linear)
- return 0;
- }
- offset = linear->offset * cpp;
- }
-#endif /* USE_XAA */
-
- return offset;
-}
-
-void
-RADEONFreeMemory(
- ScrnInfoPtr pScrn,
- void *mem_struct
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
-#ifdef USE_EXA
- if (info->useEXA) {
- ExaOffscreenArea *area = mem_struct;
-
- if (area != NULL)
- exaOffscreenFree(pScrn->pScreen, area);
- }
-#endif /* USE_EXA */
-#ifdef USE_XAA
- if (!info->useEXA) {
- FBLinearPtr linear = mem_struct;
-
- if (linear != NULL)
- xf86FreeOffscreenLinear(linear);
- }
-#endif /* USE_XAA */
-}
-
-static void
-RADEONDisplayVideo(
- ScrnInfoPtr pScrn,
- xf86CrtcPtr crtc,
- RADEONPortPrivPtr pPriv,
- int id,
- int offset1, int offset2,
- int offset3, int offset4,
- int offset5, int offset6,
- short width, short height,
- int pitch,
- int left, int right, int top,
- BoxPtr dstBox,
- short src_w, short src_h,
- short drw_w, short drw_h,
- int deinterlacing_method
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp;
- double h_inc_d;
- int p1_h_accum_init, p23_h_accum_init;
- int p1_v_accum_init, p23_v_accum_init;
- int p23_blank_lines;
- int ecp_div;
- int v_inc_shift;
- int y_mult;
- int x_off;
- int y_off;
- CARD32 scaler_src;
- CARD32 dot_clock;
- int is_rgb;
- int is_planar;
- int i;
- CARD32 scale_cntl;
- double dsr;
- int tap_set;
- int predownscale=0;
- int src_w_d;
- int leftuv = 0;
- DisplayModePtr mode;
- RADEONOutputPrivatePtr radeon_output;
- xf86OutputPtr output;
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- is_rgb=0; is_planar=0;
- switch(id){
- case FOURCC_I420:
- case FOURCC_YV12:
- is_planar=1;
- break;
- case FOURCC_RGBA32:
- case FOURCC_RGB24:
- case FOURCC_RGBT16:
- case FOURCC_RGB16:
- is_rgb=1;
- break;
- default:
- break;
- }
-
- /* Here we need to find ecp_div again, as the user may have switched resolutions
- but only call OUTPLL/INPLL if needed since it may cause a 10ms delay due to
- workarounds for chip erratas */
-
- /* Figure out which head we are on for dot clock */
- if (radeon_crtc->crtc_id == 1)
- dot_clock = info->ModeReg->dot_clock_freq_2;
- else
- dot_clock = info->ModeReg->dot_clock_freq;
-
- if (dot_clock < 17500)
- ecp_div = 0;
- else
- ecp_div = 1;
-
- if (ecp_div != info->ecp_div) {
- info->ecp_div = ecp_div;
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL,
- (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (ecp_div << 8));
- }
-
- /* I suspect we may need a usleep after writing to the PLL. if you play a video too soon
- after switching crtcs in mergedfb clone mode you get a temporary one pixel line of colorkey
- on the right edge video output.
- Is this still the case? Might have been chips which need the errata,
- there is now plenty of usleep after INPLL/OUTPLL for those...*/
-
- v_inc_shift = 20;
- y_mult = 1;
-
- mode = &crtc->mode;
-
- if (mode->Flags & V_INTERLACE)
- v_inc_shift++;
- if (mode->Flags & V_DBLSCAN) {
- v_inc_shift--;
- y_mult = 2;
- }
-
- v_inc = (src_h << v_inc_shift) / drw_h;
-
- for (i = 0; i < xf86_config->num_output; i++) {
- output = xf86_config->output[i];
- if (output->crtc == crtc) {
- radeon_output = output->driver_private;
- if (radeon_output->Flags & RADEON_USE_RMX)
- v_inc = ((src_h * mode->CrtcVDisplay /
- radeon_output->PanelYRes) << v_inc_shift) / drw_h;
- break;
- }
- }
-
- h_inc = (1 << (12 + ecp_div));
-
- step_by_y = 1;
- step_by_uv = step_by_y;
-
- src_w_d = src_w;
-#if 0
- /* XXX this does not appear to work */
- /* if the source width was larger than what would fit in overlay scaler increase step_by values */
- i=src_w;
- while(i>info->overlay_scaler_buffer_width){
- step_by_y++;
- step_by_uv++;
- h_inc >>=1;
- i=i/2;
- }
-#else
- /* predownscale instead (yes this hurts quality) - will only work for widths up
- to 2 times the overlay_scaler_buffer_width, should be enough */
- if (src_w_d > info->overlay_scaler_buffer_width) {
- src_w_d /= 2; /* odd widths? */
- predownscale = 1;
- }
-#endif
-
- h_inc_d = src_w_d;
- h_inc_d = h_inc_d/drw_w;
- /* we could do a tad better - but why
- bother when this concerns downscaling and the code is so much more
- hairy */
- while(h_inc*h_inc_d >= (2 << 12)) {
- if(!is_rgb && (((h_inc+h_inc/2)*h_inc_d)<(2<<12))){
- step_by_uv = step_by_y+1;
- break;
- }
- step_by_y++;
- step_by_uv = step_by_y;
- h_inc >>= 1;
- }
-
- h_inc_uv = h_inc>>(step_by_uv-step_by_y);
- h_inc = h_inc * h_inc_d;
- h_inc_uv = h_inc_uv * h_inc_d;
- /* info->overlay_scaler_buffer_width is magic number - maximum line length the overlay scaler can fit
- in the buffer for 2 tap filtering */
- /* the only place it is documented in is in ATI source code */
- /* we need twice as much space for 4 tap filtering.. */
- /* under special circumstances turn on 4 tap filtering */
- /* disable this code for now as it has a DISASTROUS effect on image quality when upscaling
- at least on rv250 (only as long as the drw_w*2 <=... requirement is still met of course) */
-#if 0
- if(!is_rgb && (step_by_y==1) && (step_by_uv==1) && (h_inc < (1<<12))
- && (deinterlacing_method!=METHOD_WEAVE)
- && (drw_w*2 <= info->overlay_scaler_buffer_width)){
- step_by_y=0;
- step_by_uv=1;
- h_inc_uv = h_inc;
- }
-#endif
-
- /* keep everything in 16.16 */
-
- if (is_planar) {
- offset1 += ((left >> 16) & ~15);
- offset2 += ((left >> 16) & ~31) >> 1;
- offset3 += ((left >> 16) & ~31) >> 1;
- offset4 += ((left >> 16) & ~15);
- offset5 += ((left >> 16) & ~31) >> 1;
- offset6 += ((left >> 16) & ~31) >> 1;
- offset2 |= RADEON_VIF_BUF0_PITCH_SEL;
- offset3 |= RADEON_VIF_BUF0_PITCH_SEL;
- offset5 |= RADEON_VIF_BUF0_PITCH_SEL;
- offset6 |= RADEON_VIF_BUF0_PITCH_SEL;
- }
- else {
- /* is this really correct for non-2-byte formats? */
- offset1 += ((left >> 16) & ~7) << 1;
- offset2 += ((left >> 16) & ~7) << 1;
- offset3 += ((left >> 16) & ~7) << 1;
- offset4 += ((left >> 16) & ~7) << 1;
- offset5 += ((left >> 16) & ~7) << 1;
- offset6 += ((left >> 16) & ~7) << 1;
- }
-
- tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
- p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
- ((tmp << 12) & 0xf0000000);
-
- tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc_uv << 2);
- p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
- ((tmp << 12) & 0x70000000);
-
- tmp = (top & 0x0000ffff) + 0x00018000;
- p1_v_accum_init = ((tmp << 4) & 0x03ff8000) |
- (((deinterlacing_method!=METHOD_WEAVE)&&!is_rgb)?0x03:0x01);
-
- if (is_planar) {
- p23_v_accum_init = ((tmp << 4) & 0x03ff8000) |
- ((deinterlacing_method != METHOD_WEAVE) ? 0x03 : 0x01);
- p23_blank_lines = (((src_h >> 1) - 1) << 16);
- }
- else {
- p23_v_accum_init = 0;
- p23_blank_lines = 0;
- }
-
- if (is_planar) {
- leftuv = ((left >> 16) >> 1) & 15;
- left = (left >> 16) & 15;
- }
- else {
- left = (left >> 16) & 7;
- if (!is_rgb)
- leftuv = left >> 1;
- }
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK);
- if (info->accelOn) RADEON_SYNC(info, pScrn);
- while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_LOCK_READBACK));
-
- RADEONWaitForFifo(pScrn, 10);
- OUTREG(RADEON_OV0_H_INC, h_inc | ((is_rgb? h_inc_uv: (h_inc_uv >> 1)) << 16));
- OUTREG(RADEON_OV0_STEP_BY, step_by_y | (step_by_uv << 8) |
- predownscale << 4 | predownscale << 12);
-
- x_off = 8;
- y_off = 0;
-
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_R200))
- x_off = 0;
-
- /* needed to make the overlay work on crtc1 in leftof and above modes */
- /* XXX: may need to adjust x_off/y_off for dualhead like mergedfb -- need to test */
- /*
- if (srel == radeonLeftOf) {
- x_off -= mode->CrtcHDisplay;
- }
- if (srel == radeonAbove) {
- y_off -= mode->CrtcVDisplay;
- }
- */
-
- /* Put the hardware overlay on CRTC2:
- *
- * Since one hardware overlay can not be displayed on two heads
- * at the same time, we might need to consider using software
- * rendering for the second head.
- */
-
- if (radeon_crtc->crtc_id == 1) {
- x_off = 0;
- OUTREG(RADEON_OV1_Y_X_START, ((dstBox->x1 + x_off) |
- ((dstBox->y1*y_mult) << 16)));
- OUTREG(RADEON_OV1_Y_X_END, ((dstBox->x2 + x_off) |
- ((dstBox->y2*y_mult) << 16)));
- scaler_src = RADEON_SCALER_CRTC_SEL;
- } else {
- OUTREG(RADEON_OV0_Y_X_START, ((dstBox->x1 + x_off) |
- (((dstBox->y1*y_mult) + y_off) << 16)));
- OUTREG(RADEON_OV0_Y_X_END, ((dstBox->x2 + x_off) |
- (((dstBox->y2*y_mult) + y_off) << 16)));
- scaler_src = 0;
- }
-
- /* program the tap coefficients for better downscaling quality.
- Could do slightly better by using hardcoded coefficients for one axis
- in case only the other axis is downscaled (see RADEON_OV0_FILTER_CNTL) */
- dsr=(double)(1<<0xC)/h_inc;
- if(dsr<0.25)dsr=0.25;
- if(dsr>1.0)dsr=1.0;
- tap_set=(int)((dsr-0.25)*100);
- for(i=0;i<5;i++){
- OUTREG(RADEON_OV0_FOUR_TAP_COEF_0+i*4, (TapCoeffs[tap_set].coeff[i][0] &0xf) |
- ((TapCoeffs[tap_set].coeff[i][1] &0x7f)<<8) |
- ((TapCoeffs[tap_set].coeff[i][2] &0x7f)<<16) |
- ((TapCoeffs[tap_set].coeff[i][3] &0xf)<<24));
- }
-
- RADEONWaitForFifo(pScrn, 11);
- OUTREG(RADEON_OV0_V_INC, v_inc);
- OUTREG(RADEON_OV0_P1_BLANK_LINES_AT_TOP, 0x00000fff | ((src_h - 1) << 16));
- OUTREG(RADEON_OV0_P23_BLANK_LINES_AT_TOP, 0x000007ff | p23_blank_lines);
- OUTREG(RADEON_OV0_VID_BUF_PITCH0_VALUE, pitch);
- OUTREG(RADEON_OV0_VID_BUF_PITCH1_VALUE, is_planar ? pitch >> 1 : pitch);
- OUTREG(RADEON_OV0_P1_X_START_END, (src_w + left - 1) | (left << 16));
- if (!is_rgb)
- src_w >>= 1;
- OUTREG(RADEON_OV0_P2_X_START_END, (src_w + leftuv - 1) | (leftuv << 16));
- OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16));
- OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1);
- OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2);
- OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3);
-
- RADEONWaitForFifo(pScrn, 9);
- OUTREG(RADEON_OV0_VID_BUF3_BASE_ADRS, offset4);
- OUTREG(RADEON_OV0_VID_BUF4_BASE_ADRS, offset5);
- OUTREG(RADEON_OV0_VID_BUF5_BASE_ADRS, offset6);
- OUTREG(RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init);
- OUTREG(RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init);
- OUTREG(RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init);
- OUTREG(RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init);
-
- scale_cntl = RADEON_SCALER_ADAPTIVE_DEINT | RADEON_SCALER_DOUBLE_BUFFER
- | RADEON_SCALER_ENABLE | RADEON_SCALER_SMART_SWITCH | (0x7f<<16) | scaler_src;
- switch(id){
- case FOURCC_UYVY:
- scale_cntl |= RADEON_SCALER_SOURCE_YVYU422;
- break;
- case FOURCC_RGB24:
- case FOURCC_RGBA32:
- scale_cntl |= RADEON_SCALER_SOURCE_32BPP | RADEON_SCALER_LIN_TRANS_BYPASS;
- break;
- case FOURCC_RGB16:
- scale_cntl |= RADEON_SCALER_SOURCE_16BPP | RADEON_SCALER_LIN_TRANS_BYPASS;
- break;
- case FOURCC_RGBT16:
- scale_cntl |= RADEON_SCALER_SOURCE_15BPP | RADEON_SCALER_LIN_TRANS_BYPASS;
- break;
- case FOURCC_YV12:
- case FOURCC_I420:
- scale_cntl |= RADEON_SCALER_SOURCE_YUV12;
- break;
- case FOURCC_YUY2:
- default:
- scale_cntl |= RADEON_SCALER_SOURCE_VYUY422
- | ((info->ChipFamily >= CHIP_FAMILY_R200) ? RADEON_SCALER_TEMPORAL_DEINT : 0);
- break;
- }
-
- OUTREG(RADEON_OV0_SCALE_CNTL, scale_cntl);
- OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0);
-}
-
-
-static void
-RADEONFillKeyHelper(DrawablePtr pDraw, CARD32 colorKey, RegionPtr clipBoxes)
-{
-#if HAVE_XV_DRAWABLE_HELPER
- xf86XVFillKeyHelperDrawable(pDraw, colorKey, clipBoxes);
-#else
- xf86XVFillKeyHelper(pDraw->pScreen, colorKey, clipBoxes);
-#endif
-}
-
-
-static int
-RADEONPutImage(
- ScrnInfoPtr pScrn,
- short src_x, short src_y,
- short drw_x, short drw_y,
- short src_w, short src_h,
- short drw_w, short drw_h,
- int id, unsigned char* buf,
- short width, short height,
- Bool Sync,
- RegionPtr clipBoxes, pointer data,
- DrawablePtr pDraw
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- INT32 xa, xb, ya, yb;
- unsigned char *dst_start;
- int new_size, offset, s2offset, s3offset;
- int srcPitch, srcPitch2, dstPitch;
- int d2line, d3line;
- int top, left, npixels, nlines, bpp;
- int idconv = id;
- BoxRec dstBox;
- CARD32 tmp;
- xf86CrtcPtr crtc;
-
- /*
- * s2offset, s3offset - byte offsets into U and V plane of the
- * source where copying starts. Y plane is
- * done by editing "buf".
- *
- * offset - byte offset to the first line of the destination.
- *
- * dst_start - byte address to the first displayed pel.
- *
- */
-
- /* make the compiler happy */
- s2offset = s3offset = srcPitch2 = 0;
- d2line = d3line = 0;
-
- if(src_w > (drw_w << 4))
- drw_w = src_w >> 4;
- if(src_h > (drw_h << 4))
- drw_h = src_h >> 4;
-
- /* Clip */
- xa = src_x;
- xb = src_x + src_w;
- ya = src_y;
- yb = src_y + src_h;
-
- dstBox.x1 = drw_x;
- dstBox.x2 = drw_x + drw_w;
- dstBox.y1 = drw_y;
- dstBox.y2 = drw_y + drw_h;
-
- if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
- return Success;
-
- if (!crtc) {
- if (pPriv->videoStatus & CLIENT_VIDEO_ON) {
- unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_OV0_SCALE_CNTL, 0);
- pPriv->videoStatus &= ~CLIENT_VIDEO_ON;
- }
- return Success;
- }
-
- dstBox.x1 -= crtc->x;
- dstBox.x2 -= crtc->x;
- dstBox.y1 -= crtc->y;
- dstBox.y2 -= crtc->y;
-
- bpp = pScrn->bitsPerPixel >> 3;
-
- switch(id) {
- case FOURCC_RGB24:
- dstPitch = width * 4;
- srcPitch = width * 3;
- break;
- case FOURCC_RGBA32:
- dstPitch = width * 4;
- srcPitch = width * 4;
- break;
- case FOURCC_RGB16:
- case FOURCC_RGBT16:
- dstPitch = width * 2;
- srcPitch = (width * 2 + 3) & ~3;
- break;
- case FOURCC_YV12:
- case FOURCC_I420:
- /* it seems rs4xx chips (all of them???) either can't handle planar
- yuv at all or would need some unknown different setup. */
- if (info->ChipFamily != CHIP_FAMILY_RS400) {
- /* need 16bytes alignment for u,v plane, so 2 times that for width
- but blitter needs 64bytes alignment. 128byte is a waste but dstpitch
- for uv planes needs to be dstpitch yplane >> 1 for now. */
- dstPitch = ((width + 127) & ~127);
- srcPitch = (width + 3) & ~3;
- }
- else {
- dstPitch = width * 2;
- srcPitch = (width + 3) & ~3;
- idconv = FOURCC_YUY2;
- }
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- dstPitch = width * 2;
- srcPitch = width * 2;
- break;
- }
-
-#ifdef XF86DRI
- if (info->directRenderingEnabled && info->DMAForXv) {
- /* The upload blit only supports multiples of 64 bytes */
- dstPitch = (dstPitch + 63) & ~63;
- } else
-#endif
- /* The overlay only supports multiples of 16 bytes */
- dstPitch = (dstPitch + 15) & ~15;
-
- new_size = dstPitch * height;
- if (idconv == FOURCC_YV12 || id == FOURCC_I420) {
- new_size += (dstPitch >> 1) * ((height + 1) & ~1);
- }
- pPriv->video_offset = RADEONAllocateMemory(pScrn, &pPriv->video_memory,
- (pPriv->doubleBuffer ?
- (new_size * 2) : new_size));
- if (pPriv->video_offset == 0)
- return BadAlloc;
-
- pPriv->currentBuffer ^= 1;
-
- /* copy data */
- top = ya >> 16;
- left = (xa >> 16) & ~1;
- npixels = ((((xb + 0xffff) >> 16) + 1) & ~1) - left;
-
- offset = (pPriv->video_offset) + (top * dstPitch);
-
- if(pPriv->doubleBuffer) {
- unsigned char *RADEONMMIO = info->MMIO;
-
- /* Wait for last flip to take effect */
- while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_FLIP_READBACK));
-
- offset += pPriv->currentBuffer * new_size;
- }
-
- dst_start = info->FB + offset;
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- if (id == idconv) {
- /* meh. Such a mess just for someone who wants to watch half the video clipped */
- top &= ~1;
- /* odd number of pixels? That may not work correctly */
- srcPitch2 = ((width >> 1) + 3) & ~3;
- /* odd number of lines? Maybe... */
- s2offset = srcPitch * ((height + 1) & ~1);
- s3offset = s2offset + srcPitch2 * ((height + 1) >> 1);
- s2offset += (top >> 1) * srcPitch2 + (left >> 1);
- s3offset += (top >> 1) * srcPitch2 + (left >> 1);
- d2line = (height * dstPitch);
- d3line = d2line + ((height + 1) >> 1) * (dstPitch >> 1);
- nlines = ((yb + 0xffff) >> 16) - top;
- d2line += (top >> 1) * (dstPitch >> 1) - (top * dstPitch);
- d3line += (top >> 1) * (dstPitch >> 1) - (top * dstPitch);
- if(id == FOURCC_YV12) {
- tmp = s2offset;
- s2offset = s3offset;
- s3offset = tmp;
- }
- RADEONCopyData(pScrn, buf + (top * srcPitch) + left, dst_start + left,
- srcPitch, dstPitch, nlines, npixels, 1);
- RADEONCopyData(pScrn, buf + s2offset, dst_start + d2line + (left >> 1),
- srcPitch2, dstPitch >> 1, (nlines + 1) >> 1, npixels >> 1, 1);
- RADEONCopyData(pScrn, buf + s3offset, dst_start + d3line + (left >> 1),
- srcPitch2, dstPitch >> 1, (nlines + 1) >> 1, npixels >> 1, 1);
- }
- else {
- s2offset = srcPitch * height;
- srcPitch2 = ((width >> 1) + 3) & ~3;
- s3offset = (srcPitch2 * (height >> 1)) + s2offset;
- top &= ~1;
- dst_start += left << 1;
- tmp = ((top >> 1) * srcPitch2) + (left >> 1);
- s2offset += tmp;
- s3offset += tmp;
- if(id == FOURCC_I420) {
- tmp = s2offset;
- s2offset = s3offset;
- s3offset = tmp;
- }
- nlines = ((((yb + 0xffff) >> 16) + 1) & ~1) - top;
- RADEONCopyMungedData(pScrn, buf + (top * srcPitch) + left,
- buf + s2offset, buf + s3offset, dst_start,
- srcPitch, srcPitch2, dstPitch, nlines, npixels);
- }
- break;
- case FOURCC_RGBT16:
- case FOURCC_RGB16:
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- left <<= 1;
- buf += (top * srcPitch) + left;
- nlines = ((yb + 0xffff) >> 16) - top;
- dst_start += left;
- RADEONCopyData(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels, 2);
- break;
- case FOURCC_RGBA32:
- buf += (top * srcPitch) + left*4;
- nlines = ((yb + 0xffff) >> 16) - top;
- dst_start += left*4;
- RADEONCopyData(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels, 4);
- break;
- case FOURCC_RGB24:
- buf += (top * srcPitch) + left*3;
- nlines = ((yb + 0xffff) >> 16) - top;
- dst_start += left*4;
- RADEONCopyRGB24Data(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels);
- break;
- }
-
- /* update cliplist */
- if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes))
- {
- REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes);
- /* draw these */
- if(pPriv->autopaint_colorkey)
- RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes);
- }
-
- /* FIXME: someone should look at these offsets, I don't think it makes sense how
- they are handled throughout the source. */
- RADEONDisplayVideo(pScrn, crtc, pPriv, idconv, offset, offset + d2line, offset + d3line,
- offset, offset + d2line, offset + d3line, width, height, dstPitch,
- xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB);
-
- pPriv->videoStatus = CLIENT_VIDEO_ON;
-
- info->VideoTimerCallback = RADEONVideoTimerCallback;
-
- return Success;
-}
-
-
-int
-RADEONQueryImageAttributes(
- ScrnInfoPtr pScrn,
- int id,
- unsigned short *w, unsigned short *h,
- int *pitches, int *offsets
-){
- int size, tmp;
-
- if(*w > 2048) *w = 2048;
- if(*h > 2048) *h = 2048;
-
- *w = (*w + 1) & ~1;
- if(offsets) offsets[0] = 0;
-
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- *h = (*h + 1) & ~1;
- size = (*w + 3) & ~3;
- if(pitches) pitches[0] = size;
- size *= *h;
- if(offsets) offsets[1] = size;
- tmp = ((*w >> 1) + 3) & ~3;
- if(pitches) pitches[1] = pitches[2] = tmp;
- tmp *= (*h >> 1);
- size += tmp;
- if(offsets) offsets[2] = size;
- size += tmp;
- break;
- case FOURCC_RGBA32:
- size = *w << 2;
- if(pitches) pitches[0] = size;
- size *= *h;
- break;
- case FOURCC_RGB24:
- size = *w * 3;
- if(pitches) pitches[0] = size;
- size *= *h;
- break;
- case FOURCC_RGBT16:
- case FOURCC_RGB16:
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- size = *w << 1;
- if(pitches) pitches[0] = size;
- size *= *h;
- break;
- }
-
- return size;
-}
-
-static void
-RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr;
-
- if(pPriv->videoStatus & TIMER_MASK) {
- if(pPriv->videoStatus & OFF_TIMER) {
- if(pPriv->offTime < now) {
- unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_OV0_SCALE_CNTL, 0);
- pPriv->videoStatus = FREE_TIMER;
- pPriv->freeTime = now + FREE_DELAY;
- }
- } else { /* FREE_TIMER */
- if(pPriv->freeTime < now) {
- if (pPriv->video_memory != NULL) {
- RADEONFreeMemory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
- }
- pPriv->videoStatus = 0;
- info->VideoTimerCallback = NULL;
- }
- }
- } else /* shouldn't get here */
- info->VideoTimerCallback = NULL;
-}
-
-/****************** Offscreen stuff ***************/
-typedef struct {
- void *surface_memory;
- Bool isOn;
-} OffscreenPrivRec, * OffscreenPrivPtr;
-
-static int
-RADEONAllocateSurface(
- ScrnInfoPtr pScrn,
- int id,
- unsigned short w,
- unsigned short h,
- XF86SurfacePtr surface
-){
- int offset, pitch, size;
- OffscreenPrivPtr pPriv;
- void *surface_memory = NULL;
- if((w > 1024) || (h > 1024))
- return BadAlloc;
-
- w = (w + 1) & ~1;
- pitch = ((w << 1) + 15) & ~15;
- size = pitch * h;
-
- offset = RADEONAllocateMemory(pScrn, &surface_memory, size);
- if (offset == 0)
- return BadAlloc;
-
- surface->width = w;
- surface->height = h;
-
- if(!(surface->pitches = xalloc(sizeof(int)))) {
- RADEONFreeMemory(pScrn, surface_memory);
- return BadAlloc;
- }
- if(!(surface->offsets = xalloc(sizeof(int)))) {
- xfree(surface->pitches);
- RADEONFreeMemory(pScrn, surface_memory);
- return BadAlloc;
- }
- if(!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) {
- xfree(surface->pitches);
- xfree(surface->offsets);
- RADEONFreeMemory(pScrn, surface_memory);
- return BadAlloc;
- }
-
- pPriv->surface_memory = surface_memory;
- pPriv->isOn = FALSE;
-
- surface->pScrn = pScrn;
- surface->id = id;
- surface->pitches[0] = pitch;
- surface->offsets[0] = offset;
- surface->devPrivate.ptr = (pointer)pPriv;
-
- return Success;
-}
-
-static int
-RADEONStopSurface(
- XF86SurfacePtr surface
-){
- OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr;
- RADEONInfoPtr info = RADEONPTR(surface->pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- if(pPriv->isOn) {
- OUTREG(RADEON_OV0_SCALE_CNTL, 0);
- pPriv->isOn = FALSE;
- }
- return Success;
-}
-
-
-static int
-RADEONFreeSurface(
- XF86SurfacePtr surface
-){
- ScrnInfoPtr pScrn = surface->pScrn;
- OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr;
-
- if(pPriv->isOn)
- RADEONStopSurface(surface);
- RADEONFreeMemory(pScrn, pPriv->surface_memory);
- xfree(surface->pitches);
- xfree(surface->offsets);
- xfree(surface->devPrivate.ptr);
-
- return Success;
-}
-
-static int
-RADEONGetSurfaceAttribute(
- ScrnInfoPtr pScrn,
- Atom attribute,
- INT32 *value
-){
- return RADEONGetPortAttribute(pScrn, attribute, value,
- (pointer)(GET_PORT_PRIVATE(pScrn)));
-}
-
-static int
-RADEONSetSurfaceAttribute(
- ScrnInfoPtr pScrn,
- Atom attribute,
- INT32 value
-){
- return RADEONSetPortAttribute(pScrn, attribute, value,
- (pointer)(GET_PORT_PRIVATE(pScrn)));
-}
-
-
-static int
-RADEONDisplaySurface(
- XF86SurfacePtr surface,
- short src_x, short src_y,
- short drw_x, short drw_y,
- short src_w, short src_h,
- short drw_w, short drw_h,
- RegionPtr clipBoxes
-){
- OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr;
- ScrnInfoPtr pScrn = surface->pScrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr;
-
- INT32 xa, ya, xb, yb;
- BoxRec dstBox;
- xf86CrtcPtr crtc;
-
- if (src_w > (drw_w << 4))
- drw_w = src_w >> 4;
- if (src_h > (drw_h << 4))
- drw_h = src_h >> 4;
-
- xa = src_x;
- xb = src_x + src_w;
- ya = src_y;
- yb = src_y + src_h;
-
- dstBox.x1 = drw_x;
- dstBox.x2 = drw_x + drw_w;
- dstBox.y1 = drw_y;
- dstBox.y2 = drw_y + drw_h;
-
- if (!radeon_crtc_clip_video(pScrn, &crtc, portPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb, clipBoxes,
- surface->width, surface->height))
- return Success;
-
- if (!crtc) {
- if (pPriv->isOn) {
- unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_OV0_SCALE_CNTL, 0);
- pPriv->isOn = FALSE;
- }
- return Success;
- }
-
- dstBox.x1 -= crtc->x;
- dstBox.x2 -= crtc->x;
- dstBox.y1 -= crtc->y;
- dstBox.y2 -= crtc->y;
-
-#if 0
- /* this isn't needed */
- RADEONResetVideo(pScrn);
-#endif
- RADEONDisplayVideo(pScrn, crtc, portPriv, surface->id,
- surface->offsets[0], surface->offsets[0],
- surface->offsets[0], surface->offsets[0],
- surface->offsets[0], surface->offsets[0],
- surface->width, surface->height, surface->pitches[0],
- xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB);
-
- if (portPriv->autopaint_colorkey)
- xf86XVFillKeyHelper(pScrn->pScreen, portPriv->colorKey, clipBoxes);
-
- pPriv->isOn = TRUE;
- /* we've prempted the XvImage stream so set its free timer */
- if (portPriv->videoStatus & CLIENT_VIDEO_ON) {
- REGION_EMPTY(pScrn->pScreen, &portPriv->clip);
- UpdateCurrentTime();
- portPriv->videoStatus = FREE_TIMER;
- portPriv->freeTime = currentTime.milliseconds + FREE_DELAY;
- info->VideoTimerCallback = RADEONVideoTimerCallback;
- }
-
- return Success;
-}
-
-
-static void
-RADEONInitOffscreenImages(ScreenPtr pScreen)
-{
-/* ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- RADEONInfoPtr info = RADEONPTR(pScrn); */
- XF86OffscreenImagePtr offscreenImages;
- /* need to free this someplace */
-
- if (!(offscreenImages = xalloc(sizeof(XF86OffscreenImageRec))))
- return;
-
- offscreenImages[0].image = &Images[0];
- offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES /*|
- VIDEO_CLIP_TO_VIEWPORT*/;
- offscreenImages[0].alloc_surface = RADEONAllocateSurface;
- offscreenImages[0].free_surface = RADEONFreeSurface;
- offscreenImages[0].display = RADEONDisplaySurface;
- offscreenImages[0].stop = RADEONStopSurface;
- offscreenImages[0].setAttribute = RADEONSetSurfaceAttribute;
- offscreenImages[0].getAttribute = RADEONGetSurfaceAttribute;
- offscreenImages[0].max_width = 2048;
- offscreenImages[0].max_height = 2048;
- offscreenImages[0].num_attributes = NUM_ATTRIBUTES;
- offscreenImages[0].attributes = Attributes;
-
- xf86XVRegisterOffscreenImages(pScreen, offscreenImages, 1);
-}
-
- /* TV-in functions */
-
-static int
-RADEONPutVideo(
- ScrnInfoPtr pScrn,
- short src_x, short src_y,
- short drw_x, short drw_y,
- short src_w, short src_h,
- short drw_w, short drw_h,
- RegionPtr clipBoxes, pointer data,
- DrawablePtr pDraw
-){
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
- unsigned char *RADEONMMIO = info->MMIO;
- INT32 xa, xb, ya, yb, top;
- unsigned int pitch, new_size, alloc_size;
- unsigned int offset1, offset2, offset3, offset4, s2offset, s3offset;
- unsigned int vbi_offset0, vbi_offset1;
- int srcPitch, srcPitch2, dstPitch;
- int bpp;
- BoxRec dstBox;
- CARD32 id, display_base;
- int width, height;
- int mult;
- int vbi_line_width, vbi_start, vbi_end;
- xf86CrtcPtr crtc;
-
- RADEON_SYNC(info, pScrn);
- /*
- * s2offset, s3offset - byte offsets into U and V plane of the
- * source where copying starts. Y plane is
- * done by editing "buf".
- *
- * offset - byte offset to the first line of the destination.
- *
- * dst_start - byte address to the first displayed pel.
- *
- */
-
- /* make the compiler happy */
- s2offset = s3offset = srcPitch2 = 0;
-
- if(src_w > (drw_w << 4))
- drw_w = src_w >> 4;
- if(src_h > (drw_h << 4))
- drw_h = src_h >> 4;
-
- /* Clip */
- xa = src_x;
- xb = src_x + src_w;
- ya = src_y;
- yb = src_y + src_h;
-
- dstBox.x1 = drw_x;
- dstBox.x2 = drw_x + drw_w;
- dstBox.y1 = drw_y;
- dstBox.y2 = drw_y + drw_h;
-
- width = InputVideoEncodings[pPriv->encoding].width;
- height = InputVideoEncodings[pPriv->encoding].height;
-
- vbi_line_width = 798*2;
- if(width<=640)
- vbi_line_width = 0x640; /* 1600 actually */
- else
- vbi_line_width = 2000; /* might need adjustment */
-
- if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
- return Success;
-
- if (!crtc) {
- if (pPriv->videoStatus & CLIENT_VIDEO_ON) {
- unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(RADEON_OV0_SCALE_CNTL, 0);
- pPriv->videoStatus &= ~CLIENT_VIDEO_ON;
- }
- return Success;
- }
-
- dstBox.x1 -= crtc->x;
- dstBox.x2 -= crtc->x;
- dstBox.y1 -= crtc->y;
- dstBox.y2 -= crtc->y;
-
- bpp = pScrn->bitsPerPixel >> 3;
- pitch = bpp * pScrn->displayWidth;
-
- switch(pPriv->overlay_deinterlacing_method){
- case METHOD_BOB:
- case METHOD_SINGLE:
- mult=2;
- break;
- case METHOD_WEAVE:
- case METHOD_ADAPTIVE:
- mult=4;
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Internal error: PutVideo\n");
- mult=4;
- }
-
- id = FOURCC_YUY2;
-
- top = ya>>16;
-#if 0
- /* setting the ID above makes this useful - needs revisiting */
- switch(id) {
- case FOURCC_YV12:
- case FOURCC_I420:
- top &= ~1;
- dstPitch = ((width << 1) + 15) & ~15;
- srcPitch = (width + 3) & ~3;
- s2offset = srcPitch * height;
- srcPitch2 = ((width >> 1) + 3) & ~3;
- s3offset = (srcPitch2 * (height >> 1)) + s2offset;
- break;
- case FOURCC_UYVY:
- case FOURCC_YUY2:
- default:
- dstPitch = ((width<<1) + 15) & ~15;
- srcPitch = (width<<1);
- break;
- }
-#else
- dstPitch = ((width<<1) + 15) & ~15;
- srcPitch = (width<<1);
-#endif
-
- new_size = dstPitch * height;
- new_size = new_size + 0x1f; /* for aligning */
- alloc_size = new_size * mult;
- if (pPriv->capture_vbi_data)
- alloc_size += 2 * 2 * vbi_line_width * 21;
-
- pPriv->video_offset = RADEONAllocateMemory(pScrn, &pPriv->video_memory,
- (pPriv->doubleBuffer ?
- (new_size * 2) : new_size));
- if (pPriv->video_offset == 0)
- return BadAlloc;
-
-/* I have suspicion that capture engine must be active _before_ Rage Theatre
- is being manipulated with.. */
-
- RADEONWaitForIdleMMIO(pScrn);
- display_base=INREG(RADEON_DISPLAY_BASE_ADDR);
-
-/* RADEONWaitForFifo(pScrn, 15); */
-
- switch(pPriv->overlay_deinterlacing_method){
- case METHOD_BOB:
- case METHOD_SINGLE:
- offset1 = (pPriv->video_offset + 0xf) & (~0xf);
- offset2 = (pPriv->video_offset + new_size + 0xf) & (~0xf);
- offset3 = offset1;
- offset4 = offset2;
- break;
- case METHOD_WEAVE:
- offset1 = (pPriv->video_offset + 0xf) & (~0xf);
- offset2 = offset1+dstPitch;
- offset3 = (pPriv->video_offset + 2 * new_size + 0xf) & (~0xf);
- offset4 = offset3+dstPitch;
- break;
- default:
- offset1 = (pPriv->video_offset + 0xf) & (~0xf);
- offset2 = (pPriv->video_offset + new_size + 0xf) & (~0xf);
- offset3 = offset1;
- offset4 = offset2;
- }
-
- OUTREG(RADEON_CAP0_BUF0_OFFSET, offset1+display_base);
- OUTREG(RADEON_CAP0_BUF0_EVEN_OFFSET, offset2+display_base);
- OUTREG(RADEON_CAP0_BUF1_OFFSET, offset3+display_base);
- OUTREG(RADEON_CAP0_BUF1_EVEN_OFFSET, offset4+display_base);
-
- OUTREG(RADEON_CAP0_ONESHOT_BUF_OFFSET, offset1+display_base);
-
- if(pPriv->capture_vbi_data){
- if ((pPriv->encoding==2)||(pPriv->encoding==8)) {
- /* PAL, SECAM */
- vbi_start = 5;
- vbi_end = 21;
- } else {
- /* NTSC */
- vbi_start = 8;
- vbi_end = 20;
- }
-
- vbi_offset0 = (pPriv->video_offset + mult * new_size * bpp + 0xf) & (~0xf);
- vbi_offset1 = vbi_offset0 + dstPitch*20;
- OUTREG(RADEON_CAP0_VBI0_OFFSET, vbi_offset0+display_base);
- OUTREG(RADEON_CAP0_VBI1_OFFSET, vbi_offset1+display_base);
- OUTREG(RADEON_CAP0_VBI2_OFFSET, 0);
- OUTREG(RADEON_CAP0_VBI3_OFFSET, 0);
- OUTREG(RADEON_CAP0_VBI_V_WINDOW, vbi_start | (vbi_end<<16));
- OUTREG(RADEON_CAP0_VBI_H_WINDOW, 0 | (vbi_line_width)<<16);
- }
-
- OUTREG(RADEON_CAP0_BUF_PITCH, dstPitch*mult/2);
- OUTREG(RADEON_CAP0_H_WINDOW, (2*width)<<16);
- OUTREG(RADEON_CAP0_V_WINDOW, (((height)+pPriv->v-1)<<16)|(pPriv->v-1));
- if(mult==2){
- OUTREG(RADEON_CAP0_CONFIG, ENABLE_RADEON_CAPTURE_BOB);
- } else {
- OUTREG(RADEON_CAP0_CONFIG, ENABLE_RADEON_CAPTURE_WEAVE);
- }
- OUTREG(RADEON_CAP0_DEBUG, 0);
-
- OUTREG(RADEON_VID_BUFFER_CONTROL, (1<<16) | 0x01);
- OUTREG(RADEON_TEST_DEBUG_CNTL, 0);
-
- if(! pPriv->video_stream_active)
- {
-
- RADEONWaitForIdleMMIO(pScrn);
- OUTREG(RADEON_VIDEOMUX_CNTL, INREG(RADEON_VIDEOMUX_CNTL)|1 );
- OUTREG(RADEON_CAP0_PORT_MODE_CNTL, (pPriv->theatre!=NULL)? 1: 0);
- OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_PCLK);
- OUTREG(RADEON_CAP0_TRIG_CNTL, 0x11);
- if(pPriv->theatre != NULL)
- {
- RADEON_RT_SetEncoding(pScrn, pPriv);
- }
- if(pPriv->msp3430 != NULL) RADEON_MSP_SetEncoding(pPriv);
- if(pPriv->tda9885 != NULL) RADEON_TDA9885_SetEncoding(pPriv);
- if(pPriv->fi1236 != NULL) RADEON_FI1236_SetEncoding(pPriv);
- if(pPriv->i2c != NULL)RADEON_board_setmisc(pPriv);
- }
-
-
- /* update cliplist */
- if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) {
- REGION_COPY(pScreen, &pPriv->clip, clipBoxes);
- /* draw these */
- if(pPriv->autopaint_colorkey)
- RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes);
- }
-
- RADEONDisplayVideo(pScrn, crtc, pPriv, id, offset1+top*srcPitch, offset2+top*srcPitch,
- offset3+top*srcPitch, offset4+top*srcPitch, offset1+top*srcPitch,
- offset2+top*srcPitch, width, height, dstPitch*mult/2,
- xa, xb, ya, &dstBox, src_w, src_h*mult/2, drw_w, drw_h, pPriv->overlay_deinterlacing_method);
-
- RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK);
- RADEONWaitForIdleMMIO(pScrn);
- while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_LOCK_READBACK));
-
-
- switch(pPriv->overlay_deinterlacing_method){
- case METHOD_BOB:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA);
- OUTREG(RADEON_OV0_AUTO_FLIP_CNTL,0 /*| RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD*/
- |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN);
- break;
- case METHOD_SINGLE:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xEEEEE | (9<<28));
- OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD
- |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN);
- break;
- case METHOD_WEAVE:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0x11111 | (9<<28));
- OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, 0 |RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD
- | RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN
- /* |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN */
- /*|RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN */
- |RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE);
- break;
- default:
- OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA);
- OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD
- |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN);
- }
-
-
- RADEONWaitForIdleMMIO(pScrn);
- OUTREG (RADEON_OV0_AUTO_FLIP_CNTL, (INREG (RADEON_OV0_AUTO_FLIP_CNTL) ^ RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE ));
- OUTREG (RADEON_OV0_AUTO_FLIP_CNTL, (INREG (RADEON_OV0_AUTO_FLIP_CNTL) ^ RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE ));
-
- OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0);
-
-#if 0
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "OV0_FLAG_CNTL=0x%08x\n", INREG(RADEON_OV0_FLAG_CNTL));
-/* OUTREG(RADEON_OV0_FLAG_CNTL, 8); */
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "OV0_VID_BUFFER_CNTL=0x%08x\n", INREG(RADEON_VID_BUFFER_CONTROL));
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CAP0_BUF_STATUS=0x%08x\n", INREG(RADEON_CAP0_BUF_STATUS));
-
-/* OUTREG(RADEON_OV0_SCALE_CNTL, 0x417f1B00); */
-#endif
-
- pPriv->videoStatus = CLIENT_VIDEO_ON;
- pPriv->video_stream_active = TRUE;
-
- info->VideoTimerCallback = RADEONVideoTimerCallback;
-
- return Success;
-}
- /* miscellaneous TV-in helper functions */
-
-static void RADEON_board_setmisc(RADEONPortPrivPtr pPriv)
-{
- /* Adjust PAL/SECAM constants for FI1216MF tuner */
- if((((pPriv->tuner_type & 0xf)==5) ||
- ((pPriv->tuner_type & 0xf)==11)||
- ((pPriv->tuner_type & 0xf)==14))
- && (pPriv->fi1236!=NULL))
- {
- if((pPriv->encoding>=1)&&(pPriv->encoding<=3)) /*PAL*/
- {
- pPriv->fi1236->parm.band_low = 0xA1;
- pPriv->fi1236->parm.band_mid = 0x91;
- pPriv->fi1236->parm.band_high = 0x31;
- }
- if((pPriv->encoding>=7)&&(pPriv->encoding<=9)) /*SECAM*/
- {
- pPriv->fi1236->parm.band_low = 0xA3;
- pPriv->fi1236->parm.band_mid = 0x93;
- pPriv->fi1236->parm.band_high = 0x33;
- }
- }
-
-}
-
-static void RADEON_RT_SetEncoding(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
-int width, height;
-RADEONWaitForIdleMMIO(pScrn);
-
-/* Disable VBI capture for anything but TV tuner */
-switch(pPriv->encoding){
- case 2:
- case 5:
- case 8:
- pPriv->capture_vbi_data=1;
- break;
- default:
- pPriv->capture_vbi_data=0;
- }
-
-switch(pPriv->encoding){
- case 1:
- xf86_RT_SetConnector(pPriv->theatre,DEC_COMPOSITE, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL);
- pPriv->v=25;
- break;
- case 2:
- xf86_RT_SetConnector(pPriv->theatre,DEC_TUNER,0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL);
- pPriv->v=25;
- break;
- case 3:
- xf86_RT_SetConnector(pPriv->theatre,DEC_SVIDEO,0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL);
- pPriv->v=25;
- break;
- case 4:
- xf86_RT_SetConnector(pPriv->theatre, DEC_COMPOSITE,0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_NTSC | extNONE);
- pPriv->v=23;
- break;
- case 5:
- xf86_RT_SetConnector(pPriv->theatre, DEC_TUNER, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_NTSC | extNONE);
- pPriv->v=23;
- break;
- case 6:
- xf86_RT_SetConnector(pPriv->theatre, DEC_SVIDEO, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_NTSC | extNONE);
- pPriv->v=23;
- break;
- case 7:
- xf86_RT_SetConnector(pPriv->theatre, DEC_COMPOSITE, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_SECAM | extNONE);
- pPriv->v=25;
- break;
- case 8:
- xf86_RT_SetConnector(pPriv->theatre, DEC_TUNER, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_SECAM | extNONE);
- pPriv->v=25;
- break;
- case 9:
- xf86_RT_SetConnector(pPriv->theatre, DEC_SVIDEO, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_SECAM | extNONE);
- pPriv->v=25;
- break;
- case 10:
- xf86_RT_SetConnector(pPriv->theatre,DEC_COMPOSITE, 0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL_60);
- pPriv->v=25;
- break;
- case 11:
- xf86_RT_SetConnector(pPriv->theatre,DEC_TUNER,0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL_60);
- pPriv->v=25;
- break;
- case 12:
- xf86_RT_SetConnector(pPriv->theatre,DEC_SVIDEO,0);
- xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL_60);
- pPriv->v=25;
- break;
- default:
- pPriv->v=0;
- return;
- }
-xf86_RT_SetInterlace(pPriv->theatre, 1);
-width = InputVideoEncodings[pPriv->encoding].width;
-height = InputVideoEncodings[pPriv->encoding].height;
-xf86_RT_SetOutputVideoSize(pPriv->theatre, width, height*2, 0, pPriv->capture_vbi_data);
-}
-
-static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv)
-{
-xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_FAST_MUTE);
-switch(pPriv->encoding){
- case 1:
- pPriv->msp3430->standard = MSP3430_PAL;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_3;
- break;
- case 2:
- pPriv->msp3430->standard = MSP3430_PAL;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_1;
- break;
- case 3:
- pPriv->msp3430->standard = MSP3430_PAL;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_2;
- break;
- case 4:
- pPriv->msp3430->standard = MSP3430_NTSC;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_3;
- break;
- case 5:
- pPriv->msp3430->standard = MSP3430_NTSC;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_1;
- break;
- case 6:
- pPriv->msp3430->standard = MSP3430_NTSC;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_2;
- break;
- case 7:
- pPriv->msp3430->standard = MSP3430_SECAM;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_3;
- break;
- case 8:
- pPriv->msp3430->standard = MSP3430_SECAM;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_1;
- break;
- case 9:
- pPriv->msp3430->standard = MSP3430_SECAM;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_2;
- break;
- case 10:
- pPriv->msp3430->standard = MSP3430_SECAM;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_3;
- break;
- case 11:
- pPriv->msp3430->standard = MSP3430_SECAM;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_1;
- break;
- case 12:
- pPriv->msp3430->standard = MSP3430_SECAM;
- pPriv->msp3430->connector = MSP3430_CONNECTOR_2;
- break;
- default:
- return;
- }
-xf86_InitMSP3430(pPriv->msp3430);
-xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume));
-}
-
-static void RADEON_TDA9885_SetEncoding(RADEONPortPrivPtr pPriv)
-{
-TDA9885Ptr t=pPriv->tda9885;
-
-switch(pPriv->encoding){
- /* PAL */
- case 1:
- case 2:
- case 3:
- t->standard_video_if=2;
- t->standard_sound_carrier=1;
- t->modulation=2; /* negative FM */
- break;
- /* NTSC */
- case 4:
- case 5:
- case 6:
- t->standard_video_if=1;
- t->standard_sound_carrier=0;
- t->modulation=2; /* negative FM */
- break;
- /* SECAM */
- case 7:
- case 8:
- case 9:
- case 10:
- case 11:
- case 12:
- t->standard_video_if=0;
- t->standard_sound_carrier=3;
- t->modulation=0; /* positive AM */
- break;
- default:
- return;
- }
-xf86_tda9885_setparameters(pPriv->tda9885);
-xf86_tda9885_getstatus(pPriv->tda9885);
-xf86_tda9885_dumpstatus(pPriv->tda9885);
-}
-
-static void RADEON_FI1236_SetEncoding(RADEONPortPrivPtr pPriv)
-{
-/* at the moment this only affect MT2032 */
-switch(pPriv->encoding){
- /* PAL */
- case 1:
- case 2:
- case 3:
- pPriv->fi1236->video_if=38.900;
- break;
- /* NTSC */
- case 4:
- case 5:
- case 6:
- pPriv->fi1236->video_if=45.7812;
- pPriv->fi1236->video_if=45.750;
- pPriv->fi1236->video_if=45.125;
- break;
- /* SECAM */
- case 7:
- case 8:
- case 9:
- case 10:
- case 11:
- case 12:
- pPriv->fi1236->video_if=58.7812;
- break;
- default:
- return;
- }
-}
-
diff --git a/src/radeon_video.h b/src/radeon_video.h
deleted file mode 100644
index f897e07..0000000
--- a/src/radeon_video.h
+++ /dev/null
@@ -1,145 +0,0 @@
-#ifndef __RADEON_VIDEO_H__
-#define __RADEON_VIDEO_H__
-
-#include "xf86i2c.h"
-#include "fi1236.h"
-#include "msp3430.h"
-#include "tda9885.h"
-#include "uda1380.h"
-#include "i2c_def.h"
-
-#include "generic_bus.h"
-#include "theatre.h"
-
-#include "xf86Crtc.h"
-
-/* Xvideo port struct */
-typedef struct {
- CARD32 transform_index;
- CARD32 gamma; /* gamma value x 1000 */
- int brightness;
- int saturation;
- int hue;
- int contrast;
- int red_intensity;
- int green_intensity;
- int blue_intensity;
-
- /* overlay composition mode */
- int alpha_mode; /* 0 = key mode, 1 = global mode */
- int ov_alpha;
- int gr_alpha;
-
- /* i2c bus and devices */
- I2CBusPtr i2c;
- CARD32 radeon_i2c_timing;
- CARD32 radeon_M;
- CARD32 radeon_N;
- CARD32 i2c_status;
- CARD32 i2c_cntl;
-
- FI1236Ptr fi1236;
- CARD8 tuner_type;
- MSP3430Ptr msp3430;
- TDA9885Ptr tda9885;
- UDA1380Ptr uda1380;
-
- /* VIP bus and devices */
- GENERIC_BUS_Ptr VIP;
- TheatrePtr theatre;
-
- Bool video_stream_active;
- int encoding;
- CARD32 frequency;
- int volume;
- Bool mute;
- int sap_channel;
- int v;
- CARD32 adjustment; /* general purpose variable */
-
-#define METHOD_BOB 0
-#define METHOD_SINGLE 1
-#define METHOD_WEAVE 2
-#define METHOD_ADAPTIVE 3
-
- int overlay_deinterlacing_method;
-
- int capture_vbi_data;
-
- int dec_brightness;
- int dec_saturation;
- int dec_hue;
- int dec_contrast;
-
- Bool doubleBuffer;
- unsigned char currentBuffer;
- RegionRec clip;
- CARD32 colorKey;
- CARD32 videoStatus;
- Time offTime;
- Time freeTime;
- Bool autopaint_colorkey;
- xf86CrtcPtr desired_crtc;
-
- int size;
-#ifdef USE_EXA
- ExaOffscreenArea *off_screen;
-#endif
-
- void *video_memory;
- int video_offset;
-
- Atom device_id, location_id, instance_id;
-
- /* textured video */
- Bool textured;
- DrawablePtr pDraw;
- PixmapPtr pPixmap;
-
- CARD32 src_offset;
- CARD32 src_pitch;
- CARD8 *src_addr;
-
- int id;
- int src_w, src_h, dst_w, dst_h;
- int w, h;
- int drw_x, drw_y;
-} RADEONPortPrivRec, *RADEONPortPrivPtr;
-
-
-void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
-void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
-
-void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
-void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
-
-CARD32
-RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size);
-void
-RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct);
-
-int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer);
-int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer);
-void RADEONStopVideo(ScrnInfoPtr, pointer, Bool);
-void RADEONQueryBestSize(ScrnInfoPtr, Bool, short, short, short, short,
- unsigned int *, unsigned int *, pointer);
-int RADEONQueryImageAttributes(ScrnInfoPtr, int, unsigned short *,
- unsigned short *, int *, int *);
-
-XF86VideoAdaptorPtr
-RADEONSetupImageTexturedVideo(ScreenPtr pScreen);
-
-void
-RADEONCopyData(ScrnInfoPtr pScrn,
- unsigned char *src, unsigned char *dst,
- unsigned int srcPitch, unsigned int dstPitch,
- unsigned int h, unsigned int w, unsigned int bpp);
-
-void
-RADEONCopyMungedData(ScrnInfoPtr pScrn,
- unsigned char *src1, unsigned char *src2,
- unsigned char *src3, unsigned char *dst1,
- unsigned int srcPitch, unsigned int srcPitch2,
- unsigned int dstPitch, unsigned int h, unsigned int w);
-
-#endif
diff --git a/src/radeon_vip.c b/src/radeon_vip.c
deleted file mode 100644
index 7ee4ab5..0000000
--- a/src/radeon_vip.c
+++ /dev/null
@@ -1,362 +0,0 @@
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-
-#include "radeon.h"
-#include "radeon_reg.h"
-#include "radeon_macros.h"
-#include "radeon_probe.h"
-#include <X11/extensions/Xv.h>
-#include "radeon_video.h"
-
-#include "xf86.h"
-#include "atipciids.h"
-
-#include "generic_bus.h"
-#include "theatre_reg.h"
-
-#define VIP_NAME "RADEON VIP BUS"
-#define VIP_TYPE "ATI VIP BUS"
-
-/* Status defines */
-#define VIP_BUSY 0
-#define VIP_IDLE 1
-#define VIP_RESET 2
-
-static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2)
-{
- long count;
- switch(ioctl){
- case GB_IOCTL_GET_NAME:
- count=strlen(VIP_NAME)+1;
- if(count>arg1)return FALSE;
- memcpy(arg2,VIP_NAME,count);
- return TRUE;
-
- case GB_IOCTL_GET_TYPE:
- count=strlen(VIP_TYPE)+1;
- if(count>arg1)return FALSE;
- memcpy(arg2,VIP_TYPE,count);
- return TRUE;
-
- default:
- return FALSE;
- }
-}
-
-static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- CARD32 timeout;
-
- RADEONWaitForIdleMMIO(pScrn);
- timeout = INREG(RADEON_VIPH_TIMEOUT_STAT);
- if(timeout & RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT) /* lockup ?? */
- {
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK);
- RADEONWaitForIdleMMIO(pScrn);
- return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
- }
- RADEONWaitForIdleMMIO(pScrn);
- return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
-}
-
-static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- CARD32 timeout;
-
- RADEONWaitForIdleMMIO(pScrn);
- timeout = INREG(VIPH_TIMEOUT_STAT);
- if((timeout & 0x0000000f) & channel) /* lockup ?? */
- {
- xf86DrvMsg(b->scrnIndex, X_INFO, "RADEON_fifo_idle\n");
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
- RADEONWaitForIdleMMIO(pScrn);
- return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
- }
- RADEONWaitForIdleMMIO(pScrn);
- return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
-}
-
-/* address format:
- ((device & 0x3)<<14) | (fifo << 12) | (addr)
-*/
-
-#define VIP_WAIT_FOR_IDLE() { \
- int i2ctries = 0; \
- while (i2ctries < 10) { \
- status = RADEONVIP_idle(b); \
- if (status==VIP_BUSY) \
- { \
- usleep(1000); \
- i2ctries++; \
- } else break; \
- } \
- }
-
-static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 status,tmp;
-
- if((count!=1) && (count!=2) && (count!=4))
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
- return FALSE;
- }
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_VIPH_REG_ADDR, address | 0x2000);
- write_mem_barrier();
- VIP_WAIT_FOR_IDLE();
- if(VIP_IDLE != status) return FALSE;
-
-/*
- disable RADEON_VIPH_REGR_DIS to enable VIP cycle.
- The LSB of RADEON_VIPH_TIMEOUT_STAT are set to 0
- because 1 would have acknowledged various VIP
- interrupts unexpectedly
-*/
- RADEONWaitForIdleMMIO(pScrn);
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
- write_mem_barrier();
-/*
- the value returned here is garbage. The read merely initiates
- a register cycle
-*/
- RADEONWaitForIdleMMIO(pScrn);
- INREG(RADEON_VIPH_REG_DATA);
-
- VIP_WAIT_FOR_IDLE();
- if(VIP_IDLE != status) return FALSE;
-/*
- set RADEON_VIPH_REGR_DIS so that the read won't take too long.
-*/
- RADEONWaitForIdleMMIO(pScrn);
- tmp=INREG(RADEON_VIPH_TIMEOUT_STAT);
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- write_mem_barrier();
- RADEONWaitForIdleMMIO(pScrn);
- switch(count){
- case 1:
- *buffer=(CARD8)(INREG(RADEON_VIPH_REG_DATA) & 0xff);
- break;
- case 2:
- *(CARD16 *)buffer=(CARD16) (INREG(RADEON_VIPH_REG_DATA) & 0xffff);
- break;
- case 4:
- *(CARD32 *)buffer=(CARD32) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff);
- break;
- }
- VIP_WAIT_FOR_IDLE();
- if(VIP_IDLE != status) return FALSE;
- /*
- so that reading RADEON_VIPH_REG_DATA would not trigger unnecessary vip cycles.
-*/
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- write_mem_barrier();
- return TRUE;
-}
-
-static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 status,tmp;
-
- if(count!=1)
- {
- xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
- return FALSE;
- }
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(VIPH_REG_ADDR, address | 0x3000);
- write_mem_barrier();
- while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
- if(VIP_IDLE != status) return FALSE;
-
-/*
- disable VIPH_REGR_DIS to enable VIP cycle.
- The LSB of VIPH_TIMEOUT_STAT are set to 0
- because 1 would have acknowledged various VIP
- interrupts unexpectedly
-*/
-
- RADEONWaitForIdleMMIO(pScrn);
- OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
- write_mem_barrier();
-
-/*
- the value returned here is garbage. The read merely initiates
- a register cycle
-*/
- RADEONWaitForIdleMMIO(pScrn);
- INREG(VIPH_REG_DATA);
-
- while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
- if(VIP_IDLE != status) return FALSE;
-
-/*
- set VIPH_REGR_DIS so that the read won't take too long.
-*/
- RADEONWaitForIdleMMIO(pScrn);
- tmp=INREG(VIPH_TIMEOUT_STAT);
- OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- write_mem_barrier();
-
- RADEONWaitForIdleMMIO(pScrn);
- switch(count){
- case 1:
- *buffer=(CARD8)(INREG(VIPH_REG_DATA) & 0xff);
- break;
- case 2:
- *(CARD16 *)buffer=(CARD16) (INREG(VIPH_REG_DATA) & 0xffff);
- break;
- case 4:
- *(CARD32 *)buffer=(CARD32) ( INREG(VIPH_REG_DATA) & 0xffffffff);
- break;
- }
- while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
- if(VIP_IDLE != status) return FALSE;
-
- /*
- so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
-*/
- OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- write_mem_barrier();
- return TRUE;
-
-
-}
-
-
-static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- CARD32 status;
-
-
- if((count!=4))
- {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to access VIP bus with non-stadard transaction length\n");
- return FALSE;
- }
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000));
- while(VIP_BUSY == (status = RADEONVIP_idle(b)));
-
- if(VIP_IDLE != status) return FALSE;
-
- RADEONWaitForFifo(pScrn, 2);
- switch(count){
- case 4:
- OUTREG(RADEON_VIPH_REG_DATA, *(CARD32 *)buffer);
- break;
- }
- write_mem_barrier();
- while(VIP_BUSY == (status = RADEONVIP_idle(b)));
- if(VIP_IDLE != status) return FALSE;
- return TRUE;
-}
-
-static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer)
-{
- ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
- CARD32 status;
- CARD32 i;
-
- RADEONWaitForFifo(pScrn, 2);
- OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000);
- while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
-
-
- if(VIP_IDLE != status){
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
- return FALSE;
- }
-
- RADEONWaitForFifo(pScrn, 2);
- for (i = 0; i < count; i+=4)
- {
- OUTREG(VIPH_REG_DATA, *(CARD32*)(buffer + i));
- write_mem_barrier();
- while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
- if(VIP_IDLE != status)
- {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write to VIPH_REG_DATA\n");
- return FALSE;
- }
- }
-
- return TRUE;
-}
-
-void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
-
-
- RADEONWaitForIdleMMIO(pScrn);
- switch(info->ChipFamily){
- case CHIP_FAMILY_RV250:
- case CHIP_FAMILY_RV350:
- case CHIP_FAMILY_R350:
- case CHIP_FAMILY_R300:
- OUTREG(RADEON_VIPH_CONTROL, 0x003F0009); /* slowest, timeout in 16 phases */
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
- OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
- OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
- break;
- case CHIP_FAMILY_RV380:
- OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
- OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
- OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
- break;
- default:
- OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */
- OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
- OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
- OUTREG(RADEON_VIPH_BM_CHUNK, 0x151);
- OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
- }
-}
-
-void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
-{
- pPriv->VIP=xcalloc(1,sizeof(GENERIC_BUS_Rec));
- pPriv->VIP->scrnIndex=pScrn->scrnIndex;
- pPriv->VIP->DriverPrivate.ptr=pPriv;
- pPriv->VIP->ioctl=RADEONVIP_ioctl;
- pPriv->VIP->read=RADEONVIP_read;
- pPriv->VIP->write=RADEONVIP_write;
- pPriv->VIP->fifo_read=RADEONVIP_fifo_read;
- pPriv->VIP->fifo_write=RADEONVIP_fifo_write;
-
- RADEONVIP_reset(pScrn, pPriv);
-}
diff --git a/src/theatre.c b/src/theatre.c
deleted file mode 100644
index a5aadfb..0000000
--- a/src/theatre.c
+++ /dev/null
@@ -1,2209 +0,0 @@
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <unistd.h>
-#include "xf86.h"
-#include "generic_bus.h"
-#include "theatre.h"
-#include "theatre_reg.h"
-
-#undef read
-#undef write
-#undef ioctl
-
-static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data);
-}
-
-static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data);
-}
-
-#define RT_regr(reg,data) theatre_read(t,(reg),(data))
-#define RT_regw(reg,data) theatre_write(t,(reg),(data))
-#define VIP_TYPE "ATI VIP BUS"
-
-
-#if 0
-TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b)
-{
- TheatrePtr t;
- CARD32 i;
- CARD32 val;
- char s[20];
-
- b->ioctl(b,GB_IOCTL_GET_TYPE,20,s);
- if(strcmp(VIP_TYPE, s)){
- xf86DrvMsg(b->scrnIndex, X_ERROR, "DetectTheatre must be called with bus of type \"%s\", not \"%s\"\n",
- VIP_TYPE, s);
- return NULL;
- }
-
- t = xcalloc(1,sizeof(TheatreRec));
- t->VIP = b;
- t->theatre_num = -1;
- t->mode=MODE_UNINITIALIZED;
-
- b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val);
- for(i=0;i<4;i++)
- {
- if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val))
- {
- if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n",i,val);
- if(t->theatre_num>=0)continue; /* already found one instance */
- switch(val){
- case RT100_ATI_ID:
- t->theatre_num=i;
- t->theatre_id=RT100_ATI_ID;
- break;
- case RT200_ATI_ID:
- t->theatre_num=i;
- t->theatre_id=RT200_ATI_ID;
- break;
- }
- } else {
- xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i);
- }
- }
- if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n",t->theatre_num,t->theatre_id);
-
- if(t->theatre_id==RT200_ATI_ID){
- xf86DrvMsg(b->scrnIndex, X_INFO, "Rage Theatre 200 is not supported yet\n");
- t->theatre_num=-1;
- }
-
- if(t->theatre_num < 0)
- {
- xfree(t);
- return NULL;
- }
-
- RT_regr(VIP_VIP_REVISION_ID, &val);
- xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n", val);
-
-#if 0
-DumpRageTheatreRegsByName(t);
-#endif
- return t;
-}
-#endif
-
-enum
-{
-fld_tmpReg1=0,
-fld_tmpReg2,
-fld_tmpReg3,
-fld_LP_CONTRAST,
-fld_LP_BRIGHTNESS,
-fld_CP_HUE_CNTL,
-fld_LUMA_FILTER,
-fld_H_SCALE_RATIO,
-fld_H_SHARPNESS,
-fld_V_SCALE_RATIO,
-fld_V_DEINTERLACE_ON,
-fld_V_BYPSS,
-fld_V_DITHER_ON,
-fld_EVENF_OFFSET,
-fld_ODDF_OFFSET,
-fld_INTERLACE_DETECTED,
-fld_VS_LINE_COUNT,
-fld_VS_DETECTED_LINES,
-fld_VS_ITU656_VB,
-fld_VBI_CC_DATA,
-fld_VBI_CC_WT,
-fld_VBI_CC_WT_ACK,
-fld_VBI_CC_HOLD,
-fld_VBI_DECODE_EN,
-fld_VBI_CC_DTO_P,
-fld_VBI_20BIT_DTO_P,
-fld_VBI_CC_LEVEL,
-fld_VBI_20BIT_LEVEL,
-fld_VBI_CLK_RUNIN_GAIN,
-fld_H_VBI_WIND_START,
-fld_H_VBI_WIND_END,
-fld_V_VBI_WIND_START,
-fld_V_VBI_WIND_END,
-fld_VBI_20BIT_DATA0,
-fld_VBI_20BIT_DATA1,
-fld_VBI_20BIT_WT,
-fld_VBI_20BIT_WT_ACK,
-fld_VBI_20BIT_HOLD,
-fld_VBI_CAPTURE_ENABLE,
-fld_VBI_EDS_DATA,
-fld_VBI_EDS_WT,
-fld_VBI_EDS_WT_ACK,
-fld_VBI_EDS_HOLD,
-fld_VBI_SCALING_RATIO,
-fld_VBI_ALIGNER_ENABLE,
-fld_H_ACTIVE_START,
-fld_H_ACTIVE_END,
-fld_V_ACTIVE_START,
-fld_V_ACTIVE_END,
-fld_CH_HEIGHT,
-fld_CH_KILL_LEVEL,
-fld_CH_AGC_ERROR_LIM,
-fld_CH_AGC_FILTER_EN,
-fld_CH_AGC_LOOP_SPEED,
-fld_HUE_ADJ,
-fld_STANDARD_SEL,
-fld_STANDARD_YC,
-fld_ADC_PDWN,
-fld_INPUT_SELECT,
-fld_ADC_PREFLO,
-fld_H_SYNC_PULSE_WIDTH,
-fld_HS_GENLOCKED,
-fld_HS_SYNC_IN_WIN,
-fld_VIN_ASYNC_RST,
-fld_DVS_ASYNC_RST,
-fld_VIP_VENDOR_ID,
-fld_VIP_DEVICE_ID,
-fld_VIP_REVISION_ID,
-fld_BLACK_INT_START,
-fld_BLACK_INT_LENGTH,
-fld_UV_INT_START,
-fld_U_INT_LENGTH,
-fld_V_INT_LENGTH,
-fld_CRDR_ACTIVE_GAIN,
-fld_CBDB_ACTIVE_GAIN,
-fld_DVS_DIRECTION,
-fld_DVS_VBI_CARD8_SWAP,
-fld_DVS_CLK_SELECT,
-fld_CONTINUOUS_STREAM,
-fld_DVSOUT_CLK_DRV,
-fld_DVSOUT_DATA_DRV,
-fld_COMB_CNTL0,
-fld_COMB_CNTL1,
-fld_COMB_CNTL2,
-fld_COMB_LENGTH,
-fld_SYNCTIP_REF0,
-fld_SYNCTIP_REF1,
-fld_CLAMP_REF,
-fld_AGC_PEAKWHITE,
-fld_VBI_PEAKWHITE,
-fld_WPA_THRESHOLD,
-fld_WPA_TRIGGER_LO,
-fld_WPA_TRIGGER_HIGH,
-fld_LOCKOUT_START,
-fld_LOCKOUT_END,
-fld_CH_DTO_INC,
-fld_PLL_SGAIN,
-fld_PLL_FGAIN,
-fld_CR_BURST_GAIN,
-fld_CB_BURST_GAIN,
-fld_VERT_LOCKOUT_START,
-fld_VERT_LOCKOUT_END,
-fld_H_IN_WIND_START,
-fld_V_IN_WIND_START,
-fld_H_OUT_WIND_WIDTH,
-fld_V_OUT_WIND_WIDTH,
-fld_HS_LINE_TOTAL,
-fld_MIN_PULSE_WIDTH,
-fld_MAX_PULSE_WIDTH,
-fld_WIN_CLOSE_LIMIT,
-fld_WIN_OPEN_LIMIT,
-fld_VSYNC_INT_TRIGGER,
-fld_VSYNC_INT_HOLD,
-fld_VIN_M0,
-fld_VIN_N0,
-fld_MNFLIP_EN,
-fld_VIN_P,
-fld_REG_CLK_SEL,
-fld_VIN_M1,
-fld_VIN_N1,
-fld_VIN_DRIVER_SEL,
-fld_VIN_MNFLIP_REQ,
-fld_VIN_MNFLIP_DONE,
-fld_TV_LOCK_TO_VIN,
-fld_TV_P_FOR_WINCLK,
-fld_VINRST,
-fld_VIN_CLK_SEL,
-fld_VS_FIELD_BLANK_START,
-fld_VS_FIELD_BLANK_END,
-fld_VS_FIELD_IDLOCATION,
-fld_VS_FRAME_TOTAL,
-fld_SYNC_TIP_START,
-fld_SYNC_TIP_LENGTH,
-fld_GAIN_FORCE_DATA,
-fld_GAIN_FORCE_EN,
-fld_I_CLAMP_SEL,
-fld_I_AGC_SEL,
-fld_EXT_CLAMP_CAP,
-fld_EXT_AGC_CAP,
-fld_DECI_DITHER_EN,
-fld_ADC_PREFHI,
-fld_ADC_CH_GAIN_SEL,
-fld_HS_PLL_SGAIN,
-fld_NREn,
-fld_NRGainCntl,
-fld_NRBWTresh,
-fld_NRGCTresh,
-fld_NRCoefDespeclMode,
-fld_GPIO_5_OE,
-fld_GPIO_6_OE,
-fld_GPIO_5_OUT,
-fld_GPIO_6_OUT,
-
-regRT_MAX_REGS
-} a;
-
-
-typedef struct {
- CARD8 size;
- CARD32 fld_id;
- CARD32 dwRegAddrLSBs;
- CARD32 dwFldOffsetLSBs;
- CARD32 dwMaskLSBs;
- CARD32 addr2;
- CARD32 offs2;
- CARD32 mask2;
- CARD32 dwCurrValue;
- CARD32 rw;
- } RTREGMAP;
-
-#define READONLY 1
-#define WRITEONLY 2
-#define READWRITE 3
-
-/* Rage Theatre's Register Mappings, including the default values: */
-RTREGMAP RT_RegMap[regRT_MAX_REGS]={
-/*
-{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W
-*/
-{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE },
-{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE },
-{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE },
-{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE },
-{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE },
-{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE },
-{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE },
-{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE },
-{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE },
-{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE },
-{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE },
-{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE },
-{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE },
-{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE },
-{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE },
-{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY },
-{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY },
-{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY },
-{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY },
-{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE },
-{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE },
-{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY },
-{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE },
-{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE },
-{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE },
-{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE },
-{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE },
-{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE },
-{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE },
-{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE },
-{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE },
-{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE },
-{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */
-{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE },
-{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE },
-{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE },
-{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY },
-{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE },
-{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE },
-{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE },
-{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE },
-{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY },
-{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE },
-{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE },
-{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE },
-{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE },
-{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE },
-{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE },
-{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE },
-{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE },
-{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE },
-{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE },
-{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE },
-{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE },
-{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE },
-{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE },
-{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE },
-{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE },
-{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE },
-{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE },
-{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY },
-{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY },
-{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY },
-{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE },
-{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE },
-{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY },
-{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY },
-{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY },
-{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE },
-{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE },
-{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE },
-{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE },
-{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE },
-{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE },
-{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE },
-{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE },
-{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE },
-{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE },
-{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE },
-{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE },
-{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE },
-{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE },
-{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE },
-{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE },
-{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE },
-{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE },
-{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE },
-{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE },
-{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE },
-{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE },
-{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE },
-{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE },
-{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE },
-{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE },
-{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE },
-{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE },
-{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE },
-{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE },
-{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE },
-{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE },
-{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE },
-{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE },
-{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE },
-{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE },
-{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE },
-{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE },
-{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE },
-{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE },
-{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE },
-{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE },
-{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE },
-{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE },
-{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE },
-{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE },
-{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE },
-{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE },
-{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE },
-{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE },
-{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE },
-{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE },
-{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE },
-{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE },
-{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY },
-{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE },
-{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE },
-{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE },
-{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE },
-{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE },
-{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE },
-{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE },
-{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE },
-{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE },
-{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE },
-{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE },
-{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE },
-{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE },
-{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE },
-{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE },
-{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE },
-{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE },
-{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE },
-{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE },
-{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE },
-{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE },
-{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE },
-{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE },
-{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE },
-{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE },
-{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE },
-{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE },
-{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE },
-{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE },
-};
-
-/* Rage Theatre's register fields default values: */
-CARD32 RT_RegDef[regRT_MAX_REGS]=
-{
-fld_tmpReg1_def,
-fld_tmpReg2_def,
-fld_tmpReg3_def,
-fld_LP_CONTRAST_def,
-fld_LP_BRIGHTNESS_def,
-fld_CP_HUE_CNTL_def,
-fld_LUMA_FILTER_def,
-fld_H_SCALE_RATIO_def,
-fld_H_SHARPNESS_def,
-fld_V_SCALE_RATIO_def,
-fld_V_DEINTERLACE_ON_def,
-fld_V_BYPSS_def,
-fld_V_DITHER_ON_def,
-fld_EVENF_OFFSET_def,
-fld_ODDF_OFFSET_def,
-fld_INTERLACE_DETECTED_def,
-fld_VS_LINE_COUNT_def,
-fld_VS_DETECTED_LINES_def,
-fld_VS_ITU656_VB_def,
-fld_VBI_CC_DATA_def,
-fld_VBI_CC_WT_def,
-fld_VBI_CC_WT_ACK_def,
-fld_VBI_CC_HOLD_def,
-fld_VBI_DECODE_EN_def,
-fld_VBI_CC_DTO_P_def,
-fld_VBI_20BIT_DTO_P_def,
-fld_VBI_CC_LEVEL_def,
-fld_VBI_20BIT_LEVEL_def,
-fld_VBI_CLK_RUNIN_GAIN_def,
-fld_H_VBI_WIND_START_def,
-fld_H_VBI_WIND_END_def,
-fld_V_VBI_WIND_START_def,
-fld_V_VBI_WIND_END_def,
-fld_VBI_20BIT_DATA0_def,
-fld_VBI_20BIT_DATA1_def,
-fld_VBI_20BIT_WT_def,
-fld_VBI_20BIT_WT_ACK_def,
-fld_VBI_20BIT_HOLD_def,
-fld_VBI_CAPTURE_ENABLE_def,
-fld_VBI_EDS_DATA_def,
-fld_VBI_EDS_WT_def,
-fld_VBI_EDS_WT_ACK_def,
-fld_VBI_EDS_HOLD_def,
-fld_VBI_SCALING_RATIO_def,
-fld_VBI_ALIGNER_ENABLE_def,
-fld_H_ACTIVE_START_def,
-fld_H_ACTIVE_END_def,
-fld_V_ACTIVE_START_def,
-fld_V_ACTIVE_END_def,
-fld_CH_HEIGHT_def,
-fld_CH_KILL_LEVEL_def,
-fld_CH_AGC_ERROR_LIM_def,
-fld_CH_AGC_FILTER_EN_def,
-fld_CH_AGC_LOOP_SPEED_def,
-fld_HUE_ADJ_def,
-fld_STANDARD_SEL_def,
-fld_STANDARD_YC_def,
-fld_ADC_PDWN_def,
-fld_INPUT_SELECT_def,
-fld_ADC_PREFLO_def,
-fld_H_SYNC_PULSE_WIDTH_def,
-fld_HS_GENLOCKED_def,
-fld_HS_SYNC_IN_WIN_def,
-fld_VIN_ASYNC_RST_def,
-fld_DVS_ASYNC_RST_def,
-fld_VIP_VENDOR_ID_def,
-fld_VIP_DEVICE_ID_def,
-fld_VIP_REVISION_ID_def,
-fld_BLACK_INT_START_def,
-fld_BLACK_INT_LENGTH_def,
-fld_UV_INT_START_def,
-fld_U_INT_LENGTH_def,
-fld_V_INT_LENGTH_def,
-fld_CRDR_ACTIVE_GAIN_def,
-fld_CBDB_ACTIVE_GAIN_def,
-fld_DVS_DIRECTION_def,
-fld_DVS_VBI_CARD8_SWAP_def,
-fld_DVS_CLK_SELECT_def,
-fld_CONTINUOUS_STREAM_def,
-fld_DVSOUT_CLK_DRV_def,
-fld_DVSOUT_DATA_DRV_def,
-fld_COMB_CNTL0_def,
-fld_COMB_CNTL1_def,
-fld_COMB_CNTL2_def,
-fld_COMB_LENGTH_def,
-fld_SYNCTIP_REF0_def,
-fld_SYNCTIP_REF1_def,
-fld_CLAMP_REF_def,
-fld_AGC_PEAKWHITE_def,
-fld_VBI_PEAKWHITE_def,
-fld_WPA_THRESHOLD_def,
-fld_WPA_TRIGGER_LO_def,
-fld_WPA_TRIGGER_HIGH_def,
-fld_LOCKOUT_START_def,
-fld_LOCKOUT_END_def,
-fld_CH_DTO_INC_def,
-fld_PLL_SGAIN_def,
-fld_PLL_FGAIN_def,
-fld_CR_BURST_GAIN_def,
-fld_CB_BURST_GAIN_def,
-fld_VERT_LOCKOUT_START_def,
-fld_VERT_LOCKOUT_END_def,
-fld_H_IN_WIND_START_def,
-fld_V_IN_WIND_START_def,
-fld_H_OUT_WIND_WIDTH_def,
-fld_V_OUT_WIND_WIDTH_def,
-fld_HS_LINE_TOTAL_def,
-fld_MIN_PULSE_WIDTH_def,
-fld_MAX_PULSE_WIDTH_def,
-fld_WIN_CLOSE_LIMIT_def,
-fld_WIN_OPEN_LIMIT_def,
-fld_VSYNC_INT_TRIGGER_def,
-fld_VSYNC_INT_HOLD_def,
-fld_VIN_M0_def,
-fld_VIN_N0_def,
-fld_MNFLIP_EN_def,
-fld_VIN_P_def,
-fld_REG_CLK_SEL_def,
-fld_VIN_M1_def,
-fld_VIN_N1_def,
-fld_VIN_DRIVER_SEL_def,
-fld_VIN_MNFLIP_REQ_def,
-fld_VIN_MNFLIP_DONE_def,
-fld_TV_LOCK_TO_VIN_def,
-fld_TV_P_FOR_WINCLK_def,
-fld_VINRST_def,
-fld_VIN_CLK_SEL_def,
-fld_VS_FIELD_BLANK_START_def,
-fld_VS_FIELD_BLANK_END_def,
-fld_VS_FIELD_IDLOCATION_def,
-fld_VS_FRAME_TOTAL_def,
-fld_SYNC_TIP_START_def,
-fld_SYNC_TIP_LENGTH_def,
-fld_GAIN_FORCE_DATA_def,
-fld_GAIN_FORCE_EN_def,
-fld_I_CLAMP_SEL_def,
-fld_I_AGC_SEL_def,
-fld_EXT_CLAMP_CAP_def,
-fld_EXT_AGC_CAP_def,
-fld_DECI_DITHER_EN_def,
-fld_ADC_PREFHI_def,
-fld_ADC_CH_GAIN_SEL_def,
-fld_HS_PLL_SGAIN_def,
-fld_NREn_def,
-fld_NRGainCntl_def,
-fld_NRBWTresh_def,
-fld_NRGCTresh_def,
-fld_NRCoefDespeclMode_def,
-fld_GPIO_5_OE_def,
-fld_GPIO_6_OE_def,
-fld_GPIO_5_OUT_def,
-fld_GPIO_6_OUT_def,
-};
-
-/****************************************************************************
- * WriteRT_fld (CARD32 dwReg, CARD32 dwData) *
- * Function: Writes a register field within Rage Theatre *
- * Inputs: CARD32 dwReg = register field to be written *
- * CARD32 dwData = data that will be written to the reg field *
- * Outputs: NONE *
- ****************************************************************************/
-static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData)
-{
- CARD32 dwResult=0;
- CARD32 dwValue=0;
-
- if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE)
- {
- dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) |
- (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs);
-
- if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE)
- {
- /* update the memory mapped registers */
- RT_RegMap[dwReg].dwCurrValue = dwData;
- }
-
- }
-
- return;
-
-} /* WriteRT_fld ()... */
-
-/****************************************************************************
- * ReadRT_fld (CARD32 dwReg) *
- * Function: Reads a register field within Rage Theatre *
- * Inputs: CARD32 dwReg = register field to be read *
- * Outputs: CARD32 - value read from register field *
- ****************************************************************************/
-static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg)
-{
- CARD32 dwResult=0;
-
- if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE)
- {
- RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >>
- RT_RegMap[dwReg].dwFldOffsetLSBs);
- return (RT_RegMap[dwReg].dwCurrValue);
- }
- else
- {
- return (0xFFFFFFFF);
- }
-
-} /* ReadRT_fld ()... */
-
-#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b))
-#define ReadRT_fld(a) ReadRT_fld1(t,(a))
-
-/****************************************************************************
- * RT_SetVINClock (CARD16 wStandard) *
- * Function: to set the VIN clock for the selected standard *
- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * Outputs: NONE *
- ****************************************************************************/
-static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard)
-{
- CARD32 dwM0=0, dwN0=0, dwP=0;
- CARD8 ref_freq;
-
- /* Determine the reference frequency first. This can be obtained
- from the MMTABLE.video_decoder_type field (bits 4:7)
- The Rage Theatre currently only supports reference frequencies of
- 27 or 29.49 MHz. */
- /*
- R128ReadBIOS(0x48,
- (CARD8 *)&bios_header, sizeof(bios_header));
- R128ReadBIOS(bios_header + 0x30,
- (CARD8 *)&pll_info_block, sizeof(pll_info_block));
-
- R128ReadBIOS(pll_info_block+0x07, &video_decoder_type, sizeof(video_decoder_type));
- */
- ref_freq = (t->video_decoder_type & 0xF0) >> 4;
-
-
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC): /* NTSC GROUP - 480 lines */
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extNTSC):
- case (extNTSC_J):
- if (ref_freq == RT_FREF_2950)
- {
- dwM0 = 0x39;
- dwN0 = 0x14C;
- dwP = 0x6;
- }
- else
- {
- dwM0 = 0x0B;
- dwN0 = 0x46;
- dwP = 0x6;
- }
- break;
-
- case (extNTSC_443):
- if (ref_freq == RT_FREF_2950)
- {
- dwM0 = 0x23;
- dwN0 = 0x88;
- dwP = 0x7;
- }
- else
- {
- dwM0 = 0x2C;
- dwN0 = 0x121;
- dwP = 0x5;
- }
- break;
-
- case (extPAL_M):
- if (ref_freq == RT_FREF_2950)
- {
- dwM0 = 0x2C;
- dwN0 = 0x12B;
- dwP = 0x7;
- }
- else
- {
- dwM0 = 0x0B;
- dwN0 = 0x46;
- dwP = 0x6;
- }
- break;
-
- default:
- return;
- }
- break;
- case (DEC_PAL):
- switch (wStandard & 0xFF00)
- {
- case (extPAL):
- case (extPAL_N):
- case (extPAL_BGHI):
- case (extPAL_60):
- if (ref_freq == RT_FREF_2950)
- {
- dwM0 = 0x0E;
- dwN0 = 0x65;
- dwP = 0x6;
- }
- else
- {
- dwM0 = 0x2C;
- dwN0 = 0x0121;
- dwP = 0x5;
- }
- break;
-
- case (extPAL_NCOMB):
- if (ref_freq == RT_FREF_2950)
- {
- dwM0 = 0x23;
- dwN0 = 0x88;
- dwP = 0x7;
- }
- else
- {
- dwM0 = 0x37;
- dwN0 = 0x1D3;
- dwP = 0x8;
- }
- break;
-
- default:
- return;
- }
- break;
-
- case (DEC_SECAM):
- if (ref_freq == RT_FREF_2950)
- {
- dwM0 = 0xE;
- dwN0 = 0x65;
- dwP = 0x6;
- }
- else
- {
- dwM0 = 0x2C;
- dwN0 = 0x121;
- dwP = 0x5;
- }
- break;
- }
-
- /* VIN_PLL_CNTL */
- WriteRT_fld (fld_VIN_M0, dwM0);
- WriteRT_fld (fld_VIN_N0, dwN0);
- WriteRT_fld (fld_VIN_P, dwP);
-
- return;
-} /* RT_SetVINClock ()... */
-
-/****************************************************************************
- * RT_SetTint (int hue) *
- * Function: sets the tint (hue) for the Rage Theatre video in *
- * Inputs: int hue - the hue value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetTint (TheatrePtr t, int hue)
-{
- CARD32 nhue = 0;
-
- t->iHue=hue;
- /* Scale hue value from -1000<->1000 to -180<->180 */
- hue = (double)(hue+1000) * 0.18 - 180;
-
- /* Validate Hue level */
- if (hue < -180)
- {
- hue = -180;
- }
- else if (hue > 180)
- {
- hue = 180;
- }
-
- /* save the "validated" hue, but scale it back up to -1000<->1000 */
- t->iHue = (double)hue/0.18;
-
- switch (t->wStandard & 0x00FF)
- {
- case (DEC_NTSC): /* original ATI code had _empty_ section for PAL/SECAM... which did not work,
- obviously */
- case (DEC_PAL):
- case (DEC_SECAM):
- if (hue >= 0)
- {
- nhue = (CARD32) (256 * hue)/360;
- }
- else
- {
- nhue = (CARD32) (256 * (hue + 360))/360;
- }
- break;
-
- default: break;
- }
-
- WriteRT_fld(fld_CP_HUE_CNTL, nhue);
-
- return;
-
-} /* RT_SetTint ()... */
-
-
-/****************************************************************************
- * RT_SetSaturation (int Saturation) *
- * Function: sets the saturation level for the Rage Theatre video in *
- * Inputs: int Saturation - the saturation value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetSaturation (TheatrePtr t, int Saturation)
-{
- CARD16 wSaturation_V, wSaturation_U;
- double dbSaturation = 0, dbCrGain = 0, dbCbGain = 0;
-
- /* VALIDATE SATURATION LEVEL */
- if (Saturation < -1000L)
- {
- Saturation = -1000;
- }
- else if (Saturation > 1000L)
- {
- Saturation = 1000;
- }
-
- t->iSaturation = Saturation;
-
- if (Saturation > 0)
- {
- /* Scale saturation up, to use full allowable register width */
- Saturation = (double)(Saturation) * 4.9;
- }
-
- dbSaturation = (double) (Saturation+1000.0) / 1000.0;
-
- CalculateCrCbGain (t, &dbCrGain, &dbCbGain, t->wStandard);
-
- wSaturation_U = (CARD16) ((dbCrGain * dbSaturation * 128.0) + 0.5);
- wSaturation_V = (CARD16) ((dbCbGain * dbSaturation * 128.0) + 0.5);
-
- /* SET SATURATION LEVEL */
- WriteRT_fld (fld_CRDR_ACTIVE_GAIN, wSaturation_U);
- WriteRT_fld (fld_CBDB_ACTIVE_GAIN, wSaturation_V);
-
- t->wSaturation_U = wSaturation_U;
- t->wSaturation_V = wSaturation_V;
-
- return;
-
-} /* RT_SetSaturation ()...*/
-
-/****************************************************************************
- * RT_SetBrightness (int Brightness) *
- * Function: sets the brightness level for the Rage Theatre video in *
- * Inputs: int Brightness - the brightness value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetBrightness (TheatrePtr t, int Brightness)
-{
- double dbSynctipRef0=0, dbContrast=1;
-
- double dbYgain=0;
- double dbBrightness=0;
- double dbSetup=0;
- CARD16 wBrightness=0;
-
- /* VALIDATE BRIGHTNESS LEVEL */
- if (Brightness < -1000)
- {
- Brightness = -1000;
- }
- else if (Brightness > 1000)
- {
- Brightness = 1000;
- }
-
- /* Save value */
- t->iBrightness = Brightness;
-
- t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0;
-
- dbBrightness = (double) (Brightness)/10.0;
-
- dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0);
-
- if(t->dbContrast == 0)
- {
- t->dbContrast = 1.0; /*NTSC default; */
- }
-
- dbContrast = (double) t->dbContrast;
-
- /* Use the following formula to determine the brightness level */
- switch (t->wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- if ((t->wStandard & 0xFF00) == extNTSC_J)
- {
- dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /40.0);
- }
- else
- {
- dbSetup = 7.5 * (double)(dbSynctipRef0) / 40.0;
- dbYgain = 219.0 / (92.5 * (double)(dbSynctipRef0) / 40.0);
- }
- break;
- case (DEC_PAL):
- case (DEC_SECAM):
- dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /43.0);
- break;
- default:
- break;
- }
-
- wBrightness = (CARD16) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain))));
-
- WriteRT_fld (fld_LP_BRIGHTNESS, wBrightness);
-
- /*RT_SetSaturation (t->iSaturation); */
-
- return;
-
-} /* RT_SetBrightness ()... */
-
-
-/****************************************************************************
- * RT_SetSharpness (CARD16 wSharpness) *
- * Function: sets the sharpness level for the Rage Theatre video in *
- * Inputs: CARD16 wSharpness - the sharpness value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness)
-{
- switch (wSharpness)
- {
- case DEC_SMOOTH :
- WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS);
- t->wSharpness = RT_NORM_SHARPNESS;
- break;
- case DEC_SHARP :
- WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS);
- t->wSharpness = RT_HIGH_SHARPNESS;
- break;
- default:
- break;
- }
- return;
-
-} /* RT_SetSharpness ()... */
-
-
-/****************************************************************************
- * RT_SetContrast (int Contrast) *
- * Function: sets the contrast level for the Rage Theatre video in *
- * Inputs: int Contrast - the contrast value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetContrast (TheatrePtr t, int Contrast)
-{
- double dbSynctipRef0=0, dbContrast=0;
- double dbYgain=0;
- CARD8 bTempContrast=0;
-
- /* VALIDATE CONTRAST LEVEL */
- if (Contrast < -1000)
- {
- Contrast = -1000;
- }
- else if (Contrast > 1000)
- {
- Contrast = 1000;
- }
-
- /* Save contrast value */
- t->iContrast = Contrast;
-
- dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0);
- dbContrast = (double) (Contrast+1000.0) / 1000.0;
-
- switch (t->wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- if ((t->wStandard & 0xFF00) == (extNTSC_J))
- {
- dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /40.0);
- }
- else
- {
- dbYgain = 219.0 / ( 92.5 * (double)(dbSynctipRef0) /40.0);
- }
- break;
- case (DEC_PAL):
- case (DEC_SECAM):
- dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /43.0);
- break;
- default:
- break;
- }
-
- bTempContrast = (CARD8) ((dbContrast * dbYgain * 64) + 0.5);
-
- WriteRT_fld (fld_LP_CONTRAST, (CARD32)bTempContrast);
-
- /* Save value for future modification */
- t->dbContrast = dbContrast;
-
- return;
-
-} /* RT_SetContrast ()... */
-
-/****************************************************************************
- * RT_SetInterlace (CARD8 bInterlace) *
- * Function: to set the interlacing pattern for the Rage Theatre video in *
- * Inputs: CARD8 bInterlace *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace)
-{
-
- switch(bInterlace)
- {
- case (TRUE): /*DEC_INTERLACE */
- WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1);
- t->wInterlaced = (CARD16) RT_DECINTERLACED;
- break;
- case (FALSE): /*DEC_NONINTERLACE */
- WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED);
- t->wInterlaced = (CARD16) RT_DECNONINTERLACED;
- break;
- default:
- break;
- }
-
- return;
-
-} /* RT_SetInterlace ()... */
-
-/****************************************************************************
- * GetStandardConstants (double *LPeriod, double *FPeriod, *
- * double *Fsamp, CARD16 wStandard) *
- * Function: return timing values for a given standard *
- * Inputs: double *LPeriod -
- * double *FPeriod -
- * double *Fsamp - sampling frequency used for a given standard *
- * CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * Outputs: NONE *
- ****************************************************************************/
-static void GetStandardConstants (double *LPeriod, double *FPeriod,
- double *Fsamp, CARD16 wStandard)
-{
- *LPeriod = 0.0;
- *FPeriod = 0.0;
- *Fsamp = 0.0;
-
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC): /*NTSC GROUP - 480 lines*/
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extNTSC):
- case (extNTSC_J):
- *LPeriod = (double) 63.5555;
- *FPeriod = (double) 16.6833;
- *Fsamp = (double) 28.63636;
- break;
- case (extPAL_M):
- *LPeriod = (double) 63.492;
- *FPeriod = (double) 16.667;
- *Fsamp = (double) 28.63689192;
- break;
- default:
- return;
- }
- break;
- case (DEC_PAL):
- if( (wStandard & 0xFF00) == extPAL_N )
- {
- *LPeriod = (double) 64.0;
- *FPeriod = (double) 20.0;
- *Fsamp = (double) 28.65645;
- }
- else
- {
- *LPeriod = (double) 64.0;
- *FPeriod = (double) 20.0;
- *Fsamp = (double) 35.46895;
- }
- break;
- case (DEC_SECAM):
- *LPeriod = (double) 64.0;
- *FPeriod = (double) 20.0;
- *Fsamp = (double) 35.46895;
- break;
- }
- return;
-
-} /* GetStandardConstants ()...*/
-
-
-/****************************************************************************
- * RT_SetStandard (CARD16 wStandard) *
- * Function: to set the input standard for the Rage Theatre video in *
- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetStandard (TheatrePtr t, CARD16 wStandard)
-{
- double dbFsamp=0, dbLPeriod=0, dbFPeriod=0;
- CARD16 wFrameTotal = 0;
- double dbSPPeriod = 4.70;
-
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n",
- wStandard);
- t->wStandard = wStandard;
-
- /* Get the constants for the given standard. */
- GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard);
-
- wFrameTotal = (CARD16) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5);
-
- /* Procedures before setting the standards: */
- WriteRT_fld (fld_VIN_CLK_SEL, RT_REF_CLK);
- WriteRT_fld (fld_VINRST, RT_VINRST_RESET);
-
- RT_SetVINClock (t, wStandard);
-
- WriteRT_fld (fld_VINRST, RT_VINRST_ACTIVE);
- WriteRT_fld (fld_VIN_CLK_SEL, RT_PLL_VIN_CLK);
-
- /* Program the new standards: */
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC): /*NTSC GROUP - 480 lines */
- WriteRT_fld (fld_STANDARD_SEL, RT_NTSC);
- WriteRT_fld (fld_SYNCTIP_REF0, RT_NTSCM_SYNCTIP_REF0);
- WriteRT_fld (fld_SYNCTIP_REF1, RT_NTSCM_SYNCTIP_REF1);
- WriteRT_fld (fld_CLAMP_REF, RT_NTSCM_CLAMP_REF);
- WriteRT_fld (fld_AGC_PEAKWHITE, RT_NTSCM_PEAKWHITE);
- WriteRT_fld (fld_VBI_PEAKWHITE, RT_NTSCM_VBI_PEAKWHITE);
- WriteRT_fld (fld_WPA_THRESHOLD, RT_NTSCM_WPA_THRESHOLD);
- WriteRT_fld (fld_WPA_TRIGGER_LO, RT_NTSCM_WPA_TRIGGER_LO);
- WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_NTSCM_WPA_TRIGGER_HIGH);
- WriteRT_fld (fld_LOCKOUT_START, RT_NTSCM_LP_LOCKOUT_START);
- WriteRT_fld (fld_LOCKOUT_END, RT_NTSCM_LP_LOCKOUT_END);
- WriteRT_fld (fld_CH_DTO_INC, RT_NTSCM_CH_DTO_INC);
- WriteRT_fld (fld_PLL_SGAIN, RT_NTSCM_CH_PLL_SGAIN);
- WriteRT_fld (fld_PLL_FGAIN, RT_NTSCM_CH_PLL_FGAIN);
-
- WriteRT_fld (fld_CH_HEIGHT, RT_NTSCM_CH_HEIGHT);
- WriteRT_fld (fld_CH_KILL_LEVEL, RT_NTSCM_CH_KILL_LEVEL);
-
- WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_NTSCM_CH_AGC_ERROR_LIM);
- WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_NTSCM_CH_AGC_FILTER_EN);
- WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_NTSCM_CH_AGC_LOOP_SPEED);
-
- WriteRT_fld (fld_VS_FIELD_BLANK_START, RT_NTSCM_VS_FIELD_BLANK_START);
- WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_NTSCM_VS_FIELD_BLANK_END);
-
- WriteRT_fld (fld_H_ACTIVE_START, RT_NTSCM_H_ACTIVE_START);
- WriteRT_fld (fld_H_ACTIVE_END, RT_NTSCM_H_ACTIVE_END);
-
- WriteRT_fld (fld_V_ACTIVE_START, RT_NTSCM_V_ACTIVE_START);
- WriteRT_fld (fld_V_ACTIVE_END, RT_NTSCM_V_ACTIVE_END);
-
- WriteRT_fld (fld_H_VBI_WIND_START, RT_NTSCM_H_VBI_WIND_START);
- WriteRT_fld (fld_H_VBI_WIND_END, RT_NTSCM_H_VBI_WIND_END);
-
- WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START);
- WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END);
-
- WriteRT_fld (fld_UV_INT_START, (CARD8)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32));
-
- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_NTSCM_VSYNC_INT_TRIGGER);
- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_NTSCM_VSYNC_INT_HOLD);
-
- switch (wStandard & 0xFF00)
- {
- case (extPAL_M):
- case (extNONE):
- case (extNTSC):
- WriteRT_fld (fld_CR_BURST_GAIN, RT_NTSCM_CR_BURST_GAIN);
- WriteRT_fld (fld_CB_BURST_GAIN, RT_NTSCM_CB_BURST_GAIN);
-
- WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_NTSCM_CRDR_ACTIVE_GAIN);
- WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_NTSCM_CBDB_ACTIVE_GAIN);
-
- WriteRT_fld (fld_VERT_LOCKOUT_START, RT_NTSCM_VERT_LOCKOUT_START);
- WriteRT_fld (fld_VERT_LOCKOUT_END, RT_NTSCM_VERT_LOCKOUT_END);
-
- break;
- case (extNTSC_J):
- WriteRT_fld (fld_CR_BURST_GAIN, RT_NTSCJ_CR_BURST_GAIN);
- WriteRT_fld (fld_CB_BURST_GAIN, RT_NTSCJ_CB_BURST_GAIN);
-
- WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_NTSCJ_CRDR_ACTIVE_GAIN);
- WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_NTSCJ_CBDB_ACTIVE_GAIN);
-
- WriteRT_fld (fld_CH_HEIGHT, RT_NTSCJ_CH_HEIGHT);
- WriteRT_fld (fld_CH_KILL_LEVEL, RT_NTSCJ_CH_KILL_LEVEL);
-
- WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_NTSCJ_CH_AGC_ERROR_LIM);
- WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_NTSCJ_CH_AGC_FILTER_EN);
- WriteRT_fld (fld_CH_AGC_LOOP_SPEED, RT_NTSCJ_CH_AGC_LOOP_SPEED);
-
- WriteRT_fld (fld_VERT_LOCKOUT_START, RT_NTSCJ_VERT_LOCKOUT_START);
- WriteRT_fld (fld_VERT_LOCKOUT_END, RT_NTSCJ_VERT_LOCKOUT_END);
-
- break;
- default:
- break;
- }
- break;
- case (DEC_PAL): /*PAL GROUP - 525 lines */
- WriteRT_fld (fld_STANDARD_SEL, RT_PAL);
- WriteRT_fld (fld_SYNCTIP_REF0, RT_PAL_SYNCTIP_REF0);
- WriteRT_fld (fld_SYNCTIP_REF1, RT_PAL_SYNCTIP_REF1);
-
- WriteRT_fld (fld_CLAMP_REF, RT_PAL_CLAMP_REF);
- WriteRT_fld (fld_AGC_PEAKWHITE, RT_PAL_PEAKWHITE);
- WriteRT_fld (fld_VBI_PEAKWHITE, RT_PAL_VBI_PEAKWHITE);
-
- WriteRT_fld (fld_WPA_THRESHOLD, RT_PAL_WPA_THRESHOLD);
- WriteRT_fld (fld_WPA_TRIGGER_LO, RT_PAL_WPA_TRIGGER_LO);
- WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_PAL_WPA_TRIGGER_HIGH);
-
- WriteRT_fld (fld_LOCKOUT_START,RT_PAL_LP_LOCKOUT_START);
- WriteRT_fld (fld_LOCKOUT_END, RT_PAL_LP_LOCKOUT_END);
- WriteRT_fld (fld_CH_DTO_INC, RT_PAL_CH_DTO_INC);
- WriteRT_fld (fld_PLL_SGAIN, RT_PAL_CH_PLL_SGAIN);
- WriteRT_fld (fld_PLL_FGAIN, RT_PAL_CH_PLL_FGAIN);
-
- WriteRT_fld (fld_CR_BURST_GAIN, RT_PAL_CR_BURST_GAIN);
- WriteRT_fld (fld_CB_BURST_GAIN, RT_PAL_CB_BURST_GAIN);
-
- WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_PAL_CRDR_ACTIVE_GAIN);
- WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_PAL_CBDB_ACTIVE_GAIN);
-
- WriteRT_fld (fld_CH_HEIGHT, RT_PAL_CH_HEIGHT);
- WriteRT_fld (fld_CH_KILL_LEVEL, RT_PAL_CH_KILL_LEVEL);
-
- WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_PAL_CH_AGC_ERROR_LIM);
- WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_PAL_CH_AGC_FILTER_EN);
- WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_PAL_CH_AGC_LOOP_SPEED);
-
- WriteRT_fld (fld_VERT_LOCKOUT_START, RT_PAL_VERT_LOCKOUT_START);
- WriteRT_fld (fld_VERT_LOCKOUT_END, RT_PAL_VERT_LOCKOUT_END);
- WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START);
-
- WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END);
-
- WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START);
- WriteRT_fld (fld_H_ACTIVE_END, RT_PAL_H_ACTIVE_END);
-
- WriteRT_fld (fld_V_ACTIVE_START, RT_PAL_V_ACTIVE_START);
- WriteRT_fld (fld_V_ACTIVE_END, RT_PAL_V_ACTIVE_END);
-
- WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START);
- WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END);
-
- WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START);
- WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END);
-
- /* Magic 0.10 is correct - according to Ivo. Also see SECAM code below */
-/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */
- WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 ));
-
- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER);
- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD);
-
- break;
- case (DEC_SECAM): /*PAL GROUP*/
- WriteRT_fld (fld_STANDARD_SEL, RT_SECAM);
- WriteRT_fld (fld_SYNCTIP_REF0, RT_SECAM_SYNCTIP_REF0);
- WriteRT_fld (fld_SYNCTIP_REF1, RT_SECAM_SYNCTIP_REF1);
- WriteRT_fld (fld_CLAMP_REF, RT_SECAM_CLAMP_REF);
- WriteRT_fld (fld_AGC_PEAKWHITE, RT_SECAM_PEAKWHITE);
- WriteRT_fld (fld_VBI_PEAKWHITE, RT_SECAM_VBI_PEAKWHITE);
-
- WriteRT_fld (fld_WPA_THRESHOLD, RT_SECAM_WPA_THRESHOLD);
-
- WriteRT_fld (fld_WPA_TRIGGER_LO, RT_SECAM_WPA_TRIGGER_LO);
- WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_SECAM_WPA_TRIGGER_HIGH);
-
- WriteRT_fld (fld_LOCKOUT_START,RT_SECAM_LP_LOCKOUT_START);
- WriteRT_fld (fld_LOCKOUT_END, RT_SECAM_LP_LOCKOUT_END);
-
- WriteRT_fld (fld_CH_DTO_INC, RT_SECAM_CH_DTO_INC);
- WriteRT_fld (fld_PLL_SGAIN, RT_SECAM_CH_PLL_SGAIN);
- WriteRT_fld (fld_PLL_FGAIN, RT_SECAM_CH_PLL_FGAIN);
-
- WriteRT_fld (fld_CR_BURST_GAIN, RT_SECAM_CR_BURST_GAIN);
- WriteRT_fld (fld_CB_BURST_GAIN, RT_SECAM_CB_BURST_GAIN);
-
- WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_SECAM_CRDR_ACTIVE_GAIN);
- WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_SECAM_CBDB_ACTIVE_GAIN);
-
- WriteRT_fld (fld_CH_HEIGHT, RT_SECAM_CH_HEIGHT);
- WriteRT_fld (fld_CH_KILL_LEVEL, RT_SECAM_CH_KILL_LEVEL);
-
- WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_SECAM_CH_AGC_ERROR_LIM);
- WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_SECAM_CH_AGC_FILTER_EN);
- WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_SECAM_CH_AGC_LOOP_SPEED);
-
- WriteRT_fld (fld_VERT_LOCKOUT_START, RT_SECAM_VERT_LOCKOUT_START); /*Might not need */
- WriteRT_fld (fld_VERT_LOCKOUT_END, RT_SECAM_VERT_LOCKOUT_END); /* Might not need */
-
- WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START);
- WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END);
-
- WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START);
- WriteRT_fld (fld_H_ACTIVE_END, RT_PAL_H_ACTIVE_END);
-
- WriteRT_fld (fld_V_ACTIVE_START, RT_PAL_V_ACTIVE_START);
- WriteRT_fld (fld_V_ACTIVE_END, RT_PAL_V_ACTIVE_END);
-
- WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START);
- WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END);
-
- WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START);
- WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END);
-
- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER);
- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD);
-
-/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */
- WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 ));
-
- break;
- default:
- break;
- }
-
- if (t->wConnector == DEC_SVIDEO)
- {
-
- RT_SetCombFilter (t, wStandard, RT_SVIDEO);
- }
- else
- {
- /* Set up extra (connector and std) registers. */
- RT_SetCombFilter (t, wStandard, RT_COMPOSITE);
- }
-
- /* Set the following values according to the formulas */
- WriteRT_fld (fld_HS_LINE_TOTAL, (CARD16)((dbLPeriod * dbFsamp / 2.0) +0.5));
- /* According to Ivo PAL/SECAM needs different treatment */
- switch(wStandard & 0x00FF)
- {
- case DEC_PAL:
- case DEC_SECAM:
- WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.5 * dbSPPeriod * dbFsamp/2.0));
- WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.5 * dbSPPeriod * dbFsamp/2.0));
- WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16));
- WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(2.39 * dbSPPeriod * dbFsamp / 2.0));
- /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)RT_PAL_FIELD_IDLOCATION); */
- /* According to docs the following value will work right, though the resulting stream deviates
- slightly from CCIR..., in particular the value that was before will do nuts to VCRs in
- pause/rewind state. */
- WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01);
- WriteRT_fld (fld_HS_PLL_SGAIN, 2);
- break;
- case DEC_NTSC:
- WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.75 * dbSPPeriod * dbFsamp/2.0));
- WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.25 * dbSPPeriod * dbFsamp/2.0));
- WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16));
- WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(1.15 * dbSPPeriod * dbFsamp / 2.0));
- /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)fld_VS_FIELD_IDLOCATION_def);*/
- /* I think the default value was the same as the one here.. does not hurt to hardcode it */
- WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01);
-
- }
-
- WriteRT_fld (fld_VS_FRAME_TOTAL, (CARD16)(wFrameTotal) + 10);
- WriteRT_fld (fld_BLACK_INT_START, (CARD8)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 ));
- WriteRT_fld (fld_SYNC_TIP_START, (CARD16)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 ));
-
- return;
-
-} /* RT_SetStandard ()... */
-
-
-
-/****************************************************************************
- * RT_SetCombFilter (CARD16 wStandard, CARD16 wConnector) *
- * Function: sets the input comb filter based on the standard and *
- * connector being used (composite vs. svideo) *
- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * CARD16 wConnector - COMPOSITE, SVIDEO *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector)
-{
- CARD32 dwComb_Cntl0=0;
- CARD32 dwComb_Cntl1=0;
- CARD32 dwComb_Cntl2=0;
- CARD32 dwComb_Line_Length=0;
-
- switch (wConnector)
- {
- case RT_COMPOSITE:
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extNTSC):
- case (extNTSC_J):
- dwComb_Cntl0= RT_NTSCM_COMB_CNTL0_COMPOSITE;
- dwComb_Cntl1= RT_NTSCM_COMB_CNTL1_COMPOSITE;
- dwComb_Cntl2= RT_NTSCM_COMB_CNTL2_COMPOSITE;
- dwComb_Line_Length= RT_NTSCM_COMB_LENGTH_COMPOSITE;
- break;
- case (extPAL_M):
- dwComb_Cntl0= RT_PALM_COMB_CNTL0_COMPOSITE;
- dwComb_Cntl1= RT_PALM_COMB_CNTL1_COMPOSITE;
- dwComb_Cntl2= RT_PALM_COMB_CNTL2_COMPOSITE;
- dwComb_Line_Length= RT_PALM_COMB_LENGTH_COMPOSITE;
- break;
- default:
- return;
- }
- break;
- case (DEC_PAL):
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extPAL):
- dwComb_Cntl0= RT_PAL_COMB_CNTL0_COMPOSITE;
- dwComb_Cntl1= RT_PAL_COMB_CNTL1_COMPOSITE;
- dwComb_Cntl2= RT_PAL_COMB_CNTL2_COMPOSITE;
- dwComb_Line_Length= RT_PAL_COMB_LENGTH_COMPOSITE;
- break;
- case (extPAL_N):
- dwComb_Cntl0= RT_PALN_COMB_CNTL0_COMPOSITE;
- dwComb_Cntl1= RT_PALN_COMB_CNTL1_COMPOSITE;
- dwComb_Cntl2= RT_PALN_COMB_CNTL2_COMPOSITE;
- dwComb_Line_Length= RT_PALN_COMB_LENGTH_COMPOSITE;
- break;
- default:
- return;
- }
- break;
- case (DEC_SECAM):
- dwComb_Cntl0= RT_SECAM_COMB_CNTL0_COMPOSITE;
- dwComb_Cntl1= RT_SECAM_COMB_CNTL1_COMPOSITE;
- dwComb_Cntl2= RT_SECAM_COMB_CNTL2_COMPOSITE;
- dwComb_Line_Length= RT_SECAM_COMB_LENGTH_COMPOSITE;
- break;
- default:
- return;
- }
- break;
- case RT_SVIDEO:
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extNTSC):
- dwComb_Cntl0= RT_NTSCM_COMB_CNTL0_SVIDEO;
- dwComb_Cntl1= RT_NTSCM_COMB_CNTL1_SVIDEO;
- dwComb_Cntl2= RT_NTSCM_COMB_CNTL2_SVIDEO;
- dwComb_Line_Length= RT_NTSCM_COMB_LENGTH_SVIDEO;
- break;
- case (extPAL_M):
- dwComb_Cntl0= RT_PALM_COMB_CNTL0_SVIDEO;
- dwComb_Cntl1= RT_PALM_COMB_CNTL1_SVIDEO;
- dwComb_Cntl2= RT_PALM_COMB_CNTL2_SVIDEO;
- dwComb_Line_Length= RT_PALM_COMB_LENGTH_SVIDEO;
- break;
- default:
- return;
- }
- break;
- case (DEC_PAL):
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extPAL):
- dwComb_Cntl0= RT_PAL_COMB_CNTL0_SVIDEO;
- dwComb_Cntl1= RT_PAL_COMB_CNTL1_SVIDEO;
- dwComb_Cntl2= RT_PAL_COMB_CNTL2_SVIDEO;
- dwComb_Line_Length= RT_PAL_COMB_LENGTH_SVIDEO;
- break;
- case (extPAL_N):
- dwComb_Cntl0= RT_PALN_COMB_CNTL0_SVIDEO;
- dwComb_Cntl1= RT_PALN_COMB_CNTL1_SVIDEO;
- dwComb_Cntl2= RT_PALN_COMB_CNTL2_SVIDEO;
- dwComb_Line_Length= RT_PALN_COMB_LENGTH_SVIDEO;
- break;
- default:
- return;
- }
- break;
- case (DEC_SECAM):
- dwComb_Cntl0= RT_SECAM_COMB_CNTL0_SVIDEO;
- dwComb_Cntl1= RT_SECAM_COMB_CNTL1_SVIDEO;
- dwComb_Cntl2= RT_SECAM_COMB_CNTL2_SVIDEO;
- dwComb_Line_Length= RT_SECAM_COMB_LENGTH_SVIDEO;
- break;
- default:
- return;
- }
- break;
- default:
- return;
- }
-
- WriteRT_fld (fld_COMB_CNTL0, dwComb_Cntl0);
- WriteRT_fld (fld_COMB_CNTL1, dwComb_Cntl1);
- WriteRT_fld (fld_COMB_CNTL2, dwComb_Cntl2);
- WriteRT_fld (fld_COMB_LENGTH, dwComb_Line_Length);
-
- return;
-
-} /* RT_SetCombFilter ()... */
-
-
-/****************************************************************************
- * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, *
- * CARD8 fCC_On, CARD8 fVBICap_On) *
- * Function: sets the output video size for the Rage Theatre video in *
- * Inputs: CARD16 wHorzSize - width of output in pixels *
- * CARD16 wVertSize - height of output in pixels (lines) *
- * CARD8 fCC_On - enable CC output *
- * CARD8 fVBI_Cap_On - enable VBI capture *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On)
-{
- CARD32 dwHwinStart=0;
- CARD32 dwHScaleRatio=0;
- CARD32 dwHActiveLength=0;
- CARD32 dwVwinStart=0;
- CARD32 dwVScaleRatio=0;
- CARD32 dwVActiveLength=0;
- CARD32 dwTempRatio=0;
- CARD32 dwEvenFieldOffset=0;
- CARD32 dwOddFieldOffset=0;
- CARD32 dwXin=0;
- CARD32 dwYin=0;
-
- if (fVBICap_On)
- {
- WriteRT_fld (fld_VBI_CAPTURE_ENABLE, 1);
- WriteRT_fld (fld_VBI_SCALING_RATIO, fld_VBI_SCALING_RATIO_def);
- switch (t->wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- WriteRT_fld (fld_H_VBI_WIND_START, RT_NTSCM_H_VBI_WIND_START);
- WriteRT_fld (fld_H_VBI_WIND_END, RT_NTSCM_H_VBI_WIND_END);
- WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START);
- WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END);
- break;
- case (DEC_PAL):
- WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START);
- WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END);
- WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START);
- WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END);
- break;
- case (DEC_SECAM):
- WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START);
- WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END);
- WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START);
- WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END);
- break;
- default:
- break;
- }
- }
- else
- {
- WriteRT_fld (fld_VBI_CAPTURE_ENABLE, 0);
- }
-
- if (t->wInterlaced != RT_DECINTERLACED)
- {
- wVertSize *= 2;
- }
-
- /*1. Calculate Horizontal Scaling ratio:*/
- switch (t->wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- dwHwinStart = RT_NTSCM_H_IN_START;
- dwXin = (ReadRT_fld (fld_H_ACTIVE_END) - ReadRT_fld (fld_H_ACTIVE_START)); /*tempscaler*/
- dwXin = RT_NTSC_H_ACTIVE_SIZE;
- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize);
- dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/
- dwHActiveLength = wHorzSize;
- break;
- case (DEC_PAL):
- dwHwinStart = RT_PAL_H_IN_START;
- dwXin = RT_PAL_H_ACTIVE_SIZE;
- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize);
- dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/
- dwHActiveLength = wHorzSize;
- break;
- case (DEC_SECAM):
- dwHwinStart = RT_SECAM_H_IN_START;
- dwXin = RT_SECAM_H_ACTIVE_SIZE;
- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize);
- dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/
- dwHActiveLength = wHorzSize;
- break;
- default:
- break;
- }
-
- /*2. Calculate Vertical Scaling ratio:*/
- switch (t->wStandard & 0x00FF)
- {
- case (DEC_NTSC):
- dwVwinStart = RT_NTSCM_V_IN_START;
- /* dwYin = (ReadRT_fld (fld_V_ACTIVE_END) - ReadRT_fld (fld_V_ACTIVE_START)); */ /*tempscaler*/
- dwYin = RT_NTSCM_V_ACTIVE_SIZE;
- dwTempRatio = (CARD32)((long) wVertSize / dwYin);
- dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin);
- dwVScaleRatio = dwVScaleRatio & 0x00000FFF;
- dwVActiveLength = wVertSize/2;
- break;
- case (DEC_PAL):
- dwVwinStart = RT_PAL_V_IN_START;
- dwYin = RT_PAL_V_ACTIVE_SIZE;
- dwTempRatio = (CARD32)(wVertSize/dwYin);
- dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin);
- dwVScaleRatio = dwVScaleRatio & 0x00000FFF;
- dwVActiveLength = wVertSize/2;
- break;
- case (DEC_SECAM):
- dwVwinStart = RT_SECAM_V_IN_START;
- dwYin = RT_SECAM_V_ACTIVE_SIZE;
- dwTempRatio = (CARD32) (wVertSize / dwYin);
- dwVScaleRatio = (CARD32) ((long) wVertSize * 2048L / dwYin);
- dwVScaleRatio = dwVScaleRatio & 0x00000FFF;
- dwVActiveLength = wVertSize/2;
- break;
- default:
- break;
- }
-
- /*4. Set up offset based on if interlaced or not:*/
- if (t->wInterlaced == RT_DECINTERLACED)
- {
- dwEvenFieldOffset = (CARD32) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0);
- dwOddFieldOffset = dwEvenFieldOffset;
- WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1);
- }
- else
- {
- dwEvenFieldOffset = (CARD32)(dwTempRatio * 512.0);
- dwOddFieldOffset = (CARD32)(2048 - dwEvenFieldOffset);
- WriteRT_fld (fld_V_DEINTERLACE_ON, 0x0);
- }
-
- /* Set the registers:*/
- WriteRT_fld (fld_H_IN_WIND_START, dwHwinStart);
- WriteRT_fld (fld_H_SCALE_RATIO, dwHScaleRatio);
- WriteRT_fld (fld_H_OUT_WIND_WIDTH, dwHActiveLength);
-
- WriteRT_fld (fld_V_IN_WIND_START, dwVwinStart);
- WriteRT_fld (fld_V_SCALE_RATIO, dwVScaleRatio);
- WriteRT_fld (fld_V_OUT_WIND_WIDTH, dwVActiveLength);
-
- WriteRT_fld (fld_EVENF_OFFSET, dwEvenFieldOffset);
- WriteRT_fld (fld_ODDF_OFFSET, dwOddFieldOffset);
-
- t->dwHorzScalingRatio = dwHScaleRatio;
- t->dwVertScalingRatio = dwVScaleRatio;
-
- return;
-
-} /* RT_SetOutputVideoSize ()...*/
-
-
-
-/****************************************************************************
- * CalculateCrCbGain (double *CrGain, double *CbGain, CARD16 wStandard) *
- * Function: *
- * Inputs: double *CrGain -
- * double *CbGain -
- * CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * Outputs: NONE *
- ****************************************************************************/
-void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard)
-{
- #define UVFLTGAIN 1.5
- #define FRMAX 280000.0
- #define FBMAX 230000.0
-
- double dbSynctipRef0=0, dbFsamp=0, dbLPeriod=0, dbFPeriod=0;
-
- dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0);
-
- GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard);
-
- *CrGain=0.0;
- *CbGain=0.0;
-
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC): /*NTSC GROUP - 480 lines*/
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extNTSC):
- case (extPAL_M):
- *CrGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN);
- *CbGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN);
- break;
- case (extNTSC_J):
- *CrGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/100.0) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN);
- *CbGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/100.0) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN);
- break;
- default:
- return;
- }
- break;
- case (DEC_PAL):
- *CrGain = (double)(43.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN);
- *CbGain = (double)(43.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN);
- break;
- case (DEC_SECAM):
- *CrGain = (double) 32.0 * 32768.0 / FRMAX / (33554432.0 / dbFsamp) * (1.597 / 1.902) / UVFLTGAIN;
- *CbGain = (double) 32.0 * 32768.0 / FBMAX / (33554432.0 / dbFsamp) * (1.267 / 1.505) / UVFLTGAIN;
- break;
- }
-
- return;
-
-} /* CalculateCrCbGain ()...*/
-
-
-/****************************************************************************
- * RT_SetConnector (CARD16 wStandard, int tunerFlag) *
- * Function:
- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * int tunerFlag
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag)
-{
- CARD32 dwTempContrast=0;
- int i;
- long counter;
-
- t->wConnector = wConnector;
-
- /* Get the contrast value - make sure we are viewing a visible line*/
- counter=0;
- #if 0
- while (!((ReadRT_fld (fld_VS_LINE_COUNT)> 1) && (ReadRT_fld (fld_VS_LINE_COUNT)<20)) && (counter < 100000)){
- #endif
- while ((ReadRT_fld (fld_VS_LINE_COUNT)<20) && (counter < 10000)){
- counter++;
- }
- dwTempContrast = ReadRT_fld (fld_LP_CONTRAST);
- if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
- "Rage Theatre: timeout waiting for line count (%u)\n",
- (unsigned)ReadRT_fld (fld_VS_LINE_COUNT));
-
-
- WriteRT_fld (fld_LP_CONTRAST, 0x0);
-
- switch (wConnector)
- {
- case (DEC_TUNER): /* Tuner*/
- WriteRT_fld (fld_INPUT_SELECT, t->wTunerConnector );
- WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE);
- RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE);
- break;
- case (DEC_COMPOSITE): /* Comp*/
- WriteRT_fld (fld_INPUT_SELECT, t->wComp0Connector);
- WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE);
- RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE);
- break;
- case (DEC_SVIDEO): /* Svideo*/
- WriteRT_fld (fld_INPUT_SELECT, t->wSVideo0Connector);
- WriteRT_fld (fld_STANDARD_YC, RT_SVIDEO);
- RT_SetCombFilter (t, t->wStandard, RT_SVIDEO);
- break;
- default:
- WriteRT_fld (fld_INPUT_SELECT, t->wComp0Connector);
- WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE);
- RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE);
- break;
- }
-
- t->wConnector = wConnector;
-
- WriteRT_fld (fld_COMB_CNTL1, ReadRT_fld (fld_COMB_CNTL1) ^ 0x100);
- WriteRT_fld (fld_COMB_CNTL1, ReadRT_fld (fld_COMB_CNTL1) ^ 0x100);
-
- /* wait at most 1 sec here
- VIP bus has a bandwidth of 27MB and it is 8bit.
- A single Rage Theatre read should take at least 6 bytes (2 for address one way and 4 for data the other way)
- However there are also latencies associated with such reads, plus latencies for PCI accesses.
-
- I guess we should not be doing more than 100000 per second.. At some point
- I should really write a program to time this.
- */
- i = 100000;
-
- while ((i>=0) && (! ReadRT_fld (fld_HS_GENLOCKED)))
- {
- i--;
- }
- if(i<0) xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Rage Theatre: waiting for fld_HS_GENLOCKED failed\n");
- /* now we are waiting for a non-visible line.. and there is absolutely no point to wait too long */
- counter = 0;
- while (!((ReadRT_fld (fld_VS_LINE_COUNT)> 1) && (ReadRT_fld (fld_VS_LINE_COUNT)<20)) && (counter < 10000)){
- counter++;
- }
- WriteRT_fld (fld_LP_CONTRAST, dwTempContrast);
- if(counter>=10000)xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
- "Rage Theatre: timeout waiting for line count (%u)\n",
- (unsigned)ReadRT_fld (fld_VS_LINE_COUNT));
-
-
-
- return;
-
-} /* RT_SetConnector ()...*/
-
-
-void InitTheatre(TheatrePtr t)
-{
- CARD32 data;
-
-
- /* 0 reset Rage Theatre */
- ShutdownTheatre(t);
- usleep(100000);
-
- t->mode=MODE_INITIALIZATION_IN_PROGRESS;
- /* 1.
- Set the VIN_PLL to NTSC value */
- RT_SetVINClock(t, RT_NTSC);
-
- /* Take VINRST and L54RST out of reset */
- RT_regr (VIP_PLL_CNTL1, &data);
- RT_regw (VIP_PLL_CNTL1, data & ~((RT_VINRST_RESET << 1) | (RT_L54RST_RESET << 3)));
- RT_regr (VIP_PLL_CNTL1, &data);
-
- /* Set VIN_CLK_SEL to PLL_VIN_CLK */
- RT_regr (VIP_CLOCK_SEL_CNTL, &data);
- RT_regw (VIP_CLOCK_SEL_CNTL, data | (RT_PLL_VIN_CLK << 7));
- RT_regr (VIP_CLOCK_SEL_CNTL, &data);
-
- /* 2.
- Set HW_DEBUG to 0xF000 before setting the standards registers */
- RT_regw (VIP_HW_DEBUG, 0x0000F000);
-
- /* wait for things to settle */
- usleep(100000);
-
- RT_SetStandard(t, t->wStandard);
-
- /* 3.
- Set DVS port to OUTPUT */
- RT_regr (VIP_DVS_PORT_CTRL, &data);
- RT_regw (VIP_DVS_PORT_CTRL, data | RT_DVSDIR_OUT);
- RT_regr (VIP_DVS_PORT_CTRL, &data);
-
- /* 4.
- Set default values for ADC_CNTL */
- RT_regw (VIP_ADC_CNTL, RT_ADC_CNTL_DEFAULT);
-
- /* 5.
- Clear the VIN_ASYNC_RST bit */
- RT_regr (VIP_MASTER_CNTL, &data);
- RT_regw (VIP_MASTER_CNTL, data & ~0x20);
- RT_regr (VIP_MASTER_CNTL, &data);
-
- /* Clear the DVS_ASYNC_RST bit */
- RT_regr (VIP_MASTER_CNTL, &data);
- RT_regw (VIP_MASTER_CNTL, data & ~(RT_DVS_ASYNC_RST));
- RT_regr (VIP_MASTER_CNTL, &data);
-
- /* Set the GENLOCK delay */
- RT_regw (VIP_HS_GENLOCKDELAY, 0x10);
-
- RT_regr (fld_DVS_DIRECTION, &data);
- RT_regw (fld_DVS_DIRECTION, data & RT_DVSDIR_OUT);
-/* WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); */
-
- t->mode=MODE_INITIALIZED_FOR_TV_IN;
-}
-
-
-void ShutdownTheatre(TheatrePtr t)
-{
- WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE);
- WriteRT_fld (fld_VINRST , RT_VINRST_RESET);
- WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE);
- WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN);
- t->mode=MODE_UNINITIALIZED;
-}
-
-void DumpRageTheatreRegs(TheatrePtr t)
-{
- int i;
- CARD32 data;
-
- for(i=0;i<0x900;i+=4)
- {
- RT_regr(i, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
- "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data);
- }
-
-}
-
-void DumpRageTheatreRegsByName(TheatrePtr t)
-{
- int i;
- CARD32 data;
- struct { char *name; long addr; } rt_reg_list[]={
- { "ADC_CNTL ", 0x0400 },
- { "ADC_DEBUG ", 0x0404 },
- { "AUD_CLK_DIVIDERS ", 0x00e8 },
- { "AUD_DTO_INCREMENTS ", 0x00ec },
- { "AUD_PLL_CNTL ", 0x00e0 },
- { "AUD_PLL_FINE_CNTL ", 0x00e4 },
- { "CLKOUT_CNTL ", 0x004c },
- { "CLKOUT_GPIO_CNTL ", 0x0038 },
- { "CLOCK_SEL_CNTL ", 0x00d0 },
- { "COMB_CNTL0 ", 0x0440 },
- { "COMB_CNTL1 ", 0x0444 },
- { "COMB_CNTL2 ", 0x0448 },
- { "COMB_LINE_LENGTH ", 0x044c },
- { "CP_ACTIVE_GAIN ", 0x0594 },
- { "CP_AGC_CNTL ", 0x0590 },
- { "CP_BURST_GAIN ", 0x058c },
- { "CP_DEBUG_FORCE ", 0x05b8 },
- { "CP_HUE_CNTL ", 0x0588 },
- { "CP_PLL_CNTL0 ", 0x0580 },
- { "CP_PLL_CNTL1 ", 0x0584 },
- { "CP_PLL_STATUS0 ", 0x0598 },
- { "CP_PLL_STATUS1 ", 0x059c },
- { "CP_PLL_STATUS2 ", 0x05a0 },
- { "CP_PLL_STATUS3 ", 0x05a4 },
- { "CP_PLL_STATUS4 ", 0x05a8 },
- { "CP_PLL_STATUS5 ", 0x05ac },
- { "CP_PLL_STATUS6 ", 0x05b0 },
- { "CP_PLL_STATUS7 ", 0x05b4 },
- { "CP_VERT_LOCKOUT ", 0x05bc },
- { "CRC_CNTL ", 0x02c0 },
- { "CRT_DTO_INCREMENTS ", 0x0394 },
- { "CRT_PLL_CNTL ", 0x00c4 },
- { "CRT_PLL_FINE_CNTL ", 0x00bc },
- { "DECODER_DEBUG_CNTL ", 0x05d4 },
- { "DELAY_ONE_MAP_A ", 0x0114 },
- { "DELAY_ONE_MAP_B ", 0x0118 },
- { "DELAY_ZERO_MAP_A ", 0x011c },
- { "DELAY_ZERO_MAP_B ", 0x0120 },
- { "DFCOUNT ", 0x00a4 },
- { "DFRESTART ", 0x00a8 },
- { "DHRESTART ", 0x00ac },
- { "DVRESTART ", 0x00b0 },
- { "DVS_PORT_CTRL ", 0x0610 },
- { "DVS_PORT_READBACK ", 0x0614 },
- { "FIFOA_CONFIG ", 0x0800 },
- { "FIFOB_CONFIG ", 0x0804 },
- { "FIFOC_CONFIG ", 0x0808 },
- { "FRAME_LOCK_CNTL ", 0x0100 },
- { "GAIN_LIMIT_SETTINGS ", 0x01e4 },
- { "GPIO_CNTL ", 0x0034 },
- { "GPIO_INOUT ", 0x0030 },
- { "HCOUNT ", 0x0090 },
- { "HDISP ", 0x0084 },
- { "HOST_RD_WT_CNTL ", 0x0188 },
- { "HOST_READ_DATA ", 0x0180 },
- { "HOST_WRITE_DATA ", 0x0184 },
- { "HSIZE ", 0x0088 },
- { "HSTART ", 0x008c },
- { "HS_DTOINC ", 0x0484 },
- { "HS_GENLOCKDELAY ", 0x0490 },
- { "HS_MINMAXWIDTH ", 0x048c },
- { "HS_PLINE ", 0x0480 },
- { "HS_PLLGAIN ", 0x0488 },
- { "HS_PLL_ERROR ", 0x04a0 },
- { "HS_PLL_FS_PATH ", 0x04a4 },
- { "HS_PULSE_WIDTH ", 0x049c },
- { "HS_WINDOW_LIMIT ", 0x0494 },
- { "HS_WINDOW_OC_SPEED ", 0x0498 },
- { "HTOTAL ", 0x0080 },
- { "HW_DEBUG ", 0x0010 },
- { "H_ACTIVE_WINDOW ", 0x05c0 },
- { "H_SCALER_CONTROL ", 0x0600 },
- { "H_VBI_WINDOW ", 0x05c8 },
- { "I2C_CNTL ", 0x0054 },
- { "I2C_CNTL_0 ", 0x0020 },
- { "I2C_CNTL_1 ", 0x0024 },
- { "I2C_DATA ", 0x0028 },
- { "I2S_RECEIVE_CNTL ", 0x081c },
- { "I2S_TRANSMIT_CNTL ", 0x0818 },
- { "IIS_TX_CNT_REG ", 0x0824 },
- { "INT_CNTL ", 0x002c },
- { "L54_DTO_INCREMENTS ", 0x00f8 },
- { "L54_PLL_CNTL ", 0x00f0 },
- { "L54_PLL_FINE_CNTL ", 0x00f4 },
- { "LINEAR_GAIN_SETTINGS ", 0x01e8 },
- { "LP_AGC_CLAMP_CNTL0 ", 0x0500 },
- { "LP_AGC_CLAMP_CNTL1 ", 0x0504 },
- { "LP_BLACK_LEVEL ", 0x051c },
- { "LP_BRIGHTNESS ", 0x0508 },
- { "LP_CONTRAST ", 0x050c },
- { "LP_SLICE_LEVEL ", 0x0520 },
- { "LP_SLICE_LIMIT ", 0x0510 },
- { "LP_SYNCTIP_LEVEL ", 0x0524 },
- { "LP_VERT_LOCKOUT ", 0x0528 },
- { "LP_WPA_CNTL0 ", 0x0514 },
- { "LP_WPA_CNTL1 ", 0x0518 },
- { "MASTER_CNTL ", 0x0040 },
- { "MODULATOR_CNTL1 ", 0x0200 },
- { "MODULATOR_CNTL2 ", 0x0204 },
- { "MV_LEVEL_CNTL1 ", 0x0210 },
- { "MV_LEVEL_CNTL2 ", 0x0214 },
- { "MV_MODE_CNTL ", 0x0208 },
- { "MV_STATUS ", 0x0330 },
- { "MV_STRIPE_CNTL ", 0x020c },
- { "NOISE_CNTL0 ", 0x0450 },
- { "PLL_CNTL0 ", 0x00c8 },
- { "PLL_CNTL1 ", 0x00fc },
- { "PLL_TEST_CNTL ", 0x00cc },
- { "PRE_DAC_MUX_CNTL ", 0x0240 },
- { "RGB_CNTL ", 0x0048 },
- { "RIPINTF_PORT_CNTL ", 0x003c },
- { "SCALER_IN_WINDOW ", 0x0618 },
- { "SCALER_OUT_WINDOW ", 0x061c },
- { "SG_BLACK_GATE ", 0x04c0 },
- { "SG_SYNCTIP_GATE ", 0x04c4 },
- { "SG_UVGATE_GATE ", 0x04c8 },
- { "SINGLE_STEP_DATA ", 0x05d8 },
- { "SPDIF_AC3_PREAMBLE ", 0x0814 },
- { "SPDIF_CHANNEL_STAT ", 0x0810 },
- { "SPDIF_PORT_CNTL ", 0x080c },
- { "SPDIF_TX_CNT_REG ", 0x0820 },
- { "STANDARD_SELECT ", 0x0408 },
- { "SW_SCRATCH ", 0x0014 },
- { "SYNC_CNTL ", 0x0050 },
- { "SYNC_LOCK_CNTL ", 0x0104 },
- { "SYNC_SIZE ", 0x00b4 },
- { "THERMO2BIN_STATUS ", 0x040c },
- { "TIMING_CNTL ", 0x01c4 },
- { "TVO_DATA_DELAY_A ", 0x0140 },
- { "TVO_DATA_DELAY_B ", 0x0144 },
- { "TVO_SYNC_PAT_ACCUM ", 0x0108 },
- { "TVO_SYNC_PAT_EXPECT ", 0x0110 },
- { "TVO_SYNC_THRESHOLD ", 0x010c },
- { "TV_DAC_CNTL ", 0x0280 },
- { "TV_DTO_INCREMENTS ", 0x0390 },
- { "TV_PLL_CNTL ", 0x00c0 },
- { "TV_PLL_FINE_CNTL ", 0x00b8 },
- { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 },
- { "UPSAMP_COEFF0_0 ", 0x0340 },
- { "UPSAMP_COEFF0_1 ", 0x0344 },
- { "UPSAMP_COEFF0_2 ", 0x0348 },
- { "UPSAMP_COEFF1_0 ", 0x034c },
- { "UPSAMP_COEFF1_1 ", 0x0350 },
- { "UPSAMP_COEFF1_2 ", 0x0354 },
- { "UPSAMP_COEFF2_0 ", 0x0358 },
- { "UPSAMP_COEFF2_1 ", 0x035c },
- { "UPSAMP_COEFF2_2 ", 0x0360 },
- { "UPSAMP_COEFF3_0 ", 0x0364 },
- { "UPSAMP_COEFF3_1 ", 0x0368 },
- { "UPSAMP_COEFF3_2 ", 0x036c },
- { "UPSAMP_COEFF4_0 ", 0x0370 },
- { "UPSAMP_COEFF4_1 ", 0x0374 },
- { "UPSAMP_COEFF4_2 ", 0x0378 },
- { "UV_ADR ", 0x0300 },
- { "VBI_20BIT_CNTL ", 0x02d0 },
- { "VBI_CC_CNTL ", 0x02c8 },
- { "VBI_CONTROL ", 0x05d0 },
- { "VBI_DTO_CNTL ", 0x02d4 },
- { "VBI_EDS_CNTL ", 0x02cc },
- { "VBI_LEVEL_CNTL ", 0x02d8 },
- { "VBI_SCALER_CONTROL ", 0x060c },
- { "VCOUNT ", 0x009c },
- { "VDISP ", 0x0098 },
- { "VFTOTAL ", 0x00a0 },
- { "VIDEO_PORT_SIG ", 0x02c4 },
- { "VIN_PLL_CNTL ", 0x00d4 },
- { "VIN_PLL_FINE_CNTL ", 0x00d8 },
- { "VIP_COMMAND_STATUS ", 0x0008 },
- { "VIP_REVISION_ID ", 0x000c },
- { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 },
- { "VIP_VENDOR_DEVICE_ID ", 0x0000 },
- { "VSCALER_CNTL1 ", 0x01c0 },
- { "VSCALER_CNTL2 ", 0x01c8 },
- { "VSYNC_DIFF_CNTL ", 0x03a0 },
- { "VSYNC_DIFF_LIMITS ", 0x03a4 },
- { "VSYNC_DIFF_RD_DATA ", 0x03a8 },
- { "VS_BLANKING_CNTL ", 0x0544 },
- { "VS_COUNTER_CNTL ", 0x054c },
- { "VS_DETECTOR_CNTL ", 0x0540 },
- { "VS_FIELD_ID_CNTL ", 0x0548 },
- { "VS_FRAME_TOTAL ", 0x0550 },
- { "VS_LINE_COUNT ", 0x0554 },
- { "VTOTAL ", 0x0094 },
- { "V_ACTIVE_WINDOW ", 0x05c4 },
- { "V_DEINTERLACE_CONTROL ", 0x0608 },
- { "V_SCALER_CONTROL ", 0x0604 },
- { "V_VBI_WINDOW ", 0x05cc },
- { "Y_FALL_CNTL ", 0x01cc },
- { "Y_RISE_CNTL ", 0x01d0 },
- { "Y_SAW_TOOTH_CNTL ", 0x01d4 },
- {NULL, 0}
- };
-
- for(i=0; rt_reg_list[i].name!=NULL;i++){
- RT_regr(rt_reg_list[i].addr, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
- "register (0x%04lx) %s is equal to 0x%08x\n",
- rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data);
- }
-
-}
-
-void ResetTheatreRegsForNoTVout(TheatrePtr t)
-{
- RT_regw(VIP_CLKOUT_CNTL, 0x0);
- RT_regw(VIP_HCOUNT, 0x0);
- RT_regw(VIP_VCOUNT, 0x0);
- RT_regw(VIP_DFCOUNT, 0x0);
- #if 0
- RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
- RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
- #endif
- RT_regw(VIP_FRAME_LOCK_CNTL, 0x0);
-}
-
-
-void ResetTheatreRegsForTVout(TheatrePtr t)
-{
-/* RT_regw(VIP_HW_DEBUG, 0x200); */
-/* RT_regw(VIP_INT_CNTL, 0x0);
- RT_regw(VIP_GPIO_INOUT, 0x10090000);
- RT_regw(VIP_GPIO_INOUT, 0x340b0000); */
-/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */
- RT_regw(VIP_CLKOUT_CNTL, 0x29);
-#if 1
- RT_regw(VIP_HCOUNT, 0x1d1);
- RT_regw(VIP_VCOUNT, 0x1e3);
-#else
- RT_regw(VIP_HCOUNT, 0x322);
- RT_regw(VIP_VCOUNT, 0x151);
-#endif
- RT_regw(VIP_DFCOUNT, 0x01);
-/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */
- RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
- RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
-/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */
- RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f);
-/* RT_regw(VIP_ADC_CNTL, 0x02a420a8);
- RT_regw(VIP_COMB_CNTL_0, 0x0d438083);
- RT_regw(VIP_COMB_CNTL_2, 0x06080102);
- RT_regw(VIP_HS_MINMAXWIDTH, 0x462f);
- ...
- */
-/*
- RT_regw(VIP_HS_PULSE_WIDTH, 0x359);
- RT_regw(VIP_HS_PLL_ERROR, 0xab6);
- RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8);
- RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005);
- */
-}
diff --git a/src/theatre.h b/src/theatre.h
deleted file mode 100644
index 958b443..0000000
--- a/src/theatre.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef __THEATRE_H__
-#define __THEATRE_H__
-
-#define MODE_UNINITIALIZED 1
-#define MODE_INITIALIZATION_IN_PROGRESS 2
-#define MODE_INITIALIZED_FOR_TV_IN 3
-
-typedef struct {
- GENERIC_BUS_Ptr VIP;
-
- int theatre_num;
- CARD32 theatre_id;
- int mode;
- char* microc_path;
- char* microc_type;
-
- CARD16 video_decoder_type;
- CARD32 wStandard;
- CARD32 wConnector;
- int iHue;
- int iSaturation;
- CARD32 wSaturation_U;
- CARD32 wSaturation_V;
- int iBrightness;
- int dbBrightnessRatio;
- CARD32 wSharpness;
- int iContrast;
- int dbContrast;
- CARD32 wInterlaced;
- CARD32 wTunerConnector;
- CARD32 wComp0Connector;
- CARD32 wSVideo0Connector;
- CARD32 dwHorzScalingRatio;
- CARD32 dwVertScalingRatio;
-
- } TheatreRec, * TheatrePtr;
-
-/* DO NOT FORGET to setup constants before calling InitTheatre */
-void InitTheatre(TheatrePtr t);
-
-void RT_SetTint (TheatrePtr t, int hue);
-void RT_SetSaturation (TheatrePtr t, int Saturation);
-void RT_SetBrightness (TheatrePtr t, int Brightness);
-void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness);
-void RT_SetContrast (TheatrePtr t, int Contrast);
-void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace);
-void RT_SetStandard (TheatrePtr t, CARD16 wStandard);
-void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector);
-void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On);
-void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard);
-void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag);
-
-void RageTheatreDebugGain(TheatrePtr t, Bool on, CARD32 gain);
-void ShutdownTheatre(TheatrePtr t);
-void DumpRageTheatreRegs(TheatrePtr t);
-void ResetTheatreRegsForTVout(TheatrePtr t);
-void ResetTheatreRegsForNoTVout(TheatrePtr t);
-
-
-#define xf86_InitTheatre ((void (*)(TheatrePtr t))LoaderSymbol("InitTheatre"))
-
-#define xf86_RT_SetTint ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetTint"))
-#define xf86_RT_SetSaturation ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetSaturation"))
-#define xf86_RT_SetBrightness ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetBrightness"))
-#define xf86_RT_SetSharpness ((void (*)(TheatrePtr, CARD16))LoaderSymbol("RT_SetSharpness"))
-#define xf86_RT_SetContrast ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetContrast"))
-#define xf86_RT_SetInterlace ((void (*)(TheatrePtr, CARD8))LoaderSymbol("RT_SetInterlace"))
-#define xf86_RT_SetStandard ((void (*)(TheatrePtr, CARD16))LoaderSymbol("RT_SetStandard"))
-#define xf86_RT_SetOutputVideoSize ((void (*)(TheatrePtr, CARD16, CARD16, CARD8, CARD8))LoaderSymbol("RT_SetOutputVideoSize"))
-#define xf86_RT_SetConnector ((void (*)(TheatrePtr, CARD16, int))LoaderSymbol("RT_SetConnector"))
-
-#define xf86_RageTheatreDebugGain ((void (*)(TheatrePtr, Bool, CARD32))LoaderSymbol("RageTheatreDebugGain"))
-#define xf86_ShutdownTheatre ((void (*)(TheatrePtr))LoaderSymbol("ShutdownTheatre"))
-#define xf86_DumpRageTheatreRegs ((void (*)(TheatrePtr))LoaderSymbol("DumpRageTheatreRegs"))
-#define xf86_ResetTheatreRegsForTVout ((void (*)(TheatrePtr))LoaderSymbol("ResetTheatreRegsForTVout"))
-#define xf86_ResetTheatreRegsForNoTVout ((void (*)(TheatrePtr))LoaderSymbol("ResetTheatreRegsForNoTVout"))
-#define xf86_RT_GetSignalStatus ((void (*)(TheatrePtr))LoaderSymbol("xf86_RT_GetSignalStatus"))
-
-#endif
diff --git a/src/theatre200.c b/src/theatre200.c
deleted file mode 100644
index 672f01e..0000000
--- a/src/theatre200.c
+++ /dev/null
@@ -1,2275 +0,0 @@
-/*************************************************************************************
- *
- * Copyright (C) 2005 Bogdan D. bogdand at users.sourceforge.net
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of this
- * software and associated documentation files (the "Software"), to deal in the Software
- * without restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all copies or
- * substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
- * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
- * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of the author shall not be used in advertising or
- * otherwise to promote the sale, use or other dealings in this Software without prior written
- * authorization from the author.
- *
- * $Log$
- * Revision 1.6 2006/03/22 22:30:14 krh
- * 2006-03-22 Kristian Høgsberg <krh at redhat.com>
- *
- * * src/theatre200.c: Convert use of xf86fopen() and other xf86
- * wrapped libc symbols to use libc symbols directly. The xf86*
- * versions aren't supposed to be used directly.
- *
- * * src/ *.c: Drop libc wrapper; don't include xf86_ansic.h and add
- * includes now missing.
- *
- * Revision 1.4 2005/08/28 18:00:23 bogdand
- * Modified the licens type from GPL to a X/MIT one
- *
- * Revision 1.3 2005/07/11 02:29:45 ajax
- * Prep for modular builds by adding guarded #include "config.h" everywhere.
- *
- * Revision 1.2 2005/07/01 22:43:11 daniels
- * Change all misc.h and os.h references to <X11/foo.h>.
- *
- *
- ************************************************************************************/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stdio.h>
-#include <string.h>
-
-#include "xf86.h"
-#include "generic_bus.h"
-#include "radeon_reg.h"
-#include "radeon.h"
-#include "theatre_reg.h"
-#include "theatre200.h"
-#include "radeon_macros.h"
-
-#undef read
-#undef write
-#undef ioctl
-
-void DumpRageTheatreRegsByName(TheatrePtr t);
-
-static int DownloadMicrocode(TheatrePtr t);
-static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen);
-static void microc_clean(struct rt200_microc_data* microc_datap, int screen);
-static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap);
-static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap);
-
-static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0);
-static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector);
-//static CARD32 dsp_reset(TheatrePtr t);
-static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate);
-static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard);
-static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format);
-static CARD32 dsp_video_standard_detection(TheatrePtr t);
-//static CARD32 dsp_get_signallockstatus(TheatrePtr t);
-//static CARD32 dsp_get_signallinenumber(TheatrePtr t);
-
-static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness);
-static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast);
-//static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness);
-static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint);
-static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation);
-static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end);
-static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end);
-static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right);
-static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute);
-//static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option);
-static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode);
-static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state);
-
-static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data);
-}
-
-static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data);
-}
-
-static Bool theatre_fifo_read(TheatrePtr t,CARD32 fifo, CARD8 *data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (CARD8 *) data);
-}
-
-static Bool theatre_fifo_write(TheatrePtr t,CARD32 fifo, CARD32 count, CARD8* buffer)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (CARD8 *)buffer);
-}
-
-#define RT_regr(reg,data) theatre_read(t,(reg),(data))
-#define RT_regw(reg,data) theatre_write(t,(reg),(data))
-#define RT_fifor(fifo,data) theatre_fifo_read(t,(fifo),(data))
-#define RT_fifow(fifo,count,data) theatre_fifo_write(t,(fifo),(count),(data))
-#define VIP_TYPE "ATI VIP BUS"
-
-static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen)
-{
- FILE* file;
- struct rt200_microc_head* microc_headp = µc_datap->microc_head;
- struct rt200_microc_seg* seg_list = NULL;
- struct rt200_microc_seg* curr_seg = NULL;
- struct rt200_microc_seg* prev_seg = NULL;
- int i;
-
- if (micro_path == NULL)
- return -1;
-
- if (micro_type == NULL)
- return -1;
-
- file = fopen(micro_path, "r");
- if (file == NULL) {
- ERROR_0("Cannot open microcode file\n");
- return -1;
- }
-
- if (!strcmp(micro_type, "BINARY"))
- {
- if (fread(microc_headp, sizeof(struct rt200_microc_head), 1, file) != 1)
- {
- ERROR("Cannot read header from file: %s\n", micro_path);
- goto fail_exit;
- }
-
- DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg);
-
- if (microc_headp->num_seg == 0)
- goto fail_exit;
-
- for (i = 0; i < microc_headp->num_seg; i++)
- {
- int ret;
-
- curr_seg = (struct rt200_microc_seg*)Xalloc(sizeof(struct rt200_microc_seg));
- if (curr_seg == NULL)
- {
- ERROR_0("Cannot allocate memory\n");
- goto fail_exit;
- }
-
- ret = fread(&curr_seg->num_bytes, 4, 1, file);
- ret += fread(&curr_seg->download_dst, 4, 1, file);
- ret += fread(&curr_seg->crc_val, 4, 1, file);
- if (ret != 3)
- {
- ERROR("Cannot read segment from microcode file: %s\n", micro_path);
- goto fail_exit;
- }
-
- curr_seg->data = (unsigned char*)Xalloc(curr_seg->num_bytes);
- if (curr_seg->data == NULL)
- {
- ERROR_0("cannot allocate memory\n");
- goto fail_exit;
- }
-
- DEBUG("Microcode: segment number: %x\n", i);
- DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes);
- DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst);
- DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val);
-
- if (seg_list)
- {
- prev_seg->next = curr_seg;
- curr_seg->next = NULL;
- prev_seg = curr_seg;
- }
- else
- seg_list = prev_seg = curr_seg;
-
- }
-
- curr_seg = seg_list;
- while (curr_seg)
- {
- if (fread(curr_seg->data, curr_seg->num_bytes, 1, file) != 1)
- {
- ERROR_0("Cannot read segment data\n");
- goto fail_exit;
- }
-
- curr_seg = curr_seg->next;
- }
- }
- else if (!strcmp(micro_type, "ASCII"))
- {
- char tmp1[12], tmp2[12], tmp3[12], tmp4[12];
- unsigned int ltmp;
-
- if ((fgets(tmp1, 12, file) != NULL) &&
- (fgets(tmp2, 12, file) != NULL) &&
- (fgets(tmp3, 12, file) != NULL) &&
- fgets(tmp4, 12, file) != NULL)
- {
- microc_headp->device_id = strtoul(tmp1, NULL, 16);
- microc_headp->vendor_id = strtoul(tmp2, NULL, 16);
- microc_headp->revision_id = strtoul(tmp3, NULL, 16);
- microc_headp->num_seg = strtoul(tmp4, NULL, 16);
- }
- else
- {
- ERROR("Cannot read header from file: %s\n", micro_path);
- goto fail_exit;
- }
-
- DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg);
-
- if (microc_headp->num_seg == 0)
- goto fail_exit;
-
- for (i = 0; i < microc_headp->num_seg; i++)
- {
- curr_seg = (struct rt200_microc_seg*)Xalloc(sizeof(struct rt200_microc_seg));
- if (curr_seg == NULL)
- {
- ERROR_0("Cannot allocate memory\n");
- goto fail_exit;
- }
-
- if (fgets(tmp1, 12, file) != NULL &&
- fgets(tmp2, 12, file) != NULL &&
- fgets(tmp3, 12, file) != NULL)
- {
- curr_seg->num_bytes = strtoul(tmp1, NULL, 16);
- curr_seg->download_dst = strtoul(tmp2, NULL, 16);
- curr_seg->crc_val = strtoul(tmp3, NULL, 16);
- }
- else
- {
- ERROR("Cannot read segment from microcode file: %s\n", micro_path);
- goto fail_exit;
- }
-
- curr_seg->data = (unsigned char*)Xalloc(curr_seg->num_bytes);
- if (curr_seg->data == NULL)
- {
- ERROR_0("cannot allocate memory\n");
- goto fail_exit;
- }
-
- DEBUG("Microcode: segment number: %x\n", i);
- DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes);
- DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst);
- DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val);
-
- if (seg_list)
- {
- curr_seg->next = NULL;
- prev_seg->next = curr_seg;
- prev_seg = curr_seg;
- }
- else
- seg_list = prev_seg = curr_seg;
- }
-
- curr_seg = seg_list;
- while (curr_seg)
- {
- for ( i = 0; i < curr_seg->num_bytes; i+=4)
- {
-
- if (fgets(tmp1, 12, file) == NULL)
- {
- ERROR_0("Cannot read from file\n");
- goto fail_exit;
- }
- ltmp = strtoul(tmp1, NULL, 16);
-
- *(unsigned int*)(curr_seg->data + i) = ltmp;
- }
-
- curr_seg = curr_seg->next;
- }
-
- }
- else
- {
- ERROR("File type %s unknown\n", micro_type);
- }
-
- microc_datap->microc_seg_list = seg_list;
-
- fclose(file);
- return 0;
-
-fail_exit:
- curr_seg = seg_list;
- while(curr_seg)
- {
- Xfree(curr_seg->data);
- prev_seg = curr_seg;
- curr_seg = curr_seg->next;
- Xfree(prev_seg);
- }
- fclose(file);
-
- return -1;
-}
-
-static void microc_clean(struct rt200_microc_data* microc_datap, int screen)
-{
- struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list;
- struct rt200_microc_seg* prev_seg;
-
- while(seg_list)
- {
- Xfree(seg_list->data);
- prev_seg = seg_list;
- seg_list = seg_list->next;
- Xfree(prev_seg);
- }
-}
-
-static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap)
-{
- CARD32 data;
- int i = 0;
- int screen = t->VIP->scrnIndex;
-
- /* Map FIFOD to DSP Port I/O port */
- RT_regr(VIP_HOSTINTF_PORT_CNTL, &data);
- RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE));
-
- /* The default endianess is LE. It matches the ost one for x86 */
- RT_regr(VIP_HOSTINTF_PORT_CNTL, &data);
- RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP));
-
- /* Wait until Shuttle bus channel 14 is available */
- RT_regr(VIP_TC_STATUS, &data);
- while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000))
- RT_regr(VIP_TC_STATUS, &data);
-
- DEBUG_0("Microcode: dsp_init: channel 14 available\n");
-
- return 0;
-}
-
-static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap)
-{
- struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list;
- CARD8 data8;
- CARD32 data, fb_scratch0, fb_scratch1;
- CARD32 i;
- CARD32 tries = 0;
- CARD32 result = 0;
- CARD32 seg_id = 0;
- int screen = t->VIP->scrnIndex;
-
- DEBUG("Microcode: before everything: %x\n", data8);
-
- if (RT_fifor(0x000, &data8))
- DEBUG("Microcode: FIFO status0: %x\n", data8);
- else
- {
- ERROR_0("Microcode: error reading FIFO status0\n");
- return -1;
- }
-
-
- if (RT_fifor(0x100, &data8))
- DEBUG("Microcode: FIFO status1: %x\n", data8);
- else
- {
- ERROR_0("Microcode: error reading FIFO status1\n");
- return -1;
- }
-
- /*
- * Download the Boot Code and CRC Checking Code (first segment)
- */
- seg_id = 1;
- while(result != DSP_OK && tries < 10)
- {
- /* Put DSP in reset before download (0x02) */
- RT_regr(VIP_TC_DOWNLOAD, &data);
- RT_regw(VIP_TC_DOWNLOAD, (data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE) | (0x02 << 17));
-
- /*
- * Configure shuttle bus for tranfer between DSP I/O "Program Interface"
- * and Program Memory at address 0
- */
-
- RT_regw(VIP_TC_SOURCE, 0x90000000);
- RT_regw(VIP_TC_DESTINATION, 0x00000000);
- RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7));
-
- /* Load first segment */
- DEBUG_0("Microcode: Loading first segment\n");
-
- if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data))
- {
- ERROR_0("Microcode: write to FIFOD failed\n");
- return -1;
- }
-
- /* Wait until Shuttle bus channel 14 is available */
- i = data = 0;
- RT_regr(VIP_TC_STATUS, &data);
- while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000))
- RT_regr(VIP_TC_STATUS, &data);
-
- if (i >= 10000)
- {
- ERROR_0("Microcode: channel 14 timeout\n");
- return -1;
- }
-
- DEBUG_0("Microcode: dsp_load: checkpoint 1\n");
- DEBUG("Microcode: TC_STATUS: %x\n", data);
-
- /* transfer the code from program memory to data memory */
- RT_regw(VIP_TC_SOURCE, 0x00000000);
- RT_regw(VIP_TC_DESTINATION, 0x10000000);
- RT_regw(VIP_TC_COMMAND, 0xe0000006 | ((seg_list->num_bytes - 1) << 7));
-
- /* Wait until Shuttle bus channel 14 is available */
- i = data = 0;
- RT_regr(VIP_TC_STATUS, &data);
- while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000))
- RT_regr(VIP_TC_STATUS, &data);
-
- if (i >= 10000)
- {
- ERROR_0("Microcode: channel 14 timeout\n");
- return -1;
- }
- DEBUG_0("Microcode: dsp_load: checkpoint 2\n");
- DEBUG("Microcode: TC_STATUS: %x\n", data);
-
- /* Take DSP out from reset (0x0) */
- data = 0;
- RT_regr(VIP_TC_DOWNLOAD, &data);
- RT_regw(VIP_TC_DOWNLOAD, data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE);
-
- RT_regr(VIP_TC_STATUS, &data);
- DEBUG_0("Microcode: dsp_load: checkpoint 3\n");
- DEBUG("Microcode: TC_STATUS: %x\n", data);
-
- /* send dsp_download_check_CRC */
- fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193);
- fb_scratch1 = (unsigned int)seg_list->crc_val;
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG_0("Microcode: dsp_load: checkpoint 4\n");
- }
-
- if (tries >= 10)
- {
- ERROR_0("Microcode: Download of boot degment failed\n");
- return -1;
- }
-
- DEBUG_0("Microcode: Download of boot code succeeded\n");
-
- while((seg_list = seg_list->next) != NULL)
- {
- seg_id++;
- result = tries = 0;
- while(result != DSP_OK && tries < 10)
- {
- /*
- * Configure shuttle bus for tranfer between DSP I/O "Program Interface"
- * and Data Memory at address 0
- */
-
- RT_regw(VIP_TC_SOURCE, 0x90000000);
- RT_regw(VIP_TC_DESTINATION, 0x10000000);
- RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7));
-
- if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data))
- {
- ERROR_0("Microcode: write to FIFOD failed\n");
- return -1;
- }
-
- i = data = 0;
- RT_regr(VIP_TC_STATUS, &data);
- while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000))
- RT_regr(VIP_TC_STATUS, &data);
-
- /* send dsp_download_check_CRC */
- fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193);
- fb_scratch1 = (unsigned int)seg_list->crc_val;
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
- }
-
- if (i >=10)
- {
- ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id);
- return -1;
- }
-
- DEBUG("Microcode: segment: %x loaded\n", seg_id);
-
- /*
- * The segment is downloaded correctly to data memory. Now move it to code memory
- * by using dsp_download_code_transfer command.
- */
-
- fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 194);
- fb_scratch1 = (unsigned int)seg_list->download_dst;
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- if (result != DSP_OK)
- {
- ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id);
- return -1;
- }
- }
-
- DEBUG_0("Microcode: download complete\n");
-
- /*
- * The last step is sending dsp_download_check_CRC with "download complete"
- */
-
- fb_scratch0 = ((165 << 8) & 0xff00) | (0xff & 193);
- fb_scratch1 = (unsigned int)0x11111;
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- if (result == DSP_OK)
- DEBUG_0("Microcode: DSP microcode successfully loaded\n");
- else
- {
- ERROR_0("Microcode: DSP microcode UNsuccessfully loaded\n");
- return -1;
- }
-
- return 0;
-}
-
-static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0)
-{
- CARD32 data;
- int i;
-
- /*
- * Clear the FB_INT0 bit in INT_CNTL
- */
- RT_regr(VIP_INT_CNTL, &data);
- RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR);
-
- /*
- * Write FB_SCRATCHx registers. If FB_SCRATCH1==0 then we have a DWORD command.
- */
- RT_regw(VIP_FB_SCRATCH0, fb_scratch0);
- if (fb_scratch1 != 0)
- RT_regw(VIP_FB_SCRATCH1, fb_scratch1);
-
- /*
- * Attention DSP. We are talking to you.
- */
- RT_regr(VIP_FB_INT, &data);
- RT_regw(VIP_FB_INT, data | VIP_FB_INT__INT_7);
-
- /*
- * Wait (by polling) for the DSP to process the command.
- */
- i = 0;
- RT_regr(VIP_INT_CNTL, &data);
- while((!(data & VIP_INT_CNTL__FB_INT0)) /*&& (i++ < 10000)*/)
- RT_regr(VIP_INT_CNTL, &data);
-
- /*
- * The return code is in FB_SCRATCH0
- */
- RT_regr(VIP_FB_SCRATCH0, &fb_scratch0);
-
- /*
- * If we are here it means we got an answer. Clear the FB_INT0 bit.
- */
- RT_regr(VIP_INT_CNTL, &data);
- RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR);
-
-
- return fb_scratch0;
-}
-
-static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector)
-{
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff);
-
- result = dsp_send_command(t, 0, fb_scratch0);
-
- DEBUG_2("dsp_set_video_input_connector: %x, result: %x\n", connector, result);
-
- return result;
-}
-
-#if 0
-static CARD32 dsp_reset(TheatrePtr t)
-{
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff);
-
- result = dsp_send_command(t, 0, fb_scratch0);
-
- DEBUG("dsp_reset: %x\n", result);
-
- return result;
-}
-#endif
-
-static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate)
-{
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff);
-
- result = dsp_send_command(t, 0, fb_scratch0);
-
- DEBUG("dsp_set_lowpowerstate: %x\n", result);
-
- return result;
-}
-static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard)
-{
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff);
-
- result = dsp_send_command(t, 0, fb_scratch0);
-
- DEBUG("dsp_set_video_standard: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format)
-{
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff);
-
- result = dsp_send_command(t, 0, fb_scratch0);
-
- DEBUG("dsp_set_videostreamformat: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_video_standard_detection(TheatrePtr t)
-{
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = 0 | (54 & 0xff);
-
- result = dsp_send_command(t, 0, fb_scratch0);
-
- DEBUG("dsp_video_standard_detection: %x\n", result);
-
- return result;
-}
-
-#if 0
-static CARD32 dsp_get_signallockstatus(TheatrePtr t)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = 0 | (77 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG_3("dsp_get_signallockstatus: %x, h_pll: %x, v_pll: %x\n", \
- result, (result >> 8) & 0xff, (result >> 16) & 0xff);
-
- return result;
-}
-
-static CARD32 dsp_get_signallinenumber(TheatrePtr t)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = 0 | (78 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG_2("dsp_get_signallinenumber: %x, linenum: %x\n", \
- result, (result >> 8) & 0xffff);
-
- return result;
-}
-#endif
-
-static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_brightness: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_contrast: %x\n", result);
-
- return result;
-}
-
-#if 0
-static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = 0 | (73 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_sharpness: %x\n", result);
-
- return result;
-}
-#endif
-
-static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_tint: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_saturation: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff);
- fb_scratch1 = ((horz_end << 16) & 0xffff0000) | (horz_start & 0xffff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_video_scaler_horizontal: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff);
- fb_scratch1 = ((vert_end << 16) & 0xffff0000) | (vert_start & 0xffff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_video_scaler_vertical: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_audio_mute: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_set_audio_volume: %x\n", result);
-
- return result;
-}
-
-#if 0
-static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_audio_detection: %x\n", result);
-
- return result;
-}
-#endif
-
-static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_configure_i2s_port: %x\n", result);
-
- return result;
-}
-
-static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state)
-{
- CARD32 fb_scratch1 = 0;
- CARD32 fb_scratch0 = 0;
- CARD32 result;
- int screen = t->VIP->scrnIndex;
-
- fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff);
-
- result = dsp_send_command(t, fb_scratch1, fb_scratch0);
-
- DEBUG("dsp_configure_spdif_port: %x\n", result);
-
- return result;
-}
-
-enum
-{
-fld_tmpReg1=0,
-fld_tmpReg2,
-fld_tmpReg3,
-fld_LP_CONTRAST,
-fld_LP_BRIGHTNESS,
-fld_CP_HUE_CNTL,
-fld_LUMA_FILTER,
-fld_H_SCALE_RATIO,
-fld_H_SHARPNESS,
-fld_V_SCALE_RATIO,
-fld_V_DEINTERLACE_ON,
-fld_V_BYPSS,
-fld_V_DITHER_ON,
-fld_EVENF_OFFSET,
-fld_ODDF_OFFSET,
-fld_INTERLACE_DETECTED,
-fld_VS_LINE_COUNT,
-fld_VS_DETECTED_LINES,
-fld_VS_ITU656_VB,
-fld_VBI_CC_DATA,
-fld_VBI_CC_WT,
-fld_VBI_CC_WT_ACK,
-fld_VBI_CC_HOLD,
-fld_VBI_DECODE_EN,
-fld_VBI_CC_DTO_P,
-fld_VBI_20BIT_DTO_P,
-fld_VBI_CC_LEVEL,
-fld_VBI_20BIT_LEVEL,
-fld_VBI_CLK_RUNIN_GAIN,
-fld_H_VBI_WIND_START,
-fld_H_VBI_WIND_END,
-fld_V_VBI_WIND_START,
-fld_V_VBI_WIND_END,
-fld_VBI_20BIT_DATA0,
-fld_VBI_20BIT_DATA1,
-fld_VBI_20BIT_WT,
-fld_VBI_20BIT_WT_ACK,
-fld_VBI_20BIT_HOLD,
-fld_VBI_CAPTURE_ENABLE,
-fld_VBI_EDS_DATA,
-fld_VBI_EDS_WT,
-fld_VBI_EDS_WT_ACK,
-fld_VBI_EDS_HOLD,
-fld_VBI_SCALING_RATIO,
-fld_VBI_ALIGNER_ENABLE,
-fld_H_ACTIVE_START,
-fld_H_ACTIVE_END,
-fld_V_ACTIVE_START,
-fld_V_ACTIVE_END,
-fld_CH_HEIGHT,
-fld_CH_KILL_LEVEL,
-fld_CH_AGC_ERROR_LIM,
-fld_CH_AGC_FILTER_EN,
-fld_CH_AGC_LOOP_SPEED,
-fld_HUE_ADJ,
-fld_STANDARD_SEL,
-fld_STANDARD_YC,
-fld_ADC_PDWN,
-fld_INPUT_SELECT,
-fld_ADC_PREFLO,
-fld_H_SYNC_PULSE_WIDTH,
-fld_HS_GENLOCKED,
-fld_HS_SYNC_IN_WIN,
-fld_VIN_ASYNC_RST,
-fld_DVS_ASYNC_RST,
-fld_VIP_VENDOR_ID,
-fld_VIP_DEVICE_ID,
-fld_VIP_REVISION_ID,
-fld_BLACK_INT_START,
-fld_BLACK_INT_LENGTH,
-fld_UV_INT_START,
-fld_U_INT_LENGTH,
-fld_V_INT_LENGTH,
-fld_CRDR_ACTIVE_GAIN,
-fld_CBDB_ACTIVE_GAIN,
-fld_DVS_DIRECTION,
-fld_DVS_VBI_CARD8_SWAP,
-fld_DVS_CLK_SELECT,
-fld_CONTINUOUS_STREAM,
-fld_DVSOUT_CLK_DRV,
-fld_DVSOUT_DATA_DRV,
-fld_COMB_CNTL0,
-fld_COMB_CNTL1,
-fld_COMB_CNTL2,
-fld_COMB_LENGTH,
-fld_SYNCTIP_REF0,
-fld_SYNCTIP_REF1,
-fld_CLAMP_REF,
-fld_AGC_PEAKWHITE,
-fld_VBI_PEAKWHITE,
-fld_WPA_THRESHOLD,
-fld_WPA_TRIGGER_LO,
-fld_WPA_TRIGGER_HIGH,
-fld_LOCKOUT_START,
-fld_LOCKOUT_END,
-fld_CH_DTO_INC,
-fld_PLL_SGAIN,
-fld_PLL_FGAIN,
-fld_CR_BURST_GAIN,
-fld_CB_BURST_GAIN,
-fld_VERT_LOCKOUT_START,
-fld_VERT_LOCKOUT_END,
-fld_H_IN_WIND_START,
-fld_V_IN_WIND_START,
-fld_H_OUT_WIND_WIDTH,
-fld_V_OUT_WIND_WIDTH,
-fld_HS_LINE_TOTAL,
-fld_MIN_PULSE_WIDTH,
-fld_MAX_PULSE_WIDTH,
-fld_WIN_CLOSE_LIMIT,
-fld_WIN_OPEN_LIMIT,
-fld_VSYNC_INT_TRIGGER,
-fld_VSYNC_INT_HOLD,
-fld_VIN_M0,
-fld_VIN_N0,
-fld_MNFLIP_EN,
-fld_VIN_P,
-fld_REG_CLK_SEL,
-fld_VIN_M1,
-fld_VIN_N1,
-fld_VIN_DRIVER_SEL,
-fld_VIN_MNFLIP_REQ,
-fld_VIN_MNFLIP_DONE,
-fld_TV_LOCK_TO_VIN,
-fld_TV_P_FOR_WINCLK,
-fld_VINRST,
-fld_VIN_CLK_SEL,
-fld_VS_FIELD_BLANK_START,
-fld_VS_FIELD_BLANK_END,
-fld_VS_FIELD_IDLOCATION,
-fld_VS_FRAME_TOTAL,
-fld_SYNC_TIP_START,
-fld_SYNC_TIP_LENGTH,
-fld_GAIN_FORCE_DATA,
-fld_GAIN_FORCE_EN,
-fld_I_CLAMP_SEL,
-fld_I_AGC_SEL,
-fld_EXT_CLAMP_CAP,
-fld_EXT_AGC_CAP,
-fld_DECI_DITHER_EN,
-fld_ADC_PREFHI,
-fld_ADC_CH_GAIN_SEL,
-fld_HS_PLL_SGAIN,
-fld_NREn,
-fld_NRGainCntl,
-fld_NRBWTresh,
-fld_NRGCTresh,
-fld_NRCoefDespeclMode,
-fld_GPIO_5_OE,
-fld_GPIO_6_OE,
-fld_GPIO_5_OUT,
-fld_GPIO_6_OUT,
-
-regRT_MAX_REGS
-} a;
-
-
-typedef struct {
- CARD8 size;
- CARD32 fld_id;
- CARD32 dwRegAddrLSBs;
- CARD32 dwFldOffsetLSBs;
- CARD32 dwMaskLSBs;
- CARD32 addr2;
- CARD32 offs2;
- CARD32 mask2;
- CARD32 dwCurrValue;
- CARD32 rw;
- } RTREGMAP;
-
-#define READONLY 1
-#define WRITEONLY 2
-#define READWRITE 3
-
-/* Rage Theatre's Register Mappings, including the default values: */
-RTREGMAP RT_RegMap[regRT_MAX_REGS]={
-/*
-{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W
-*/
-{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE },
-{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE },
-{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE },
-{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE },
-{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE },
-{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE },
-{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE },
-{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE },
-{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE },
-{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE },
-{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE },
-{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE },
-{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE },
-{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE },
-{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE },
-{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY },
-{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY },
-{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY },
-{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY },
-{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE },
-{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE },
-{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY },
-{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE },
-{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE },
-{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE },
-{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE },
-{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE },
-{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE },
-{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE },
-{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE },
-{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE },
-{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE },
-{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */
-{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE },
-{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE },
-{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE },
-{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY },
-{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE },
-{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE },
-{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE },
-{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE },
-{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY },
-{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE },
-{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE },
-{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE },
-{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE },
-{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE },
-{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE },
-{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE },
-{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE },
-{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE },
-{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE },
-{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE },
-{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE },
-{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE },
-{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE },
-{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE },
-{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE },
-{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE },
-{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE },
-{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY },
-{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY },
-{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY },
-{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE },
-{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE },
-{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY },
-{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY },
-{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY },
-{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE },
-{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE },
-{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE },
-{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE },
-{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE },
-{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE },
-{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE },
-{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE },
-{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE },
-{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE },
-{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE },
-{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE },
-{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE },
-{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE },
-{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE },
-{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE },
-{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE },
-{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE },
-{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE },
-{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE },
-{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE },
-{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE },
-{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE },
-{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE },
-{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE },
-{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE },
-{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE },
-{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE },
-{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE },
-{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE },
-{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE },
-{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE },
-{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE },
-{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE },
-{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE },
-{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE },
-{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE },
-{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE },
-{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE },
-{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE },
-{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE },
-{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE },
-{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE },
-{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE },
-{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE },
-{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE },
-{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE },
-{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE },
-{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE },
-{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE },
-{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE },
-{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE },
-{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE },
-{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE },
-{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY },
-{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE },
-{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE },
-{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE },
-{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE },
-{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE },
-{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE },
-{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE },
-{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE },
-{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE },
-{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE },
-{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE },
-{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE },
-{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE },
-{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE },
-{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE },
-{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE },
-{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE },
-{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE },
-{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE },
-{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE },
-{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE },
-{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE },
-{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE },
-{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE },
-{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE },
-{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE },
-{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE },
-{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE },
-{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE },
-};
-
-/* Rage Theatre's register fields default values: */
-CARD32 RT_RegDef[regRT_MAX_REGS]=
-{
-fld_tmpReg1_def,
-fld_tmpReg2_def,
-fld_tmpReg3_def,
-fld_LP_CONTRAST_def,
-fld_LP_BRIGHTNESS_def,
-fld_CP_HUE_CNTL_def,
-fld_LUMA_FILTER_def,
-fld_H_SCALE_RATIO_def,
-fld_H_SHARPNESS_def,
-fld_V_SCALE_RATIO_def,
-fld_V_DEINTERLACE_ON_def,
-fld_V_BYPSS_def,
-fld_V_DITHER_ON_def,
-fld_EVENF_OFFSET_def,
-fld_ODDF_OFFSET_def,
-fld_INTERLACE_DETECTED_def,
-fld_VS_LINE_COUNT_def,
-fld_VS_DETECTED_LINES_def,
-fld_VS_ITU656_VB_def,
-fld_VBI_CC_DATA_def,
-fld_VBI_CC_WT_def,
-fld_VBI_CC_WT_ACK_def,
-fld_VBI_CC_HOLD_def,
-fld_VBI_DECODE_EN_def,
-fld_VBI_CC_DTO_P_def,
-fld_VBI_20BIT_DTO_P_def,
-fld_VBI_CC_LEVEL_def,
-fld_VBI_20BIT_LEVEL_def,
-fld_VBI_CLK_RUNIN_GAIN_def,
-fld_H_VBI_WIND_START_def,
-fld_H_VBI_WIND_END_def,
-fld_V_VBI_WIND_START_def,
-fld_V_VBI_WIND_END_def,
-fld_VBI_20BIT_DATA0_def,
-fld_VBI_20BIT_DATA1_def,
-fld_VBI_20BIT_WT_def,
-fld_VBI_20BIT_WT_ACK_def,
-fld_VBI_20BIT_HOLD_def,
-fld_VBI_CAPTURE_ENABLE_def,
-fld_VBI_EDS_DATA_def,
-fld_VBI_EDS_WT_def,
-fld_VBI_EDS_WT_ACK_def,
-fld_VBI_EDS_HOLD_def,
-fld_VBI_SCALING_RATIO_def,
-fld_VBI_ALIGNER_ENABLE_def,
-fld_H_ACTIVE_START_def,
-fld_H_ACTIVE_END_def,
-fld_V_ACTIVE_START_def,
-fld_V_ACTIVE_END_def,
-fld_CH_HEIGHT_def,
-fld_CH_KILL_LEVEL_def,
-fld_CH_AGC_ERROR_LIM_def,
-fld_CH_AGC_FILTER_EN_def,
-fld_CH_AGC_LOOP_SPEED_def,
-fld_HUE_ADJ_def,
-fld_STANDARD_SEL_def,
-fld_STANDARD_YC_def,
-fld_ADC_PDWN_def,
-fld_INPUT_SELECT_def,
-fld_ADC_PREFLO_def,
-fld_H_SYNC_PULSE_WIDTH_def,
-fld_HS_GENLOCKED_def,
-fld_HS_SYNC_IN_WIN_def,
-fld_VIN_ASYNC_RST_def,
-fld_DVS_ASYNC_RST_def,
-fld_VIP_VENDOR_ID_def,
-fld_VIP_DEVICE_ID_def,
-fld_VIP_REVISION_ID_def,
-fld_BLACK_INT_START_def,
-fld_BLACK_INT_LENGTH_def,
-fld_UV_INT_START_def,
-fld_U_INT_LENGTH_def,
-fld_V_INT_LENGTH_def,
-fld_CRDR_ACTIVE_GAIN_def,
-fld_CBDB_ACTIVE_GAIN_def,
-fld_DVS_DIRECTION_def,
-fld_DVS_VBI_CARD8_SWAP_def,
-fld_DVS_CLK_SELECT_def,
-fld_CONTINUOUS_STREAM_def,
-fld_DVSOUT_CLK_DRV_def,
-fld_DVSOUT_DATA_DRV_def,
-fld_COMB_CNTL0_def,
-fld_COMB_CNTL1_def,
-fld_COMB_CNTL2_def,
-fld_COMB_LENGTH_def,
-fld_SYNCTIP_REF0_def,
-fld_SYNCTIP_REF1_def,
-fld_CLAMP_REF_def,
-fld_AGC_PEAKWHITE_def,
-fld_VBI_PEAKWHITE_def,
-fld_WPA_THRESHOLD_def,
-fld_WPA_TRIGGER_LO_def,
-fld_WPA_TRIGGER_HIGH_def,
-fld_LOCKOUT_START_def,
-fld_LOCKOUT_END_def,
-fld_CH_DTO_INC_def,
-fld_PLL_SGAIN_def,
-fld_PLL_FGAIN_def,
-fld_CR_BURST_GAIN_def,
-fld_CB_BURST_GAIN_def,
-fld_VERT_LOCKOUT_START_def,
-fld_VERT_LOCKOUT_END_def,
-fld_H_IN_WIND_START_def,
-fld_V_IN_WIND_START_def,
-fld_H_OUT_WIND_WIDTH_def,
-fld_V_OUT_WIND_WIDTH_def,
-fld_HS_LINE_TOTAL_def,
-fld_MIN_PULSE_WIDTH_def,
-fld_MAX_PULSE_WIDTH_def,
-fld_WIN_CLOSE_LIMIT_def,
-fld_WIN_OPEN_LIMIT_def,
-fld_VSYNC_INT_TRIGGER_def,
-fld_VSYNC_INT_HOLD_def,
-fld_VIN_M0_def,
-fld_VIN_N0_def,
-fld_MNFLIP_EN_def,
-fld_VIN_P_def,
-fld_REG_CLK_SEL_def,
-fld_VIN_M1_def,
-fld_VIN_N1_def,
-fld_VIN_DRIVER_SEL_def,
-fld_VIN_MNFLIP_REQ_def,
-fld_VIN_MNFLIP_DONE_def,
-fld_TV_LOCK_TO_VIN_def,
-fld_TV_P_FOR_WINCLK_def,
-fld_VINRST_def,
-fld_VIN_CLK_SEL_def,
-fld_VS_FIELD_BLANK_START_def,
-fld_VS_FIELD_BLANK_END_def,
-fld_VS_FIELD_IDLOCATION_def,
-fld_VS_FRAME_TOTAL_def,
-fld_SYNC_TIP_START_def,
-fld_SYNC_TIP_LENGTH_def,
-fld_GAIN_FORCE_DATA_def,
-fld_GAIN_FORCE_EN_def,
-fld_I_CLAMP_SEL_def,
-fld_I_AGC_SEL_def,
-fld_EXT_CLAMP_CAP_def,
-fld_EXT_AGC_CAP_def,
-fld_DECI_DITHER_EN_def,
-fld_ADC_PREFHI_def,
-fld_ADC_CH_GAIN_SEL_def,
-fld_HS_PLL_SGAIN_def,
-fld_NREn_def,
-fld_NRGainCntl_def,
-fld_NRBWTresh_def,
-fld_NRGCTresh_def,
-fld_NRCoefDespeclMode_def,
-fld_GPIO_5_OE_def,
-fld_GPIO_6_OE_def,
-fld_GPIO_5_OUT_def,
-fld_GPIO_6_OUT_def,
-};
-
-/****************************************************************************
- * WriteRT_fld (CARD32 dwReg, CARD32 dwData) *
- * Function: Writes a register field within Rage Theatre *
- * Inputs: CARD32 dwReg = register field to be written *
- * CARD32 dwData = data that will be written to the reg field *
- * Outputs: NONE *
- ****************************************************************************/
-static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData)
-{
- CARD32 dwResult=0;
- CARD32 dwValue=0;
-
- if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE)
- {
- dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) |
- (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs);
-
- if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE)
- {
- /* update the memory mapped registers */
- RT_RegMap[dwReg].dwCurrValue = dwData;
- }
- }
-
- return;
-
-} /* WriteRT_fld ()... */
-
-#if 0
-/****************************************************************************
- * ReadRT_fld (CARD32 dwReg) *
- * Function: Reads a register field within Rage Theatre *
- * Inputs: CARD32 dwReg = register field to be read *
- * Outputs: CARD32 - value read from register field *
- ****************************************************************************/
-static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg)
-{
- CARD32 dwResult=0;
-
- if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE)
- {
- RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >>
- RT_RegMap[dwReg].dwFldOffsetLSBs);
- return (RT_RegMap[dwReg].dwCurrValue);
- }
- else
- {
- return (0xFFFFFFFF);
- }
-
-} /* ReadRT_fld ()... */
-
-#define ReadRT_fld(a) ReadRT_fld1(t,(a))
-#endif
-
-#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b))
-
-
-/****************************************************************************
- * RT_SetTint (int hue) *
- * Function: sets the tint (hue) for the Rage Theatre video in *
- * Inputs: int hue - the hue value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetTint (TheatrePtr t, int hue)
-{
- /* Validate Hue level */
- if (hue < -1000)
- {
- hue = -1000;
- }
- else if (hue > 1000)
- {
- hue = 1000;
- }
-
- t->iHue=hue;
-
- dsp_set_tint(t, (CARD8)((hue*255)/2000 + 128));
-
-} /* RT_SetTint ()... */
-
-
-/****************************************************************************
- * RT_SetSaturation (int Saturation) *
- * Function: sets the saturation level for the Rage Theatre video in *
- * Inputs: int Saturation - the saturation value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetSaturation (TheatrePtr t, int Saturation)
-{
- /* VALIDATE SATURATION LEVEL */
- if (Saturation < -1000L)
- {
- Saturation = -1000;
- }
- else if (Saturation > 1000L)
- {
- Saturation = 1000;
- }
-
- t->iSaturation = Saturation;
-
- /* RT200 has saturation in range 0 to 255 with nominal value 128 */
- dsp_set_saturation(t, (CARD8)((Saturation*255)/2000 + 128));
-
- return;
-} /* RT_SetSaturation ()...*/
-
-/****************************************************************************
- * RT_SetBrightness (int Brightness) *
- * Function: sets the brightness level for the Rage Theatre video in *
- * Inputs: int Brightness - the brightness value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetBrightness (TheatrePtr t, int Brightness)
-{
- /* VALIDATE BRIGHTNESS LEVEL */
- if (Brightness < -1000)
- {
- Brightness = -1000;
- }
- else if (Brightness > 1000)
- {
- Brightness = 1000;
- }
-
- /* Save value */
- t->iBrightness = Brightness;
- t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0;
-
- /* RT200 is having brightness level from 0 to 255 with 128 nominal value */
- dsp_set_brightness(t, (CARD8)((Brightness*255)/2000 + 128));
-
- return;
-} /* RT_SetBrightness ()... */
-
-
-/****************************************************************************
- * RT_SetSharpness (CARD16 wSharpness) *
- * Function: sets the sharpness level for the Rage Theatre video in *
- * Inputs: CARD16 wSharpness - the sharpness value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness)
-{
- switch (wSharpness)
- {
- case DEC_SMOOTH :
- WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS);
- t->wSharpness = RT_NORM_SHARPNESS;
- break;
- case DEC_SHARP :
- WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS);
- t->wSharpness = RT_HIGH_SHARPNESS;
- break;
- default:
- break;
- }
- return;
-
-} /* RT_SetSharpness ()... */
-
-
-/****************************************************************************
- * RT_SetContrast (int Contrast) *
- * Function: sets the contrast level for the Rage Theatre video in *
- * Inputs: int Contrast - the contrast value to be set. *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetContrast (TheatrePtr t, int Contrast)
-{
- /* VALIDATE CONTRAST LEVEL */
- if (Contrast < -1000)
- {
- Contrast = -1000;
- }
- else if (Contrast > 1000)
- {
- Contrast = 1000;
- }
-
- /* Save contrast value */
- t->iContrast = Contrast;
- t->dbContrast = (double) (Contrast+1000.0) / 1000.0;
-
- /* RT200 has contrast values between 0 to 255 with nominal value at 128 */
- dsp_set_contrast(t, (CARD8)((Contrast*255)/2000 + 128));
- return;
-
-} /* RT_SetContrast ()... */
-
-/****************************************************************************
- * RT_SetInterlace (CARD8 bInterlace) *
- * Function: to set the interlacing pattern for the Rage Theatre video in *
- * Inputs: CARD8 bInterlace *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace)
-{
- switch(bInterlace)
- {
- case (TRUE): /*DEC_INTERLACE */
- WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1);
- t->wInterlaced = (CARD16) RT_DECINTERLACED;
- break;
- case (FALSE): /*DEC_NONINTERLACE */
- WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED);
- t->wInterlaced = (CARD16) RT_DECNONINTERLACED;
- break;
- default:
- break;
- }
-
- return;
-
-} /* RT_SetInterlace ()... */
-
-
-/****************************************************************************
- * RT_SetStandard (CARD16 wStandard) *
- * Function: to set the input standard for the Rage Theatre video in *
- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetStandard (TheatrePtr t, CARD16 wStandard)
-{
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n",
- wStandard);
-
- t->wStandard = wStandard;
-
- /* Program the new standards: */
- switch (wStandard & 0x00FF)
- {
- case (DEC_NTSC): /*NTSC GROUP - 480 lines */
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extNTSC):
- dsp_set_video_standard(t, 2);
- break;
- case (extNTSC_J):
- dsp_set_video_standard(t, RT200_NTSC_J);
- break;
- case (extNTSC_443):
- dsp_set_video_standard(t, RT200_NTSC_433);
- break;
- default:
- dsp_video_standard_detection(t);
- break;
- }
- break;
- case (DEC_PAL): /*PAL GROUP - 625 lines */
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extPAL):
- case (extPAL_B):
- case (extPAL_BGHI):
- dsp_set_video_standard(t, RT200_PAL_B);
- break;
- case (extPAL_D):
- dsp_set_video_standard(t, RT200_PAL_D);
- break;
- case (extPAL_G):
- dsp_set_video_standard(t, RT200_PAL_G);
- break;
- case (extPAL_H):
- dsp_set_video_standard(t, RT200_PAL_H);
- break;
- case (extPAL_I):
- dsp_set_video_standard(t, RT200_PAL_D);
- break;
- case (extPAL_N):
- dsp_set_video_standard(t, RT200_PAL_N);
- break;
- case (extPAL_NCOMB):
- dsp_set_video_standard(t, RT200_PAL_Ncomb);
- break;
- case (extPAL_M):
- dsp_set_video_standard(t, RT200_PAL_M);
- break;
- case (extPAL_60):
- dsp_set_video_standard(t, RT200_PAL_60);
- break;
- default:
- dsp_video_standard_detection(t);
- break;
- }
- break;
- case (DEC_SECAM): /*SECAM GROUP*/
- switch (wStandard & 0xFF00)
- {
- case (extNONE):
- case (extSECAM):
- dsp_set_video_standard(t, RT200_SECAM);
- break;
- case (extSECAM_B):
- dsp_set_video_standard(t, RT200_SECAM_B);
- break;
- case (extSECAM_D):
- dsp_set_video_standard(t, RT200_SECAM_D);
- break;
- case (extSECAM_G):
- dsp_set_video_standard(t, RT200_SECAM_G);
- break;
- case (extSECAM_H):
- dsp_set_video_standard(t, RT200_SECAM_H);
- break;
- case (extSECAM_K):
- dsp_set_video_standard(t, RT200_SECAM_K);
- break;
- case (extSECAM_K1):
- dsp_set_video_standard(t, RT200_SECAM_K1);
- break;
- case (extSECAM_L):
- dsp_set_video_standard(t, RT200_SECAM_L);
- break;
- case (extSECAM_L1):
- dsp_set_video_standard(t, RT200_SECAM_L1);
- break;
- default:
- dsp_video_standard_detection(t);
- break;
- }
- break;
- default:
- dsp_video_standard_detection(t);
- }
-
-} /* RT_SetStandard ()... */
-
-
-/****************************************************************************
- * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, *
- * CARD8 fCC_On, CARD8 fVBICap_On) *
- * Function: sets the output video size for the Rage Theatre video in *
- * Inputs: CARD16 wHorzSize - width of output in pixels *
- * CARD16 wVertSize - height of output in pixels (lines) *
- * CARD8 fCC_On - enable CC output *
- * CARD8 fVBI_Cap_On - enable VBI capture *
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On)
-{
- /* VBI is ignored now */
-
- /*
- * If I pass the (wHorzSize, 0, 0) (wVertSize, 0, 0) the image does not synchronize
- */
- dsp_set_video_scaler_horizontal(t, 0, 0, 0);
- dsp_set_video_scaler_vertical(t, 0, 0, 0);
-
-} /* RT_SetOutputVideoSize ()...*/
-
-
-/****************************************************************************
- * RT_SetConnector (CARD16 wStandard, int tunerFlag) *
- * Function:
- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
- * int tunerFlag
- * Outputs: NONE *
- ****************************************************************************/
-void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag)
-{
- CARD32 data;
-
- t->wConnector = wConnector;
-
- theatre_read(t, VIP_GPIO_CNTL, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n",
- (unsigned)data);
-
- theatre_read(t, VIP_GPIO_INOUT, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n",
- (unsigned)data);
-
- switch (wConnector)
- {
- case (DEC_TUNER): /* Tuner*/
- /* RT200 does not have any input connector 0 */
- dsp_set_video_input_connector(t, t->wTunerConnector + 1);
-
- /* this is to set the analog mux used for sond */
- theatre_read(t, VIP_GPIO_CNTL, &data);
- data &= ~0x10;
- theatre_write(t, VIP_GPIO_CNTL, data);
-
- theatre_read(t, VIP_GPIO_INOUT, &data);
- data &= ~0x10;
- theatre_write(t, VIP_GPIO_INOUT, data);
-
- break;
- case (DEC_COMPOSITE): /* Comp*/
- dsp_set_video_input_connector(t, t->wComp0Connector);
-
- /* this is to set the analog mux used for sond */
- theatre_read(t, VIP_GPIO_CNTL, &data);
- data |= 0x10;
- theatre_write(t, VIP_GPIO_CNTL, data);
-
- theatre_read(t, VIP_GPIO_INOUT, &data);
- data |= 0x10;
- theatre_write(t, VIP_GPIO_INOUT, data);
-
- break;
- case (DEC_SVIDEO): /* Svideo*/
- dsp_set_video_input_connector(t, t->wSVideo0Connector);
-
- /* this is to set the analog mux used for sond */
- theatre_read(t, VIP_GPIO_CNTL, &data);
- data |= 0x10;
- theatre_write(t, VIP_GPIO_CNTL, data);
-
- theatre_read(t, VIP_GPIO_INOUT, &data);
- data |= 0x10;
- theatre_write(t, VIP_GPIO_INOUT, data);
-
- break;
- default:
- dsp_set_video_input_connector(t, t->wComp0Connector);
- }
-
- theatre_read(t, VIP_GPIO_CNTL, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n",
- (unsigned)data);
-
- theatre_read(t, VIP_GPIO_INOUT, &data);
- xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n",
- (unsigned)data);
-
-
- dsp_configure_i2s_port(t, 0, 0, 0);
- dsp_configure_spdif_port(t, 0);
-
- /*dsp_audio_detection(t, 0);*/
- dsp_audio_mute(t, 1, 1);
- dsp_set_audio_volume(t, 128, 128, 0);
-
-} /* RT_SetConnector ()...*/
-
-
-void InitTheatre(TheatrePtr t)
-{
- CARD32 data;
- CARD32 M, N, P;
-
- /* this will give 108Mhz at 27Mhz reference */
- M = 28;
- N = 224;
- P = 1;
-
- ShutdownTheatre(t);
- usleep(100000);
- t->mode=MODE_INITIALIZATION_IN_PROGRESS;
-
-
- data = M | (N << 11) | (P <<24);
- RT_regw(VIP_DSP_PLL_CNTL, data);
-
- RT_regr(VIP_PLL_CNTL0, &data);
- data |= 0x2000;
- RT_regw(VIP_PLL_CNTL0, data);
-
- /* RT_regw(VIP_I2C_SLVCNTL, 0x249); */
- RT_regr(VIP_PLL_CNTL1, &data);
- data |= 0x00030003;
- RT_regw(VIP_PLL_CNTL1, data);
-
- RT_regr(VIP_PLL_CNTL0, &data);
- data &= 0xfffffffc;
- RT_regw(VIP_PLL_CNTL0, data);
- usleep(15000);
-
- RT_regr(VIP_CLOCK_SEL_CNTL, &data);
- data |= 0x1b;
- RT_regw(VIP_CLOCK_SEL_CNTL, data);
-
- RT_regr(VIP_MASTER_CNTL, &data);
- data &= 0xffffff07;
- RT_regw(VIP_MASTER_CNTL, data);
- data &= 0xffffff03;
- RT_regw(VIP_MASTER_CNTL, data);
- usleep(1000);
-
- if (t->microc_path == NULL)
- {
- t->microc_path = DEFAULT_MICROC_PATH;
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use default microcode path: %s\n", DEFAULT_MICROC_PATH);
- }
- else
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use microcode path: %s\n", t->microc_path);
-
-
- if (t->microc_type == NULL)
- {
- t->microc_type = DEFAULT_MICROC_TYPE;
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use default microcode type: %s\n", DEFAULT_MICROC_TYPE);
- }
- else
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use microcode type: %s\n", t->microc_type);
-
- if (DownloadMicrocode(t) < 0)
- {
- ShutdownTheatre(t);
- return;
- }
-
- dsp_set_lowpowerstate(t, 1);
- dsp_set_videostreamformat(t, 1);
-
- t->mode=MODE_INITIALIZED_FOR_TV_IN;
-}
-
-static int DownloadMicrocode(TheatrePtr t)
-{
- struct rt200_microc_data microc_data;
- microc_data.microc_seg_list = NULL;
-
- if (microc_load(t->microc_path, t->microc_type, µc_data, t->VIP->scrnIndex) < 0)
- {
- xf86DrvMsg(t->VIP->scrnIndex, X_ERROR, "Microcode: cannot load microcode\n");
- goto err_exit;
- }
- else
- {
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: device_id: %x\n", microc_data.microc_head.device_id);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: vendor_id: %x\n", microc_data.microc_head.vendor_id);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: rev_id: %x\n", microc_data.microc_head.revision_id);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: num_seg: %x\n", microc_data.microc_head.num_seg);
- }
-
- if (dsp_init(t, µc_data) < 0)
- {
- xf86DrvMsg(t->VIP->scrnIndex, X_ERROR, "Microcode: dsp_init failed\n");
- goto err_exit;
- }
- else
- {
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: dsp_init OK\n");
- }
-
- if (dsp_load(t, µc_data) < 0)
- {
- xf86DrvMsg(t->VIP->scrnIndex, X_ERROR, "Microcode: dsp_download failed\n");
- goto err_exit;
- }
- else
- {
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: dsp_download OK\n");
- }
-
- microc_clean(µc_data, t->VIP->scrnIndex);
- return 0;
-
-err_exit:
-
- microc_clean(µc_data, t->VIP->scrnIndex);
- return -1;
-
-}
-
-
-void ShutdownTheatre(TheatrePtr t)
-{
-#if 0
- WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE);
- WriteRT_fld (fld_VINRST , RT_VINRST_RESET);
- WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE);
- WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN);
-#endif
- t->mode=MODE_UNINITIALIZED;
-}
-
-void DumpRageTheatreRegs(TheatrePtr t)
-{
- int i;
- CARD32 data;
-
- for(i=0;i<0x900;i+=4)
- {
- RT_regr(i, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
- "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data);
- }
-
-}
-
-void DumpRageTheatreRegsByName(TheatrePtr t)
-{
- int i;
- CARD32 data;
- struct { char *name; long addr; } rt_reg_list[]={
- { "ADC_CNTL ", 0x0400 },
- { "ADC_DEBUG ", 0x0404 },
- { "AUD_CLK_DIVIDERS ", 0x00e8 },
- { "AUD_DTO_INCREMENTS ", 0x00ec },
- { "AUD_PLL_CNTL ", 0x00e0 },
- { "AUD_PLL_FINE_CNTL ", 0x00e4 },
- { "CLKOUT_CNTL ", 0x004c },
- { "CLKOUT_GPIO_CNTL ", 0x0038 },
- { "CLOCK_SEL_CNTL ", 0x00d0 },
- { "COMB_CNTL0 ", 0x0440 },
- { "COMB_CNTL1 ", 0x0444 },
- { "COMB_CNTL2 ", 0x0448 },
- { "COMB_LINE_LENGTH ", 0x044c },
- { "CP_ACTIVE_GAIN ", 0x0594 },
- { "CP_AGC_CNTL ", 0x0590 },
- { "CP_BURST_GAIN ", 0x058c },
- { "CP_DEBUG_FORCE ", 0x05b8 },
- { "CP_HUE_CNTL ", 0x0588 },
- { "CP_PLL_CNTL0 ", 0x0580 },
- { "CP_PLL_CNTL1 ", 0x0584 },
- { "CP_PLL_STATUS0 ", 0x0598 },
- { "CP_PLL_STATUS1 ", 0x059c },
- { "CP_PLL_STATUS2 ", 0x05a0 },
- { "CP_PLL_STATUS3 ", 0x05a4 },
- { "CP_PLL_STATUS4 ", 0x05a8 },
- { "CP_PLL_STATUS5 ", 0x05ac },
- { "CP_PLL_STATUS6 ", 0x05b0 },
- { "CP_PLL_STATUS7 ", 0x05b4 },
- { "CP_VERT_LOCKOUT ", 0x05bc },
- { "CRC_CNTL ", 0x02c0 },
- { "CRT_DTO_INCREMENTS ", 0x0394 },
- { "CRT_PLL_CNTL ", 0x00c4 },
- { "CRT_PLL_FINE_CNTL ", 0x00bc },
- { "DECODER_DEBUG_CNTL ", 0x05d4 },
- { "DELAY_ONE_MAP_A ", 0x0114 },
- { "DELAY_ONE_MAP_B ", 0x0118 },
- { "DELAY_ZERO_MAP_A ", 0x011c },
- { "DELAY_ZERO_MAP_B ", 0x0120 },
- { "DFCOUNT ", 0x00a4 },
- { "DFRESTART ", 0x00a8 },
- { "DHRESTART ", 0x00ac },
- { "DVRESTART ", 0x00b0 },
- { "DVS_PORT_CTRL ", 0x0610 },
- { "DVS_PORT_READBACK ", 0x0614 },
- { "FIFOA_CONFIG ", 0x0800 },
- { "FIFOB_CONFIG ", 0x0804 },
- { "FIFOC_CONFIG ", 0x0808 },
- { "FRAME_LOCK_CNTL ", 0x0100 },
- { "GAIN_LIMIT_SETTINGS ", 0x01e4 },
- { "GPIO_CNTL ", 0x0034 },
- { "GPIO_INOUT ", 0x0030 },
- { "HCOUNT ", 0x0090 },
- { "HDISP ", 0x0084 },
- { "HOST_RD_WT_CNTL ", 0x0188 },
- { "HOST_READ_DATA ", 0x0180 },
- { "HOST_WRITE_DATA ", 0x0184 },
- { "HSIZE ", 0x0088 },
- { "HSTART ", 0x008c },
- { "HS_DTOINC ", 0x0484 },
- { "HS_GENLOCKDELAY ", 0x0490 },
- { "HS_MINMAXWIDTH ", 0x048c },
- { "HS_PLINE ", 0x0480 },
- { "HS_PLLGAIN ", 0x0488 },
- { "HS_PLL_ERROR ", 0x04a0 },
- { "HS_PLL_FS_PATH ", 0x04a4 },
- { "HS_PULSE_WIDTH ", 0x049c },
- { "HS_WINDOW_LIMIT ", 0x0494 },
- { "HS_WINDOW_OC_SPEED ", 0x0498 },
- { "HTOTAL ", 0x0080 },
- { "HW_DEBUG ", 0x0010 },
- { "H_ACTIVE_WINDOW ", 0x05c0 },
- { "H_SCALER_CONTROL ", 0x0600 },
- { "H_VBI_WINDOW ", 0x05c8 },
- { "I2C_CNTL ", 0x0054 },
- { "I2C_CNTL_0 ", 0x0020 },
- { "I2C_CNTL_1 ", 0x0024 },
- { "I2C_DATA ", 0x0028 },
- { "I2S_RECEIVE_CNTL ", 0x081c },
- { "I2S_TRANSMIT_CNTL ", 0x0818 },
- { "IIS_TX_CNT_REG ", 0x0824 },
- { "INT_CNTL ", 0x002c },
- { "L54_DTO_INCREMENTS ", 0x00f8 },
- { "L54_PLL_CNTL ", 0x00f0 },
- { "L54_PLL_FINE_CNTL ", 0x00f4 },
- { "LINEAR_GAIN_SETTINGS ", 0x01e8 },
- { "LP_AGC_CLAMP_CNTL0 ", 0x0500 },
- { "LP_AGC_CLAMP_CNTL1 ", 0x0504 },
- { "LP_BLACK_LEVEL ", 0x051c },
- { "LP_BRIGHTNESS ", 0x0508 },
- { "LP_CONTRAST ", 0x050c },
- { "LP_SLICE_LEVEL ", 0x0520 },
- { "LP_SLICE_LIMIT ", 0x0510 },
- { "LP_SYNCTIP_LEVEL ", 0x0524 },
- { "LP_VERT_LOCKOUT ", 0x0528 },
- { "LP_WPA_CNTL0 ", 0x0514 },
- { "LP_WPA_CNTL1 ", 0x0518 },
- { "MASTER_CNTL ", 0x0040 },
- { "MODULATOR_CNTL1 ", 0x0200 },
- { "MODULATOR_CNTL2 ", 0x0204 },
- { "MV_LEVEL_CNTL1 ", 0x0210 },
- { "MV_LEVEL_CNTL2 ", 0x0214 },
- { "MV_MODE_CNTL ", 0x0208 },
- { "MV_STATUS ", 0x0330 },
- { "MV_STRIPE_CNTL ", 0x020c },
- { "NOISE_CNTL0 ", 0x0450 },
- { "PLL_CNTL0 ", 0x00c8 },
- { "PLL_CNTL1 ", 0x00fc },
- { "PLL_TEST_CNTL ", 0x00cc },
- { "PRE_DAC_MUX_CNTL ", 0x0240 },
- { "RGB_CNTL ", 0x0048 },
- { "RIPINTF_PORT_CNTL ", 0x003c },
- { "SCALER_IN_WINDOW ", 0x0618 },
- { "SCALER_OUT_WINDOW ", 0x061c },
- { "SG_BLACK_GATE ", 0x04c0 },
- { "SG_SYNCTIP_GATE ", 0x04c4 },
- { "SG_UVGATE_GATE ", 0x04c8 },
- { "SINGLE_STEP_DATA ", 0x05d8 },
- { "SPDIF_AC3_PREAMBLE ", 0x0814 },
- { "SPDIF_CHANNEL_STAT ", 0x0810 },
- { "SPDIF_PORT_CNTL ", 0x080c },
- { "SPDIF_TX_CNT_REG ", 0x0820 },
- { "STANDARD_SELECT ", 0x0408 },
- { "SW_SCRATCH ", 0x0014 },
- { "SYNC_CNTL ", 0x0050 },
- { "SYNC_LOCK_CNTL ", 0x0104 },
- { "SYNC_SIZE ", 0x00b4 },
- { "THERMO2BIN_STATUS ", 0x040c },
- { "TIMING_CNTL ", 0x01c4 },
- { "TVO_DATA_DELAY_A ", 0x0140 },
- { "TVO_DATA_DELAY_B ", 0x0144 },
- { "TVO_SYNC_PAT_ACCUM ", 0x0108 },
- { "TVO_SYNC_PAT_EXPECT ", 0x0110 },
- { "TVO_SYNC_THRESHOLD ", 0x010c },
- { "TV_DAC_CNTL ", 0x0280 },
- { "TV_DTO_INCREMENTS ", 0x0390 },
- { "TV_PLL_CNTL ", 0x00c0 },
- { "TV_PLL_FINE_CNTL ", 0x00b8 },
- { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 },
- { "UPSAMP_COEFF0_0 ", 0x0340 },
- { "UPSAMP_COEFF0_1 ", 0x0344 },
- { "UPSAMP_COEFF0_2 ", 0x0348 },
- { "UPSAMP_COEFF1_0 ", 0x034c },
- { "UPSAMP_COEFF1_1 ", 0x0350 },
- { "UPSAMP_COEFF1_2 ", 0x0354 },
- { "UPSAMP_COEFF2_0 ", 0x0358 },
- { "UPSAMP_COEFF2_1 ", 0x035c },
- { "UPSAMP_COEFF2_2 ", 0x0360 },
- { "UPSAMP_COEFF3_0 ", 0x0364 },
- { "UPSAMP_COEFF3_1 ", 0x0368 },
- { "UPSAMP_COEFF3_2 ", 0x036c },
- { "UPSAMP_COEFF4_0 ", 0x0370 },
- { "UPSAMP_COEFF4_1 ", 0x0374 },
- { "UPSAMP_COEFF4_2 ", 0x0378 },
- { "UV_ADR ", 0x0300 },
- { "VBI_20BIT_CNTL ", 0x02d0 },
- { "VBI_CC_CNTL ", 0x02c8 },
- { "VBI_CONTROL ", 0x05d0 },
- { "VBI_DTO_CNTL ", 0x02d4 },
- { "VBI_EDS_CNTL ", 0x02cc },
- { "VBI_LEVEL_CNTL ", 0x02d8 },
- { "VBI_SCALER_CONTROL ", 0x060c },
- { "VCOUNT ", 0x009c },
- { "VDISP ", 0x0098 },
- { "VFTOTAL ", 0x00a0 },
- { "VIDEO_PORT_SIG ", 0x02c4 },
- { "VIN_PLL_CNTL ", 0x00d4 },
- { "VIN_PLL_FINE_CNTL ", 0x00d8 },
- { "VIP_COMMAND_STATUS ", 0x0008 },
- { "VIP_REVISION_ID ", 0x000c },
- { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 },
- { "VIP_VENDOR_DEVICE_ID ", 0x0000 },
- { "VSCALER_CNTL1 ", 0x01c0 },
- { "VSCALER_CNTL2 ", 0x01c8 },
- { "VSYNC_DIFF_CNTL ", 0x03a0 },
- { "VSYNC_DIFF_LIMITS ", 0x03a4 },
- { "VSYNC_DIFF_RD_DATA ", 0x03a8 },
- { "VS_BLANKING_CNTL ", 0x0544 },
- { "VS_COUNTER_CNTL ", 0x054c },
- { "VS_DETECTOR_CNTL ", 0x0540 },
- { "VS_FIELD_ID_CNTL ", 0x0548 },
- { "VS_FRAME_TOTAL ", 0x0550 },
- { "VS_LINE_COUNT ", 0x0554 },
- { "VTOTAL ", 0x0094 },
- { "V_ACTIVE_WINDOW ", 0x05c4 },
- { "V_DEINTERLACE_CONTROL ", 0x0608 },
- { "V_SCALER_CONTROL ", 0x0604 },
- { "V_VBI_WINDOW ", 0x05cc },
- { "Y_FALL_CNTL ", 0x01cc },
- { "Y_RISE_CNTL ", 0x01d0 },
- { "Y_SAW_TOOTH_CNTL ", 0x01d4 },
- {NULL, 0}
- };
-
- for(i=0; rt_reg_list[i].name!=NULL;i++){
- RT_regr(rt_reg_list[i].addr, &data);
- xf86DrvMsg(t->VIP->scrnIndex, X_INFO,
- "register (0x%04lx) %s is equal to 0x%08x\n",
- rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data);
- }
-
-}
-
-void ResetTheatreRegsForNoTVout(TheatrePtr t)
-{
- RT_regw(VIP_CLKOUT_CNTL, 0x0);
- RT_regw(VIP_HCOUNT, 0x0);
- RT_regw(VIP_VCOUNT, 0x0);
- RT_regw(VIP_DFCOUNT, 0x0);
- #if 0
- RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
- RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
- #endif
- RT_regw(VIP_FRAME_LOCK_CNTL, 0x0);
-}
-
-
-void ResetTheatreRegsForTVout(TheatrePtr t)
-{
-/* RT_regw(VIP_HW_DEBUG, 0x200); */
-/* RT_regw(VIP_INT_CNTL, 0x0);
- RT_regw(VIP_GPIO_INOUT, 0x10090000);
- RT_regw(VIP_GPIO_INOUT, 0x340b0000); */
-/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */
- RT_regw(VIP_CLKOUT_CNTL, 0x29);
-#if 1
- RT_regw(VIP_HCOUNT, 0x1d1);
- RT_regw(VIP_VCOUNT, 0x1e3);
-#else
- RT_regw(VIP_HCOUNT, 0x322);
- RT_regw(VIP_VCOUNT, 0x151);
-#endif
- RT_regw(VIP_DFCOUNT, 0x01);
-/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */
- RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
- RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
-/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */
- RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f);
-/* RT_regw(VIP_ADC_CNTL, 0x02a420a8);
- RT_regw(VIP_COMB_CNTL_0, 0x0d438083);
- RT_regw(VIP_COMB_CNTL_2, 0x06080102);
- RT_regw(VIP_HS_MINMAXWIDTH, 0x462f);
- ...
- */
-/*
- RT_regw(VIP_HS_PULSE_WIDTH, 0x359);
- RT_regw(VIP_HS_PLL_ERROR, 0xab6);
- RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8);
- RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005);
- */
-}
-
diff --git a/src/theatre200.h b/src/theatre200.h
deleted file mode 100644
index 815bd91..0000000
--- a/src/theatre200.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*************************************************************************************
- * Copyright (C) 2005 Bogdan D. bogdand at users.sourceforge.net
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of this
- * software and associated documentation files (the "Software"), to deal in the Software
- * without restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all copies or
- * substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
- * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
- * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of the author shall not be used in advertising or
- * otherwise to promote the sale, use or other dealings in this Software without prior written
- * authorization from the author.
- *
- * $Log$
- * Revision 1.5 2005/12/08 17:54:40 kem
- * Allow hard-coded paths to be configurable.
- *
- * Revision 1.4 2005/11/07 19:28:40 bogdand
- * Replaced the variadic macros(gcc) by macros according to C99 standard
- *
- * Revision 1.3 2005/08/28 18:00:23 bogdand
- * Modified the licens type from GPL to a X/MIT one
- *
- * Revision 1.2 2005/07/01 22:43:11 daniels
- * Change all misc.h and os.h references to <X11/foo.h>.
- *
- *
- ************************************************************************************/
-
-#ifndef __THEATRE200_H__
-#define __THEATRE200_H__
-
-#include "theatre.h"
-
-#ifdef MICROC_DIR
-#define DEFAULT_MICROC_PATH MICROC_DIR"/rt2_pmem.bin"
-#else
-#define DEFAULT_MICROC_PATH "/usr/X11R6/lib/modules/multimedia/rt2_pmem.bin"
-#endif
-#define DEFAULT_MICROC_TYPE "BINARY"
-
-/* #define ENABLE_DEBUG 1 */
-
-#ifdef ENABLE_DEBUG
-#define ERROR_0(str) xf86DrvMsg(screen, X_ERROR, str)
-#define DEBUG_0(str) xf86DrvMsg(screen, X_INFO, str)
-#define ERROR(str,param1) xf86DrvMsg(screen, X_ERROR, str, param1)
-#define DEBUG(str,param1) xf86DrvMsg(screen, X_INFO, str, param1)
-#define ERROR_2(str,param1,param2) xf86DrvMsg(screen, X_ERROR, str, param1, param2)
-#define DEBUG_2(str,param1,param2) xf86DrvMsg(screen, X_INFO, str, param1, param2)
-#define ERROR_3(str,param1,param2,param3) xf86DrvMsg(screen, X_ERROR, str, param1, param2, param3)
-#define DEBUG_3(str,param1,param2,param3) xf86DrvMsg(screen, X_INFO, str, param1, param2, param3)
-#else
-#define ERROR_0(str) (void)screen
-#define DEBUG_0(str) (void)screen
-#define ERROR(str,param1) (void)screen
-#define DEBUG(str,param1) (void)screen
-#define ERROR_2(str,param1,param2) (void)screen
-#define DEBUG_2(str,param1,param2) (void)screen
-#define ERROR_3(str,param1,param2,param3) (void)screen
-#define DEBUG_3(str,param1,param2,param3) (void)screen
-#endif
-
-
-#define DSP_OK 0x21
-#define DSP_INVALID_PARAMETER 0x22
-#define DSP_MISSING_PARAMETER 0x23
-#define DSP_UNKNOWN_COMMAND 0x24
-#define DSP_UNSUCCESS 0x25
-#define DSP_BUSY 0x26
-#define DSP_RESET_REQUIRED 0x27
-#define DSP_UNKNOWN_RESULT 0x28
-#define DSP_CRC_ERROR 0x29
-#define DSP_AUDIO_GAIN_ADJ_FAIL 0x2a
-#define DSP_AUDIO_GAIN_CHK_ERROR 0x2b
-#define DSP_WARNING 0x2c
-#define DSP_POWERDOWN_MODE 0x2d
-
-#define RT200_NTSC_M 0x01
-#define RT200_NTSC_433 0x03
-#define RT200_NTSC_J 0x04
-#define RT200_PAL_B 0x05
-#define RT200_PAL_D 0x06
-#define RT200_PAL_G 0x07
-#define RT200_PAL_H 0x08
-#define RT200_PAL_I 0x09
-#define RT200_PAL_N 0x0a
-#define RT200_PAL_Ncomb 0x0b
-#define RT200_PAL_M 0x0c
-#define RT200_PAL_60 0x0d
-#define RT200_SECAM 0x0e
-#define RT200_SECAM_B 0x0f
-#define RT200_SECAM_D 0x10
-#define RT200_SECAM_G 0x11
-#define RT200_SECAM_H 0x12
-#define RT200_SECAM_K 0x13
-#define RT200_SECAM_K1 0x14
-#define RT200_SECAM_L 0x15
-#define RT200_SECAM_L1 0x16
-#define RT200_480i 0x17
-#define RT200_480p 0x18
-#define RT200_576i 0x19
-#define RT200_720p 0x1a
-#define RT200_1080i 0x1b
-
-struct rt200_microc_head
-{
- unsigned int device_id;
- unsigned int vendor_id;
- unsigned int revision_id;
- unsigned int num_seg;
-};
-
-struct rt200_microc_seg
-{
- unsigned int num_bytes;
- unsigned int download_dst;
- unsigned int crc_val;
-
- unsigned char* data;
- struct rt200_microc_seg* next;
-};
-
-
-struct rt200_microc_data
-{
- struct rt200_microc_head microc_head;
- struct rt200_microc_seg* microc_seg_list;
-};
-
-#endif
diff --git a/src/theatre200_module.c b/src/theatre200_module.c
deleted file mode 100644
index 7e7d357..0000000
--- a/src/theatre200_module.c
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "xf86Module.h"
-
-static MODULESETUPPROTO(theatre200Setup);
-
-
-static XF86ModuleVersionInfo theatre200VersRec =
-{
- "theatre200",
- MODULEVENDORSTRING,
- MODINFOSTRING1,
- MODINFOSTRING2,
- XORG_VERSION_CURRENT,
- 1, 0, 0,
- ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */
- ABI_VIDEODRV_VERSION,
- MOD_CLASS_NONE,
- {0,0,0,0}
-};
-
-_X_EXPORT XF86ModuleData theatre200ModuleData = {
- &theatre200VersRec,
- theatre200Setup,
- NULL
-};
-
-static pointer
-theatre200Setup(pointer module, pointer opts, int *errmaj, int *errmin) {
- return (pointer)1;
-}
diff --git a/src/theatre_detect.c b/src/theatre_detect.c
deleted file mode 100644
index 8770911..0000000
--- a/src/theatre_detect.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*************************************************************************************
- *
- * Copyright (C) 2005 Bogdan D. bogdand at users.sourceforge.net
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of this
- * software and associated documentation files (the "Software"), to deal in the Software
- * without restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all copies or
- * substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
- * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
- * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of the author shall not be used in advertising or
- * otherwise to promote the sale, use or other dealings in this Software without prior written
- * authorization from the author.
- *
- * $Log$
- * Revision 1.4 2005/08/28 18:00:23 bogdand
- * Modified the licens type from GPL to a X/MIT one
- *
- * Revision 1.3 2005/07/11 02:29:45 ajax
- * Prep for modular builds by adding guarded #include "config.h" everywhere.
- *
- * Revision 1.2 2005/07/01 22:43:11 daniels
- * Change all misc.h and os.h references to <X11/foo.h>.
- *
- *
- ************************************************************************************/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <string.h>
-#include "xf86.h"
-#include "generic_bus.h"
-#include "theatre.h"
-#include "theatre_reg.h"
-
-static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data);
-}
-
-/* Unused code - reference */
-#if 0
-static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data)
-{
- if(t->theatre_num<0)return FALSE;
- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data);
-}
-#define RT_regw(reg,data) theatre_write(t,(reg),(data))
-#endif
-
-#define RT_regr(reg,data) theatre_read(t,(reg),(data))
-#define VIP_TYPE "ATI VIP BUS"
-
-
-TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b)
-{
- TheatrePtr t;
- int i;
- CARD32 val;
- char s[20];
-
- b->ioctl(b,GB_IOCTL_GET_TYPE,20,s);
- if(strcmp(VIP_TYPE, s)){
- xf86DrvMsg(b->scrnIndex, X_ERROR, "DetectTheatre must be called with bus of type \"%s\", not \"%s\"\n",
- VIP_TYPE, s);
- return NULL;
- }
-
- t = xcalloc(1,sizeof(TheatreRec));
- t->VIP = b;
- t->theatre_num = -1;
- t->mode=MODE_UNINITIALIZED;
-
- b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val);
- for(i=0;i<4;i++)
- {
- if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val))
- {
- if(val)xf86DrvMsg(b->scrnIndex, X_INFO,
- "Device %d on VIP bus ids as 0x%08x\n", i,
- (unsigned)val);
- if(t->theatre_num>=0)continue; /* already found one instance */
- switch(val){
- case RT100_ATI_ID:
- t->theatre_num=i;
- t->theatre_id=RT100_ATI_ID;
- break;
- case RT200_ATI_ID:
- t->theatre_num=i;
- t->theatre_id=RT200_ATI_ID;
- break;
- }
- } else {
- xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i);
- }
- }
- if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO,
- "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n",
- t->theatre_num, (unsigned)t->theatre_id);
-
- if(t->theatre_num < 0)
- {
- xfree(t);
- return NULL;
- }
-
- RT_regr(VIP_VIP_REVISION_ID, &val);
- xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n",
- (unsigned)val);
-
-#if 0
-DumpRageTheatreRegsByName(t);
-#endif
-
- return t;
-}
-
diff --git a/src/theatre_detect.h b/src/theatre_detect.h
deleted file mode 100644
index 5fed160..0000000
--- a/src/theatre_detect.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*************************************************************************************
- * Copyright (C) 2005 Bogdan D. bogdand at users.sourceforge.net
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of this
- * software and associated documentation files (the "Software"), to deal in the Software
- * without restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all copies or
- * substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
- * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
- * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Except as contained in this notice, the name of the author shall not be used in advertising or
- * otherwise to promote the sale, use or other dealings in this Software without prior written
- * authorization from the author.
- *
- * $Log$
- * Revision 1.3 2005/08/28 18:00:23 bogdand
- * Modified the licens type from GPL to a X/MIT one
- *
- * Revision 1.2 2005/07/01 22:43:11 daniels
- * Change all misc.h and os.h references to <X11/foo.h>.
- *
- *
- ************************************************************************************/
-
-#ifndef __THEATRE_DETECT_H__
-#define __THEATRE_DETECT_H__
-
-/*
- * Created by Bogdan D. bogdand at users.sourceforge.net
- */
-
-
-TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b);
-
-
-#define xf86_DetectTheatre ((TheatrePtr (*)(GENERIC_BUS_Ptr))LoaderSymbol("DetectTheatre"))
-
-#endif
diff --git a/src/theatre_detect_module.c b/src/theatre_detect_module.c
deleted file mode 100644
index 1546ce2..0000000
--- a/src/theatre_detect_module.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Created by Bogdan D. bogdand at users.sourceforge.net
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "xf86Module.h"
-
-static MODULESETUPPROTO(theatre_detectSetup);
-
-
-static XF86ModuleVersionInfo theatre_detectVersRec =
-{
- "theatre_detect",
- MODULEVENDORSTRING,
- MODINFOSTRING1,
- MODINFOSTRING2,
- XORG_VERSION_CURRENT,
- 1, 0, 0,
- ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */
- ABI_VIDEODRV_VERSION,
- MOD_CLASS_NONE,
- {0,0,0,0}
-};
-
-_X_EXPORT XF86ModuleData theatre_detectModuleData = {
- &theatre_detectVersRec,
- theatre_detectSetup,
- NULL
-};
-
-static pointer
-theatre_detectSetup(pointer module, pointer opts, int *errmaj, int *errmin) {
- return (pointer)1;
-}
diff --git a/src/theatre_module.c b/src/theatre_module.c
deleted file mode 100644
index 608b356..0000000
--- a/src/theatre_module.c
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "xf86Module.h"
-
-static MODULESETUPPROTO(theatreSetup);
-
-
-static XF86ModuleVersionInfo theatreVersRec =
-{
- "theatre",
- MODULEVENDORSTRING,
- MODINFOSTRING1,
- MODINFOSTRING2,
- XORG_VERSION_CURRENT,
- 1, 0, 0,
- ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */
- ABI_VIDEODRV_VERSION,
- MOD_CLASS_NONE,
- {0,0,0,0}
-};
-
-_X_EXPORT XF86ModuleData theatreModuleData = {
- &theatreVersRec,
- theatreSetup,
- NULL
-};
-
-static pointer
-theatreSetup(pointer module, pointer opts, int *errmaj, int *errmin) {
- return (pointer)1;
-}
diff --git a/src/theatre_reg.h b/src/theatre_reg.h
deleted file mode 100644
index c681001..0000000
--- a/src/theatre_reg.h
+++ /dev/null
@@ -1,876 +0,0 @@
-#ifndef __THEATRE_REGS_H__
-#define __THEATRE_REGS_H__
-
-
-#define VIPH_CH0_DATA 0x0c00
-#define VIPH_CH1_DATA 0x0c04
-#define VIPH_CH2_DATA 0x0c08
-#define VIPH_CH3_DATA 0x0c0c
-#define VIPH_CH0_ADDR 0x0c10
-#define VIPH_CH1_ADDR 0x0c14
-#define VIPH_CH2_ADDR 0x0c18
-#define VIPH_CH3_ADDR 0x0c1c
-#define VIPH_CH0_SBCNT 0x0c20
-#define VIPH_CH1_SBCNT 0x0c24
-#define VIPH_CH2_SBCNT 0x0c28
-#define VIPH_CH3_SBCNT 0x0c2c
-#define VIPH_CH0_ABCNT 0x0c30
-#define VIPH_CH1_ABCNT 0x0c34
-#define VIPH_CH2_ABCNT 0x0c38
-#define VIPH_CH3_ABCNT 0x0c3c
-#define VIPH_CONTROL 0x0c40
-#define VIPH_DV_LAT 0x0c44
-#define VIPH_BM_CHUNK 0x0c48
-#define VIPH_DV_INT 0x0c4c
-#define VIPH_TIMEOUT_STAT 0x0c50
-
-#define VIPH_REG_DATA 0x0084
-#define VIPH_REG_ADDR 0x0080
-
-/* Address Space Rage Theatre Registers (VIP Access) */
-#define VIP_VIP_VENDOR_DEVICE_ID 0x0000
-#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004
-#define VIP_VIP_COMMAND_STATUS 0x0008
-#define VIP_VIP_REVISION_ID 0x000c
-#define VIP_HW_DEBUG 0x0010
-#define VIP_SW_SCRATCH 0x0014
-#define VIP_I2C_CNTL_0 0x0020
-#define VIP_I2C_CNTL_1 0x0024
-#define VIP_I2C_DATA 0x0028
-#define VIP_INT_CNTL 0x002c
-/* RT200 */
-#define VIP_INT_CNTL__FB_INT0 0x02000000
-#define VIP_INT_CNTL__FB_INT0_CLR 0x02000000
-#define VIP_GPIO_INOUT 0x0030
-#define VIP_GPIO_CNTL 0x0034
-#define VIP_CLKOUT_GPIO_CNTL 0x0038
-#define VIP_RIPINTF_PORT_CNTL 0x003c
-
-/* RT200 */
-#define VIP_GPIO_INOUT 0x0030
-#define VIP_GPIO_CNTL 0x0034
-#define VIP_HOSTINTF_PORT_CNTL 0x003c
-#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SN 0x00000008
-#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SP 0x00000080
-#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SR 0x00000100
-#define VIP_HOSTINTF_PORT_CNTL__SUB_SYS_ID_EN 0x00010000
-#define VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE 0x00300000
-#define VIP_HOSTINTF_PORT_CNTL__FIFOA_ENDIAN_SWAP 0x00c00000
-#define VIP_HOSTINTF_PORT_CNTL__FIFOB_ENDIAN_SWAP 0x03000000
-#define VIP_HOSTINTF_PORT_CNTL__FIFOC_ENDIAN_SWAP 0x0c000000
-#define VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP 0x30000000
-#define VIP_HOSTINTF_PORT_CNTL__FIFOE_ENDIAN_SWAP 0xc0000000
-
-/* RT200 */
-#define VIP_DSP_PLL_CNTL 0x0bc
-
-/* RT200 */
-#define VIP_TC_SOURCE 0x300
-#define VIP_TC_DESTINATION 0x304
-#define VIP_TC_COMMAND 0x308
-
-/* RT200 */
-#define VIP_TC_STATUS 0x030c
-#define VIP_TC_STATUS__TC_CHAN_BUSY 0x00007fff
-#define VIP_TC_STATUS__TC_WRITE_PENDING 0x00008000
-#define VIP_TC_STATUS__TC_FIFO_4_EMPTY 0x00040000
-#define VIP_TC_STATUS__TC_FIFO_6_EMPTY 0x00080000
-#define VIP_TC_STATUS__TC_FIFO_8_EMPTY 0x00100000
-#define VIP_TC_STATUS__TC_FIFO_10_EMPTY 0x00200000
-#define VIP_TC_STATUS__TC_FIFO_4_FULL 0x04000000
-#define VIP_TC_STATUS__TC_FIFO_6_FULL 0x08080000
-#define VIP_TC_STATUS__TC_FIFO_8_FULL 0x10080000
-#define VIP_TC_STATUS__TC_FIFO_10_FULL 0x20080000
-#define VIP_TC_STATUS__DSP_ILLEGAL_OP 0x80080000
-
-/* RT200 */
-#define VIP_TC_DOWNLOAD 0x0310
-#define VIP_TC_DOWNLOAD__TC_DONE_MASK 0x00003fff
-#define VIP_TC_DOWNLOAD__TC_RESET_MODE 0x00060000
-
-/* RT200 */
-#define VIP_FB_INT 0x0314
-#define VIP_FB_INT__INT_7 0x00000080
-#define VIP_FB_SCRATCH0 0x0318
-#define VIP_FB_SCRATCH1 0x031c
-
-#define VIP_ADC_CNTL 0x0400
-#define VIP_ADC_DEBUG 0x0404
-#define VIP_STANDARD_SELECT 0x0408
-#define VIP_THERMO2BIN_STATUS 0x040c
-#define VIP_COMB_CNTL0 0x0440
-#define VIP_COMB_CNTL1 0x0444
-#define VIP_COMB_CNTL2 0x0448
-#define VIP_COMB_LINE_LENGTH 0x044c
-#define VIP_NOISE_CNTL0 0x0450
-#define VIP_HS_PLINE 0x0480
-#define VIP_HS_DTOINC 0x0484
-#define VIP_HS_PLLGAIN 0x0488
-#define VIP_HS_MINMAXWIDTH 0x048c
-#define VIP_HS_GENLOCKDELAY 0x0490
-#define VIP_HS_WINDOW_LIMIT 0x0494
-#define VIP_HS_WINDOW_OC_SPEED 0x0498
-#define VIP_HS_PULSE_WIDTH 0x049c
-#define VIP_HS_PLL_ERROR 0x04a0
-#define VIP_HS_PLL_FS_PATH 0x04a4
-#define VIP_SG_BLACK_GATE 0x04c0
-#define VIP_SG_SYNCTIP_GATE 0x04c4
-#define VIP_SG_UVGATE_GATE 0x04c8
-#define VIP_LP_AGC_CLAMP_CNTL0 0x0500
-#define VIP_LP_AGC_CLAMP_CNTL1 0x0504
-#define VIP_LP_BRIGHTNESS 0x0508
-#define VIP_LP_CONTRAST 0x050c
-#define VIP_LP_SLICE_LIMIT 0x0510
-#define VIP_LP_WPA_CNTL0 0x0514
-#define VIP_LP_WPA_CNTL1 0x0518
-#define VIP_LP_BLACK_LEVEL 0x051c
-#define VIP_LP_SLICE_LEVEL 0x0520
-#define VIP_LP_SYNCTIP_LEVEL 0x0524
-#define VIP_LP_VERT_LOCKOUT 0x0528
-#define VIP_VS_DETECTOR_CNTL 0x0540
-#define VIP_VS_BLANKING_CNTL 0x0544
-#define VIP_VS_FIELD_ID_CNTL 0x0548
-#define VIP_VS_COUNTER_CNTL 0x054c
-#define VIP_VS_FRAME_TOTAL 0x0550
-#define VIP_VS_LINE_COUNT 0x0554
-#define VIP_CP_PLL_CNTL0 0x0580
-#define VIP_CP_PLL_CNTL1 0x0584
-#define VIP_CP_HUE_CNTL 0x0588
-#define VIP_CP_BURST_GAIN 0x058c
-#define VIP_CP_AGC_CNTL 0x0590
-#define VIP_CP_ACTIVE_GAIN 0x0594
-#define VIP_CP_PLL_STATUS0 0x0598
-#define VIP_CP_PLL_STATUS1 0x059c
-#define VIP_CP_PLL_STATUS2 0x05a0
-#define VIP_CP_PLL_STATUS3 0x05a4
-#define VIP_CP_PLL_STATUS4 0x05a8
-#define VIP_CP_PLL_STATUS5 0x05ac
-#define VIP_CP_PLL_STATUS6 0x05b0
-#define VIP_CP_PLL_STATUS7 0x05b4
-#define VIP_CP_DEBUG_FORCE 0x05b8
-#define VIP_CP_VERT_LOCKOUT 0x05bc
-#define VIP_H_ACTIVE_WINDOW 0x05c0
-#define VIP_V_ACTIVE_WINDOW 0x05c4
-#define VIP_H_VBI_WINDOW 0x05c8
-#define VIP_V_VBI_WINDOW 0x05cc
-#define VIP_VBI_CONTROL 0x05d0
-#define VIP_DECODER_DEBUG_CNTL 0x05d4
-#define VIP_SINGLE_STEP_DATA 0x05d8
-#define VIP_MASTER_CNTL 0x0040
-#define VIP_RGB_CNTL 0x0048
-#define VIP_CLKOUT_CNTL 0x004c
-#define VIP_SYNC_CNTL 0x0050
-#define VIP_I2C_CNTL 0x0054
-#define VIP_HTOTAL 0x0080
-#define VIP_HDISP 0x0084
-#define VIP_HSIZE 0x0088
-#define VIP_HSTART 0x008c
-#define VIP_HCOUNT 0x0090
-#define VIP_VTOTAL 0x0094
-#define VIP_VDISP 0x0098
-#define VIP_VCOUNT 0x009c
-#define VIP_VFTOTAL 0x00a0
-#define VIP_DFCOUNT 0x00a4
-#define VIP_DFRESTART 0x00a8
-#define VIP_DHRESTART 0x00ac
-#define VIP_DVRESTART 0x00b0
-#define VIP_SYNC_SIZE 0x00b4
-#define VIP_TV_PLL_FINE_CNTL 0x00b8
-#define VIP_CRT_PLL_FINE_CNTL 0x00bc
-#define VIP_TV_PLL_CNTL 0x00c0
-#define VIP_CRT_PLL_CNTL 0x00c4
-#define VIP_PLL_CNTL0 0x00c8
-#define VIP_PLL_TEST_CNTL 0x00cc
-#define VIP_CLOCK_SEL_CNTL 0x00d0
-#define VIP_VIN_PLL_CNTL 0x00d4
-#define VIP_VIN_PLL_FINE_CNTL 0x00d8
-#define VIP_AUD_PLL_CNTL 0x00e0
-#define VIP_AUD_PLL_FINE_CNTL 0x00e4
-#define VIP_AUD_CLK_DIVIDERS 0x00e8
-#define VIP_AUD_DTO_INCREMENTS 0x00ec
-#define VIP_L54_PLL_CNTL 0x00f0
-#define VIP_L54_PLL_FINE_CNTL 0x00f4
-#define VIP_L54_DTO_INCREMENTS 0x00f8
-#define VIP_PLL_CNTL1 0x00fc
-#define VIP_FRAME_LOCK_CNTL 0x0100
-#define VIP_SYNC_LOCK_CNTL 0x0104
-#define VIP_TVO_SYNC_PAT_ACCUM 0x0108
-#define VIP_TVO_SYNC_THRESHOLD 0x010c
-#define VIP_TVO_SYNC_PAT_EXPECT 0x0110
-#define VIP_DELAY_ONE_MAP_A 0x0114
-#define VIP_DELAY_ONE_MAP_B 0x0118
-#define VIP_DELAY_ZERO_MAP_A 0x011c
-#define VIP_DELAY_ZERO_MAP_B 0x0120
-#define VIP_TVO_DATA_DELAY_A 0x0140
-#define VIP_TVO_DATA_DELAY_B 0x0144
-#define VIP_HOST_READ_DATA 0x0180
-#define VIP_HOST_WRITE_DATA 0x0184
-#define VIP_HOST_RD_WT_CNTL 0x0188
-#define VIP_VSCALER_CNTL1 0x01c0
-#define VIP_TIMING_CNTL 0x01c4
-#define VIP_VSCALER_CNTL2 0x01c8
-#define VIP_Y_FALL_CNTL 0x01cc
-#define VIP_Y_RISE_CNTL 0x01d0
-#define VIP_Y_SAW_TOOTH_CNTL 0x01d4
-#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0
-#define VIP_GAIN_LIMIT_SETTINGS 0x01e4
-#define VIP_LINEAR_GAIN_SETTINGS 0x01e8
-#define VIP_MODULATOR_CNTL1 0x0200
-#define VIP_MODULATOR_CNTL2 0x0204
-#define VIP_MV_MODE_CNTL 0x0208
-#define VIP_MV_STRIPE_CNTL 0x020c
-#define VIP_MV_LEVEL_CNTL1 0x0210
-#define VIP_MV_LEVEL_CNTL2 0x0214
-#define VIP_PRE_DAC_MUX_CNTL 0x0240
-#define VIP_TV_DAC_CNTL 0x0280
-#define VIP_CRC_CNTL 0x02c0
-#define VIP_VIDEO_PORT_SIG 0x02c4
-#define VIP_VBI_CC_CNTL 0x02c8
-#define VIP_VBI_EDS_CNTL 0x02cc
-#define VIP_VBI_20BIT_CNTL 0x02d0
-#define VIP_VBI_DTO_CNTL 0x02d4
-#define VIP_VBI_LEVEL_CNTL 0x02d8
-#define VIP_UV_ADR 0x0300
-#define VIP_MV_STATUS 0x0330
-#define VIP_UPSAMP_COEFF0_0 0x0340
-#define VIP_UPSAMP_COEFF0_1 0x0344
-#define VIP_UPSAMP_COEFF0_2 0x0348
-#define VIP_UPSAMP_COEFF1_0 0x034c
-#define VIP_UPSAMP_COEFF1_1 0x0350
-#define VIP_UPSAMP_COEFF1_2 0x0354
-#define VIP_UPSAMP_COEFF2_0 0x0358
-#define VIP_UPSAMP_COEFF2_1 0x035c
-#define VIP_UPSAMP_COEFF2_2 0x0360
-#define VIP_UPSAMP_COEFF3_0 0x0364
-#define VIP_UPSAMP_COEFF3_1 0x0368
-#define VIP_UPSAMP_COEFF3_2 0x036c
-#define VIP_UPSAMP_COEFF4_0 0x0370
-#define VIP_UPSAMP_COEFF4_1 0x0374
-#define VIP_UPSAMP_COEFF4_2 0x0378
-#define VIP_TV_DTO_INCREMENTS 0x0390
-#define VIP_CRT_DTO_INCREMENTS 0x0394
-#define VIP_VSYNC_DIFF_CNTL 0x03a0
-#define VIP_VSYNC_DIFF_LIMITS 0x03a4
-#define VIP_VSYNC_DIFF_RD_DATA 0x03a8
-#define VIP_SCALER_IN_WINDOW 0x0618
-#define VIP_SCALER_OUT_WINDOW 0x061c
-#define VIP_H_SCALER_CONTROL 0x0600
-#define VIP_V_SCALER_CONTROL 0x0604
-#define VIP_V_DEINTERLACE_CONTROL 0x0608
-#define VIP_VBI_SCALER_CONTROL 0x060c
-#define VIP_DVS_PORT_CTRL 0x0610
-#define VIP_DVS_PORT_READBACK 0x0614
-#define VIP_FIFOA_CONFIG 0x0800
-#define VIP_FIFOB_CONFIG 0x0804
-#define VIP_FIFOC_CONFIG 0x0808
-#define VIP_SPDIF_PORT_CNTL 0x080c
-#define VIP_SPDIF_CHANNEL_STAT 0x0810
-#define VIP_SPDIF_AC3_PREAMBLE 0x0814
-#define VIP_I2S_TRANSMIT_CNTL 0x0818
-#define VIP_I2S_RECEIVE_CNTL 0x081c
-#define VIP_SPDIF_TX_CNT_REG 0x0820
-#define VIP_IIS_TX_CNT_REG 0x0824
-
-/* Status defines */
-#define VIP_BUSY 0
-#define VIP_IDLE 1
-#define VIP_RESET 2
-
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT 0x00000001
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK 0x00000001
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT 0x00000002
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK 0x00000002
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT 0x00000004
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK 0x00000004
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT 0x00000008
-#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK 0x00000008
-
-#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
-#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
-#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
-#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
-
-#define RT100_ATI_ID 0x4D541002
-#define RT200_ATI_ID 0x4d4a1002
-
-/* Register/Field values: */
-#define RT_COMP0 0x0
-#define RT_COMP1 0x1
-#define RT_COMP2 0x2
-#define RT_YF_COMP3 0x3
-#define RT_YR_COMP3 0x4
-#define RT_YCF_COMP4 0x5
-#define RT_YCR_COMP4 0x6
-
-/* Video standard defines */
-#define RT_NTSC 0x0
-#define RT_PAL 0x1
-#define RT_SECAM 0x2
-#define extNONE 0x0000
-#define extNTSC 0x0100
-#define extRsvd 0x0200
-#define extPAL 0x0300
-#define extPAL_M 0x0400
-#define extPAL_N 0x0500
-#define extSECAM 0x0600
-#define extPAL_NCOMB 0x0700
-#define extNTSC_J 0x0800
-#define extNTSC_443 0x0900
-#define extPAL_BGHI 0x0A00
-#define extPAL_60 0x0B00
- /* these are used in MSP3430 */
-#define extPAL_DK1 0x0C00
-#define extPAL_AUTO 0x0D00
- /* these are used in RT200. Some are defined above */
-#define extPAL_B 0x0E00
-#define extPAL_D 0x0F00
-#define extPAL_G 0x1000
-#define extPAL_H 0x1100
-#define extPAL_I 0x1200
-#define extSECAM_B 0x1300
-#define extSECAM_D 0x1400
-#define extSECAM_G 0x1500
-#define extSECAM_H 0x1600
-#define extSECAM_K 0x1700
-#define extSECAM_K1 0x1800
-#define extSECAM_L 0x1900
-#define extSECAM_L1 0x1A00
-
-#define RT_FREF_2700 6
-#define RT_FREF_2950 5
-
-#define RT_COMPOSITE 0x0
-#define RT_SVIDEO 0x1
-
-#define RT_NORM_SHARPNESS 0x03
-#define RT_HIGH_SHARPNESS 0x0F
-
-#define RT_HUE_PAL_DEF 0x00
-
-#define RT_DECINTERLACED 0x1
-#define RT_DECNONINTERLACED 0x0
-
-#define NTSC_LINES 525
-#define PAL_SECAM_LINES 625
-
-#define RT_ASYNC_ENABLE 0x0
-#define RT_ASYNC_DISABLE 0x1
-#define RT_ASYNC_RESET 0x1
-
-#define RT_VINRST_ACTIVE 0x0
-#define RT_VINRST_RESET 0x1
-#define RT_L54RST_RESET 0x1
-
-#define RT_REF_CLK 0x0
-#define RT_PLL_VIN_CLK 0x1
-
-#define RT_VIN_ASYNC_RST 0x20
-#define RT_DVS_ASYNC_RST 0x80
-
-#define RT_ADC_ENABLE 0x0
-#define RT_ADC_DISABLE 0x1
-
-#define RT_DVSDIR_IN 0x0
-#define RT_DVSDIR_OUT 0x1
-
-#define RT_DVSCLK_HIGH 0x0
-#define RT_DVSCLK_LOW 0x1
-
-#define RT_DVSCLK_SEL_8FS 0x0
-#define RT_DVSCLK_SEL_27MHZ 0x1
-
-#define RT_DVS_CONTSTREAM 0x1
-#define RT_DVS_NONCONTSTREAM 0x0
-
-#define RT_DVSDAT_HIGH 0x0
-#define RT_DVSDAT_LOW 0x1
-
-#define RT_ADC_CNTL_DEFAULT 0x03252338
-
-/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 /* was 0x09438090 */
-#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000
-
-#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090
-
-#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/
-#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090
-
-#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090
-
-#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090
-#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090
-/* End of filter settings. */
-
-/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081
-
-#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1
-
-#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091
-#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081
-
-#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1
-
-#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010
-#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1
-/* End of filter settings. */
-
-/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010
-#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF
-
-#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */
-#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102
-
-#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */
-#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102
-
-#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102
-#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102
-
-#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102
-#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102
-/* End of filter settings. */
-
-/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */
-#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A
-#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A
-
-#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B
-#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B
-
-#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A
-#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A
-
-#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391
-#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391
-
-#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389
-#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389
-/* End of filter settings. */
-
-/* LP_AGC_CLAMP_CNTL0 */
-#define RT_NTSCM_SYNCTIP_REF0 0x00000037
-#define RT_NTSCM_SYNCTIP_REF1 0x00000029
-#define RT_NTSCM_CLAMP_REF 0x0000003B
-#define RT_NTSCM_PEAKWHITE 0x000000FF
-#define RT_NTSCM_VBI_PEAKWHITE 0x000000D2 /* was 0xc2 - docs say d2 */
-
-#define RT_NTSCM_WPA_THRESHOLD 0x00000406
-#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3
-
-#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B
-
-#define RT_NTSCM_LP_LOCKOUT_START 0x00000206
-#define RT_NTSCM_LP_LOCKOUT_END 0x00000021
-#define RT_NTSCM_CH_DTO_INC 0x00400000
-#define RT_NTSCM_CH_PLL_SGAIN 0x00000001
-#define RT_NTSCM_CH_PLL_FGAIN 0x00000002
-
-#define RT_NTSCM_CR_BURST_GAIN 0x0000007A
-#define RT_NTSCM_CB_BURST_GAIN 0x000000AC
-
-#define RT_NTSCM_CH_HEIGHT 0x000000CD
-#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0
-#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002
-#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000
-#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A
-#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC
-
-#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207
-#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E
-
-#define RT_NTSCJ_SYNCTIP_REF0 0x00000004
-#define RT_NTSCJ_SYNCTIP_REF1 0x00000012
-#define RT_NTSCJ_CLAMP_REF 0x0000003B
-#define RT_NTSCJ_PEAKWHITE 0x000000CB
-#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2
-#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0
-#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4
-#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C
-#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206
-#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021
-
-#define RT_NTSCJ_CR_BURST_GAIN 0x00000071
-#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F
-#define RT_NTSCJ_CH_HEIGHT 0x000000CD
-#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0
-#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002
-#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000
-#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071
-#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F
-#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207
-#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E
-
-#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
-#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
-#define RT_PAL_CLAMP_REF 0x0000003B
-#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
-#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
-#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */
-
-#define RT_PAL_WPA_TRIGGER_LO 0x00000096
-#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2
-#define RT_PAL_LP_LOCKOUT_START 0x00000263
-#define RT_PAL_LP_LOCKOUT_END 0x0000002C
-
-#define RT_PAL_CH_DTO_INC 0x00400000
-#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */
-#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */
-#define RT_PAL_CR_BURST_GAIN 0x0000007A
-#define RT_PAL_CB_BURST_GAIN 0x000000AB
-#define RT_PAL_CH_HEIGHT 0x0000009C
-#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */
-#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */
-#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */
-#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */
-#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */
-#define RT_PAL_VERT_LOCKOUT_START 0x00000269
-#define RT_PAL_VERT_LOCKOUT_END 0x00000012
-
-#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */
-#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */
-#define RT_SECAM_CLAMP_REF 0x0000003B
-#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */
-#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */
-#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/
-
-#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */
-#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2
-#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */
-#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */
-
-#define RT_SECAM_CH_DTO_INC 0x003E7A28
-#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 - Volodya */
-#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */
-
-#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
-#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */
-#define RT_SECAM_CH_HEIGHT 0x00000066
-#define RT_SECAM_CH_KILL_LEVEL 0x00000060
-#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003
-#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000
-#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000
-
-#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */
-#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */
-#define RT_SECAM_VERT_LOCKOUT_START 0x00000269
-#define RT_SECAM_VERT_LOCKOUT_END 0x00000012
-
-#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/
-#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000a
-
-#define RT_NTSCM_FIELD_IDLOCATION 0x00000105
-#define RT_PAL_FIELD_IDLOCATION 0x00000137
-
-#define RT_NTSCM_H_ACTIVE_START 0x00000070
-#define RT_NTSCM_H_ACTIVE_END 0x00000363
-
-#define RT_PAL_H_ACTIVE_START 0x0000009A
-#define RT_PAL_H_ACTIVE_END 0x00000439
-
-#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1)
-#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1)
-
-#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */
-#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */
-
-/* VBI */
-#define RT_NTSCM_H_VBI_WIND_START 0x32 /* instead of 0x00000049 - V.D. */
-#define RT_NTSCM_H_VBI_WIND_END 0x367 /* instead of 0x00000366 - V.D. */
-
-#define RT_PAL_H_VBI_WIND_START 0x00000084
-#define RT_PAL_H_VBI_WIND_END 0x0000041F
-
-#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def
-#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def
-
-#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */
-#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */
-
-#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */
-#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */
-#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */
-
-#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA
-#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353
-
-#define RT_NTSCM_VSYNC_INT_HOLD 0x17
-#define RT_PALSEM_VSYNC_INT_HOLD 0x1C
-
-#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
-#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */
-
-#define RT_FIELD_FLIP_EN 0x4
-#define RT_V_FIELD_FLIP_INVERTED 0x2000
-
-#define RT_NTSCM_H_IN_START 0x70
-#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */
-#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */
-#define RT_NTSC_H_ACTIVE_SIZE 744
-#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */
-#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */
-#define RT_NTSCM_V_IN_START (0x23)
-#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */
-#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */
-#define RT_NTSCM_V_ACTIVE_SIZE 480
-#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */
-#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */
-
-#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D
-#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D
-#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F
-#define RT_PALM_WIN_CLOSE_LIMIT 0x4D
-#define RT_PALN_WIN_CLOSE_LIMIT 0x5F
-#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */
-
-#define RT_NTSCM_VS_FIELD_BLANK_START 0x206
-
-#define RT_NTSCM_HS_PLL_SGAIN 0x5
-#define RT_NTSCM_HS_PLL_FGAIN 0x7
-
-#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4
-#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0
-
-#define TV 0x1
-#define LINEIN 0x2
-#define MUTE 0x3
-
-#define DEC_COMPOSITE 0
-#define DEC_SVIDEO 1
-#define DEC_TUNER 2
-
-#define DEC_NTSC 0
-#define DEC_PAL 1
-#define DEC_SECAM 2
-#define DEC_NTSC_J 8
-
-#define DEC_SMOOTH 0
-#define DEC_SHARP 1
-
-/* RT Register Field Defaults: */
-#define fld_tmpReg1_def (CARD32) 0x00000000
-#define fld_tmpReg2_def (CARD32) 0x00000001
-#define fld_tmpReg3_def (CARD32) 0x00000002
-
-#define fld_LP_CONTRAST_def (CARD32) 0x0000006e
-#define fld_LP_BRIGHTNESS_def (CARD32) 0x00003ff0
-#define fld_CP_HUE_CNTL_def (CARD32) 0x00000000
-#define fld_LUMA_FILTER_def (CARD32) 0x00000001
-#define fld_H_SCALE_RATIO_def (CARD32) 0x00010000
-#define fld_H_SHARPNESS_def (CARD32) 0x00000000
-
-#define fld_V_SCALE_RATIO_def (CARD32) 0x00000800
-#define fld_V_DEINTERLACE_ON_def (CARD32) 0x00000001
-#define fld_V_BYPSS_def (CARD32) 0x00000000
-#define fld_V_DITHER_ON_def (CARD32) 0x00000001
-#define fld_EVENF_OFFSET_def (CARD32) 0x00000000
-#define fld_ODDF_OFFSET_def (CARD32) 0x00000000
-
-#define fld_INTERLACE_DETECTED_def (CARD32) 0x00000000
-
-#define fld_VS_LINE_COUNT_def (CARD32) 0x00000000
-#define fld_VS_DETECTED_LINES_def (CARD32) 0x00000000
-#define fld_VS_ITU656_VB_def (CARD32) 0x00000000
-
-#define fld_VBI_CC_DATA_def (CARD32) 0x00000000
-#define fld_VBI_CC_WT_def (CARD32) 0x00000000
-#define fld_VBI_CC_WT_ACK_def (CARD32) 0x00000000
-#define fld_VBI_CC_HOLD_def (CARD32) 0x00000000
-#define fld_VBI_DECODE_EN_def (CARD32) 0x00000000
-
-#define fld_VBI_CC_DTO_P_def (CARD32) 0x00001802
-#define fld_VBI_20BIT_DTO_P_def (CARD32) 0x0000155c
-
-#define fld_VBI_CC_LEVEL_def (CARD32) 0x0000003f
-#define fld_VBI_20BIT_LEVEL_def (CARD32) 0x00000059
-#define fld_VBI_CLK_RUNIN_GAIN_def (CARD32) 0x0000010f
-
-#define fld_H_VBI_WIND_START_def (CARD32) 0x00000041
-#define fld_H_VBI_WIND_END_def (CARD32) 0x00000366
-
-#define fld_V_VBI_WIND_START_def (CARD32) 0x0B /* instead of 0x0D - V.D. */
-#define fld_V_VBI_WIND_END_def (CARD32) 0x24
-
-#define fld_VBI_20BIT_DATA0_def (CARD32) 0x00000000
-#define fld_VBI_20BIT_DATA1_def (CARD32) 0x00000000
-#define fld_VBI_20BIT_WT_def (CARD32) 0x00000000
-#define fld_VBI_20BIT_WT_ACK_def (CARD32) 0x00000000
-#define fld_VBI_20BIT_HOLD_def (CARD32) 0x00000000
-
-#define fld_VBI_CAPTURE_ENABLE_def (CARD32) 0x00000000
-
-#define fld_VBI_EDS_DATA_def (CARD32) 0x00000000
-#define fld_VBI_EDS_WT_def (CARD32) 0x00000000
-#define fld_VBI_EDS_WT_ACK_def (CARD32) 0x00000000
-#define fld_VBI_EDS_HOLD_def (CARD32) 0x00000000
-
-#define fld_VBI_SCALING_RATIO_def (CARD32) 0x00010000
-#define fld_VBI_ALIGNER_ENABLE_def (CARD32) 0x00000000
-
-#define fld_H_ACTIVE_START_def (CARD32) 0x00000070
-#define fld_H_ACTIVE_END_def (CARD32) 0x000002f0
-
-#define fld_V_ACTIVE_START_def (CARD32) ((22-4)*2+1)
-#define fld_V_ACTIVE_END_def (CARD32) ((22+240-4)*2+2)
-
-#define fld_CH_HEIGHT_def (CARD32) 0x000000CD
-#define fld_CH_KILL_LEVEL_def (CARD32) 0x000000C0
-#define fld_CH_AGC_ERROR_LIM_def (CARD32) 0x00000002
-#define fld_CH_AGC_FILTER_EN_def (CARD32) 0x00000000
-#define fld_CH_AGC_LOOP_SPEED_def (CARD32) 0x00000000
-
-#define fld_HUE_ADJ_def (CARD32) 0x00000000
-
-#define fld_STANDARD_SEL_def (CARD32) 0x00000000
-#define fld_STANDARD_YC_def (CARD32) 0x00000000
-
-#define fld_ADC_PDWN_def (CARD32) 0x00000001
-#define fld_INPUT_SELECT_def (CARD32) 0x00000000
-
-#define fld_ADC_PREFLO_def (CARD32) 0x00000003
-#define fld_H_SYNC_PULSE_WIDTH_def (CARD32) 0x00000000
-#define fld_HS_GENLOCKED_def (CARD32) 0x00000000
-#define fld_HS_SYNC_IN_WIN_def (CARD32) 0x00000000
-
-#define fld_VIN_ASYNC_RST_def (CARD32) 0x00000001
-#define fld_DVS_ASYNC_RST_def (CARD32) 0x00000001
-
-/* Vendor IDs: */
-#define fld_VIP_VENDOR_ID_def (CARD32) 0x00001002
-#define fld_VIP_DEVICE_ID_def (CARD32) 0x00004d54
-#define fld_VIP_REVISION_ID_def (CARD32) 0x00000001
-
-/* AGC Delay Register */
-#define fld_BLACK_INT_START_def (CARD32) 0x00000031
-#define fld_BLACK_INT_LENGTH_def (CARD32) 0x0000000f
-
-#define fld_UV_INT_START_def (CARD32) 0x0000003b
-#define fld_U_INT_LENGTH_def (CARD32) 0x0000000f
-#define fld_V_INT_LENGTH_def (CARD32) 0x0000000f
-#define fld_CRDR_ACTIVE_GAIN_def (CARD32) 0x0000007a
-#define fld_CBDB_ACTIVE_GAIN_def (CARD32) 0x000000ac
-
-#define fld_DVS_DIRECTION_def (CARD32) 0x00000000
-#define fld_DVS_VBI_CARD8_SWAP_def (CARD32) 0x00000000
-#define fld_DVS_CLK_SELECT_def (CARD32) 0x00000000
-#define fld_CONTINUOUS_STREAM_def (CARD32) 0x00000000
-#define fld_DVSOUT_CLK_DRV_def (CARD32) 0x00000001
-#define fld_DVSOUT_DATA_DRV_def (CARD32) 0x00000001
-
-#define fld_COMB_CNTL0_def (CARD32) 0x09438090
-#define fld_COMB_CNTL1_def (CARD32) 0x00000010
-
-#define fld_COMB_CNTL2_def (CARD32) 0x16161010
-#define fld_COMB_LENGTH_def (CARD32) 0x0718038A
-
-#define fld_SYNCTIP_REF0_def (CARD32) 0x00000037
-#define fld_SYNCTIP_REF1_def (CARD32) 0x00000029
-#define fld_CLAMP_REF_def (CARD32) 0x0000003B
-#define fld_AGC_PEAKWHITE_def (CARD32) 0x000000FF
-#define fld_VBI_PEAKWHITE_def (CARD32) 0x000000D2
-
-#define fld_WPA_THRESHOLD_def (CARD32) 0x000003B0
-
-#define fld_WPA_TRIGGER_LO_def (CARD32) 0x000000B4
-#define fld_WPA_TRIGGER_HIGH_def (CARD32) 0x0000021C
-
-#define fld_LOCKOUT_START_def (CARD32) 0x00000206
-#define fld_LOCKOUT_END_def (CARD32) 0x00000021
-
-#define fld_CH_DTO_INC_def (CARD32) 0x00400000
-#define fld_PLL_SGAIN_def (CARD32) 0x00000001
-#define fld_PLL_FGAIN_def (CARD32) 0x00000002
-
-#define fld_CR_BURST_GAIN_def (CARD32) 0x0000007a
-#define fld_CB_BURST_GAIN_def (CARD32) 0x000000ac
-
-#define fld_VERT_LOCKOUT_START_def (CARD32) 0x00000207
-#define fld_VERT_LOCKOUT_END_def (CARD32) 0x0000000E
-
-#define fld_H_IN_WIND_START_def (CARD32) 0x00000070
-#define fld_V_IN_WIND_START_def (CARD32) 0x00000027
-
-#define fld_H_OUT_WIND_WIDTH_def (CARD32) 0x000002f4
-
-#define fld_V_OUT_WIND_WIDTH_def (CARD32) 0x000000f0
-
-#define fld_HS_LINE_TOTAL_def (CARD32) 0x0000038E
-
-#define fld_MIN_PULSE_WIDTH_def (CARD32) 0x0000002F
-#define fld_MAX_PULSE_WIDTH_def (CARD32) 0x00000046
-
-#define fld_WIN_CLOSE_LIMIT_def (CARD32) 0x0000004D
-#define fld_WIN_OPEN_LIMIT_def (CARD32) 0x000001B7
-
-#define fld_VSYNC_INT_TRIGGER_def (CARD32) 0x000002AA
-
-#define fld_VSYNC_INT_HOLD_def (CARD32) 0x0000001D
-
-#define fld_VIN_M0_def (CARD32) 0x00000039
-#define fld_VIN_N0_def (CARD32) 0x0000014c
-#define fld_MNFLIP_EN_def (CARD32) 0x00000000
-#define fld_VIN_P_def (CARD32) 0x00000006
-#define fld_REG_CLK_SEL_def (CARD32) 0x00000000
-
-#define fld_VIN_M1_def (CARD32) 0x00000000
-#define fld_VIN_N1_def (CARD32) 0x00000000
-#define fld_VIN_DRIVER_SEL_def (CARD32) 0x00000000
-#define fld_VIN_MNFLIP_REQ_def (CARD32) 0x00000000
-#define fld_VIN_MNFLIP_DONE_def (CARD32) 0x00000000
-#define fld_TV_LOCK_TO_VIN_def (CARD32) 0x00000000
-#define fld_TV_P_FOR_WINCLK_def (CARD32) 0x00000004
-
-#define fld_VINRST_def (CARD32) 0x00000001
-#define fld_VIN_CLK_SEL_def (CARD32) 0x00000000
-
-#define fld_VS_FIELD_BLANK_START_def (CARD32) 0x00000206
-
-#define fld_VS_FIELD_BLANK_END_def (CARD32) 0x0000000A
-
-/*#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000105 */
-#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000001
-#define fld_VS_FRAME_TOTAL_def (CARD32) 0x00000217
-
-#define fld_SYNC_TIP_START_def (CARD32) 0x00000372
-#define fld_SYNC_TIP_LENGTH_def (CARD32) 0x0000000F
-
-#define fld_GAIN_FORCE_DATA_def (CARD32) 0x00000000
-#define fld_GAIN_FORCE_EN_def (CARD32) 0x00000000
-#define fld_I_CLAMP_SEL_def (CARD32) 0x00000003
-#define fld_I_AGC_SEL_def (CARD32) 0x00000001
-#define fld_EXT_CLAMP_CAP_def (CARD32) 0x00000001
-#define fld_EXT_AGC_CAP_def (CARD32) 0x00000001
-#define fld_DECI_DITHER_EN_def (CARD32) 0x00000001
-#define fld_ADC_PREFHI_def (CARD32) 0x00000000
-#define fld_ADC_CH_GAIN_SEL_def (CARD32) 0x00000001
-
-#define fld_HS_PLL_SGAIN_def (CARD32) 0x00000003
-
-#define fld_NREn_def (CARD32) 0x00000000
-#define fld_NRGainCntl_def (CARD32) 0x00000000
-#define fld_NRBWTresh_def (CARD32) 0x00000000
-#define fld_NRGCTresh_def (CARD32) 0x00000000
-#define fld_NRCoefDespeclMode_def (CARD32) 0x00000000
-
-#define fld_GPIO_5_OE_def (CARD32) 0x00000000
-#define fld_GPIO_6_OE_def (CARD32) 0x00000000
-
-#define fld_GPIO_5_OUT_def (CARD32) 0x00000000
-#define fld_GPIO_6_OUT_def (CARD32) 0x00000000
-
-/* End of field default values. */
-
-#endif
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