xf86-video-ati: Branch 'master' - 2 commits

[Alex Deucher]

 src/radeon.h             |   17 ++++++++++++-----
 src/radeon_accel.c       |    8 ++++++--
 src/radeon_commonfuncs.c |   38 ++++++++++++++++++++++++++------------
 3 files changed, 44 insertions(+), 19 deletions(-)

New commits:
commit ea944f38dcfd871b27345698afea1cb986ecb049
Author: Alex Deucher <alex at samba.(none)>
Date:   Wed Feb 27 14:37:52 2008 -0500

    R300+: update RADEONCP_REFRESH() to reflect new location of scissor regs

diff --git a/src/radeon.h b/src/radeon.h
index aba3c0f..9c83a4f 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -998,11 +998,18 @@ do {									\
 	    info->needCacheFlush = FALSE;				\
 	}								\
 	RADEON_WAIT_UNTIL_IDLE();					\
-	BEGIN_RING(6);							\
-	OUT_RING_REG(RADEON_RE_TOP_LEFT,     info->re_top_left);	\
-	OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height);	\
-	OUT_RING_REG(RADEON_AUX_SC_CNTL,     info->aux_sc_cntl);	\
-	ADVANCE_RING();							\
+        if (info->ChipFamily <= CHIP_FAMILY_RV280) {                    \
+	    BEGIN_RING(6);						\
+	    OUT_RING_REG(RADEON_RE_TOP_LEFT,     info->re_top_left);	\
+	    OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height); \
+	    OUT_RING_REG(RADEON_AUX_SC_CNTL,     info->aux_sc_cntl);	\
+	    ADVANCE_RING();						\
+        } else {                                                        \
+            BEGIN_RING(4);                                              \
+            OUT_RING_REG(R300_SC_SCISSOR0, info->re_top_left);          \
+	    OUT_RING_REG(R300_SC_SCISSOR1, info->re_width_height);      \
+            ADVANCE_RING();                                             \
+	}                                                               \
 	info->CPInUse = TRUE;						\
     }									\
 } while (0)
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 8b2f167..015d176 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -390,8 +390,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
     info->sc_bottom       = RADEON_DEFAULT_SC_BOTTOM_MAX;
 
     info->re_top_left     = 0x00000000;
-    info->re_width_height = ((0x7ff << RADEON_RE_WIDTH_SHIFT) |
-			     (0x7ff << RADEON_RE_HEIGHT_SHIFT));
+    if (info->ChipFamily <= CHIP_FAMILY_RV280)
+	info->re_width_height = ((0x7ff << RADEON_RE_WIDTH_SHIFT) |
+				 (0x7ff << RADEON_RE_HEIGHT_SHIFT));
+    else
+	info->re_width_height = ((8191 << R300_SCISSOR_X_SHIFT) |
+				 (8191 << R300_SCISSOR_Y_SHIFT));
 
     info->aux_sc_cntl     = 0x00000000;
 #endif
commit b865faf95666e2172c3eec143f77fe9c524e4983
Author: Alex Deucher <alex at samba.(none)>
Date:   Wed Feb 27 14:05:44 2008 -0500

    R100/R200: move r100/r200 specific 3D setup into appropriate blocks
    
    R3xx+ doesn't have these regs.

diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 0250aef..4469cd8 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -239,6 +239,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
 	    R200_VAP_VF_MAX_VTX_NUM);
 	FINISH_ACCEL();
+
+	BEGIN_ACCEL(5);
+	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
+	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
+	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
+	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
+	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
+				       RADEON_BFACE_SOLID |
+				       RADEON_FFACE_SOLID |
+				       RADEON_VTX_PIX_CENTER_OGL |
+				       RADEON_ROUND_MODE_ROUND |
+				       RADEON_ROUND_PREC_4TH_PIX));
+	FINISH_ACCEL();
     } else {
 	BEGIN_ACCEL(2);
 	if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
@@ -252,20 +265,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	    RADEON_VTX_ST1_NONPARAMETRIC |
 	    RADEON_TEX1_W_ROUTING_USE_W0);
 	FINISH_ACCEL();
+
+	BEGIN_ACCEL(5);
+	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
+	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
+	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
+	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
+	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
+				       RADEON_BFACE_SOLID |
+				       RADEON_FFACE_SOLID |
+				       RADEON_VTX_PIX_CENTER_OGL |
+				       RADEON_ROUND_MODE_ROUND |
+				       RADEON_ROUND_PREC_4TH_PIX));
+	FINISH_ACCEL();
     }
 
-    BEGIN_ACCEL(5);
-    OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
-    OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
-    OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
-    OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
-    OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
-				   RADEON_BFACE_SOLID |
-				   RADEON_FFACE_SOLID |
-				   RADEON_VTX_PIX_CENTER_OGL |
-				   RADEON_ROUND_MODE_ROUND |
-				   RADEON_ROUND_PREC_4TH_PIX));
-    FINISH_ACCEL();
 }