xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Thu Feb 28 16:16:55 PST 2008
src/radeon_atombios.c | 28 +++++++-------------
src/radeon_driver.c | 68 +++++++++++++++++++++++++++++++++++++-------------
src/radeon_probe.h | 8 ++++-
3 files changed, 67 insertions(+), 37 deletions(-)
New commits:
commit e56062960be0c8d3947861dd5e0691fce6516b99
Author: Alex Deucher <alex at cube.(none)>
Date: Thu Feb 28 19:16:39 2008 -0500
AVIVO: save/restore scaler regs
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 10b0b8c..c38e39b 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4045,6 +4045,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
struct avivo_state *state = &save->avivo;
+ int i, j;
// state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
// state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
@@ -4110,8 +4111,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
- state->grph1.scl_enable = INREG(AVIVO_D1SCL_SCALER_ENABLE);
- state->grph1.scl_tap_control = INREG(AVIVO_D1SCL_SCALER_TAP_CONTROL);
state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
@@ -4151,8 +4150,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
- state->grph2.scl_enable = INREG(AVIVO_D2SCL_SCALER_ENABLE);
- state->grph2.scl_tap_control = INREG(AVIVO_D2SCL_SCALER_TAP_CONTROL);
state->daca.enable = INREG(AVIVO_DACA_ENABLE);
state->daca.source_select = INREG(AVIVO_DACA_SOURCE_SELECT);
@@ -4189,7 +4186,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
if (info->IsIGP) {
- int i, j = 0;
+ j = 0;
/* save DDIA regs */
for (i = 0x7200; i <= 0x7290; i += 4) {
state->ddia[j] = INREG(i);
@@ -4197,6 +4194,26 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
}
+ /* scalers */
+ j = 0;
+ for (i = 0x6578; i <= 0x65e4; i += 4) {
+ state->d1scl[j] = INREG(i);
+ state->d2scl[j] = INREG(i + 0x800);
+ j++;
+ }
+ for (i = 0x6600; i <= 0x662c; i += 4) {
+ state->d1scl[j] = INREG(i);
+ state->d2scl[j] = INREG(i + 0x800);
+ j++;
+ }
+ j = 0;
+ for (i = 0x66e8; i <= 0x66fc; i += 4) {
+ state->dxscl[j] = INREG(i);
+ j++;
+ }
+ state->dxscl[6] = INREG(0x6e30);
+ state->dxscl[7] = INREG(0x6e34);
+
if (state->crtc1.control & AVIVO_CRTC_EN)
info->crtc_on = TRUE;
@@ -4211,6 +4228,7 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
struct avivo_state *state = &restore->avivo;
+ int i, j;
// OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
// OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
@@ -4275,8 +4293,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
- OUTREG(AVIVO_D1SCL_SCALER_ENABLE, state->grph1.scl_enable);
- OUTREG(AVIVO_D1SCL_SCALER_TAP_CONTROL, state->grph1.scl_tap_control);
OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
@@ -4315,8 +4331,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
- OUTREG(AVIVO_D2SCL_SCALER_ENABLE, state->grph2.scl_enable);
- OUTREG(AVIVO_D2SCL_SCALER_TAP_CONTROL, state->grph2.scl_tap_control);
OUTREG(AVIVO_DACA_ENABLE, state->daca.enable);
OUTREG(AVIVO_DACA_SOURCE_SELECT, state->daca.source_select);
@@ -4341,15 +4355,15 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select);
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
- OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
- OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
- OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
+ OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
+ OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
+ OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
+ OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
} else {
- OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
- OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
- OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
- OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
+ OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable);
+ OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl);
+ OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl);
+ OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state);
}
if (info->IsIGP) {
@@ -4360,6 +4374,26 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
}
}
+ /* scalers */
+ j = 0;
+ for (i = 0x6578; i <= 0x65e4; i += 4) {
+ OUTREG(i, state->d1scl[j]);
+ OUTREG((i + 0x800), state->d2scl[j]);
+ j++;
+ }
+ for (i = 0x6600; i <= 0x662c; i += 4) {
+ OUTREG(i, state->d1scl[j]);
+ OUTREG((i + 0x800), state->d2scl[j]);
+ j++;
+ }
+ j = 0;
+ for (i = 0x66e8; i <= 0x66fc; i += 4) {
+ OUTREG(i, state->dxscl[j]);
+ j++;
+ }
+ OUTREG(0x6e30, state->dxscl[6]);
+ OUTREG(0x6e34, state->dxscl[7]);
+
OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 82bb153..21e3439 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -310,8 +310,6 @@ struct avivo_grph_state {
CARD32 viewport_start;
CARD32 viewport_size;
- CARD32 scl_enable;
- CARD32 scl_tap_control;
};
struct avivo_dac_state {
@@ -363,6 +361,12 @@ struct avivo_state
/* DDIA block on RS6xx chips */
CARD32 ddia[37];
+
+ /* scalers */
+ CARD32 d1scl[39];
+ CARD32 d2scl[39];
+ CARD32 dxscl[6+2];
+
};
/*
commit ae1c39a9b3e666404d0931679c9078c2e125a8bc
Author: Alex Deucher <alex at cube.(none)>
Date: Thu Feb 28 18:53:55 2008 -0500
RS6xx: rework output parsing
Turns out it's not as complex as I originially thought.
IGP chips just have non-standard GPIO entires for DDC.
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 88c220b..351939e 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1745,12 +1745,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
info->BiosConnector[i].valid = TRUE;
info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
- if (info->IsIGP && (i == ATOM_DEVICE_DFP2_INDEX))
- info->BiosConnector[i].devices = (1 << ATOM_DEVICE_DFP3_INDEX);
- else if (info->IsIGP && (i == ATOM_DEVICE_DFP3_INDEX))
- info->BiosConnector[i].devices = (1 << ATOM_DEVICE_DFP2_INDEX);
- else
- info->BiosConnector[i].devices = (1 << i);
+ info->BiosConnector[i].devices = (1 << i);
info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
@@ -1759,14 +1754,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
(i == ATOM_DEVICE_TV2_INDEX) ||
(i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_i2c.valid = FALSE;
- else if ((i == ATOM_DEVICE_DFP3_INDEX) && info->IsIGP) {
- /* DDIA port uses non-standard gpio entry */
- if (info->BiosConnector[ATOM_DEVICE_DFP2_INDEX].valid)
+ else if (info->IsIGP) {
+ /* IGP DFP ports use non-standard gpio entries */
+ if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 2);
+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
else
info->BiosConnector[i].ddc_i2c =
- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
} else
info->BiosConnector[i].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
@@ -1775,15 +1770,12 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
info->BiosConnector[i].TMDSType = TMDS_INT;
else if (i == ATOM_DEVICE_DFP2_INDEX) {
if (info->IsIGP)
- info->BiosConnector[i].TMDSType = TMDS_LVTMA;
- else
- info->BiosConnector[i].TMDSType = TMDS_EXT;
- } else if (i == ATOM_DEVICE_DFP3_INDEX) {
- if (info->IsIGP)
info->BiosConnector[i].TMDSType = TMDS_DDIA;
else
- info->BiosConnector[i].TMDSType = TMDS_LVTMA;
- } else
+ info->BiosConnector[i].TMDSType = TMDS_EXT;
+ } else if (i == ATOM_DEVICE_DFP3_INDEX)
+ info->BiosConnector[i].TMDSType = TMDS_LVTMA;
+ else
info->BiosConnector[i].TMDSType = TMDS_NONE;
/* Always set the connector type to VGA for CRT1/CRT2. if they are
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