xf86-video-ati: Branch 'master' - 2 commits

[Dave Airlie]

 src/radeon_dri.c    |    3 +--
 src/radeon_driver.c |   18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)

New commits:
commit 00ac9d2f8d58725d0d3e6b1bf7f728d9ae7e6109
Author: David Miller <davem at davemloft.net>
Date:   Sun Feb 15 18:26:14 2009 +1000

    GART: Save/restore GART table consistently.
    
    Always save the GART table with the RADEON_SURFACE_CNTL register
    zero'd out to make sure we always use the same endinanness.
    
    fixed up as per Michel's suggestion for endianness.
    
    Signed-off-by: David S. Miller <davem at davemloft.net>
    Signed-off-by: Dave Airlie <airlied at linux.ie>

diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 813b25e..d22db58 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5511,8 +5511,17 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
     	if (info->cardType == CARD_PCIE &&
 	    info->dri->pKernelDRMVersion->version_minor >= 19 &&
 	    info->FbSecureSize) {
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+	    unsigned char *RADEONMMIO = info->MMIO;
+	    unsigned int sctrl = INREG(RADEON_SURFACE_CNTL);
+
 	    /* we need to backup the PCIE GART TABLE from fb memory */
+	    OUTREG(RADEON_SURFACE_CNTL, 0);
+#endif
 	    memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+	    OUTREG(RADEON_SURFACE_CNTL, sctrl);
+#endif
     	}
 
 	/* get the DRI back into shape after resume */
@@ -5562,8 +5571,17 @@ void RADEONLeaveVT(int scrnIndex, int flags)
         if (info->cardType == CARD_PCIE &&
 	    info->dri->pKernelDRMVersion->version_minor >= 19 &&
 	    info->FbSecureSize) {
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+	    unsigned char *RADEONMMIO = info->MMIO;
+	    unsigned int sctrl = INREG(RADEON_SURFACE_CNTL);
+
             /* we need to backup the PCIE GART TABLE from fb memory */
+	    OUTREG(RADEON_SURFACE_CNTL, 0);
+#endif
             memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+	    OUTREG(RADEON_SURFACE_CNTL, sctrl);
+#endif
         }
 
 	/* Make sure 3D clients will re-upload textures to video RAM */
commit 2de90c8349409eb892edc57fd24b61b679eb7719
Author: David Miller <davem at davemloft.net>
Date:   Sun Feb 15 18:24:01 2009 +1000

    DRI: Fix page size used in RADEONDRIGetPciAperTableSize().
    
    The ATI GART has a fixed size of 4096 bytes.  So using
    the system page size here is wrong.
    
    Signed-off-by: David S. Miller <davem at davemloft.net>
    Signed-off-by: Dave Airlie <airlied at linux.ie>

diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 44b3eb6..7cf4d39 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -2295,11 +2295,10 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
 int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr  info   = RADEONPTR(pScrn);
-    int page_size  = getpagesize();
     int ret_size;
     int num_pages;
 
-    num_pages = (info->dri->pciAperSize * 1024 * 1024) / page_size;
+    num_pages = (info->dri->pciAperSize * 1024 * 1024) / 4096;
     
     ret_size = num_pages * sizeof(unsigned int);