xf86-video-intel: 6 commits - configure.ac Makefile.am src/common.h src/i810_driver.c src/i810_reg.h src/i830_debug.c src/i830_display.c src/i830_driver.c src/i830_exa.c src/i830.h src/i915_render.c src/Makefile.am uxa/uxa-accel.c uxa/uxa.c uxa/uxa-glyphs.c uxa/uxa-priv.h uxa/uxa-render.c uxa/uxa-unaccel.c
Eric Anholt
anholt at kemper.freedesktop.org
Thu Feb 26 14:51:36 PST 2009
Makefile.am | 6 --
configure.ac | 19 ++++----
src/Makefile.am | 9 +---
src/common.h | 15 +++++-
src/i810_driver.c | 8 +++
src/i810_reg.h | 4 +
src/i830.h | 6 ++
src/i830_debug.c | 42 +++++++++++++++----
src/i830_display.c | 116 ++++++++++++++++++++++++++++++++++++++++++++---------
src/i830_driver.c | 20 ++++++++-
src/i830_exa.c | 86 +++++++++++++++++++++++++++++++++++----
src/i915_render.c | 9 ++++
uxa/uxa-accel.c | 62 ++++++++++++++++++++++++++++
uxa/uxa-glyphs.c | 4 +
uxa/uxa-priv.h | 22 +++++++++-
uxa/uxa-render.c | 7 ++-
uxa/uxa-unaccel.c | 18 ++++++++
uxa/uxa.c | 31 +++++++++++++-
18 files changed, 422 insertions(+), 62 deletions(-)
New commits:
commit f53bdad1412f841075232455837578f00709c6ef
Author: Shaohua Li <shaohua.li at intel.com>
Date: Mon Feb 23 15:19:23 2009 +0800
Intel video driver patch
This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li at intel.com>
Signed-off-by: Eric Anholt <eric at anholt.net>
diff --git a/src/common.h b/src/common.h
index be222df..8b32a66 100644
--- a/src/common.h
+++ b/src/common.h
@@ -241,6 +241,13 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM 0xA011
+#define PCI_CHIP_IGD_GM_BRIDGE 0xA010
+#define PCI_CHIP_IGD_G 0xA001
+#define PCI_CHIP_IGD_G_BRIDGE 0xA000
+#endif
+
#ifndef PCI_CHIP_G35_G
#define PCI_CHIP_G35_G 0x2982
#define PCI_CHIP_G35_G_BRIDGE 0x2980
@@ -342,6 +349,9 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
+#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
+#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
@@ -349,11 +359,12 @@ extern int I810_DEBUG;
#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
- DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
+ DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
+ IS_IGD(pI810))
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
diff --git a/src/i810_driver.c b/src/i810_driver.c
index cc28ad8..c10e15b 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -143,6 +143,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
@@ -200,6 +202,8 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
+ {PCI_CHIP_IGD_GM, "IGD_GM"},
+ {PCI_CHIP_IGD_G, "IGD_G"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
@@ -234,6 +238,8 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
@@ -794,6 +800,8 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
+ case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_IGD_G:
case PCI_CHIP_I965_G:
case PCI_CHIP_G35_G:
case PCI_CHIP_I965_Q:
diff --git a/src/i810_reg.h b/src/i810_reg.h
index e2ffba1..51970c1 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -969,6 +969,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
+# define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
/**
* The i830 generation, in DAC/serial mode, defines p1 as two plus this
* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
@@ -980,6 +981,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
+# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
# define PLL_REF_INPUT_DREFCLK (0 << 13)
@@ -1228,10 +1230,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FPB0 0x06048
#define FPB1 0x0604c
# define FP_N_DIV_MASK 0x003f0000
+# define FP_N_IGD_DIV_MASK 0x00ff0000
# define FP_N_DIV_SHIFT 16
# define FP_M1_DIV_MASK 0x00003f00
# define FP_M1_DIV_SHIFT 8
# define FP_M2_DIV_MASK 0x0000003f
+# define FP_M2_IGD_DIV_MASK 0x000000ff
# define FP_M2_DIV_SHIFT 0
#define PORT_HOTPLUG_EN 0x61110
diff --git a/src/i830_debug.c b/src/i830_debug.c
index dc3712b..d99af57 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -189,6 +189,12 @@ DEBUGSTRING(i830_debug_vgacntrl)
DEBUGSTRING(i830_debug_fp)
{
+ if (IS_IGD(pI830)) {
+ return XNFprintf("n = %d, m1 = %d, m2 = %d",
+ ffs((val & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1,
+ ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
+ ((val & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT));
+ }
return XNFprintf("n = %d, m1 = %d, m2 = %d",
((val & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT),
((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
@@ -256,8 +262,13 @@ DEBUGSTRING(i830_debug_dpll)
int p1, p2 = 0;
if (IS_I9XX(pI830)) {
- p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT);
+ if (IS_IGD(pI830)) {
+ p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
+ } else {
+ p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT);
+ }
switch (val & DPLL_MODE_MASK) {
case DPLLB_MODE_DAC_SERIAL:
mode = "DAC/serial";
@@ -893,7 +904,11 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
break;
}
}
- switch ((dpll >> 16) & 0xff) {
+ if (IS_IGD(pI830))
+ i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD) & 0x1ff;
+ else
+ i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT) & 0xff;
+ switch (i) {
case 1:
p1 = 1; break;
case 2:
@@ -910,6 +925,11 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
p1 = 7; break;
case 128:
p1 = 8; break;
+ case 256:
+ if (IS_IGD(pI830)) {
+ p1 = 9;
+ break;
+ } /* fallback */
default:
p1 = 1;
xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
@@ -999,11 +1019,19 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
"fp select out of range\n");
break;
}
- n = ((fp >> 16) & 0x3f);
m1 = ((fp >> 8) & 0x3f);
- m2 = ((fp >> 0) & 0x3f);
- m = 5 * (m1 + 2) + (m2 + 2);
- dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
+ if (IS_IGD(pI830)) {
+ n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
+ m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ m = m2 + 2;
+ dot = (ref * m) / n / (p1 * p2);
+ } else {
+ n = ((fp >> 16) & 0x3f);
+ m2 = ((fp >> 0) & 0x3f);
+ m = 5 * (m1 + 2) + (m2 + 2);
+ dot = (ref * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)) / (p1 * p2);
+ }
+
xf86DrvMsg (pScrn->scrnIndex, X_INFO, "pipe %s dot %d n %d m1 %d m2 %d p1 %d p2 %d\n",
pipe == 0 ? "A" : "B", dot, n, m1, m2, p1, p2);
}
diff --git a/src/i830_display.c b/src/i830_display.c
index 16908c6..e243bfd 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -100,6 +100,8 @@ typedef struct {
#define I9XX_DOT_MAX 400000
#define I9XX_VCO_MIN 1400000
#define I9XX_VCO_MAX 2800000
+#define IGD_VCO_MIN 1700000
+#define IGD_VCO_MAX 3500000
/* Haven't found any reason to go this fast, but newer chips support it */
#define I96X_VCO_MAX 3200000
@@ -111,19 +113,31 @@ typedef struct {
*/
#define I9XX_N_MIN 1
#define I9XX_N_MAX 6
+/* IGD's Ncounter is a ring counter */
+#define IGD_N_MIN 3
+#define IGD_N_MAX 6
#define I9XX_M_MIN 70
#define I9XX_M_MAX 120
+#define IGD_M_MIN 2
+#define IGD_M_MAX 256
/* these two come from the calm1 macro */
#define I9XX_M1_MIN 10
#define I9XX_M1_MAX 22
#define I9XX_M2_MIN 5
#define I9XX_M2_MAX 9
+/* IGD M1 is reserved, and must be 0 */
+#define IGD_M1_MIN 0
+#define IGD_M1_MAX 0
+#define IGD_M2_MIN 0
+#define IGD_M2_MAX 254
#define I9XX_P_SDVO_DAC_MIN 5
#define I9XX_P_SDVO_DAC_MAX 80
#define I9XX_P_LVDS_MIN 7
#define I9XX_P_LVDS_MAX 98
+#define IGD_P_LVDS_MIN 7
+#define IGD_P_LVDS_MAX 112
#define I9XX_P1_MIN 1
#define I9XX_P1_MAX 8
#define I9XX_P2_SDVO_DAC_SLOW 10
@@ -137,6 +151,8 @@ typedef struct {
#define INTEL_LIMIT_I8XX_LVDS 1
#define INTEL_LIMIT_I9XX_SDVO_DAC 2
#define INTEL_LIMIT_I9XX_LVDS 3
+#define INTEL_LIMIT_IGD_SDVO_DAC 4
+#define INTEL_LIMIT_IGD_LVDS 5
static const intel_limit_t intel_limits[] = {
{ /* INTEL_LIMIT_I8XX_DVO_DAC */
@@ -190,6 +206,31 @@ static const intel_limit_t intel_limits[] = {
.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
},
+ { /* INTEL_LIMIT_IGD_SDVO */
+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
+ .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
+ .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
+ .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
+ },
+ { /* INTEL_LIMIT_IGD_LVDS */
+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
+ .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
+ /* IGD only supports single-channel mode. */
+ .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
+ .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
+ },
};
static const intel_limit_t *intel_limit (xf86CrtcPtr crtc)
@@ -198,11 +239,16 @@ static const intel_limit_t *intel_limit (xf86CrtcPtr crtc)
I830Ptr pI830 = I830PTR(pScrn);
const intel_limit_t *limit;
- if (IS_I9XX(pI830)) {
+ if (IS_I9XX(pI830) && !IS_IGD(pI830)) {
if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
else
limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
+ } else if (IS_IGD(pI830)) {
+ if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
+ limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
+ else
+ limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
} else {
if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
@@ -233,11 +279,23 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
clock->dot = clock->vco / clock->p;
}
+/* m1 is reserved as 0 in IGD, n is a ring counter */
+static void igd_clock(int refclk, intel_clock_t *clock)
+{
+ clock->m = clock->m2 + 2;
+ clock->p = clock->p1 * clock->p2;
+ clock->vco = refclk * clock->m / clock->n;
+ clock->dot = clock->vco / clock->p;
+}
+
static void intel_clock(I830Ptr pI830, int refclk, intel_clock_t *clock)
{
- if (IS_I9XX(pI830))
- i9xx_clock (refclk, clock);
- else
+ if (IS_I9XX(pI830)) {
+ if (IS_IGD(pI830))
+ igd_clock(refclk, clock);
+ else
+ i9xx_clock (refclk, clock);
+ } else
i8xx_clock (refclk, clock);
}
@@ -286,6 +344,8 @@ static Bool
i830PllIsValid(xf86CrtcPtr crtc, intel_clock_t *clock)
{
const intel_limit_t *limit = intel_limit (crtc);
+ ScrnInfoPtr pScrn = crtc->scrn;
+ I830Ptr pI830 = I830PTR(pScrn);
if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
i830PllInvalid ("p1 out of range\n");
@@ -295,7 +355,7 @@ i830PllIsValid(xf86CrtcPtr crtc, intel_clock_t *clock)
i830PllInvalid ("m2 out of range\n");
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
i830PllInvalid ("m1 out of range\n");
- if (clock->m1 <= clock->m2)
+ if (clock->m1 <= clock->m2 && !IS_IGD(pI830))
i830PllInvalid ("m1 <= m2\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
i830PllInvalid ("m out of range\n");
@@ -347,8 +407,11 @@ i830FindBestPLL(xf86CrtcPtr crtc, int target, int refclk, intel_clock_t *best_cl
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++)
{
- for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; clock.m2++)
+ for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++)
{
+ /* m1 is always 0 in IGD */
+ if (clock.m2 >= clock.m1 && !IS_IGD(pI830))
+ break;
for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++)
{
for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; clock.p1++)
@@ -1055,11 +1118,11 @@ i830_get_core_clock_speed(ScrnInfoPtr pScrn)
/* Core clock values taken from the published datasheets.
* The 830 may go up to 166 Mhz, which we should check.
*/
- if (IS_I945G(pI830) || IS_G33CLASS(pI830))
+ if (IS_I945G(pI830) || (IS_G33CLASS(pI830) && !IS_IGDGM(pI830)))
return 400000;
else if (IS_I915G(pI830))
return 333000;
- else if (IS_I945GM(pI830) || IS_845G(pI830))
+ else if (IS_I945GM(pI830) || IS_845G(pI830) || IS_IGDGM(pI830))
return 200000;
else if (IS_I915GM(pI830)) {
uint16_t gcfgc;
@@ -1324,7 +1387,10 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
}
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+ if (IS_IGD(pI830))
+ fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
+ else
+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
dpll = DPLL_VGA_MODE_DIS;
if (IS_I9XX(pI830)) {
@@ -1343,7 +1409,10 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
}
/* compute bitmask from p1 value */
- dpll |= (1 << (clock.p1 - 1)) << 16;
+ if (IS_IGD(pI830))
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
+ else
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
switch (clock.p2) {
case 5:
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
@@ -1915,11 +1984,20 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
fp = INREG((pipe == 0) ? FPA1 : FPB1);
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
- clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
- clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
+ if (IS_IGD(pI830)) {
+ clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
+ clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ } else {
+ clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
+ clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ }
if (IS_I9XX(pI830)) {
- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT);
+ if (IS_IGD(pI830))
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
+ else
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT);
switch (dpll & DPLL_MODE_MASK) {
case DPLLB_MODE_DAC_SERIAL:
@@ -1936,9 +2014,9 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
}
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- i9xx_clock(100000, &clock);
+ intel_clock(pI830, 100000, &clock);
else
- i9xx_clock(96000, &clock);
+ intel_clock(pI830, 96000, &clock);
} else {
Bool is_lvds = (pipe == 1) && (INREG(LVDS) & LVDS_PORT_EN);
@@ -1953,9 +2031,9 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
clock.p2 = 14;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */
+ intel_clock(pI830, 66000, &clock); /* XXX: might not be 66MHz */
else
- i8xx_clock(48000, &clock);
+ intel_clock(pI830, 48000, &clock);
} else {
if (dpll & PLL_P1_DIVIDE_BY_TWO) {
clock.p1 = 2;
@@ -1968,7 +2046,7 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
else
clock.p2 = 2;
- i8xx_clock(48000, &clock);
+ intel_clock(pI830, 48000, &clock);
}
}
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1e4da65..342a059 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -244,6 +244,8 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
+ {PCI_CHIP_IGD_GM, "IGD"},
+ {PCI_CHIP_IGD_G, "IGD"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
@@ -272,6 +274,8 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_G35_G, PCI_CHIP_G35_G, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
@@ -501,7 +505,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
/* new 4 series hardware has seperate GTT stolen with GFX stolen */
- if (IS_G4X(pI830))
+ if (IS_G4X(pI830) || IS_IGD(pI830))
range = 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
@@ -1330,6 +1334,12 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
case PCI_CHIP_I945_GME:
chipname = "945GME";
break;
+ case PCI_CHIP_IGD_GM:
+ chipname = "IGD";
+ break;
+ case PCI_CHIP_IGD_G:
+ chipname = "IGD";
+ break;
case PCI_CHIP_I965_G:
chipname = "965G";
break;
commit 22dc9a5580d77cc4707bfb8e19474e611a06ae9a
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 24 18:22:20 2009 -0800
Fix UXA for server 1.4.
diff --git a/Makefile.am b/Makefile.am
index 896427f..d1118fe 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -20,11 +20,7 @@
AUTOMAKE_OPTIONS = foreign
-if BUILD_UXA
-UXA_DIR = uxa
-endif
-
-SUBDIRS = $(UXA_DIR) src man
+SUBDIRS = uxa src man
EXTRA_DIST = README
DISTCLEANFILES = doltcompile
diff --git a/configure.ac b/configure.ac
index a6ced67..3f6f1b8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -84,7 +84,13 @@ XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
# Checks for pkg-config packages
PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES])
-PKG_CHECK_MODULES(UXA, [xorg-server >= 1.5], [BUILD_UXA=yes], [BUILD_UXA=no])
+
+PKG_CHECK_MODULES(SERVER_1_5, [xorg-server >= 1.5],
+ [SERVER_1_5=yes], [SERVER_1_5=no])
+
+if test "$SERVER_1_5" = yes; then
+ AC_DEFINE(SERVER_1_5, 1, [Building against server 1.5])
+fi
sdkdir=$(pkg-config --variable=sdkdir xorg-server)
drm_cflags=$(pkg-config --cflags libdrm)
@@ -118,11 +124,6 @@ if test x$DRI = xauto; then
fi
AC_MSG_RESULT([$DRI])
-AM_CONDITIONAL(BUILD_UXA, test $BUILD_UXA = yes)
-if test "$BUILD_UXA" = yes; then
- AC_DEFINE(I830_USE_UXA, 1, [UMA Acceleration Architecture support])
-fi
-
AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"])
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
@@ -182,8 +183,6 @@ else
fi
AC_SUBST([XMODES_CFLAGS])
-UXA_CFLAGS='-I$(top_srcdir)/uxa'
-AC_SUBST([UXA_CFLAGS])
SAVE_CPPFLAGS="$CPPFLAGS"
CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"
@@ -215,9 +214,9 @@ if test "$DRI" = yes; then
AC_DEFINE(XF86DRI_DEVEL,1,[Enable developmental DRI driver support])
fi
-dnl exaGetPixmapDriverPrivate required for DRM_MODE.
+dnl Server 1.5's set_mode_major required for DRM_MODE.
PKG_CHECK_MODULES(DRM_MODE, [xorg-server >= 1.5],
- [DRM_MODE=yes], [DRM_MODE=no])
+ [DRM_MODE=yes], [DRM_MODE=no])
if test "x$DRM_MODE" = xyes; then
AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
fi
diff --git a/src/Makefile.am b/src/Makefile.am
index cbe9fb1..e05dbab 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -31,16 +31,13 @@ SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 $(REGDUMPER)
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \
- @PCIACCESS_CFLAGS@ @UXA_CFLAGS@ \
- @XMODES_CFLAGS@ -DI830_XV -DI830_USE_XAA -DI830_USE_EXA
+ @PCIACCESS_CFLAGS@ -I$(top_srcdir)/uxa \
+ @XMODES_CFLAGS@ -DI830_XV -DI830_USE_XAA -DI830_USE_EXA -DI830_USE_UXA
intel_drv_la_LTLIBRARIES = intel_drv.la
intel_drv_la_LDFLAGS = -module -avoid-version
intel_drv_ladir = @moduledir@/drivers
-intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel
-if BUILD_UXA
-intel_drv_la_LIBADD += ../uxa/libuxa.la
-endif
+intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la
if XSERVER_LIBPCIACCESS
intel_drv_la_LIBADD += @PCIACCESS_LIBS@
endif
diff --git a/src/i830.h b/src/i830.h
index 3f10892..a0ae571 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -975,6 +975,10 @@ i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform,
void i830_enter_render(ScrnInfoPtr);
+#ifndef SERVER_1_5
+Bool xf86MonitorIsHDMI(xf86MonPtr mon);
+#endif
+
static inline void
i830_wait_ring_idle(ScrnInfoPtr pScrn)
{
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 1506ea7..1e4da65 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1140,10 +1140,12 @@ i830_pad_drawable_width(int width, int cpp)
static Bool
i830_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
{
+#ifdef DRI2
I830Ptr i830 = I830PTR(scrn);
+ int old_width = scrn->displayWidth;
+#endif
int old_x = scrn->virtualX;
int old_y = scrn->virtualY;
- int old_width = scrn->displayWidth;
if (old_x == width && old_y == height)
return TRUE;
diff --git a/src/i830_exa.c b/src/i830_exa.c
index 20e7a13..b9d6c64 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -81,6 +81,22 @@ const int I830PatternROP[16] =
ROP_1
};
+#ifdef I830_USE_UXA
+static int uxa_pixmap_index;
+#endif
+
+#ifndef SERVER_1_5
+static inline void *dixLookupPrivate(DevUnion **privates, int *key)
+{
+ return (*privates)[*key].ptr;
+}
+
+static inline void dixSetPrivate(DevUnion **privates, int *key, void *val)
+{
+ (*privates)[*key].ptr = val;
+}
+#endif
+
/**
* Returns whether a given pixmap is tiled or not.
*
@@ -761,10 +777,6 @@ I830EXAInit(ScreenPtr pScreen)
return TRUE;
}
-#ifdef I830_USE_UXA
-static int uxa_pixmap_index;
-#endif
-
dri_bo *
i830_get_pixmap_bo(PixmapPtr pixmap)
{
@@ -841,7 +853,7 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
i830->need_sync = FALSE;
}
- if (pScrn->vtSema && !pI830->use_drm_mode) {
+ if (pScrn->vtSema && !pI830->use_drm_mode && pI830->memory_manager) {
if (drm_intel_bo_pin(bo, 4096) != 0)
return FALSE;
drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW);
@@ -867,7 +879,7 @@ i830_uxa_finish_access (PixmapPtr pixmap)
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
- if (pScrn->vtSema && !pI830->use_drm_mode)
+ if (pScrn->vtSema && !pI830->use_drm_mode && pI830->memory_manager)
drm_intel_bo_unpin(bo);
else
dri_bo_unmap(bo);
@@ -914,8 +926,12 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
if (w > 32767 || h > 32767)
return NullPixmap;
+#ifdef SERVER_1_5
pixmap = fbCreatePixmap (screen, 0, 0, depth, usage);
-
+#else
+ pixmap = fbCreatePixmap (screen, 0, 0, depth);
+#endif
+
if (w && h)
{
unsigned int size;
@@ -950,6 +966,15 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
return pixmap;
}
+
+#ifndef SERVER_1_5
+static PixmapPtr
+i830_uxa_server_14_create_pixmap (ScreenPtr screen, int w, int h, int depth)
+{
+ return i830_uxa_create_pixmap(screen, w, h, depth, 0);
+}
+#endif
+
static Bool
i830_uxa_destroy_pixmap (PixmapPtr pixmap)
{
@@ -982,9 +1007,14 @@ i830_uxa_init (ScreenPtr pScreen)
ScrnInfoPtr scrn = xf86Screens[pScreen->myNum];
I830Ptr i830 = I830PTR(scrn);
+#ifdef SERVER_1_5
if (!dixRequestPrivate(&uxa_pixmap_index, 0))
return FALSE;
-
+#else
+ if (!AllocatePixmapPrivate(pScreen, uxa_pixmap_index, 0))
+ return FALSE;
+#endif
+
i830->uxa_driver = uxa_driver_alloc();
if (i830->uxa_driver == NULL) {
i830->accel = ACCEL_NONE;
@@ -1038,7 +1068,11 @@ i830_uxa_init (ScreenPtr pScreen)
return FALSE;
}
+#ifdef SERVER_1_5
pScreen->CreatePixmap = i830_uxa_create_pixmap;
+#else
+ pScreen->CreatePixmap = i830_uxa_server_14_create_pixmap;
+#endif
pScreen->DestroyPixmap = i830_uxa_destroy_pixmap;
I830SelectBuffer(scrn, I830_SELECT_FRONT);
diff --git a/uxa/uxa-accel.c b/uxa/uxa-accel.c
index 1b0af9c..e322054 100644
--- a/uxa/uxa-accel.c
+++ b/uxa/uxa-accel.c
@@ -977,6 +977,68 @@ out:
return ret;
}
+#ifndef SERVER_1_5
+void
+uxa_paint_window(WindowPtr pWin, RegionPtr pRegion, int what)
+{
+ ScreenPtr screen = pWin->drawable.pScreen;
+ uxa_screen_t *uxa_screen = uxa_get_screen(screen);
+ DDXPointRec zeros = { 0, 0 };
+
+ if (REGION_NIL(pRegion))
+ return;
+
+ if (uxa_screen->swappedOut) {
+ uxa_check_paint_window(pWin, pRegion, what);
+ return;
+ }
+
+ switch (what) {
+ case PW_BACKGROUND:
+ switch (pWin->backgroundState) {
+ case None:
+ return;
+ case ParentRelative:
+ do {
+ pWin = pWin->parent;
+ } while (pWin->backgroundState == ParentRelative);
+ (*pWin->drawable.pScreen->PaintWindowBackground)(pWin, pRegion,
+ what);
+ return;
+ case BackgroundPixel:
+ if (uxa_fill_region_solid(&pWin->drawable, pRegion,
+ pWin->background.pixel,
+ FB_ALLONES, GXcopy))
+ return;
+ break;
+ case BackgroundPixmap:
+ if (uxa_fill_region_tiled(&pWin->drawable, pRegion,
+ pWin->background.pixmap,
+ &zeros, FB_ALLONES, GXcopy))
+ return;
+ break;
+ }
+ break;
+ case PW_BORDER:
+ if (pWin->borderIsPixel) {
+ if (uxa_fill_region_solid(&pWin->drawable, pRegion,
+ pWin->border.pixel,
+ FB_ALLONES, GXcopy))
+ return;
+ break;
+ } else {
+ if (uxa_fill_region_tiled(&pWin->drawable, pRegion,
+ pWin->border.pixmap,
+ &zeros, FB_ALLONES, GXcopy))
+ return;
+ break;
+ }
+ break;
+ }
+
+ uxa_check_paint_window(pWin, pRegion, what);
+}
+#endif /* !SERVER_1_5 */
/**
* Accelerates GetImage for solid ZPixmap downloads from framebuffer memory.
diff --git a/uxa/uxa-glyphs.c b/uxa/uxa-glyphs.c
index 1c06e6d..5abd001 100644
--- a/uxa/uxa-glyphs.c
+++ b/uxa/uxa-glyphs.c
@@ -50,6 +50,8 @@
#include "mipict.h"
+#ifdef SERVER_1_5
+
#if DEBUG_GLYPH_CACHE
#define DBG_GLYPH_CACHE(a) ErrorF a
#else
@@ -887,3 +889,5 @@ uxa_glyphs (CARD8 op,
(*pScreen->DestroyPixmap) (pMaskPixmap);
}
}
+
+#endif /* SERVER_1_5 */
diff --git a/uxa/uxa-priv.h b/uxa/uxa-priv.h
index bdc6e82..d1cd341 100644
--- a/uxa/uxa-priv.h
+++ b/uxa/uxa-priv.h
@@ -26,6 +26,9 @@
#ifndef UXAPRIV_H
#define UXAPRIV_H
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
#ifdef HAVE_DIX_CONFIG_H
#include <dix-config.h>
#else
@@ -126,6 +129,10 @@ typedef struct {
CloseScreenProcPtr SavedCloseScreen;
GetImageProcPtr SavedGetImage;
GetSpansProcPtr SavedGetSpans;
+#ifndef SERVER_1_5
+ PaintWindowBackgroundProcPtr SavedPaintWindowBackground;
+ PaintWindowBorderProcPtr SavedPaintWindowBorder;
+#endif
CreatePixmapProcPtr SavedCreatePixmap;
DestroyPixmapProcPtr SavedDestroyPixmap;
CopyWindowProcPtr SavedCopyWindow;
@@ -161,7 +168,16 @@ typedef struct {
#endif
extern int uxa_screen_index;
-#define uxa_get_screen(s) ((uxa_screen_t *)dixLookupPrivate(&(s)->devPrivates, &uxa_screen_index))
+static inline uxa_screen_t *
+uxa_get_screen(ScreenPtr screen)
+{
+#ifdef SERVER_1_5
+ return (uxa_screen_t *)dixLookupPrivate(&screen->devPrivates,
+ &uxa_screen_index);
+#else
+ return screen->devPrivates[uxa_screen_index].ptr;
+#endif
+}
/** Align an offset to an arbitrary alignment */
#define UXA_ALIGN(offset, align) (((offset) + (align) - 1) - \
@@ -262,6 +278,8 @@ uxa_check_get_spans (DrawablePtr pDrawable,
int nspans,
char *pdstStart);
+void uxa_check_paint_window (WindowPtr pWin, RegionPtr pRegion, int what);
+
void
uxa_check_add_traps (PicturePtr pPicture,
INT16 x_off,
@@ -292,6 +310,8 @@ uxa_shm_put_image(DrawablePtr pDrawable, GCPtr pGC, int depth, unsigned int form
int w, int h, int sx, int sy, int sw, int sh, int dx, int dy,
char *data);
+void uxa_paint_window(WindowPtr pWin, RegionPtr pRegion, int what);
+
void
uxa_get_image (DrawablePtr pDrawable, int x, int y, int w, int h,
unsigned int format, unsigned long planeMask, char *d);
diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index b377bf5..edbf0d8 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -818,8 +818,13 @@ uxa_create_alpha_picture (ScreenPtr pScreen,
return 0;
}
+#ifdef SERVER_1_5
pPixmap = (*pScreen->CreatePixmap) (pScreen, width, height,
pPictFormat->depth, 0);
+#else
+ pPixmap = (*pScreen->CreatePixmap) (pScreen, width, height,
+ pPictFormat->depth);
+#endif
if (!pPixmap)
return 0;
pGC = GetScratchGC (pPixmap->drawable.depth, pScreen);
diff --git a/uxa/uxa-unaccel.c b/uxa/uxa-unaccel.c
index 8f86468..f63c03b 100644
--- a/uxa/uxa-unaccel.c
+++ b/uxa/uxa-unaccel.c
@@ -336,6 +336,24 @@ uxa_check_get_spans (DrawablePtr pDrawable,
}
}
+#ifndef SERVER_1_5
+void
+uxa_check_paint_window (WindowPtr pWin, RegionPtr pRegion, int what)
+{
+ ScreenPtr screen = pWin->drawable.pScreen;
+
+ UXA_FALLBACK(("from %p (%c)\n", pWin,
+ uxa_drawable_location (&pWin->drawable)));
+ if (uxa_prepare_access (&pWin->drawable, UXA_ACCESS_RW)) {
+ if (uxa_prepare_access_window (pWin)) {
+ fbPaintWindow (pWin, pRegion, what);
+ uxa_finish_access_window (pWin);
+ }
+ uxa_finish_access(&pWin->drawable);
+ }
+}
+#endif
+
void
uxa_check_composite (CARD8 op,
PicturePtr pSrc,
diff --git a/uxa/uxa.c b/uxa/uxa.c
index 0de408c..b51a282 100644
--- a/uxa/uxa.c
+++ b/uxa/uxa.c
@@ -40,6 +40,9 @@
#include "uxa.h"
int uxa_screen_index;
+#ifndef SERVER_1_5
+static int uxa_generation;
+#endif
/**
* uxa_get_drawable_pixmap() returns a backing pixmap for a given drawable.
@@ -367,12 +370,18 @@ uxa_close_screen(int i, ScreenPtr pScreen)
PictureScreenPtr ps = GetPictureScreenIfSet(pScreen);
#endif
+#ifdef SERVER_1_5
uxa_glyphs_fini(pScreen);
+#endif
pScreen->CreateGC = uxa_screen->SavedCreateGC;
pScreen->CloseScreen = uxa_screen->SavedCloseScreen;
pScreen->GetImage = uxa_screen->SavedGetImage;
pScreen->GetSpans = uxa_screen->SavedGetSpans;
+#ifndef SERVER_1_5
+ pScreen->PaintWindowBackground = uxa_screen->SavedPaintWindowBackground;
+ pScreen->PaintWindowBorder = uxa_screen->SavedPaintWindowBorder;
+#endif
pScreen->CreatePixmap = uxa_screen->SavedCreatePixmap;
pScreen->DestroyPixmap = uxa_screen->SavedDestroyPixmap;
pScreen->CopyWindow = uxa_screen->SavedCopyWindow;
@@ -469,7 +478,15 @@ uxa_driver_init(ScreenPtr screen, uxa_driver_t *uxa_driver)
uxa_screen->info = uxa_driver;
+#ifdef SERVER_1_5
dixSetPrivate(&screen->devPrivates, &uxa_screen_index, uxa_screen);
+#else
+ if (uxa_generation != serverGeneration) {
+ uxa_screen_index = AllocateScreenPrivateIndex();
+ uxa_generation = serverGeneration;
+ }
+ screen->devPrivates[uxa_screen_index].ptr = uxa_screen;
+#endif
// exaDDXDriverInit(screen);
@@ -488,6 +505,14 @@ uxa_driver_init(ScreenPtr screen, uxa_driver_t *uxa_driver)
uxa_screen->SavedGetSpans = screen->GetSpans;
screen->GetSpans = uxa_check_get_spans;
+#ifndef SERVER_1_5
+ uxa_screen->SavedPaintWindowBackground = screen->PaintWindowBackground;
+ screen->PaintWindowBackground = uxa_paint_window;
+
+ uxa_screen->SavedPaintWindowBorder = screen->PaintWindowBorder;
+ screen->PaintWindowBorder = uxa_paint_window;
+#endif /* !SERVER_1_5 */
+
uxa_screen->SavedCopyWindow = screen->CopyWindow;
screen->CopyWindow = uxa_copy_window;
@@ -505,9 +530,11 @@ uxa_driver_init(ScreenPtr screen, uxa_driver_t *uxa_driver)
uxa_screen->SavedComposite = ps->Composite;
ps->Composite = uxa_composite;
+#ifdef SERVER_1_5
uxa_screen->SavedGlyphs = ps->Glyphs;
ps->Glyphs = uxa_glyphs;
-
+#endif
+
uxa_screen->SavedTriangles = ps->Triangles;
ps->Triangles = uxa_triangles;
@@ -527,7 +554,9 @@ uxa_driver_init(ScreenPtr screen, uxa_driver_t *uxa_driver)
ShmRegisterFuncs(screen, &uxa_shm_funcs);
#endif
+#ifdef SERVER_1_5
uxa_glyphs_init(screen);
+#endif
LogMessage(X_INFO, "UXA(%d): Driver registered support for the following"
" operations:\n", screen->myNum);
commit cb1f7ec0876746c1b52b63cdb508544e9e4e32e3
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 24 21:23:59 2009 -0800
uxa: Fix composite fallback debug printing of main memory versus bo info.
It was just printing whether it was a pixmap (it is), instead of whether the
pixmap was offscreen.
diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index 60022cc..b377bf5 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -69,7 +69,7 @@ static void uxa_composite_fallback_pict_desc(PicturePtr pict, char *string, int
break;
}
- loc = uxa_get_drawable_pixmap(pict->pDrawable) ? 's' : 'm';
+ loc = uxa_drawable_is_offscreen(pict->pDrawable) ? 's' : 'm';
snprintf(size, 20, "%dx%d%s", pict->pDrawable->width,
pict->pDrawable->height, pict->repeat ?
commit 635eaa511f28fb673fe306e46ed5370e78a8a534
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 24 21:48:11 2009 -0800
Regard the screen pixmap as suitable for acceleration.
With UXA on the fake bufmgr, the screen pixmap doesn't have a BO and so
no acceleration was occurring.
diff --git a/src/i830_exa.c b/src/i830_exa.c
index d691f3d..20e7a13 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -893,6 +893,12 @@ i830_uxa_block_handler (ScreenPtr screen)
static Bool
i830_uxa_pixmap_is_offscreen(PixmapPtr pixmap)
{
+ ScreenPtr screen = pixmap->drawable.pScreen;
+
+ /* The front buffer is always in memory and pinned */
+ if (screen->GetScreenPixmap(screen) == pixmap)
+ return TRUE;
+
return i830_get_pixmap_bo (pixmap) != NULL;
}
commit 70e0261208654c6c875ad462da2734c6aa9eeb96
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 24 20:54:05 2009 -0800
Disable fb resizing for DRI1-only server so that DRI1 can initialize.
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2461e8a..1506ea7 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1684,6 +1684,10 @@ I830AccelMethodInit(ScrnInfoPtr pScrn)
pI830->can_resize = FALSE;
if (pI830->accel == ACCEL_UXA && pI830->directRenderingType != DRI_XF86DRI)
pI830->can_resize = TRUE;
+#if !defined(DRI2) && defined(XF86DRI)
+ /* Disable resizing so that DRI1 can initialize and give us GEM support. */
+ pI830->can_resize = FALSE;
+#endif
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Resizable framebuffer: %s (%d %d)\n",
commit d7aa330db31100b7cb54d8165f9a4b94329ece32
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 24 20:34:10 2009 -0800
Fix up i915 composite and common solid/copy code to use check_aperture.
This could fix complaints about binding BOs and resulting failure to render.
diff --git a/src/i830.h b/src/i830.h
index eb686ae..3f10892 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -87,6 +87,8 @@ unsigned long long I830TexOffsetStart(PixmapPtr pPix);
Bool i830_uxa_init(ScreenPtr pScreen);
void i830_uxa_create_screen_resources(ScreenPtr pScreen);
void i830_uxa_block_handler (ScreenPtr pScreen);
+Bool i830_get_aperture_space(ScrnInfoPtr pScrn, drm_intel_bo **bo_table,
+ int num_bos);
#endif
#if defined(I830_USE_UXA) || defined(I830_USE_EXA)
diff --git a/src/i830_exa.c b/src/i830_exa.c
index b878402..d691f3d 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -121,6 +121,21 @@ i830_pixmap_tiled(PixmapPtr pPixmap)
return FALSE;
}
+Bool
+i830_get_aperture_space(ScrnInfoPtr pScrn, drm_intel_bo **bo_table, int num_bos)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ bo_table[0] = pI830->batch_bo;
+ if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) {
+ intel_batch_flush(pScrn, FALSE);
+ bo_table[0] = pI830->batch_bo;
+ if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0)
+ I830FALLBACK("Couldn't get aperture space for BOs\n");
+ }
+ return TRUE;
+}
+
static unsigned long
i830_pixmap_pitch(PixmapPtr pixmap)
{
@@ -178,6 +193,10 @@ I830EXAPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
unsigned long pitch;
+ drm_intel_bo *bo_table[] = {
+ NULL, /* batch_bo */
+ i830_get_pixmap_bo(pPixmap),
+ };
if (!EXA_PM_IS_SOLID(&pPixmap->drawable, planemask))
I830FALLBACK("planemask is not solid");
@@ -195,6 +214,9 @@ I830EXAPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
if (!i830_pixmap_pitch_is_aligned(pPixmap))
I830FALLBACK("pixmap pitch not aligned");
+ if (!i830_get_aperture_space(pScrn, bo_table, ARRAY_SIZE(bo_table)))
+ return FALSE;
+
pI830->BR[13] = (I830PatternROP[alu] & 0xff) << 16 ;
switch (pPixmap->drawable.bitsPerPixel) {
case 8:
@@ -272,6 +294,11 @@ I830EXAPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
{
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
+ drm_intel_bo *bo_table[] = {
+ NULL, /* batch_bo */
+ i830_get_pixmap_bo(pSrcPixmap),
+ i830_get_pixmap_bo(pDstPixmap),
+ };
if (!EXA_PM_IS_SOLID(&pSrcPixmap->drawable, planemask))
I830FALLBACK("planemask is not solid");
@@ -279,6 +306,9 @@ I830EXAPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
if (pDstPixmap->drawable.bitsPerPixel < 8)
I830FALLBACK("under 8bpp pixmaps unsupported\n");
+ if (!i830_get_aperture_space(pScrn, bo_table, ARRAY_SIZE(bo_table)))
+ return FALSE;
+
i830_exa_check_pitch_2d(pSrcPixmap);
i830_exa_check_pitch_2d(pDstPixmap);
diff --git a/src/i915_render.c b/src/i915_render.c
index 5dd97e6..4190808 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -315,6 +315,12 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
{
ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
+ drm_intel_bo *bo_table[] = {
+ NULL, /* batch_bo */
+ i830_get_pixmap_bo(pSrc),
+ pMask ? i830_get_pixmap_bo(pMask) : NULL,
+ i830_get_pixmap_bo(pDst),
+ };
i830_exa_check_pitch_3d(pSrc);
if (pMask)
@@ -325,6 +331,9 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
&pI830->i915_render_state.dst_format))
return FALSE;
+ if (!i830_get_aperture_space(pScrn, bo_table, ARRAY_SIZE(bo_table)))
+ return FALSE;
+
pI830->i915_render_state.is_nearest = FALSE;
if (!i915_texture_setup(pSrcPicture, pSrc, 0))
I830FALLBACK("fail to setup src texture\n");
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