xf86-video-intel: src/sna/gen5_render.c src/sna/gen5_render.h src/sna/sna_gradient.c
Chris Wilson
ickle at kemper.freedesktop.org
Mon Sep 12 12:12:01 PDT 2011
src/sna/gen5_render.c | 36 +++++++++++++++++++++++-------------
src/sna/gen5_render.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++
src/sna/sna_gradient.c | 6 ++++++
3 files changed, 76 insertions(+), 13 deletions(-)
New commits:
commit 6b1ed58d63e9ac80d7d028fa3036633436154816
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Sep 12 19:07:25 2011 +0100
sna/gen5: Avoid bitfields for simple assignments
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index f60c081..d5863b1 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -645,6 +645,17 @@ static bool gen5_check_repeat(PicturePtr picture)
}
}
+static uint32_t
+gen5_tiling_bits(uint32_t tiling)
+{
+ switch (tiling) {
+ default: assert(0);
+ case I915_TILING_NONE: return 0;
+ case I915_TILING_X: return GEN5_SURFACE_TILED;
+ case I915_TILING_Y: return GEN5_SURFACE_TILED | GEN5_SURFACE_TILED_Y;
+ }
+}
+
/**
* Sets up the common fields for a surface state buffer for the given
* picture in the given surface state buffer.
@@ -657,9 +668,9 @@ gen5_bind_bo(struct sna *sna,
uint32_t format,
Bool is_dst)
{
- struct gen5_surface_state *ss;
uint32_t domains;
uint16_t offset;
+ uint32_t *ss;
/* After the first bind, we manage the cache domains within the batch */
if (is_dst) {
@@ -687,23 +698,22 @@ gen5_bind_bo(struct sna *sna,
sna->kgem.surface -=
sizeof(struct gen5_surface_state_padded) / sizeof(uint32_t);
- ss = memset(sna->kgem.batch + sna->kgem.surface, 0, sizeof(*ss));
+ ss = sna->kgem.batch + sna->kgem.surface;
- ss->ss0.surface_type = GEN5_SURFACE_2D;
- ss->ss0.surface_format = format;
+ ss[0] = (GEN5_SURFACE_2D << GEN5_SURFACE_TYPE_SHIFT |
+ GEN5_SURFACE_BLEND_ENABLED |
+ format << GEN5_SURFACE_FORMAT_SHIFT);
- ss->ss0.data_return_format = GEN5_SURFACERETURNFORMAT_FLOAT32;
- ss->ss0.color_blend = 1;
- ss->ss1.base_addr =
- kgem_add_reloc(&sna->kgem,
+ ss[1] = kgem_add_reloc(&sna->kgem,
sna->kgem.surface + 1,
bo, domains, 0);
- ss->ss2.height = height - 1;
- ss->ss2.width = width - 1;
- ss->ss3.pitch = bo->pitch - 1;
- ss->ss3.tile_walk = bo->tiling == I915_TILING_Y;
- ss->ss3.tiled_surface = bo->tiling != I915_TILING_NONE;
+ ss[2] = ((width - 1) << GEN5_SURFACE_WIDTH_SHIFT |
+ (height - 1) << GEN5_SURFACE_HEIGHT_SHIFT);
+ ss[3] = (gen5_tiling_bits(bo->tiling) |
+ (bo->pitch - 1) << GEN5_SURFACE_PITCH_SHIFT);
+ ss[4] = 0;
+ ss[5] = 0;
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss->ss1.base_addr,
diff --git a/src/sna/gen5_render.h b/src/sna/gen5_render.h
index 190580e..880a4c0 100644
--- a/src/sna/gen5_render.h
+++ b/src/sna/gen5_render.h
@@ -2131,7 +2131,54 @@ struct gen5_surface_state
} ss5;
};
+/* Surface state DW0 */
+#define GEN5_SURFACE_RC_READ_WRITE (1 << 8)
+#define GEN5_SURFACE_MIPLAYOUT_SHIFT 10
+#define GEN5_SURFACE_MIPMAPLAYOUT_BELOW 0
+#define GEN5_SURFACE_MIPMAPLAYOUT_RIGHT 1
+#define GEN5_SURFACE_CUBEFACE_ENABLES 0x3f
+#define GEN5_SURFACE_BLEND_ENABLED (1 << 13)
+#define GEN5_SURFACE_WRITEDISABLE_B_SHIFT 14
+#define GEN5_SURFACE_WRITEDISABLE_G_SHIFT 15
+#define GEN5_SURFACE_WRITEDISABLE_R_SHIFT 16
+#define GEN5_SURFACE_WRITEDISABLE_A_SHIFT 17
+#define GEN5_SURFACE_FORMAT_SHIFT 18
+#define GEN5_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
+
+#define GEN5_SURFACE_TYPE_SHIFT 29
+#define GEN5_SURFACE_TYPE_MASK GEN5_MASK(31, 29)
+#define GEN5_SURFACE_1D 0
+#define GEN5_SURFACE_2D 1
+#define GEN5_SURFACE_3D 2
+#define GEN5_SURFACE_CUBE 3
+#define GEN5_SURFACE_BUFFER 4
+#define GEN5_SURFACE_NULL 7
+/* Surface state DW2 */
+#define GEN5_SURFACE_HEIGHT_SHIFT 19
+#define GEN5_SURFACE_HEIGHT_MASK GEN5_MASK(31, 19)
+#define GEN5_SURFACE_WIDTH_SHIFT 6
+#define GEN5_SURFACE_WIDTH_MASK GEN5_MASK(18, 6)
+#define GEN5_SURFACE_LOD_SHIFT 2
+#define GEN5_SURFACE_LOD_MASK GEN5_MASK(5, 2)
+
+/* Surface state DW3 */
+#define GEN5_SURFACE_DEPTH_SHIFT 21
+#define GEN5_SURFACE_DEPTH_MASK GEN5_MASK(31, 21)
+#define GEN5_SURFACE_PITCH_SHIFT 3
+#define GEN5_SURFACE_PITCH_MASK GEN5_MASK(19, 3)
+#define GEN5_SURFACE_TILED (1 << 1)
+#define GEN5_SURFACE_TILED_Y (1 << 0)
+
+/* Surface state DW4 */
+#define GEN5_SURFACE_MIN_LOD_SHIFT 28
+#define GEN5_SURFACE_MIN_LOD_MASK GEN5_MASK(31, 28)
+
+/* Surface state DW5 */
+#define GEN5_SURFACE_X_OFFSET_SHIFT 25
+#define GEN5_SURFACE_X_OFFSET_MASK GEN5_MASK(31, 25)
+#define GEN5_SURFACE_Y_OFFSET_SHIFT 20
+#define GEN5_SURFACE_Y_OFFSET_MASK GEN5_MASK(23, 20)
struct gen5_vertex_buffer_state
{
diff --git a/src/sna/sna_gradient.c b/src/sna/sna_gradient.c
index 20850c8..a76f16e 100644
--- a/src/sna/sna_gradient.c
+++ b/src/sna/sna_gradient.c
@@ -335,11 +335,17 @@ static Bool sna_solid_cache_init(struct sna *sna)
if (!cache->cache_bo)
return FALSE;
+ /*
+ * Initialise [0] with white since it is very common and filling the
+ * zeroth slot simplifies some of the checks.
+ */
cache->color[0] = 0xffffffff;
cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t));
cache->bo[0]->pitch = 4;
+ cache->dirty = 1;
cache->size = 1;
cache->last = 0;
+
return TRUE;
}
More information about the xorg-commit
mailing list