xf86-video-intel: 2 commits - src/sna/gen6_render.c

[Chris Wilson]

 src/sna/gen6_render.c |   44 ++++++++++++++++++++------------------------
 1 file changed, 20 insertions(+), 24 deletions(-)

New commits:
commit a0c4024e32ccab70e7f7893896d30c80ad9f4240
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Fri Jan 20 09:42:18 2012 +0000

    sna/gen6: Do not enable blending on video sources
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index f39840c..cf747db 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -1832,7 +1832,6 @@ static uint32_t gen6_bind_video_source(struct sna *sna,
 	ss = memset(sna->kgem.batch + sna->kgem.surface, 0, sizeof(*ss));
 	ss->ss0.surface_type = GEN6_SURFACE_2D;
 	ss->ss0.surface_format = src_surf_format;
-	ss->ss0.color_blend = 1;
 
 	ss->ss1.base_addr =
 		kgem_add_reloc(&sna->kgem,
commit bbbda4c408c2576927582097f7cd4f606b1761fa
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Fri Jan 20 09:40:04 2012 +0000

    sna/gen6: Reduce the sampler stall if already stalling for drawrect
    
    If we are force to emit a stall for the non-pipelined workaround, we do
    not then need to emit a stall for switching samplers.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index edb6423..f39840c 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -716,17 +716,13 @@ gen6_emit_drawing_rectangle(struct sna *sna,
 	uint32_t limit = (op->dst.height - 1) << 16 | (op->dst.width - 1);
 	uint32_t offset = (uint16_t)op->dst.y << 16 | (uint16_t)op->dst.x;
 
-	if (sna->render_state.gen6.drawrect_limit == limit &&
-	    sna->render_state.gen6.drawrect_offset == offset)
-		return;
-
-	sna->render_state.gen6.drawrect_offset = offset;
-	sna->render_state.gen6.drawrect_limit = limit;
-
 	OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
 	OUT_BATCH(0);
 	OUT_BATCH(limit);
 	OUT_BATCH(offset);
+
+	sna->render_state.gen6.drawrect_offset = offset;
+	sna->render_state.gen6.drawrect_limit = limit;
 }
 
 static void
@@ -825,6 +821,20 @@ gen6_emit_state(struct sna *sna,
 {
 	bool need_stall;
 
+	gen6_emit_cc(sna, op->op, op->has_component_alpha, op->dst.format);
+	gen6_emit_sampler(sna,
+			  SAMPLER_OFFSET(op->src.filter,
+					 op->src.repeat,
+					 op->mask.filter,
+					 op->mask.repeat));
+	gen6_emit_sf(sna, op->mask.bo != NULL);
+	gen6_emit_wm(sna,
+		     op->u.gen6.wm_kernel,
+		     op->u.gen6.nr_surfaces,
+		     op->u.gen6.nr_inputs);
+	gen6_emit_vertex_elements(sna, op);
+	need_stall = gen6_emit_binding_table(sna, wm_binding_table);
+
 	/* [DevSNB-C+{W/A}] Before any depth stall flush (including those
 	 * produced by non-pipelined state commands), software needs to first
 	 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
@@ -849,23 +859,10 @@ gen6_emit_state(struct sna *sna,
 					 I915_GEM_DOMAIN_INSTRUCTION,
 					 64));
 		OUT_BATCH(0);
-	}
-
-	gen6_emit_cc(sna, op->op, op->has_component_alpha, op->dst.format);
-	gen6_emit_sampler(sna,
-			  SAMPLER_OFFSET(op->src.filter,
-					 op->src.repeat,
-					 op->mask.filter,
-					 op->mask.repeat));
-	gen6_emit_sf(sna, op->mask.bo != NULL);
-	gen6_emit_wm(sna,
-		     op->u.gen6.wm_kernel,
-		     op->u.gen6.nr_surfaces,
-		     op->u.gen6.nr_inputs);
-	gen6_emit_vertex_elements(sna, op);
-	need_stall = gen6_emit_binding_table(sna, wm_binding_table);
-	gen6_emit_drawing_rectangle(sna, op);
 
+		gen6_emit_drawing_rectangle(sna, op);
+		need_stall = false;
+	}
 	if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
 		gen6_emit_flush(sna);
 		kgem_clear_dirty(&sna->kgem);