xf86-video-intel: src/sna/gen5_render.c

[Chris Wilson]

 src/sna/gen5_render.c |   17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

New commits:
commit fb5205a86da09b344dbc20598655e917c263125c
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Mon Oct 8 09:12:33 2012 +0100

    sna/gen5: Flush pipelined ops when changing state
    
    When is a pipelined operation, not pipelined? That is the mystery posed
    by our hardware!
    
    Reported-by: Clemens Eisserer <linuxhippy at gmail.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51422
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index afd729e..5d55937 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -1215,12 +1215,12 @@ gen5_align_vertex(struct sna *sna, const struct sna_composite_op *op)
 	}
 }
 
-static void
+static bool
 gen5_emit_binding_table(struct sna *sna, uint16_t offset)
 {
 	if (!DBG_NO_STATE_CACHE &&
 	    sna->render_state.gen5.surface_table == offset)
-		return;
+		return false;
 
 	sna->render_state.gen5.surface_table = offset;
 
@@ -1232,6 +1232,8 @@ gen5_emit_binding_table(struct sna *sna, uint16_t offset)
 	OUT_BATCH(0);		/* sf */
 	/* Only the PS uses the binding table */
 	OUT_BATCH(offset*4);
+
+	return true;
 }
 
 static bool
@@ -1281,6 +1283,7 @@ gen5_emit_drawing_rectangle(struct sna *sna, const struct sna_composite_op *op)
 	    sna->render_state.gen5.drawrect_limit == limit &&
 	    sna->render_state.gen5.drawrect_offset == offset)
 		return;
+
 	sna->render_state.gen5.drawrect_offset = offset;
 	sna->render_state.gen5.drawrect_limit = limit;
 
@@ -1377,15 +1380,19 @@ gen5_emit_state(struct sna *sna,
 		const struct sna_composite_op *op,
 		uint16_t offset)
 {
+	bool flush;
+
 	/* drawrect must be first for Ironlake BLT workaround */
 	gen5_emit_drawing_rectangle(sna, op);
 
-	gen5_emit_binding_table(sna, offset);
-	if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel))
+	flush = gen5_emit_binding_table(sna, offset);
+	if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel)) {
 		gen5_emit_urb(sna);
+		flush = true;
+	}
 	gen5_emit_vertex_elements(sna, op);
 
-	if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
+	if (flush || kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
 		OUT_BATCH(MI_FLUSH);
 		kgem_clear_dirty(&sna->kgem);
 		kgem_bo_mark_dirty(op->dst.bo);