xf86-video-intel: src/sna/gen5_render.c

[Chris Wilson]

 src/sna/gen5_render.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

New commits:
commit 97fc1d4c5bd268f331aaa9f7144e4fe40837fbb0
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Fri Apr 12 10:23:43 2013 +0100

    sna/gen5: Force a MI_FLUSH between using the BLT and RENDER engines
    
    There is a workaround that says the first RENDER command following use of
    the BLT should be a non-pipelined command. To be safe, emit a MI_FLUSH
    before setting up the invariants.
    
    Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1168066
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index 7038444..b960ed6 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -756,8 +756,13 @@ gen5_emit_invariant(struct sna *sna)
 	 *
 	 * However, the kernel flushes the pipeline between batches,
 	 * so we should be safe....
-	 * OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
+	 *
+	 * On the other hand, after using BLT we must use a non-pipelined
+	 * operation...
 	 */
+	if (sna->kgem.nreloc)
+		OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
+
 	OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
 	gen5_emit_state_base_address(sna);