xf86-video-intel: 6 commits - src/sna/gen3_render.c src/sna/gen4_render.c src/sna/gen5_render.c src/sna/gen6_render.c src/sna/gen7_render.c src/sna/sna_accel.c src/sna/sna_composite.c src/sna/sna.h src/sna/sna_render.c

Chris Wilson ickle at kemper.freedesktop.org
Tue Jan 29 16:20:16 PST 2013


 src/sna/gen3_render.c   |    4 +--
 src/sna/gen4_render.c   |    4 +--
 src/sna/gen5_render.c   |    4 +--
 src/sna/gen6_render.c   |    4 +--
 src/sna/gen7_render.c   |   27 +++++++++++++++++++++++--
 src/sna/sna.h           |    3 ++
 src/sna/sna_accel.c     |   51 ++++++++++++++++++++----------------------------
 src/sna/sna_composite.c |    2 +
 src/sna/sna_render.c    |   29 +++++++++++++++++++--------
 9 files changed, 81 insertions(+), 47 deletions(-)

New commits:
commit 3fdd28419adee7145d3925cff2704143a324e9d3
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 29 22:26:15 2013 +0000

    sna: Only migrate the sample box if using the BLT engine for a composite
    
    Modify the presumption that if we are using a core operation on a shadow
    pixmap, then we are likely to continue migrating that pixmap back and
    forth.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna.h b/src/sna/sna.h
index 84d9807..e407359 100644
--- a/src/sna/sna.h
+++ b/src/sna/sna.h
@@ -434,6 +434,9 @@ void sna_pixmap_destroy(PixmapPtr pixmap);
 #define __MOVE_FORCE 0x40
 #define __MOVE_DRI 0x80
 
+bool
+sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int flags);
+
 struct sna_pixmap *sna_pixmap_move_to_gpu(PixmapPtr pixmap, unsigned flags);
 static inline struct sna_pixmap *
 sna_pixmap_force_to_gpu(PixmapPtr pixmap, unsigned flags)
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index bdaac89..7525c4f 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -2379,7 +2379,7 @@ sna_pixmap_mark_active(struct sna *sna, struct sna_pixmap *priv)
 	return priv;
 }
 
-static bool
+bool
 sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int flags)
 {
 	struct sna *sna = to_sna_from_pixmap(pixmap);
diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index fb55557..8f4f268 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -477,9 +477,15 @@ move_to_gpu(PixmapPtr pixmap, const BoxRec *box, bool blt)
 		migrate = count*w*h > pixmap->drawable.width * pixmap->drawable.height;
 	}
 
-	if (migrate && !sna_pixmap_force_to_gpu(pixmap,
-						blt ? MOVE_READ : MOVE_SOURCE_HINT | MOVE_READ))
-		return NULL;
+	if (migrate) {
+		if (blt) {
+			if (!sna_pixmap_move_area_to_gpu(pixmap, box, MOVE_READ))
+				return NULL;
+		} else {
+			if (!sna_pixmap_force_to_gpu(pixmap, MOVE_SOURCE_HINT | MOVE_READ))
+				return NULL;
+		}
+	}
 
 	return priv->gpu_bo;
 }
commit 0c3b0f11d718d915e502582e9fadd5c0577640db
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 29 22:24:30 2013 +0000

    sna: Verify that we always add the SHM CPU bo to the flush list when using
    
    As we need to synchronize that bo before the next reply, we need to keep
    track of it whenever it is active on the GPU.
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 2fef817..bdaac89 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -1263,9 +1263,10 @@ void sna_add_flush_pixmap(struct sna *sna,
 	DBG(("%s: marking pixmap=%ld for flushing\n",
 	     __FUNCTION__, priv->pixmap->drawable.serialNumber));
 	assert(bo);
+	assert(bo->flush);
 	list_move(&priv->list, &sna->flush_pixmaps);
 
-	if (bo->exec == NULL) {
+	if (bo->exec == NULL && kgem_is_idle(&sna->kgem)) {
 		DBG(("%s: new flush bo, flushin before\n", __FUNCTION__));
 		kgem_submit(&sna->kgem);
 	}
@@ -1743,6 +1744,7 @@ done:
 			DBG(("%s: syncing CPU bo\n", __FUNCTION__));
 			kgem_bo_sync__cpu_full(&sna->kgem,
 					       priv->cpu_bo, flags & MOVE_WRITE);
+			assert(!priv->shm || !kgem_bo_is_busy(priv->cpu_bo));
 		}
 		if (flags & MOVE_WRITE) {
 			DBG(("%s: discarding GPU bo in favour of CPU bo\n", __FUNCTION__));
@@ -2440,6 +2442,11 @@ sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int fl
 		priv->mapped = false;
 	}
 
+	if (priv->shm) {
+		assert(!priv->flush);
+		sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
+	}
+
 	region_set(&r, box);
 	if (MIGRATE_ALL || region_subsumes_damage(&r, priv->cpu_damage)) {
 		int n;
@@ -2454,10 +2461,6 @@ sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int fl
 							    pixmap, priv->cpu_bo, 0, 0,
 							    pixmap, priv->gpu_bo, 0, 0,
 							    box, n, 0);
-				if (ok && priv->shm) {
-					assert(!priv->flush);
-					sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-				}
 			}
 			if (!ok) {
 				if (pixmap->devPrivate.ptr == NULL) {
@@ -2498,10 +2501,6 @@ sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int fl
 						    pixmap, priv->cpu_bo, 0, 0,
 						    pixmap, priv->gpu_bo, 0, 0,
 						    box, 1, 0);
-			if (ok && priv->shm) {
-				assert(!priv->flush);
-				sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-			}
 		}
 		if (!ok) {
 			if (pixmap->devPrivate.ptr == NULL) {
@@ -2533,10 +2532,6 @@ sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int fl
 						    pixmap, priv->cpu_bo, 0, 0,
 						    pixmap, priv->gpu_bo, 0, 0,
 						    box, n, 0);
-			if (ok && priv->shm) {
-				assert(!priv->flush);
-				sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-			}
 		}
 		if (!ok) {
 			if (pixmap->devPrivate.ptr == NULL) {
@@ -2559,11 +2554,6 @@ sna_pixmap_move_area_to_gpu(PixmapPtr pixmap, const BoxRec *box, unsigned int fl
 		RegionUninit(&i);
 	}
 
-	if (priv->shm) {
-		assert(!priv->flush);
-		sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-	}
-
 done:
 	if (flags & MOVE_WRITE) {
 		priv->clear = false;
@@ -3116,6 +3106,11 @@ sna_pixmap_move_to_gpu(PixmapPtr pixmap, unsigned flags)
 		priv->mapped = false;
 	}
 
+	if (priv->shm) {
+		assert(!priv->flush);
+		sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
+	}
+
 	n = sna_damage_get_boxes(priv->cpu_damage, &box);
 	if (n) {
 		bool ok;
@@ -3161,11 +3156,6 @@ sna_pixmap_move_to_gpu(PixmapPtr pixmap, unsigned flags)
 	__sna_damage_destroy(DAMAGE_PTR(priv->cpu_damage));
 	priv->cpu_damage = NULL;
 
-	if (priv->shm) {
-		assert(!priv->flush);
-		sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-	}
-
 	/* For large bo, try to keep only a single copy around */
 	if (priv->create & KGEM_CAN_CREATE_LARGE ||
 	    flags & MOVE_SOURCE_HINT) {
@@ -4328,6 +4318,11 @@ sna_copy_boxes(DrawablePtr src, DrawablePtr dst, GCPtr gc,
 			if (!ret)
 				goto fallback;
 
+			if (src_priv->shm) {
+				assert(!src_priv->flush);
+				sna_add_flush_pixmap(sna, src_priv, src_priv->cpu_bo);
+			}
+
 			if (!sna->render.copy_boxes(sna, alu,
 						    src_pixmap, src_priv->cpu_bo, src_dx, src_dy,
 						    dst_pixmap, bo, 0, 0,
@@ -4337,11 +4332,6 @@ sna_copy_boxes(DrawablePtr src, DrawablePtr dst, GCPtr gc,
 				goto fallback;
 			}
 
-			if (src_priv->shm) {
-				assert(!src_priv->flush);
-				sna_add_flush_pixmap(sna, src_priv, src_priv->cpu_bo);
-			}
-
 			if (damage)
 				sna_damage_add(damage, region);
 			return;
diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index 82be297..fb55557 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -594,6 +594,10 @@ sna_render_pixmap_bo(struct sna *sna,
 		    !priv->cpu_bo->snoop && priv->cpu_bo->pitch < 4096) {
 			DBG(("%s: CPU all damaged\n", __FUNCTION__));
 			channel->bo = priv->cpu_bo;
+			if (priv->shm) {
+				assert(!priv->flush);
+				sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
+			}
 			goto done;
 		}
 	}
commit f743cd5734ca502aa8bdb0e1327fe84d6ce82755
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 29 18:04:40 2013 +0000

    sna: Avoid promoting SHM CPU bo to GPU to maintain coherence with SHM clients
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index 4b32b82..82be297 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -322,6 +322,14 @@ use_cpu_bo(struct sna *sna, PixmapPtr pixmap, const BoxRec *box, bool blt)
 		return NULL;
 	}
 
+	if (priv->shm) {
+		DBG(("%s: shm CPU bo, avoiding promotion to GPU\n",
+		     __FUNCTION__));
+		assert(!priv->flush);
+		sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
+		return priv->cpu_bo;
+	}
+
 	if (priv->cpu_bo->snoop && priv->source_count > SOURCE_BIAS) {
 		DBG(("%s: promoting snooped CPU bo due to reuse\n",
 		     __FUNCTION__));
@@ -385,11 +393,6 @@ use_cpu_bo(struct sna *sna, PixmapPtr pixmap, const BoxRec *box, bool blt)
 		}
 	}
 
-	if (priv->shm) {
-		assert(!priv->flush);
-		sna_add_flush_pixmap(sna, priv, priv->cpu_bo);
-	}
-
 	DBG(("%s for box=(%d, %d), (%d, %d)\n",
 	     __FUNCTION__, box->x1, box->y1, box->x2, box->y2));
 	++priv->source_count;
commit 9383c5efe9ace34970abddc5e3c84c32505b537f
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 29 17:24:24 2013 +0000

    sna/gen3+: Fix a DBG for composite_boxes()
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen3_render.c b/src/sna/gen3_render.c
index 3eb2966..06c4e78 100644
--- a/src/sna/gen3_render.c
+++ b/src/sna/gen3_render.c
@@ -2097,7 +2097,7 @@ gen3_render_composite_boxes(struct sna *sna,
 			    const struct sna_composite_op *op,
 			    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	do {
 		int nbox_this_time;
@@ -2120,7 +2120,7 @@ gen3_render_composite_boxes__thread(struct sna *sna,
 				    const struct sna_composite_op *op,
 				    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	sna_vertex_lock(&sna->render);
 	do {
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index 249d626..829f4e9 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -1150,7 +1150,7 @@ gen4_render_composite_boxes(struct sna *sna,
 			    const struct sna_composite_op *op,
 			    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	do {
 		int nbox_this_time;
@@ -1174,7 +1174,7 @@ gen4_render_composite_boxes__thread(struct sna *sna,
 				    const struct sna_composite_op *op,
 				    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	sna_vertex_lock(&sna->render);
 	do {
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index e4649c4..07e9571 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -1136,7 +1136,7 @@ gen5_render_composite_boxes(struct sna *sna,
 			    const struct sna_composite_op *op,
 			    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	do {
 		int nbox_this_time;
@@ -1160,7 +1160,7 @@ gen5_render_composite_boxes__thread(struct sna *sna,
 				    const struct sna_composite_op *op,
 				    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	sna_vertex_lock(&sna->render);
 	do {
diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index bb35e10..a9d8111 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -1377,7 +1377,7 @@ gen6_render_composite_boxes(struct sna *sna,
 			    const struct sna_composite_op *op,
 			    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	do {
 		int nbox_this_time;
@@ -1401,7 +1401,7 @@ gen6_render_composite_boxes__thread(struct sna *sna,
 				    const struct sna_composite_op *op,
 				    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	sna_vertex_lock(&sna->render);
 	do {
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index 0f39fae..dc704dd 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -1518,7 +1518,7 @@ gen7_render_composite_boxes(struct sna *sna,
 			    const struct sna_composite_op *op,
 			    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	do {
 		int nbox_this_time;
@@ -1542,7 +1542,7 @@ gen7_render_composite_boxes__thread(struct sna *sna,
 				    const struct sna_composite_op *op,
 				    const BoxRec *box, int nbox)
 {
-	DBG(("%s: nbox=%d\n", nbox));
+	DBG(("%s: nbox=%d\n", __FUNCTION__, nbox));
 
 	sna_vertex_lock(&sna->render);
 	do {
commit b02a1ea5573b6f0b58a037dd4788c04c296f7ff3
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Jan 29 09:28:33 2013 +0000

    sna: Add GT1/GT2 thread counts for Haswell
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index a3ec26e..0f39fae 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -115,6 +115,24 @@ static const struct gt_info hsw_gt_info = {
 	.urb = { 128, 64, 64 },
 };
 
+static const struct gt_info hsw_gt1_info = {
+	.max_vs_threads = 70,
+	.max_gs_threads = 70,
+	.max_wm_threads =
+		(102 - 1) << HSW_PS_MAX_THREADS_SHIFT |
+		1 << HSW_PS_SAMPLE_MASK_SHIFT,
+	.urb = { 128, 640, 256 },
+};
+
+static const struct gt_info hsw_gt2_info = {
+	.max_vs_threads = 280,
+	.max_gs_threads = 280,
+	.max_wm_threads =
+		(204 - 1) << HSW_PS_MAX_THREADS_SHIFT |
+		1 << HSW_PS_SAMPLE_MASK_SHIFT,
+	.urb = { 256, 1664, 640 },
+};
+
 static const uint32_t ps_kernel_packed[][4] = {
 #include "exa_wm_src_affine.g7b"
 #include "exa_wm_src_sample_argb.g7b"
@@ -3646,6 +3664,11 @@ static bool gen7_render_setup(struct sna *sna)
 		}
 	} else if (sna->kgem.gen == 075) {
 		state->info = &hsw_gt_info;
+		if (DEVICE_ID(sna->PciInfo) & 0xf) {
+			state->info = &hsw_gt1_info;
+			if (DEVICE_ID(sna->PciInfo) & 0x20)
+				state->info = &hsw_gt2_info;
+		}
 	} else
 		return false;
 
commit 1dc2d9ede5c7f330ebadf85d987559c8a6cb1c6b
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Mon Jan 28 23:14:57 2013 +0000

    sna: Add some more paranoia that we correctly map before fallbacks
    
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 2bb6d90..2fef817 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -1653,6 +1653,7 @@ skip_inplace_map:
 	    !sna_pixmap_alloc_cpu(sna, pixmap, priv,
 				  flags & MOVE_READ ? priv->gpu_damage && !priv->clear : 0))
 		return false;
+	assert(pixmap->devPrivate.ptr);
 
 	if (priv->clear) {
 		DBG(("%s: applying clear [%08x]\n",
@@ -1994,6 +1995,7 @@ sna_drawable_move_region_to_cpu(DrawablePtr drawable,
 			RegionTranslate(region, -dx, -dy);
 		return false;
 	}
+	assert(pixmap->devPrivate.ptr);
 
 	if (priv->gpu_bo == NULL) {
 		assert(priv->gpu_damage == NULL);
@@ -4524,6 +4526,7 @@ fallback:
 				return;
 		}
 
+		assert(dst_pixmap->devPrivate.ptr);
 		do {
 			pixman_fill(dst_pixmap->devPrivate.ptr,
 				    dst_pixmap->devKind/sizeof(uint32_t),
diff --git a/src/sna/sna_composite.c b/src/sna/sna_composite.c
index 1a2adc8..e82d5f4 100644
--- a/src/sna/sna_composite.c
+++ b/src/sna/sna_composite.c
@@ -996,6 +996,8 @@ fallback:
 	    !sna_drawable_move_to_cpu(dst->alphaMap->pDrawable, error))
 		goto done;
 
+	assert(pixmap->devPrivate.ptr);
+
 	if (op <= PictOpSrc) {
 		int nbox = REGION_NUM_RECTS(&region);
 		BoxPtr box = REGION_RECTS(&region);


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