xf86-video-intel: 4 commits - src/intel_driver.h src/intel_module.c src/sna/gen4_render.c
Chris Wilson
ickle at kemper.freedesktop.org
Tue May 14 01:37:09 PDT 2013
src/intel_driver.h | 60 ++++++++++++++++-----------
src/intel_module.c | 109 +++++++++++++++++++++++++++++++++-----------------
src/sna/gen4_render.c | 10 ++--
3 files changed, 114 insertions(+), 65 deletions(-)
New commits:
commit 3ee42de066e4629f78e254c27d07dc33e16dbc02
Author: Rodrigo Vivi <rodrigo.vivi at gmail.com>
Date: Mon May 13 17:56:30 2013 -0300
Adding more reserved PCI IDs for Haswell.
As Chris mentioned there is a tendency for us to find out more
PCI IDs only when users report. So let's add all new reserved Haswell IDs.
I didn't have better names for this reserved ids and didn't want to use rsvd1
and rsvd2 groups, so I decided to use "B" and "E" that stands for the last
id digit.
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 4b05e25..32f623b 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -201,9 +201,12 @@
#define PCI_CHIP_HASWELL_S_GT1 0x040A
#define PCI_CHIP_HASWELL_S_GT2 0x041A
#define PCI_CHIP_HASWELL_S_GT3 0x042A
-#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E
-#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E
-#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E
+#define PCI_CHIP_HASWELL_B_GT1 0x040B
+#define PCI_CHIP_HASWELL_B_GT2 0x041B
+#define PCI_CHIP_HASWELL_B_GT3 0x042B
+#define PCI_CHIP_HASWELL_E_GT1 0x040E
+#define PCI_CHIP_HASWELL_E_GT2 0x041E
+#define PCI_CHIP_HASWELL_E_GT3 0x042E
#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
@@ -214,9 +217,12 @@
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
-#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E
-#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E
-#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E
+#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0E
+#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1E
+#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2E
+#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E
+#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
+#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
@@ -227,9 +233,12 @@
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
-#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E
-#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E
-#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E
+#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B
+#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
+#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
+#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E
+#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
+#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02
#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12
@@ -240,9 +249,12 @@
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E
-#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E
-#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E
+#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B
+#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
+#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
+#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E
+#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
+#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
diff --git a/src/intel_module.c b/src/intel_module.c
index 6439eea..1e402f0 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -169,6 +169,12 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
{PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
{PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" },
+ {PCI_CHIP_HASWELL_B_GT1, "Haswell (GT1)" },
+ {PCI_CHIP_HASWELL_B_GT2, "Haswell (GT2)" },
+ {PCI_CHIP_HASWELL_B_GT3, "Haswell (GT3)" },
+ {PCI_CHIP_HASWELL_E_GT1, "Haswell (GT1)" },
+ {PCI_CHIP_HASWELL_E_GT2, "Haswell (GT2)" },
+ {PCI_CHIP_HASWELL_E_GT3, "Haswell (GT3)" },
{PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
{PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" },
{PCI_CHIP_HASWELL_SDV_D_GT3, "Haswell SDV Desktop (GT3)" },
@@ -178,6 +184,12 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" },
{PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" },
{PCI_CHIP_HASWELL_SDV_S_GT3, "Haswell SDV Server (GT3)" },
+ {PCI_CHIP_HASWELL_SDV_B_GT1, "Haswell SDV (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_B_GT2, "Haswell SDV (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_B_GT3, "Haswell SDV (GT3)" },
+ {PCI_CHIP_HASWELL_SDV_E_GT1, "Haswell SDV (GT1)" },
+ {PCI_CHIP_HASWELL_SDV_E_GT2, "Haswell SDV (GT2)" },
+ {PCI_CHIP_HASWELL_SDV_E_GT3, "Haswell SDV (GT3)" },
{PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
{PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
{PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" },
@@ -187,6 +199,12 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
{PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
{PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_B_GT3, "Haswell ULT (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" },
+ {PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" },
+ {PCI_CHIP_HASWELL_ULT_E_GT3, "Haswell ULT (GT3)" },
{PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
{PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
{PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" },
@@ -196,6 +214,12 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
{PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
{PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_B_GT1, "Haswell CRW (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_B_GT2, "Haswell CRW (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_B_GT3, "Haswell CRW (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_E_GT1, "Haswell CRW (GT1)" },
+ {PCI_CHIP_HASWELL_CRW_E_GT2, "Haswell CRW (GT2)" },
+ {PCI_CHIP_HASWELL_CRW_E_GT3, "Haswell CRW (GT3)" },
{PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" },
{-1, NULL}
};
@@ -277,9 +301,12 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT3, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT3_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT3, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
@@ -290,9 +317,12 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT3, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT3_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT3, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
@@ -303,9 +333,13 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT3, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT3_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT3, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT3, &intel_haswell_info ),
+
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT3, &intel_haswell_info ),
@@ -315,9 +349,12 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT3, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT3_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT3, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT1, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT2, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ),
commit ee96de8b1e7e4a305ee31c0ece1d9d38df8328f9
Author: Rodrigo Vivi <rodrigo.vivi at gmail.com>
Date: Mon May 13 17:56:29 2013 -0300
Fix Haswell GT3 names.
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
diff --git a/src/intel_driver.h b/src/intel_driver.h
index d109c7e..4b05e25 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -194,55 +194,55 @@
#define PCI_CHIP_HASWELL_D_GT1 0x0402
#define PCI_CHIP_HASWELL_D_GT2 0x0412
-#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_D_GT3 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_M_GT3 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040A
#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_S_GT3 0x042A
#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E
#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E
-#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD 0x042E
+#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E
#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_D_GT3 0x0C22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E
#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD 0x0C2E
+#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E
#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E
#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD 0x0A2E
+#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E
#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02
#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E
#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD 0x0D2E
+#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
diff --git a/src/intel_module.c b/src/intel_module.c
index 73cfa97..6439eea 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -162,40 +162,40 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
{PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" },
{PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" },
- {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_D_GT3, "Haswell Desktop (GT3)" },
{PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" },
{PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" },
- {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_M_GT3, "Haswell Mobile (GT3)" },
{PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" },
{PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" },
- {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" },
+ {PCI_CHIP_HASWELL_S_GT3, "Haswell Server (GT3)" },
{PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" },
{PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" },
- {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_D_GT3, "Haswell SDV Desktop (GT3)" },
{PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" },
{PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" },
- {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_M_GT3, "Haswell SDV Mobile (GT3)" },
{PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" },
{PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" },
- {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" },
+ {PCI_CHIP_HASWELL_SDV_S_GT3, "Haswell SDV Server (GT3)" },
{PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
{PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
- {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" },
{PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
{PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
- {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT3, "Haswell ULT Mobile (GT3)" },
{PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
{PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
- {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" },
{PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
{PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
- {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" },
{PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
{PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
- {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT3, "Haswell CRW Mobile (GT3)" },
{PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
{PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
- {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" },
{PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" },
{-1, NULL}
};
@@ -270,54 +270,54 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_PLUS_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT3_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT3_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT3_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT3, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ),
- INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD, &intel_haswell_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT3_RSVD, &intel_haswell_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ),
commit 979d2f8d0038aa621e1c75200b10a3819e024a66
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Apr 22 18:00:32 2013 +0100
sna/gen4: Tidy testing for an active vertex buffer id
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index 8779b85..575cc6a 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -586,7 +586,7 @@ static void gen4_emit_primitive(struct sna *sna)
static bool gen4_rectangle_begin(struct sna *sna,
const struct sna_composite_op *op)
{
- int id = op->u.gen4.ve_id;
+ unsigned int id = 1 << op->u.gen4.ve_id;
int ndwords;
if (sna_vertex_wait__locked(&sna->render) && sna->render.vertex_offset)
@@ -594,13 +594,13 @@ static bool gen4_rectangle_begin(struct sna *sna,
/* 7xpipelined pointers + 6xprimitive + 1xflush */
ndwords = op->need_magic_ca_pass? 20 : 6;
- if ((sna->render.vb_id & (1 << id)) == 0)
+ if ((sna->render.vb_id & id) == 0)
ndwords += 5;
if (!kgem_check_batch(&sna->kgem, ndwords))
return false;
- if ((sna->render.vb_id & (1 << id)) == 0)
+ if ((sna->render.vb_id & id) == 0)
gen4_emit_vertex_buffer(sna, op);
if (sna->render.vertex_offset == 0)
gen4_emit_primitive(sna);
commit 7ba63307058337af5a120ad01c93b423a3e422eb
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Apr 22 17:43:21 2013 +0100
sna/gen4: Drop unused gen parameter to SF state setup
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index 69a5c77..8779b85 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -2946,7 +2946,7 @@ static uint32_t gen4_create_vs_unit_state(struct sna_static_stream *stream)
}
static uint32_t gen4_create_sf_state(struct sna_static_stream *stream,
- int gen, uint32_t kernel)
+ uint32_t kernel)
{
struct gen4_sf_unit_state *sf;
@@ -3100,7 +3100,7 @@ static bool gen4_render_setup(struct sna *sna)
}
state->vs = gen4_create_vs_unit_state(&general);
- state->sf = gen4_create_sf_state(&general, sna->kgem.gen, sf);
+ state->sf = gen4_create_sf_state(&general, sf);
wm_state = sna_static_stream_map(&general,
sizeof(*wm_state) * KERNEL_COUNT *
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