xf86-video-intel: 4 commits - src/intel_module.c src/sna/gen2_render.c src/sna/gen3_render.c src/sna/gen4_render.c src/sna/gen5_render.c src/sna/gen6_render.c src/sna/gen7_render.c src/sna/sna_accel.c src/sna/sna_display.c src/sna/sna_render.c src/sna/sna_render.h
Chris Wilson
ickle at kemper.freedesktop.org
Wed May 29 01:55:30 PDT 2013
src/intel_module.c | 20 ++++++++++----------
src/sna/gen2_render.c | 4 ++--
src/sna/gen3_render.c | 4 ++--
src/sna/gen4_render.c | 6 +++---
src/sna/gen5_render.c | 6 +++---
src/sna/gen6_render.c | 6 +++---
src/sna/gen7_render.c | 21 ++++++++++++++-------
src/sna/sna_accel.c | 37 +++++++++++++++----------------------
src/sna/sna_display.c | 21 ++++++++++++++++++---
src/sna/sna_render.c | 3 ++-
src/sna/sna_render.h | 15 +++++++--------
11 files changed, 79 insertions(+), 64 deletions(-)
New commits:
commit b7aa05e44b1f88284183c1c73bb074dd5dce74cb
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue May 28 23:01:30 2013 +0100
sna: Sanity check that CRTC / output combination is valid
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 969d961..e927282 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -740,7 +740,15 @@ sna_crtc_apply(xf86CrtcPtr crtc)
if (output->crtc != crtc)
continue;
+ assert(output->possible_crtcs & (1 << i));
+
sna_output = output->driver_private;
+
+ DBG(("%s: attaching output '%s' %d [%d] to crtc:%d (pipe %d) (possible crtc:%x, possible clones:%x)\n",
+ __FUNCTION__, output->name, i,
+ sna_output->mode_output->connector_id,
+ sna_crtc->id, sna_crtc->pipe,
+ output->possible_crtcs, output->possible_clones));
output_ids[output_count] =
sna_output->mode_output->connector_id;
output_count++;
@@ -761,8 +769,8 @@ sna_crtc_apply(xf86CrtcPtr crtc)
arg.mode = sna_crtc->kmode;
arg.mode_valid = 1;
- DBG(("%s: applying crtc [%d] mode=%dx%d+%d+%d@%d, fb=%d%s%s update to %d outputs\n",
- __FUNCTION__, sna_crtc->id,
+ DBG(("%s: applying crtc [%d, pipe=%d] mode=%dx%d+%d+%d@%d, fb=%d%s%s update to %d outputs [%d...]\n",
+ __FUNCTION__, sna_crtc->id, sna_crtc->pipe,
arg.mode.hdisplay,
arg.mode.vdisplay,
arg.x, arg.y,
@@ -770,7 +778,7 @@ sna_crtc_apply(xf86CrtcPtr crtc)
arg.fb_id,
sna_crtc->shadow ? " [shadow]" : "",
sna_crtc->transform ? " [transformed]" : "",
- output_count));
+ output_count, output_count ? output_ids[0] : 0));
if (drmIoctl(sna->kgem.fd, DRM_IOCTL_MODE_SETCRTC, &arg))
return false;
@@ -2389,6 +2397,11 @@ sna_output_init(ScrnInfoPtr scrn, struct sna_mode *mode, int num)
output->possible_clones = enc.possible_clones;
output->interlaceAllowed = TRUE;
+ DBG(("%s: created output '%s' %d [%d] (possible crtc:%x, possible clones:%x)\n",
+ __FUNCTION__, name, num,
+ sna_output->mode_output->connector_id,
+ output->possible_crtcs, output->possible_clones));
+
return;
cleanup_output:
commit b507796679529b14c99e8937870561cd8eebebb9
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue May 28 12:13:02 2013 +0100
Add the known marketing names for the performance Haswell parts
Start filling in the names for the parts that have been announced, the
Iris branded Haswell GT3 parts.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/intel_module.c b/src/intel_module.c
index 1e402f0..8b3b196 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -192,34 +192,34 @@ static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_HASWELL_SDV_E_GT3, "Haswell SDV (GT3)" },
{PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" },
{PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" },
- {PCI_CHIP_HASWELL_ULT_D_GT3, "Haswell ULT Desktop (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_D_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" },
{PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" },
- {PCI_CHIP_HASWELL_ULT_M_GT3, "Haswell ULT Mobile (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_M_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" },
{PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" },
- {PCI_CHIP_HASWELL_ULT_S_GT3, "Haswell ULT Server (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_S_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_ULT_B_GT1, "Haswell ULT (GT1)" },
{PCI_CHIP_HASWELL_ULT_B_GT2, "Haswell ULT (GT2)" },
- {PCI_CHIP_HASWELL_ULT_B_GT3, "Haswell ULT (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_B_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_ULT_E_GT1, "Haswell ULT (GT1)" },
{PCI_CHIP_HASWELL_ULT_E_GT2, "Haswell ULT (GT2)" },
- {PCI_CHIP_HASWELL_ULT_E_GT3, "Haswell ULT (GT3)" },
+ {PCI_CHIP_HASWELL_ULT_E_GT3, "Iris(TM) Graphics 5100" },
{PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" },
{PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" },
- {PCI_CHIP_HASWELL_CRW_D_GT3, "Haswell CRW Desktop (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_D_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" },
{PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" },
- {PCI_CHIP_HASWELL_CRW_M_GT3, "Haswell CRW Mobile (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_M_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" },
{PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" },
- {PCI_CHIP_HASWELL_CRW_S_GT3, "Haswell CRW Server (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_S_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_HASWELL_CRW_B_GT1, "Haswell CRW (GT1)" },
{PCI_CHIP_HASWELL_CRW_B_GT2, "Haswell CRW (GT2)" },
- {PCI_CHIP_HASWELL_CRW_B_GT3, "Haswell CRW (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_B_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_HASWELL_CRW_E_GT1, "Haswell CRW (GT1)" },
{PCI_CHIP_HASWELL_CRW_E_GT2, "Haswell CRW (GT2)" },
- {PCI_CHIP_HASWELL_CRW_E_GT3, "Haswell CRW (GT3)" },
+ {PCI_CHIP_HASWELL_CRW_E_GT3, "Iris(TM) Pro Graphics 5200" },
{PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" },
{-1, NULL}
};
commit b3169768ddf8c8977d2ace3675611b5ec6eba7ee
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue May 28 12:02:56 2013 +0100
sna: Make the backend identifier more informative
This is useful, for example, with the multiple gen7 variants.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen2_render.c b/src/sna/gen2_render.c
index 58f2578..f09a20b 100644
--- a/src/sna/gen2_render.c
+++ b/src/sna/gen2_render.c
@@ -3436,7 +3436,7 @@ gen2_render_context_switch(struct kgem *kgem,
}
}
-bool gen2_render_init(struct sna *sna)
+const char *gen2_render_init(struct sna *sna, const char *backend)
{
struct sna_render *render = &sna->render;
@@ -3467,5 +3467,5 @@ bool gen2_render_init(struct sna *sna)
render->max_3d_size = MAX_3D_SIZE;
render->max_3d_pitch = MAX_3D_PITCH;
- return true;
+ return "Almador (gen2)";
}
diff --git a/src/sna/gen3_render.c b/src/sna/gen3_render.c
index c549ebb..94cd541 100644
--- a/src/sna/gen3_render.c
+++ b/src/sna/gen3_render.c
@@ -6204,7 +6204,7 @@ gen3_render_fini(struct sna *sna)
{
}
-bool gen3_render_init(struct sna *sna)
+const char *gen3_render_init(struct sna *sna, const char *backend)
{
struct sna_render *render = &sna->render;
@@ -6236,5 +6236,5 @@ bool gen3_render_init(struct sna *sna)
sna->kgem.retire = gen3_render_retire;
sna->kgem.expire = gen3_render_expire;
- return true;
+ return "Alviso (gen3)";
}
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index 575cc6a..e94fb6d 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -3137,10 +3137,10 @@ static bool gen4_render_setup(struct sna *sna)
return state->general_bo != NULL;
}
-bool gen4_render_init(struct sna *sna)
+const char *gen4_render_init(struct sna *sna, const char *backend)
{
if (!gen4_render_setup(sna))
- return false;
+ return backend;
sna->kgem.retire = gen4_render_retire;
sna->kgem.expire = gen4_render_expire;
@@ -3183,5 +3183,5 @@ bool gen4_render_init(struct sna *sna)
sna->render.max_3d_size = GEN4_MAX_3D_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return true;
+ return sna->kgem.gen >= 045 ? "Eaglelake (gen4.5)" : "Broadwater (gen4)";
}
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index b960ed6..2de7eb8 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -3273,10 +3273,10 @@ static bool gen5_render_setup(struct sna *sna)
return state->general_bo != NULL;
}
-bool gen5_render_init(struct sna *sna)
+const char *gen5_render_init(struct sna *sna, const char *backend)
{
if (!gen5_render_setup(sna))
- return false;
+ return backend;
sna->kgem.context_switch = gen5_render_context_switch;
sna->kgem.retire = gen5_render_retire;
@@ -3307,5 +3307,5 @@ bool gen5_render_init(struct sna *sna)
sna->render.max_3d_size = MAX_3D_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return true;
+ return "Ironlake (gen5)";
}
diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c
index f7af54e..c25ef94 100644
--- a/src/sna/gen6_render.c
+++ b/src/sna/gen6_render.c
@@ -3656,10 +3656,10 @@ static bool gen6_render_setup(struct sna *sna)
return state->general_bo != NULL;
}
-bool gen6_render_init(struct sna *sna)
+const char *gen6_render_init(struct sna *sna, const char *backend)
{
if (!gen6_render_setup(sna))
- return false;
+ return backend;
sna->kgem.context_switch = gen6_render_context_switch;
sna->kgem.retire = gen6_render_retire;
@@ -3704,5 +3704,5 @@ bool gen6_render_init(struct sna *sna)
sna->render.max_3d_size = GEN6_MAX_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return true;
+ return "Sandybridge (gen6)";
}
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index 5cbed9d..6dbf1d2 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -3718,12 +3718,13 @@ static bool is_mobile(struct sna *sna)
return (DEVICE_ID(sna->PciInfo) & 0xf) == 0x6;
}
-static bool gen7_render_setup(struct sna *sna)
+static const char *gen7_render_setup(struct sna *sna)
{
struct gen7_render_state *state = &sna->render_state.gen7;
struct sna_static_stream general;
struct gen7_sampler_state *ss;
int i, j, k, l, m;
+ const char *backend;
if (sna->kgem.gen == 070) {
state->info = &ivb_gt_info;
@@ -3732,8 +3733,10 @@ static bool gen7_render_setup(struct sna *sna)
if (is_gt2(sna))
state->info = &ivb_gt2_info; /* XXX requires GT_MODE WiZ disabled */
}
+ backend = "Ivybridge (gen7)";
} else if (sna->kgem.gen == 071) {
state->info = &ivb_gt_info;
+ backend = "Valleyview (gen7)";
} else if (sna->kgem.gen == 075) {
state->info = &hsw_gt_info;
if (DEVICE_ID(sna->PciInfo) & 0xf) {
@@ -3741,8 +3744,9 @@ static bool gen7_render_setup(struct sna *sna)
if (is_gt2(sna))
state->info = &hsw_gt2_info;
}
+ backend = "Haswell (gen7.5)";
} else
- return false;
+ return NULL;
sna_static_stream_init(&general);
@@ -3803,13 +3807,16 @@ static bool gen7_render_setup(struct sna *sna)
state->cc_blend = gen7_composite_create_blend_state(&general);
state->general_bo = sna_static_stream_fini(sna, &general);
- return state->general_bo != NULL;
+ return state->general_bo ? backend : NULL;
}
-bool gen7_render_init(struct sna *sna)
+const char *gen7_render_init(struct sna *sna, const char *parent)
{
- if (!gen7_render_setup(sna))
- return false;
+ const char *backend;
+
+ backend = gen7_render_setup(sna);
+ if (backend == NULL)
+ return parent;
sna->kgem.context_switch = gen7_render_context_switch;
sna->kgem.retire = gen7_render_retire;
@@ -3853,5 +3860,5 @@ bool gen7_render_init(struct sna *sna)
sna->render.max_3d_size = GEN7_MAX_SIZE;
sna->render.max_3d_pitch = 1 << 18;
- return true;
+ return backend;
}
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index d8e2746..3e3e75c 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -14672,29 +14672,22 @@ bool sna_accel_init(ScreenPtr screen, struct sna *sna)
if (!sna_picture_init(screen))
return false;
- backend = "generic";
- no_render_init(sna);
+ backend = no_render_init(sna);
+ if (sna_option_accel_blt(sna) || sna->info->gen >= 0100)
+ (void)backend;
+ else if (sna->info->gen >= 070)
+ backend = gen7_render_init(sna, backend);
+ else if (sna->info->gen >= 060)
+ backend = gen6_render_init(sna, backend);
+ else if (sna->info->gen >= 050)
+ backend = gen5_render_init(sna, backend);
+ else if (sna->info->gen >= 040)
+ backend = gen4_render_init(sna, backend);
+ else if (sna->info->gen >= 030)
+ backend = gen3_render_init(sna, backend);
+ else if (sna->info->gen >= 020)
+ backend = gen2_render_init(sna, backend);
- if (sna_option_accel_blt(sna) || sna->info->gen >= 0100) {
- } else if (sna->info->gen >= 070) {
- if (gen7_render_init(sna))
- backend = "IvyBridge";
- } else if (sna->info->gen >= 060) {
- if (gen6_render_init(sna))
- backend = "SandyBridge";
- } else if (sna->info->gen >= 050) {
- if (gen5_render_init(sna))
- backend = "Ironlake";
- } else if (sna->info->gen >= 040) {
- if (gen4_render_init(sna))
- backend = "Broadwater/Crestline";
- } else if (sna->info->gen >= 030) {
- if (gen3_render_init(sna))
- backend = "gen3";
- } else if (sna->info->gen >= 020) {
- if (gen2_render_init(sna))
- backend = "gen2";
- }
DBG(("%s(backend=%s, prefer_gpu=%x)\n",
__FUNCTION__, backend, sna->render.prefer_gpu));
diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c
index c19a283..6e95e55 100644
--- a/src/sna/sna_render.c
+++ b/src/sna/sna_render.c
@@ -282,7 +282,7 @@ no_render_fini(struct sna *sna)
(void)sna;
}
-void no_render_init(struct sna *sna)
+const char *no_render_init(struct sna *sna)
{
struct sna_render *render = &sna->render;
@@ -315,6 +315,7 @@ void no_render_init(struct sna *sna)
sna->kgem.ring = KGEM_BLT;
sna_vertex_init(sna);
+ return "generic";
}
static struct kgem_bo *
diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
index 1a15b70..d4406c3 100644
--- a/src/sna/sna_render.h
+++ b/src/sna/sna_render.h
@@ -541,14 +541,13 @@ bool sna_get_rgba_from_pixel(uint32_t pixel,
uint32_t format);
bool sna_picture_is_solid(PicturePtr picture, uint32_t *color);
-void no_render_init(struct sna *sna);
-
-bool gen2_render_init(struct sna *sna);
-bool gen3_render_init(struct sna *sna);
-bool gen4_render_init(struct sna *sna);
-bool gen5_render_init(struct sna *sna);
-bool gen6_render_init(struct sna *sna);
-bool gen7_render_init(struct sna *sna);
+const char *no_render_init(struct sna *sna);
+const char *gen2_render_init(struct sna *sna, const char *backend);
+const char *gen3_render_init(struct sna *sna, const char *backend);
+const char *gen4_render_init(struct sna *sna, const char *backend);
+const char *gen5_render_init(struct sna *sna, const char *backend);
+const char *gen6_render_init(struct sna *sna, const char *backend);
+const char *gen7_render_init(struct sna *sna, const char *backend);
bool sna_tiling_composite(uint32_t op,
PicturePtr src,
commit 0839e3316a02380cd64d354ee0ec9d4c2b8eecf4
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue May 28 11:18:14 2013 +0100
sna: Call mode update after disabling outputs upon VT switch
Perform a second sanity check that all the outputs we expect to be
active remain so following the cleanup after VT switching.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index d4c77cb..969d961 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -929,6 +929,8 @@ void sna_mode_disable_unused(struct sna *sna)
if (!xf86_config->crtc[i]->enabled)
sna_crtc_disable(xf86_config->crtc[i]);
}
+
+ sna_mode_update(sna);
}
static struct kgem_bo *sna_create_bo_for_fbcon(struct sna *sna,
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