xf86-video-ati: Branch 'master'

[Alex Deucher]

 src/evergreen_exa.c                 |   15 ++++++++++-----
 src/evergreen_textured_videofuncs.c |   15 ++++++++++-----
 src/radeon_drm.h                    |    2 ++
 3 files changed, 22 insertions(+), 10 deletions(-)

New commits:
commit f1dc677e79cd7a88d7379a934ebc7d87a3b18805
Author: Christopher James Halse Rogers <raof at ubuntu.com>
Date:   Mon Sep 23 12:25:29 2013 -0700

    EXA/evergreen: Paranoia around linear tiling. (v2)
    
    The last two bytes of tiling_mode contain the actual tiling mode; the rest are
    extra tiling configuration bits. These configuration bits are not necessarily
    zero for a linear buffer, so mask them out before checking for linearity
    
    v2: Also fix up evergreen_textured_videofuncs.c
    
    agd5f: remove trailing whitespace
    
    Signed-off-by: Christopher James Halse Rogers <raof at ubuntu.com>
    Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index ccd102d..abb5076 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -156,7 +156,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     if (accel_state->planemask & 0xff000000)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
-    if (accel_state->dst_obj.tiling_flags == 0) {
+    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+	RADEON_TILING_LINEAR) {
 	cb_conf.array_mode = 0;
 	cb_conf.non_disp_tiling = 1;
     }
@@ -335,7 +336,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
     tex_res.base_level          = 0;
     tex_res.last_level          = 0;
     tex_res.perf_modulation     = 0;
-    if (accel_state->src_obj[0].tiling_flags == 0)
+    if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+	RADEON_TILING_LINEAR)
 	tex_res.array_mode          = 0;
     evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
 
@@ -378,7 +380,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
     if (accel_state->planemask & 0xff000000)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
-    if (accel_state->dst_obj.tiling_flags == 0) {
+    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+	RADEON_TILING_LINEAR) {
 	cb_conf.array_mode = 0;
 	cb_conf.non_disp_tiling = 1;
     }
@@ -1001,7 +1004,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
     tex_res.base_level          = 0;
     tex_res.last_level          = 0;
     tex_res.perf_modulation     = 0;
-    if (accel_state->src_obj[unit].tiling_flags == 0)
+    if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) ==
+	RADEON_TILING_LINEAR)
 	tex_res.array_mode          = 0;
     evergreen_set_tex_resource  (pScrn, &tex_res, accel_state->src_obj[unit].domain);
 
@@ -1449,7 +1453,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
     cb_conf.rop = 3;
     cb_conf.pmask = 0xf;
-    if (accel_state->dst_obj.tiling_flags == 0) {
+    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+	RADEON_TILING_LINEAR) {
 	cb_conf.array_mode = 0;
 	cb_conf.non_disp_tiling = 1;
     }
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index be00ecf..20805ff 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -246,7 +246,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 	tex_res.last_level          = 0;
 	tex_res.perf_modulation     = 0;
 	tex_res.interlaced          = 0;
-	if (accel_state->src_obj[0].tiling_flags == 0)
+	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+	    RADEON_TILING_LINEAR)
 	    tex_res.array_mode          = 1;
 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
 
@@ -279,7 +280,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 	tex_res.base                = pPriv->planev_offset;
 	tex_res.mip_base            = pPriv->planev_offset;
 	tex_res.size                = tex_res.pitch * (pPriv->h >> 1);
-	if (accel_state->src_obj[0].tiling_flags == 0)
+	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+	    RADEON_TILING_LINEAR)
 	    tex_res.array_mode          = 1;
 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
 
@@ -302,7 +304,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 	tex_res.base                = pPriv->planeu_offset;
 	tex_res.mip_base            = pPriv->planeu_offset;
 	tex_res.size                = tex_res.pitch * (pPriv->h >> 1);
-	if (accel_state->src_obj[0].tiling_flags == 0)
+	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+	    RADEON_TILING_LINEAR)
 	    tex_res.array_mode          = 1;
 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
 
@@ -342,7 +345,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 	tex_res.last_level          = 0;
 	tex_res.perf_modulation     = 0;
 	tex_res.interlaced          = 0;
-	if (accel_state->src_obj[0].tiling_flags == 0)
+	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+	    RADEON_TILING_LINEAR)
 	    tex_res.array_mode          = 1;
 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
 
@@ -397,7 +401,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     cb_conf.blend_clamp = 1;
     cb_conf.pmask = 0xf;
     cb_conf.rop = 3;
-    if (accel_state->dst_obj.tiling_flags == 0) {
+    if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+	RADEON_TILING_LINEAR) {
 	cb_conf.array_mode = 1;
 	cb_conf.non_disp_tiling = 1;
     }
diff --git a/src/radeon_drm.h b/src/radeon_drm.h
index 042e822..2bbd8fa 100644
--- a/src/radeon_drm.h
+++ b/src/radeon_drm.h
@@ -800,6 +800,8 @@ struct drm_radeon_gem_create {
 	uint32_t	flags;
 };
 
+#define RADEON_TILING_MASK				0xff
+#define RADEON_TILING_LINEAR				0x0
 #define RADEON_TILING_MACRO				0x1
 #define RADEON_TILING_MICRO				0x2
 #define RADEON_TILING_SWAP_16BIT			0x4