[Bug 43191] Radeons needs 2D (MACRO) color tiling for optimal performance

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=43191

--- Comment #20 from Simon Farnsworth <simon.farnsworth at onelan.co.uk> 2011-11-29 06:27:37 PST ---
I cannot reproduce the lockup now that I've added the "avoid infinite loops in
pageflip code" patch; I'm guessing that the udelay(1) in there keeps the chip
happy.

I have, however, noticed that I've got rendering to the back buffer partially
overwriting the front buffer. If I put code in radeon_dri2.c to force buffers
obtained via the DDX to be properly aligned, I see Mesa asking for buffers of
size 300x300, but proper alignment being 512x304 for this hardware.

I think this implies that Mesa isn't coping with tiling properly, and am going
to dive into that code base.

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