Radeon DRM GART mapping bogosity

Benjamin Herrenschmidt benh at kernel.crashing.org
Tue May 3 01:20:39 PDT 2005

On Tue, 2005-05-03 at 10:09 +0200, Jerome Glisse wrote:

> Has i still doesn't understand the big pictures of video drivers, i
> was wondering
> if this could have an impact on bytes swapping on r300. Thus the problem
> of bit blit we have on r300 & X driver. I don't think so but as i don't well
> understand all this... 

Well, it depends which byteswapping :) (Though paulus did some hacks for
that recently iirc).

Here is a short explanation of the memory mapping of a radeon:

 - Card view. This is the view of memory from the GPU point of view
(things you put in OFFSET registers etc...). The video RAM is mapped by
MC_FB_LOCATION which indicates location and size, and the AGP space by
MC_AGP_LOCATION. I'm on purpose ignoring the case of "PCI GART" which
can be considered as similar to AGP in that discussion. These affect the
MC (Memory Controller), so they define where an access from the engine
or the CRTCs ends up. I'm fairly sure that if you provide an address
outside of those 2 ranges, the card does a normal PCI bus master cycle
to that address. CONFIG_MEMSIZE is usually the total VRAM size. I'm not
100% sure how much of that register is actually _used_ by the HW, but
it's generally safe to assume it contains a correct value except for
some M6 chips where we need to fix it up when it's 0 (oops, the patch I
posted didn't do it !)

 - Bus view (that is vew from outside of the card, like the CPU). PCI
BAR 0 exposes a PCI region of the size CONFIG_APER_SIZE * 2. (That is 2
"apertures"). The actual value of CONFIG_APER_SIZE is defined by straps
on the video board or motherboard. Each aperture is 1/2 of the PCI
space. The way they actually map to video memory though depends on the
setting of the bit HOST_PATH_CNTL::HDP_APER_CNTL:

   0 : Both apertures map to the same area of video memory which starts
from the beginning of video RAM
   1 : Apertures map contiguous portion of memory. That is, if
CONFIG_APER_SIZE is 64Mb, then access to aperture 0 will access vram
from 0 to 64Mb-1 while access to aperture 1 will access vram from 64Mb
to 128Mb-1.

Each apperture can have a different swapper setting. This swapper
setting, though, afaik, only has an effect for datas written by the host
(but then, I'm not totally sure of what engine host data blits are
supposed to do).

Now, the setting above has to be done the most intelligently you can
based on 1) do you need 2 apertures with different swapper settings
(typical of BE machines) or not, 2) what is your CONFIG_APER_SIZE
strapping vs. how much VRAM you have ... You can see both kind of setups
on Mac cards.


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