EXA support for nv driver
lars at trolltech.com
Tue Sep 6 00:29:38 PDT 2005
On Friday 26 August 2005 17:37, Michel Dänzer wrote:
> On Fri, 2005-08-26 at 09:43 +0200, Lars Knoll wrote:
> > On Friday 26 August 2005 08:58, Benjamin Herrenschmidt wrote:
> > > On Fri, 2005-08-26 at 08:41 +0200, Lars Knoll wrote:
> > > > Wouldn't mapping the actual RAM page be better anyway, as that one
> > > > could be mapped cachable, whereas the GART memory usually is write
> > > > combining only?
> > >
> > > Mapping cacheable ? Hrm... I'm not sure that would work with many
> > > chipsets as I'm not sure they would trigger proper coherency protocol
> > > when beeing accessed by the card. I currently map them non-cacheable on
> > > Macs but it might be worth trying on some chipsets I suppose...
> > Hmmm... true. I remember vaguely having read that some newer chipsets
> > support this, but I couldn't find the reference anymore.
> You mean PCIe chipsets? ;) AFAIK AGP is explicitly specified not to be
> cache coherent.
AGP 3.0 seems to allow for cache coherency:
See section 4.1.4 in
and section D.5 in
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