Request for Intel 915 hw information

Krzysztof Halasa khc at
Tue Sep 18 18:28:08 PDT 2007


Simple questions for you Intel experts. I'm using interlaced mode
on PIPE A:

How do I read currently displayed scan line number, and/or field
number? Is it the following?

#define PIPEAFRAMEHIGH          0x70040
#define PIPE_FRAME_HIGH_MASK    0x0000ffff
#define PIPEAFRAMEPIXEL         0x70044
#define PIPE_FRAME_LOW_MASK     0xff000000
#define PIPE_FRAME_LOW_SHIFT    24

(and 0x71040 + 0x71044 for PIPEB)?

On my 915 PIPEACONF, PIPEA_DSL and the above registers produce:

0x80C00000 288       0          0x1207A04E
0x80C00000 288       0          0x1307A03E
0x80C00000 288       0          0x1407A026
0x80C00000 288       0          0x1507A06E
0x80C00000 288       0          0x1607A06A
0x80C00000 288       0          0x1707A0CA
0x80C00000 288       0          0x1807A126
0x80C00000 288       0          0x1907A0EB
0x80C00000 288       0          0x1A07A0C2
0x80C00000 288       0          0x1B07A149
0x80C00000 288       0          0x1C07A076
0x80C00000 288       0          0x1D07A19C
0x80C00000 288       0          0x1E07A031

Why is FRAME_HIGH always 0 for PIPE A (the active one)? Not implemented
on 915?

Should I expect the 8 MSBs of FRAME_PIXEL to always be the frame (field)
count? On all chips?
Can I assume that even/odd frame# in FRAME_PIXEL = even/odd field in
output, or something like that?

What is PIPEA_DSL? Is it implemented on 915 and/or other chips?

Is it possible to generate IRQ only on the second (final) vertical

Obviously I'm trying to reliably sync interlaced video to the full
interlaced frame (in IRQ handler), is

	field_parity = (INREG(PIPEAFRAMEPIXEL) >> 24) & 1

a reliable way to do it?

How about that Xvideo overlay, is it possible to have no vertical
scaling etc. in interlaced mode? Current code causes the chip
to deinterlace somehow, even if I have 576 visible lines and 576-line
video stream.

Thanks in advance.
Krzysztof Halasa

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