Request for Intel 915 hw information

Krzysztof Halasa khc at
Fri Sep 21 07:55:14 PDT 2007

Jesse Barnes <jbarnes at> writes:

> Err yes, that's what I meant.  However, there are separate bits in the 
> PIPE*STAT registers for controlling whether you get vblank interrupts 
> on even or odd frames or both.
> The odd event enable bit is 21 and even is 20.  They shouldn't be on 
> unless an interlaced mode is active.

Well, it doesn't seem to work at the moment. I have set bit 20 or 21
and I'm still getting IRQs every field. Perhaps I should ACK the IRQ
field event somehow?

Is there a specific way, order etc. I should set the bits?

I noticed other bits in PIPEASTAT are changed by the chip itself.
They seem to be "write 1 to clear" status bits type and they seem
to indicate the field. I'm getting (after some time) value 0x233 so
they are (at least) bits 0, 1, 4, 5 and 9.

Do you know meaning of all PIPExSTAT bits?
It seems bits 4 and 5 indicate a completed field (at least one of
a given odd/even type). For non-interlaced mode I don't get these
two bits, only 0, 1 and 9.

It seems I can set PIPExSTAT bits 16 - 21, 24 - 26, 28 - 29 (writing
"1" and reading back gives "1"). Writing 0xFFFFFFFF reads back as
0x373F0000. Perhaps the lower half (0 - 15) are the i915->CPU status
bits and 16-31 (some unused) are CPU->i915 "command" bits?

Is it like that on all i830 and later, so I can put it in the code

> Ok, so you're actually getting each field.  Good enough I guess.

Yes. It would be better if I get only the second IRQ but if the
IRQ handler can determine which field is it getting both isn't
a problem.

> "In interlaced display timings, the scan line counter provides the 
> current line in the field.  One field will have a total number of lines 
> that is one greater than the other field."

I always get 288 (576/2) in the IRQ handler but is seems that, for one
field, the value eventually reaches 289 (so I could use this info
post-IRQ, though PIPExSTAT is obviously better).

> Well, there's PIPEAFRAMEPIX (the low part of the frame count register 
> set).  The low 24 bits of that register contain the pixel count, so you 
> could try to use that.

Yes but it's per field, not per frame.

But it seems the status bits (4 and 5) in PIPExSTAT are enough.
I would appreciate it if you let me know the "official" names (and
meanings) of all the PIPExSTAT register bits (including 4 and 5).

Thanks for your help.
Krzysztof Halasa

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