[xserver-commit] xserver/hw/kdrive/ati ati_draw.h,NONE,1.1.2.1 ati_drawtmp.h,NONE,1.1.2.1 ati_dri.c,NONE,1.1.2.1 ati_dri.h,NONE,1.1.2.1 ati_dripriv.h,NONE,1.1.2.1 ati_sarea.h,NONE,1.1.2.1 r128_common.h,NONE,1.1.2.1 r128_sarea.h,NONE,1.1.2.1 radeon_common.h,NONE,1.1.2.1 radeon_sarea.h,NONE,1.1.2.1 Makefile.am,1.2,1.2.2.1 ati.c,1.7,1.7.2.1 ati.h,1.3,1.3.2.1 ati_draw.c,1.5,1.5.2.1 ati_reg.h,1.2,1.2.2.1 ati_stub.c,1.2,1.2.2.1
Eric Anholt
xserver-commit@pdx.freedesktop.org
Mon, 01 Dec 2003 14:56:38 -0800
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Committed by: anholt
Update of /cvs/xserver/xserver/hw/kdrive/ati
In directory pdx:/home/anholt/xserver-dri/hw/kdrive/ati
Modified Files:
Tag: dri-0-1-branch
Makefile.am ati.c ati.h ati_draw.c ati_reg.h ati_stub.c
Added Files:
Tag: dri-0-1-branch
ati_draw.h ati_drawtmp.h ati_dri.c ati_dri.h ati_dripriv.h
ati_sarea.h r128_common.h r128_sarea.h radeon_common.h
radeon_sarea.h
Log Message:
- Initial add of enough of the DRI to create a 2d driver that uses
the DRM for its acceleration.
- Converted the ATI driver to use the DRM to execute rendering
commands using DMA instead of MMIO when available.
--- NEW FILE: ati_draw.h ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: ati_drawtmp.h ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: ati_dri.c ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: ati_dri.h ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: ati_dripriv.h ---
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dripriv.h,v 1.3 2000/11/18 19:37:11 tsi Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
* SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Rickard E. Faith <faith@valinux.com>
* Kevin E. Martin <martin@valinux.com>
*
*/
#ifndef _ATI_DRIPRIV_H_
#define _ATI_DRIPRIV_H_
#ifdef GLXEXT
#include "GL/glxint.h"
extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs,
void **configprivs);
#endif
typedef struct {
/* Nothing here yet */
int dummy;
} ATIConfigPrivRec, *ATIConfigPrivPtr;
typedef struct {
/* Nothing here yet */
int dummy;
} ATIDRIContextRec, *ATIDRIContextPtr;
#endif
--- NEW FILE: ati_sarea.h ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: r128_common.h ---
/* r128_common.h -- common header definitions for R128 2D/3D/DRM suite
* Created: Sun Apr 9 18:16:28 2000 by kevin@precisioninsight.com
*
* Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Author:
* Gareth Hughes <gareth@valinux.com>
* Kevin E. Martin <martin@valinux.com>
*
* Converted to common header format:
* Jens Owen <jens@tungstengraphics.com>
*
* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_common.h,v 1.2 2002/12/16 16:19:10 dawes Exp $
*
*/
#ifndef _R128_COMMON_H_
#define _R128_COMMON_H_
#include "X11/Xmd.h"
/*
* WARNING: If you change any of these defines, make sure to change
* the kernel include file as well (r128_drm.h)
*/
/* Driver specific DRM command indices
* NOTE: these are not OS specific, but they are driver specific
*/
#define DRM_R128_INIT 0x00
#define DRM_R128_CCE_START 0x01
#define DRM_R128_CCE_STOP 0x02
#define DRM_R128_CCE_RESET 0x03
#define DRM_R128_CCE_IDLE 0x04
#define DRM_R128_UNDEFINED1 0x05
#define DRM_R128_RESET 0x06
#define DRM_R128_SWAP 0x07
#define DRM_R128_CLEAR 0x08
#define DRM_R128_VERTEX 0x09
#define DRM_R128_INDICES 0x0a
#define DRM_R128_BLIT 0x0b
#define DRM_R128_DEPTH 0x0c
#define DRM_R128_STIPPLE 0x0d
#define DRM_R128_UNDEFINED2 0x0e
#define DRM_R128_INDIRECT 0x0f
#define DRM_R128_FULLSCREEN 0x10
#define DRM_R128_CLEAR2 0x11
#define DRM_R128_GETPARAM 0x12
#define DRM_R128_FLIP 0x13
#define DRM_R128_FRONT_BUFFER 0x1
#define DRM_R128_BACK_BUFFER 0x2
#define DRM_R128_DEPTH_BUFFER 0x4
typedef struct {
enum {
DRM_R128_INIT_CCE = 0x01,
DRM_R128_CLEANUP_CCE = 0x02
} func;
unsigned long sarea_priv_offset;
int is_pci;
int cce_mode;
int cce_secure; /* FIXME: Deprecated, we should remove this */
int ring_size;
int usec_timeout;
unsigned int fb_bpp;
unsigned int front_offset, front_pitch;
unsigned int back_offset, back_pitch;
unsigned int depth_bpp;
unsigned int depth_offset, depth_pitch;
unsigned int span_offset;
unsigned long fb_offset;
unsigned long mmio_offset;
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
} drmR128Init;
typedef struct {
int flush;
int idle;
} drmR128CCEStop;
typedef struct {
int idx;
int start;
int end;
int discard;
} drmR128Indirect;
typedef struct {
int idx;
int pitch;
int offset;
int format;
unsigned short x, y;
unsigned short width, height;
} drmR128Blit;
typedef struct {
enum {
DRM_R128_WRITE_SPAN = 0x01,
DRM_R128_WRITE_PIXELS = 0x02,
DRM_R128_READ_SPAN = 0x03,
DRM_R128_READ_PIXELS = 0x04
} func;
int n;
int *x;
int *y;
unsigned int *buffer;
unsigned char *mask;
} drmR128Depth;
typedef struct {
int prim;
int idx; /* Index of vertex buffer */
int count; /* Number of vertices in buffer */
int discard; /* Client finished with buffer? */
} drmR128Vertex;
typedef struct {
unsigned int *mask;
} drmR128Stipple;
typedef struct {
unsigned int flags;
unsigned int clear_color;
unsigned int clear_depth;
unsigned int color_mask;
unsigned int depth_mask;
} drmR128Clear;
typedef struct {
enum {
DRM_R128_INIT_FULLSCREEN = 0x01,
DRM_R128_CLEANUP_FULLSCREEN = 0x02
} func;
} drmR128Fullscreen;
typedef struct drm_r128_getparam {
int param;
int *value;
} drmR128GetParam;
#define R128_PARAM_IRQ_NR 1
#endif
--- NEW FILE: r128_sarea.h ---
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_sarea.h,v 1.7 2002/02/16 21:26:35 herrb Exp $ */
/*
* Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
* Precision Insight, Inc., Cedar Park, Texas, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
* SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Kevin E. Martin <martin@valinux.com>
* Gareth Hughes <gareth@valinux.com>
*
*/
#ifndef _R128_SAREA_H_
#define _R128_SAREA_H_
/* WARNING: If you change any of these defines, make sure to change the
* defines in the kernel file (r128_drm.h)
*/
#ifndef __R128_SAREA_DEFINES__
#define __R128_SAREA_DEFINES__
/* What needs to be changed for the current vertex buffer?
*/
#define R128_UPLOAD_CONTEXT 0x001
#define R128_UPLOAD_SETUP 0x002
#define R128_UPLOAD_TEX0 0x004
#define R128_UPLOAD_TEX1 0x008
#define R128_UPLOAD_TEX0IMAGES 0x010
#define R128_UPLOAD_TEX1IMAGES 0x020
#define R128_UPLOAD_CORE 0x040
#define R128_UPLOAD_MASKS 0x080
#define R128_UPLOAD_WINDOW 0x100
#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
#define R128_REQUIRE_QUIESCENCE 0x400
#define R128_UPLOAD_ALL 0x7ff
#define R128_FRONT 0x1
#define R128_BACK 0x2
#define R128_DEPTH 0x4
/* Primitive types
*/
#define R128_POINTS 0x1
#define R128_LINES 0x2
#define R128_LINE_STRIP 0x3
#define R128_TRIANGLES 0x4
#define R128_TRIANGLE_FAN 0x5
#define R128_TRIANGLE_STRIP 0x6
/* Vertex/indirect buffer size
*/
#define R128_BUFFER_SIZE 16384
/* Byte offsets for indirect buffer data
*/
#define R128_INDEX_PRIM_OFFSET 20
#define R128_HOSTDATA_BLIT_OFFSET 32
/* Keep these small for testing
*/
#define R128_NR_SAREA_CLIPRECTS 12
#define R128_NR_CONTEXT_REGS 12
#define R128_MAX_TEXTURE_LEVELS 11
#define R128_MAX_TEXTURE_UNITS 2
#endif /* __R128_SAREA_DEFINES__ */
typedef struct {
/* Context state - can be written in one large chunk */
unsigned int dst_pitch_offset_c;
unsigned int dp_gui_master_cntl_c;
unsigned int sc_top_left_c;
unsigned int sc_bottom_right_c;
unsigned int z_offset_c;
unsigned int z_pitch_c;
unsigned int z_sten_cntl_c;
unsigned int tex_cntl_c;
unsigned int misc_3d_state_cntl_reg;
unsigned int texture_clr_cmp_clr_c;
unsigned int texture_clr_cmp_msk_c;
unsigned int fog_color_c;
/* Texture state */
unsigned int tex_size_pitch_c;
unsigned int constant_color_c;
/* Setup state */
unsigned int pm4_vc_fpu_setup;
unsigned int setup_cntl;
/* Mask state */
unsigned int dp_write_mask;
unsigned int sten_ref_mask_c;
unsigned int plane_3d_mask_c;
/* Window state */
unsigned int window_xy_offset;
/* Core state */
unsigned int scale_3d_cntl;
} r128_context_regs_t;
/* Setup registers for each texture unit
*/
typedef struct {
unsigned int tex_cntl;
unsigned int tex_combine_cntl;
unsigned int tex_size_pitch;
unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
unsigned int tex_border_color;
} r128_texture_regs_t;
typedef struct {
/* The channel for communication of state information to the kernel
* on firing a vertex buffer.
*/
r128_context_regs_t ContextState;
r128_texture_regs_t TexState[R128_MAX_TEXTURE_UNITS];
unsigned int dirty;
unsigned int vertsize;
unsigned int vc_format;
#ifdef XF86DRI
/* The current cliprects, or a subset thereof.
*/
XF86DRIClipRectRec boxes[R128_NR_SAREA_CLIPRECTS];
unsigned int nbox;
#endif
/* Counters for throttling of rendering clients.
*/
unsigned int last_frame;
unsigned int last_dispatch;
/* Maintain an LRU of contiguous regions of texture space. If you
* think you own a region of texture memory, and it has an age
* different to the one you set, then you are mistaken and it has
* been stolen by another client. If global texAge hasn't changed,
* there is no need to walk the list.
*
* These regions can be used as a proxy for the fine-grained texture
* information of other clients - by maintaining them in the same
* lru which is used to age their own textures, clients have an
* approximate lru for the whole of global texture space, and can
* make informed decisions as to which areas to kick out. There is
* no need to choose whether to kick out your own texture or someone
* else's - simply eject them all in LRU order.
*/
/* Last elt is sentinal */
drmTextureRegion texList[ATI_NR_TEX_HEAPS][ATI_NR_TEX_REGIONS+1];
/* last time texture was uploaded */
unsigned int texAge[ATI_NR_TEX_HEAPS];
int ctxOwner; /* last context to upload state */
int pfAllowPageFlip; /* set by the 2d driver, read by the client */
int pfCurrentPage; /* set by kernel, read by others */
} R128SAREAPriv, *R128SAREAPrivPtr;
#endif
--- NEW FILE: radeon_common.h ---
/* radeon_common.h -- common header definitions for Radeon 2D/3D/DRM suite
*
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Author:
* Gareth Hughes <gareth@valinux.com>
* Kevin E. Martin <martin@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
*
* Converted to common header format:
* Jens Owen <jens@tungstengraphics.com>
*
* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2003/04/07 01:22:09 martin Exp $
*
*/
#ifndef _RADEON_COMMON_H_
#define _RADEON_COMMON_H_
#include <inttypes.h>
/* WARNING: If you change any of these defines, make sure to change
* the kernel include file as well (radeon_drm.h)
*/
/* Driver specific DRM command indices
* NOTE: these are not OS specific, but they are driver specific
*/
#define DRM_RADEON_CP_INIT 0x00
#define DRM_RADEON_CP_START 0x01
#define DRM_RADEON_CP_STOP 0x02
#define DRM_RADEON_CP_RESET 0x03
#define DRM_RADEON_CP_IDLE 0x04
#define DRM_RADEON_RESET 0x05
#define DRM_RADEON_FULLSCREEN 0x06
#define DRM_RADEON_SWAP 0x07
#define DRM_RADEON_CLEAR 0x08
#define DRM_RADEON_VERTEX 0x09
#define DRM_RADEON_INDICES 0x0a
#define DRM_RADEON_STIPPLE 0x0c
#define DRM_RADEON_INDIRECT 0x0d
#define DRM_RADEON_TEXTURE 0x0e
#define DRM_RADEON_VERTEX2 0x0f
#define DRM_RADEON_CMDBUF 0x10
#define DRM_RADEON_GETPARAM 0x11
#define DRM_RADEON_FLIP 0x12
#define DRM_RADEON_ALLOC 0x13
#define DRM_RADEON_FREE 0x14
#define DRM_RADEON_INIT_HEAP 0x15
#define DRM_RADEON_IRQ_EMIT 0x16
#define DRM_RADEON_IRQ_WAIT 0x17
#define DRM_RADEON_CP_RESUME 0x18
#define DRM_RADEON_SETPARAM 0x19
#define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39
#define RADEON_FRONT 0x1
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
#define RADEON_CLEAR_X1 0
#define RADEON_CLEAR_Y1 1
#define RADEON_CLEAR_X2 2
#define RADEON_CLEAR_Y2 3
#define RADEON_CLEAR_DEPTH 4
typedef struct {
enum {
DRM_RADEON_INIT_CP = 0x01,
DRM_RADEON_CLEANUP_CP = 0x02,
DRM_RADEON_INIT_R200_CP = 0x03
} func;
unsigned long sarea_priv_offset;
int is_pci;
int cp_mode;
int gart_size;
int ring_size;
int usec_timeout;
unsigned int fb_bpp;
unsigned int front_offset, front_pitch;
unsigned int back_offset, back_pitch;
unsigned int depth_bpp;
unsigned int depth_offset, depth_pitch;
unsigned long fb_offset;
unsigned long mmio_offset;
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long gart_textures_offset;
} drmRadeonInit;
typedef struct {
int flush;
int idle;
} drmRadeonCPStop;
typedef struct {
int idx;
int start;
int end;
int discard;
} drmRadeonIndirect;
typedef union drmRadeonClearR {
float f[5];
unsigned int ui[5];
} drmRadeonClearRect;
typedef struct drmRadeonClearT {
unsigned int flags;
unsigned int clear_color;
unsigned int clear_depth;
unsigned int color_mask;
unsigned int depth_mask; /* misnamed field: should be stencil */
drmRadeonClearRect *depth_boxes;
} drmRadeonClearType;
typedef struct drmRadeonFullscreenT {
enum {
RADEON_INIT_FULLSCREEN = 0x01,
RADEON_CLEANUP_FULLSCREEN = 0x02
} func;
} drmRadeonFullscreenType;
typedef struct {
unsigned int *mask;
} drmRadeonStipple;
typedef struct {
unsigned int x;
unsigned int y;
unsigned int width;
unsigned int height;
const void *data;
} drmRadeonTexImage;
typedef struct {
unsigned int offset;
int pitch;
int format;
int width; /* Texture image coordinates */
int height;
drmRadeonTexImage *image;
} drmRadeonTexture;
#define RADEON_MAX_TEXTURE_UNITS 3
/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
*/
typedef struct {
struct {
unsigned int pp_misc; /* 0x1c14 */
unsigned int pp_fog_color;
unsigned int re_solid_color;
unsigned int rb3d_blendcntl;
unsigned int rb3d_depthoffset;
unsigned int rb3d_depthpitch;
unsigned int rb3d_zstencilcntl;
unsigned int pp_cntl; /* 0x1c38 */
unsigned int rb3d_cntl;
unsigned int rb3d_coloroffset;
unsigned int re_width_height;
unsigned int rb3d_colorpitch;
} context;
struct {
unsigned int se_cntl;
} setup1;
struct {
unsigned int se_coord_fmt; /* 0x1c50 */
} vertex;
struct {
unsigned int re_line_pattern; /* 0x1cd0 */
unsigned int re_line_state;
unsigned int se_line_width; /* 0x1db8 */
} line;
struct {
unsigned int pp_lum_matrix; /* 0x1d00 */
unsigned int pp_rot_matrix_0; /* 0x1d58 */
unsigned int pp_rot_matrix_1;
} bumpmap;
struct {
unsigned int rb3d_stencilrefmask; /* 0x1d7c */
unsigned int rb3d_ropcntl;
unsigned int rb3d_planemask;
} mask;
struct {
unsigned int se_vport_xscale; /* 0x1d98 */
unsigned int se_vport_xoffset;
unsigned int se_vport_yscale;
unsigned int se_vport_yoffset;
unsigned int se_vport_zscale;
unsigned int se_vport_zoffset;
} viewport;
struct {
unsigned int se_cntl_status; /* 0x2140 */
} setup2;
struct {
unsigned int re_top_left; /*ignored*/ /* 0x26c0 */
unsigned int re_misc;
} misc;
struct {
unsigned int pp_txfilter;
unsigned int pp_txformat;
unsigned int pp_txoffset;
unsigned int pp_txcblend;
unsigned int pp_txablend;
unsigned int pp_tfactor;
unsigned int pp_border_color;
} texture[RADEON_MAX_TEXTURE_UNITS];
struct {
unsigned int se_zbias_factor;
unsigned int se_zbias_constant;
} zbias;
unsigned int dirty;
} drmRadeonState;
/* 1.1 vertex ioctl. Used in compatibility modes.
*/
typedef struct {
int prim;
int idx; /* Index of vertex buffer */
int count; /* Number of vertices in buffer */
int discard; /* Client finished with buffer? */
} drmRadeonVertex;
typedef struct {
unsigned int start;
unsigned int finish;
unsigned int prim:8;
unsigned int stateidx:8;
unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
unsigned int vc_format;
} drmRadeonPrim;
typedef struct {
int idx; /* Index of vertex buffer */
int discard; /* Client finished with buffer? */
int nr_states;
drmRadeonState *state;
int nr_prims;
drmRadeonPrim *prim;
} drmRadeonVertex2;
#define RADEON_MAX_STATES 16
#define RADEON_MAX_PRIMS 64
/* Command buffer. Replace with true dma stream?
*/
typedef struct {
int bufsz;
char *buf;
int nbox;
drmClipRect *boxes;
} drmRadeonCmdBuffer;
/* New style per-packet identifiers for use in cmd_buffer ioctl with
* the RADEON_EMIT_PACKET command. Comments relate new packets to old
* state bits and the packet size:
*/
#define RADEON_EMIT_PP_MISC 0 /* context/7 */
#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/6 */
#define R200_EMIT_TFACTOR_0 30 /* tf/6 */
#define R200_EMIT_VTX_FMT_0 31 /* vtx/4 */
#define R200_EMIT_VAP_CTL 32 /* vap/1 */
#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
#define R200_EMIT_PP_CUBIC_FACES_0 61
#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
#define R200_EMIT_PP_CUBIC_FACES_1 63
#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
#define R200_EMIT_PP_CUBIC_FACES_2 65
#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
#define R200_EMIT_PP_CUBIC_FACES_3 67
#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
#define R200_EMIT_PP_CUBIC_FACES_4 69
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
#define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define RADEON_MAX_STATE_PACKETS 76
/* Commands understood by cmd_buffer ioctl. More can be added but
* obviously these can't be removed or changed:
*/
#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
#define RADEON_CMD_SCALARS 2 /* emit scalar data */
#define RADEON_CMD_VECTORS 3 /* emit vector data */
#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
#define RADEON_CMD_PACKET3 5 /* emit hw packet */
#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
#define RADEON_CMD_SCALARS2 7 /* R200 stopgap */
#define RADEON_CMD_WAIT 8 /* synchronization */
typedef union {
int i;
struct {
unsigned char cmd_type, pad0, pad1, pad2;
} header;
struct {
unsigned char cmd_type, packet_id, pad0, pad1;
} packet;
struct {
unsigned char cmd_type, offset, stride, count;
} scalars;
struct {
unsigned char cmd_type, offset, stride, count;
} vectors;
struct {
unsigned char cmd_type, buf_idx, pad0, pad1;
} dma;
struct {
unsigned char cmd_type, flags, pad0, pad1;
} wait;
} drmRadeonCmdHeader;
#define RADEON_WAIT_2D 0x1
#define RADEON_WAIT_3D 0x2
typedef struct drm_radeon_getparam {
int param;
int *value;
} drmRadeonGetParam;
#define RADEON_PARAM_GART_BUFFER_OFFSET 1
#define RADEON_PARAM_LAST_FRAME 2
#define RADEON_PARAM_LAST_DISPATCH 3
#define RADEON_PARAM_LAST_CLEAR 4
#define RADEON_PARAM_IRQ_NR 5
#define RADEON_PARAM_GART_BASE 6
#define RADEON_MEM_REGION_GART 1
#define RADEON_MEM_REGION_FB 2
typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
int *region_offset; /* offset from start of fb or GART */
} drmRadeonMemAlloc;
typedef struct drm_radeon_mem_free {
int region;
int region_offset;
} drmRadeonMemFree;
typedef struct drm_radeon_mem_init_heap {
int region;
int size;
int start;
} drmRadeonMemInitHeap;
/* 1.6: Userspace can request & wait on irq's:
*/
typedef struct drm_radeon_irq_emit {
int *irq_seq;
} drmRadeonIrqEmit;
typedef struct drm_radeon_irq_wait {
int irq_seq;
} drmRadeonIrqWait;
/* 1.10: Clients tell the DRM where they think the framebuffer is located in
* the card's address space, via a new generic ioctl to set parameters
*/
typedef struct drm_radeon_set_param {
unsigned int param;
int64_t value;
} drmRadeonSetParam;
#define RADEON_SETPARAM_FB_LOCATION 1
#endif
--- NEW FILE: radeon_sarea.h ---
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.5 2002/10/30 12:52:14 alanh Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Gareth Hughes <gareth@valinux.com>
*
*/
#ifndef _RADEON_SAREA_H_
#define _RADEON_SAREA_H_
/* WARNING: If you change any of these defines, make sure to change the
* defines in the kernel file (radeon_drm.h)
*/
#ifndef __RADEON_SAREA_DEFINES__
#define __RADEON_SAREA_DEFINES__
/* What needs to be changed for the current vertex buffer? */
#define RADEON_UPLOAD_CONTEXT 0x00000001
#define RADEON_UPLOAD_VERTFMT 0x00000002
#define RADEON_UPLOAD_LINE 0x00000004
#define RADEON_UPLOAD_BUMPMAP 0x00000008
#define RADEON_UPLOAD_MASKS 0x00000010
#define RADEON_UPLOAD_VIEWPORT 0x00000020
#define RADEON_UPLOAD_SETUP 0x00000040
#define RADEON_UPLOAD_TCL 0x00000080
#define RADEON_UPLOAD_MISC 0x00000100
#define RADEON_UPLOAD_TEX0 0x00000200
#define RADEON_UPLOAD_TEX1 0x00000400
#define RADEON_UPLOAD_TEX2 0x00000800
#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
#define RADEON_REQUIRE_QUIESCENCE 0x00010000
#define RADEON_UPLOAD_ZBIAS 0x00020000
#define RADEON_UPLOAD_ALL 0x0002ffff
#define RADEON_UPLOAD_CONTEXT_ALL 0x000201ff
#define RADEON_FRONT 0x1
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
/* Primitive types */
#define RADEON_POINTS 0x1
#define RADEON_LINES 0x2
#define RADEON_LINE_STRIP 0x3
#define RADEON_TRIANGLES 0x4
#define RADEON_TRIANGLE_FAN 0x5
#define RADEON_TRIANGLE_STRIP 0x6
#define RADEON_3VTX_POINTS 0x9
#define RADEON_3VTX_LINES 0xa
/* Vertex/indirect buffer size */
#define RADEON_BUFFER_SIZE 65536
/* Byte offsets for indirect buffer data */
#define RADEON_INDEX_PRIM_OFFSET 20
#define RADEON_HOSTDATA_BLIT_OFFSET 32
#define RADEON_SCRATCH_REG_OFFSET 32
/* Keep these small for testing */
#define RADEON_NR_SAREA_CLIPRECTS 12
#define RADEON_MAX_TEXTURE_LEVELS 12
#define RADEON_MAX_TEXTURE_UNITS 3
/* Blits have strict offset rules. All blit offset must be aligned on
* a 1K-byte boundary.
*/
#define RADEON_OFFSET_SHIFT 10
#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
#endif /* __RADEON_SAREA_DEFINES__ */
typedef struct {
unsigned int red;
unsigned int green;
unsigned int blue;
unsigned int alpha;
} radeon_color_regs_t;
typedef struct {
/* Context state */
unsigned int pp_misc;
unsigned int pp_fog_color;
unsigned int re_solid_color;
unsigned int rb3d_blendcntl;
unsigned int rb3d_depthoffset;
unsigned int rb3d_depthpitch;
unsigned int rb3d_zstencilcntl;
unsigned int pp_cntl;
unsigned int rb3d_cntl;
unsigned int rb3d_coloroffset;
unsigned int re_width_height;
unsigned int rb3d_colorpitch;
unsigned int se_cntl;
/* Vertex format state */
unsigned int se_coord_fmt;
/* Line state */
unsigned int re_line_pattern;
unsigned int re_line_state;
unsigned int se_line_width;
/* Bumpmap state */
unsigned int pp_lum_matrix;
unsigned int pp_rot_matrix_0;
unsigned int pp_rot_matrix_1;
/* Mask state */
unsigned int rb3d_stencilrefmask;
unsigned int rb3d_ropcntl;
unsigned int rb3d_planemask;
/* Viewport state */
unsigned int se_vport_xscale;
unsigned int se_vport_xoffset;
unsigned int se_vport_yscale;
unsigned int se_vport_yoffset;
unsigned int se_vport_zscale;
unsigned int se_vport_zoffset;
/* Setup state */
unsigned int se_cntl_status;
/* Misc state */
unsigned int re_top_left;
unsigned int re_misc;
} radeon_context_regs_t;
/* Setup registers for each texture unit */
typedef struct {
unsigned int pp_txfilter;
unsigned int pp_txformat;
unsigned int pp_txoffset;
unsigned int pp_txcblend;
unsigned int pp_txablend;
unsigned int pp_tfactor;
unsigned int pp_border_color;
} radeon_texture_regs_t;
typedef struct {
/* The channel for communication of state information to the kernel
* on firing a vertex buffer.
*/
radeon_context_regs_t ContextState;
radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
unsigned int dirty;
unsigned int vertsize;
unsigned int vc_format;
/* The current cliprects, or a subset thereof */
XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
unsigned int nbox;
/* Counters for throttling of rendering clients */
unsigned int last_frame;
unsigned int last_dispatch;
unsigned int last_clear;
/* Maintain an LRU of contiguous regions of texture space. If you
* think you own a region of texture memory, and it has an age
* different to the one you set, then you are mistaken and it has
* been stolen by another client. If global texAge hasn't changed,
* there is no need to walk the list.
*
* These regions can be used as a proxy for the fine-grained texture
* information of other clients - by maintaining them in the same
* lru which is used to age their own textures, clients have an
* approximate lru for the whole of global texture space, and can
* make informed decisions as to which areas to kick out. There is
* no need to choose whether to kick out your own texture or someone
* else's - simply eject them all in LRU order.
*/
/* Last elt is sentinal */
drmTextureRegion texList[ATI_NR_TEX_HEAPS][ATI_NR_TEX_REGIONS+1];
/* last time texture was uploaded */
unsigned int texAge[ATI_NR_TEX_HEAPS];
int ctxOwner; /* last context to upload state */
int pfAllowPageFlip; /* set by the 2d driver, read by the client */
int pfCurrentPage; /* set by kernel, read by others */
int crtc2_base; /* for pageflipping with CloneMode */
} RADEONSAREAPriv, *RADEONSAREAPrivPtr;
#endif
Index: Makefile.am
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/Makefile.am,v
retrieving revision 1.2
retrieving revision 1.2.2.1
diff -u -d -r1.2 -r1.2.2.1
--- Makefile.am 1 Dec 2003 04:33:33 -0000 1.2
+++ Makefile.am 1 Dec 2003 22:56:06 -0000 1.2.2.1
@@ -1,3 +1,17 @@
+if DRI
+DRI_INCLUDES = -I$(top_srcdir)/dri \
+ -I$(top_srcdir)/drm
+DRI_LIBS = $(top_builddir)/dri/libdri.a \
+ $(top_builddir)/drm/libdrm.a
+DRI_SOURCES = ati_dri.c \
+ ati_dri.h \
+ ati_dripriv.h \
+ r128_common.h \
+ r128_sarea.h \
+ radeon_common.h \
+ radeon_sarea.h
+endif
+
if KDRIVEFBDEV
FBDEV_INCLUDES =-I$(top_srcdir)/hw/kdrive/fbdev
FBDEV_LIBS = $(top_builddir)/hw/kdrive/fbdev/libfbdev.a
@@ -8,9 +22,9 @@
VESA_LIBS = $(top_builddir)/hw/kdrive/vesa/libvesa.a
endif
-
INCLUDES = \
@KDRIVE_INCS@ \
+ $(DRI_INCLUDES) \
$(FBDEV_INCLUDES) \
$(VESA_INCLUDES) \
@XSERVER_CFLAGS@
@@ -25,15 +39,19 @@
libati_a_SOURCES = \
ati_draw.c \
+ ati_draw.h \
+ ati_drawtmp.h \
ati.c \
ati.h \
- ati_reg.h
+ ati_reg.h \
+ $(DRI_SOURCES)
Xati_SOURCES = \
ati_stub.c
Xati_LDADD = \
libati.a \
+ $(DRI_LIBS) \
$(FBDEV_LIBS) \
$(VESA_LIBS) \
@KDRIVE_LIBS@ \
Index: ati.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati.c,v
retrieving revision 1.7
retrieving revision 1.7.2.1
diff -u -d -r1.7 -r1.7.2.1
--- ati.c 1 Dec 2003 04:33:33 -0000 1.7
+++ ati.c 1 Dec 2003 22:56:06 -0000 1.7.2.1
@@ -27,130 +27,140 @@
#include <config.h>
#endif
#include "ati.h"
+#include "ati_reg.h"
-struct pci_id_list radeon_id_list[] = {
- {0x1002, 0x4136, "ATI Radeon RS100"},
- {0x1002, 0x4137, "ATI Radeon RS200"},
- {0x1002, 0x4237, "ATI Radeon RS250"},
- {0x1002, 0x4144, "ATI Radeon R300 AD"},
- {0x1002, 0x4145, "ATI Radeon R300 AE"},
- {0x1002, 0x4146, "ATI Radeon R300 AF"},
- {0x1002, 0x4147, "ATI Radeon R300 AG"},
- {0x1002, 0x4148, "ATI Radeon R350 AH"},
- {0x1002, 0x4149, "ATI Radeon R350 AI"},
- {0x1002, 0x414a, "ATI Radeon R350 AJ"},
- {0x1002, 0x414b, "ATI Radeon R350 AK"},
- {0x1002, 0x4150, "ATI Radeon RV350 AP"},
- {0x1002, 0x4151, "ATI Radeon RV350 AQ"},
- {0x1002, 0x4152, "ATI Radeon RV350 AR"},
- {0x1002, 0x4153, "ATI Radeon RV350 AS"},
- {0x1002, 0x4154, "ATI Radeon RV350 AT"},
- {0x1002, 0x4156, "ATI Radeon RV350 AV"},
- {0x1002, 0x4242, "ATI Radeon R200 BB"},
- {0x1002, 0x4243, "ATI Radeon R200 BC"},
- {0x1002, 0x4336, "ATI Radeon RS100"},
- {0x1002, 0x4337, "ATI Radeon RS200"},
- {0x1002, 0x4437, "ATI Radeon RS250"},
- {0x1002, 0x4964, "ATI Radeon RV250 Id"},
- {0x1002, 0x4965, "ATI Radeon RV250 Ie"},
- {0x1002, 0x4966, "ATI Radeon RV250 If"},
- {0x1002, 0x4967, "ATI Radeon RV250 Ig"},
- {0x1002, 0x4c57, "ATI Radeon RV200 LW"},
- {0x1002, 0x4c58, "ATI Radeon RV200 LX"},
- {0x1002, 0x4c59, "ATI Radeon Mobility M6 LY"},
- {0x1002, 0x4c5a, "ATI Radeon Mobility LZ"},
- {0x1002, 0x4c64, "ATI Radeon RV250 Ld"},
- {0x1002, 0x4c65, "ATI Radeon RV250 Le"},
- {0x1002, 0x4c66, "ATI Radeon Mobility M9 RV250 Lf"},
- {0x1002, 0x4c67, "ATI Radeon RV250 Lg"},
- {0x1002, 0x4e44, "ATI Radeon R300 ND"},
- {0x1002, 0x4e45, "ATI Radeon R300 NE"},
- {0x1002, 0x4e46, "ATI Radeon R300 NF"},
- {0x1002, 0x4e47, "ATI Radeon R300 NG"},
- {0x1002, 0x4e48, "ATI Radeon R350 NH"},
- {0x1002, 0x4e49, "ATI Radeon R350 NI"},
- {0x1002, 0x4e4a, "ATI Radeon R350 NJ"},
- {0x1002, 0x4e4b, "ATI Radeon R350 NK"},
- {0x1002, 0x4e50, "ATI Radeon Mobility RV350 NP"},
- {0x1002, 0x4e51, "ATI Radeon Mobility RV350 NQ"},
- {0x1002, 0x4e52, "ATI Radeon Mobility RV350 NR"},
- {0x1002, 0x4e53, "ATI Radeon Mobility RV350 NS"},
- {0x1002, 0x4e54, "ATI Radeon Mobility RV350 NT"},
- {0x1002, 0x4e56, "ATI Radeon Mobility RV350 NV"},
- {0x1002, 0x5144, "ATI Radeon R100 QD"},
- {0x1002, 0x5145, "ATI Radeon R100 QE"},
- {0x1002, 0x5146, "ATI Radeon R100 QF"},
- {0x1002, 0x5147, "ATI Radeon R100 QG"},
- {0x1002, 0x5148, "ATI Radeon R200 QH"},
- {0x1002, 0x514c, "ATI Radeon R200 QL"},
- {0x1002, 0x514d, "ATI Radeon R200 QM"},
- {0x1002, 0x5157, "ATI Radeon RV200 QW"},
- {0x1002, 0x5158, "ATI Radeon RV200 QX"},
- {0x1002, 0x5159, "ATI Radeon RV100 QY"},
- {0x1002, 0x515a, "ATI Radeon RV100 QZ"},
- {0x1002, 0x5834, "ATI Radeon RS300"},
- {0x1002, 0x5835, "ATI Radeon Mobility RS300"},
- {0x1002, 0x5941, "ATI Radeon RV280 (9200)"},
- {0x1002, 0x5961, "ATI Radeon RV280 (9200 SE)"},
- {0x1002, 0x5964, "ATI Radeon RV280 (9200 SE)"},
- {0x1002, 0x5c60, "ATI Radeon RV280"},
- {0x1002, 0x5c61, "ATI Mobility Radeon RV280"},
- {0x1002, 0x5c62, "ATI Radeon RV280"},
- {0x1002, 0x5c63, "ATI Mobility Radeon RV280"},
- {0x1002, 0x5c64, "ATI Radeon RV280"},
- {0, 0, NULL}
+struct pci_id_entry ati_pci_ids[] = {
+ {0x1002, 0x4136, 0x1, "ATI Radeon RS100"},
+ {0x1002, 0x4137, 0x3, "ATI Radeon RS200"},
+ {0x1002, 0x4237, 0x3, "ATI Radeon RS250"},
+ {0x1002, 0x4144, 0x5, "ATI Radeon R300 AD"},
+ {0x1002, 0x4145, 0x5, "ATI Radeon R300 AE"},
+ {0x1002, 0x4146, 0x5, "ATI Radeon R300 AF"},
+ {0x1002, 0x4147, 0x5, "ATI Radeon R300 AG"},
+ {0x1002, 0x4148, 0x5, "ATI Radeon R350 AH"},
+ {0x1002, 0x4149, 0x5, "ATI Radeon R350 AI"},
+ {0x1002, 0x414a, 0x5, "ATI Radeon R350 AJ"},
+ {0x1002, 0x414b, 0x5, "ATI Radeon R350 AK"},
+ {0x1002, 0x4150, 0x5, "ATI Radeon RV350 AP"},
+ {0x1002, 0x4151, 0x5, "ATI Radeon RV350 AQ"},
+ {0x1002, 0x4152, 0x5, "ATI Radeon RV350 AR"},
+ {0x1002, 0x4153, 0x5, "ATI Radeon RV350 AS"},
+ {0x1002, 0x4154, 0x5, "ATI Radeon RV350 AT"},
+ {0x1002, 0x4156, 0x5, "ATI Radeon RV350 AV"},
+ {0x1002, 0x4242, 0x3, "ATI Radeon R200 BB"},
+ {0x1002, 0x4243, 0x3, "ATI Radeon R200 BC"},
+ {0x1002, 0x4336, 0x1, "ATI Radeon RS100"},
+ {0x1002, 0x4337, 0x3, "ATI Radeon RS200"},
+ {0x1002, 0x4437, 0x3, "ATI Radeon RS250"},
+ {0x1002, 0x4964, 0x3, "ATI Radeon RV250 Id"},
+ {0x1002, 0x4965, 0x3, "ATI Radeon RV250 Ie"},
+ {0x1002, 0x4966, 0x3, "ATI Radeon RV250 If"},
+ {0x1002, 0x4967, 0x3, "ATI Radeon RV250 Ig"},
+ {0x1002, 0x4c45, 0x0, "ATI Rage 128 LE"},
+ {0x1002, 0x4c46, 0x0, "ATI Rage 128 LF"},
+ {0x1002, 0x4c57, 0x3, "ATI Radeon RV200 LW"},
+ {0x1002, 0x4c58, 0x3, "ATI Radeon RV200 LX"},
+ {0x1002, 0x4c59, 0x3, "ATI Radeon Mobility M6 LY"},
+ {0x1002, 0x4c5a, 0x3, "ATI Radeon Mobility LZ"},
+ {0x1002, 0x4c64, 0x3, "ATI Radeon RV250 Ld"},
+ {0x1002, 0x4c65, 0x3, "ATI Radeon RV250 Le"},
+ {0x1002, 0x4c66, 0x3, "ATI Radeon Mobility M9 RV250 Lf"},
+ {0x1002, 0x4c67, 0x3, "ATI Radeon RV250 Lg"},
+ {0x1002, 0x4d46, 0x0, "ATI Rage 128 MF"},
+ {0x1002, 0x4d46, 0x0, "ATI Rage 128 ML"},
+ {0x1002, 0x4e44, 0x5, "ATI Radeon R300 ND"},
+ {0x1002, 0x4e45, 0x5, "ATI Radeon R300 NE"},
+ {0x1002, 0x4e46, 0x5, "ATI Radeon R300 NF"},
+ {0x1002, 0x4e47, 0x5, "ATI Radeon R300 NG"},
+ {0x1002, 0x4e48, 0x5, "ATI Radeon R350 NH"},
+ {0x1002, 0x4e49, 0x5, "ATI Radeon R350 NI"},
+ {0x1002, 0x4e4a, 0x5, "ATI Radeon R350 NJ"},
+ {0x1002, 0x4e4b, 0x5, "ATI Radeon R350 NK"},
+ {0x1002, 0x4e50, 0x5, "ATI Radeon Mobility RV350 NP"},
+ {0x1002, 0x4e51, 0x5, "ATI Radeon Mobility RV350 NQ"},
+ {0x1002, 0x4e52, 0x5, "ATI Radeon Mobility RV350 NR"},
+ {0x1002, 0x4e53, 0x5, "ATI Radeon Mobility RV350 NS"},
+ {0x1002, 0x4e54, 0x5, "ATI Radeon Mobility RV350 NT"},
+ {0x1002, 0x4e56, 0x5, "ATI Radeon Mobility RV350 NV"},
+ {0x1002, 0x5041, 0x0, "ATI Rage 128 PA"},
+ {0x1002, 0x5042, 0x0, "ATI Rage 128 PB"},
+ {0x1002, 0x5043, 0x0, "ATI Rage 128 PC"},
+ {0x1002, 0x5044, 0x0, "ATI Rage 128 PD"},
+ {0x1002, 0x5045, 0x0, "ATI Rage 128 PE"},
+ {0x1002, 0x5046, 0x0, "ATI Rage 128 PF"},
+ {0x1002, 0x5047, 0x0, "ATI Rage 128 PG"},
+ {0x1002, 0x5048, 0x0, "ATI Rage 128 PH"},
+ {0x1002, 0x5049, 0x0, "ATI Rage 128 PI"},
+ {0x1002, 0x504a, 0x0, "ATI Rage 128 PJ"},
+ {0x1002, 0x504b, 0x0, "ATI Rage 128 PK"},
+ {0x1002, 0x504c, 0x0, "ATI Rage 128 PL"},
+ {0x1002, 0x504d, 0x0, "ATI Rage 128 PM"},
+ {0x1002, 0x504e, 0x0, "ATI Rage 128 PN"},
+ {0x1002, 0x504f, 0x0, "ATI Rage 128 PO"},
+ {0x1002, 0x5050, 0x0, "ATI Rage 128 PP"},
+ {0x1002, 0x5051, 0x0, "ATI Rage 128 PQ"},
+ {0x1002, 0x5052, 0x0, "ATI Rage 128 PR"},
+ {0x1002, 0x5053, 0x0, "ATI Rage 128 PS"},
+ {0x1002, 0x5054, 0x0, "ATI Rage 128 PT"},
+ {0x1002, 0x5055, 0x0, "ATI Rage 128 PU"},
+ {0x1002, 0x5056, 0x0, "ATI Rage 128 PV"},
+ {0x1002, 0x5057, 0x0, "ATI Rage 128 PW"},
+ {0x1002, 0x5058, 0x0, "ATI Rage 128 PX"},
+ {0x1002, 0x5144, 0x1, "ATI Radeon R100 QD"},
+ {0x1002, 0x5145, 0x1, "ATI Radeon R100 QE"},
+ {0x1002, 0x5146, 0x1, "ATI Radeon R100 QF"},
+ {0x1002, 0x5147, 0x1, "ATI Radeon R100 QG"},
+ {0x1002, 0x5148, 0x1, "ATI Radeon R200 QH"},
+ {0x1002, 0x514c, 0x1, "ATI Radeon R200 QL"},
+ {0x1002, 0x514d, 0x1, "ATI Radeon R200 QM"},
+ {0x1002, 0x5157, 0x1, "ATI Radeon RV200 QW"},
+ {0x1002, 0x5158, 0x1, "ATI Radeon RV200 QX"},
+ {0x1002, 0x5159, 0x1, "ATI Radeon RV100 QY"},
+ {0x1002, 0x515a, 0x1, "ATI Radeon RV100 QZ"},
+ {0x1002, 0x5245, 0x0, "ATI Rage 128 RE"},
+ {0x1002, 0x5246, 0x0, "ATI Rage 128 RF"},
+ {0x1002, 0x5247, 0x0, "ATI Rage 128 RG"},
+ {0x1002, 0x524b, 0x0, "ATI Rage 128 RK"},
+ {0x1002, 0x524c, 0x0, "ATI Rage 128 RL"},
+ {0x1002, 0x5345, 0x0, "ATI Rage 128 SE"},
+ {0x1002, 0x5346, 0x0, "ATI Rage 128 SF"},
+ {0x1002, 0x5347, 0x0, "ATI Rage 128 SG"},
+ {0x1002, 0x5348, 0x0, "ATI Rage 128 SH"},
+ {0x1002, 0x534b, 0x0, "ATI Rage 128 SK"},
+ {0x1002, 0x534c, 0x0, "ATI Rage 128 SL"},
+ {0x1002, 0x534d, 0x0, "ATI Rage 128 SM"},
+ {0x1002, 0x534e, 0x0, "ATI Rage 128 SN"},
+ {0x1002, 0x5446, 0x0, "ATI Rage 128 TF"},
+ {0x1002, 0x544c, 0x0, "ATI Rage 128 TL"},
+ {0x1002, 0x5452, 0x0, "ATI Rage 128 TR"},
+ {0x1002, 0x5453, 0x0, "ATI Rage 128 TS"},
+ {0x1002, 0x5454, 0x0, "ATI Rage 128 TT"},
+ {0x1002, 0x5455, 0x0, "ATI Rage 128 TU"},
+ {0x1002, 0x5834, 0x5, "ATI Radeon RS300"},
+ {0x1002, 0x5835, 0x5, "ATI Radeon RS300 Mobility"},
+ {0x1002, 0x5941, 0x3, "ATI Radeon RV280 (9200)"},
+ {0x1002, 0x5961, 0x3, "ATI Radeon RV280 (9200 SE)"},
+ {0x1002, 0x5964, 0x3, "ATI Radeon RV280 (9200 SE)"},
+ {0x1002, 0x5c60, 0x3, "ATI Radeon RV280"},
+ {0x1002, 0x5c61, 0x3, "ATI Radeon RV280 Mobility"},
+ {0x1002, 0x5c62, 0x3, "ATI Radeon RV280"},
+ {0x1002, 0x5c63, 0x3, "ATI Radeon RV280 Mobility"},
+ {0x1002, 0x5c64, 0x3, "ATI Radeon RV280"},
+ {0, 0, 0, NULL}
};
-struct pci_id_list r128_id_list[] = {
- {0x1002, 0x4c45, "ATI Rage 128 LE"},
- {0x1002, 0x4c46, "ATI Rage 128 LF"},
- {0x1002, 0x4d46, "ATI Rage 128 MF"},
- {0x1002, 0x4d46, "ATI Rage 128 ML"},
- {0x1002, 0x5041, "ATI Rage 128 PA"},
- {0x1002, 0x5042, "ATI Rage 128 PB"},
- {0x1002, 0x5043, "ATI Rage 128 PC"},
- {0x1002, 0x5044, "ATI Rage 128 PD"},
- {0x1002, 0x5045, "ATI Rage 128 PE"},
- {0x1002, 0x5046, "ATI Rage 128 PF"},
- {0x1002, 0x5047, "ATI Rage 128 PG"},
- {0x1002, 0x5048, "ATI Rage 128 PH"},
- {0x1002, 0x5049, "ATI Rage 128 PI"},
- {0x1002, 0x504a, "ATI Rage 128 PJ"},
- {0x1002, 0x504b, "ATI Rage 128 PK"},
- {0x1002, 0x504c, "ATI Rage 128 PL"},
- {0x1002, 0x504d, "ATI Rage 128 PM"},
- {0x1002, 0x504e, "ATI Rage 128 PN"},
- {0x1002, 0x504f, "ATI Rage 128 PO"},
- {0x1002, 0x5050, "ATI Rage 128 PP"},
- {0x1002, 0x5051, "ATI Rage 128 PQ"},
- {0x1002, 0x5052, "ATI Rage 128 PR"},
- {0x1002, 0x5053, "ATI Rage 128 PS"},
- {0x1002, 0x5054, "ATI Rage 128 PT"},
- {0x1002, 0x5055, "ATI Rage 128 PU"},
- {0x1002, 0x5056, "ATI Rage 128 PV"},
- {0x1002, 0x5057, "ATI Rage 128 PW"},
- {0x1002, 0x5058, "ATI Rage 128 PX"},
- {0x1002, 0x5245, "ATI Rage 128 RE"},
- {0x1002, 0x5246, "ATI Rage 128 RF"},
- {0x1002, 0x5247, "ATI Rage 128 RG"},
- {0x1002, 0x524b, "ATI Rage 128 RK"},
- {0x1002, 0x524c, "ATI Rage 128 RL"},
- {0x1002, 0x5345, "ATI Rage 128 SE"},
- {0x1002, 0x5346, "ATI Rage 128 SF"},
- {0x1002, 0x5347, "ATI Rage 128 SG"},
- {0x1002, 0x5348, "ATI Rage 128 SH"},
- {0x1002, 0x534b, "ATI Rage 128 SK"},
- {0x1002, 0x534c, "ATI Rage 128 SL"},
- {0x1002, 0x534d, "ATI Rage 128 SM"},
- {0x1002, 0x534e, "ATI Rage 128 SN"},
- {0x1002, 0x5446, "ATI Rage 128 TF"},
- {0x1002, 0x544c, "ATI Rage 128 TL"},
- {0x1002, 0x5452, "ATI Rage 128 TR"},
- {0x1002, 0x5453, "ATI Rage 128 TS"},
- {0x1002, 0x5454, "ATI Rage 128 TT"},
- {0x1002, 0x5455, "ATI Rage 128 TU"},
- {0, 0, NULL}
-};
+static char *
+make_busid(KdCardAttr *attr)
+{
+ char *busid;
+
+ busid = xalloc(20);
+ if (busid == NULL)
+ return NULL;
+ snprintf(busid, 20, "pci:%04x:%02x:%02x.%d", attr->domain, attr->bus,
+ attr->slot, attr->func);
+ return busid;
+}
static Bool
ATICardInit(KdCardInfo *card)
@@ -205,11 +215,28 @@
return FALSE;
}
+ atic->busid = make_busid(&card->attr);
+ if (atic->busid == NULL)
+ return FALSE;
+
+#ifdef USE_DRI
+ /* We demand identification by busid, not driver name */
+ atic->drmFd = drmOpen(NULL, atic->busid);
+ if (atic->drmFd < 0)
+ ErrorF("Failed to open DRM. DMA won't be used.\n");
+#endif /* USE_DRI */
+
card->driver = atic;
- for (i = 0; radeon_id_list[i].name != NULL; i++) {
- if (radeon_id_list[i].device == card->attr.deviceID)
- atic->is_radeon = TRUE;
+ for (i = 0; ati_pci_ids[i].name != NULL; i++) {
+ struct pci_id_entry *id = &ati_pci_ids[i];
+ if (id->device == card->attr.deviceID) {
+ if (id->caps & CAP_RADEON) {
+ if (id->caps & CAP_R200)
+ atic->is_r200 = TRUE;
+ atic->is_radeon = TRUE;
+ }
+ }
}
return TRUE;
}
@@ -227,15 +254,14 @@
ATIScreenInit(KdScreenInfo *screen)
{
ATIScreenInfo *atis;
- ATICardInfo *atic = screen->card->driver;
+ ATICardInfo(screen);
int success = FALSE;
atis = xcalloc(sizeof(ATIScreenInfo), 1);
if (atis == NULL)
return FALSE;
- if (screen->fb[0].depth == 0)
- screen->fb[0].depth = 16;
+ atis->atic = atic;
screen->driver = atis;
Index: ati.h
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati.h,v
retrieving revision 1.3
retrieving revision 1.3.2.1
diff -u -d -r1.3 -r1.3.2.1
--- ati.h 1 Dec 2003 04:33:33 -0000 1.3
+++ ati.h 1 Dec 2003 22:56:06 -0000 1.3.2.1
@@ -35,8 +35,14 @@
#include <vesa.h>
#endif
+#ifdef XF86DRI
+#define USE_DRI
+#include "libdrm.h"
+#include "dri.h"
+#endif
+
#define RADEON_REG_BASE(c) ((c)->attr.address[1])
-#define RADEON_REG_SIZE(c) (0x10000)
+#define RADEON_REG_SIZE(c) (0x4000)
#ifdef __powerpc__
@@ -75,9 +81,14 @@
typedef volatile CARD16 VOL16;
typedef volatile CARD32 VOL32;
-struct pci_id_list {
+#define CAP_RADEON 0x1 /* Whether it's a Radeon vs R128 */
+#define CAP_R200 0x2 /* If CAP_RADEON, whether it's an R200 */
+#define CAP_NODRM 0x4 /* Set if no initialization for the DRM yet. */
+
+struct pci_id_entry {
CARD16 vendor;
CARD16 device;
+ CARD8 caps;
char *name;
};
@@ -107,8 +118,14 @@
} backend_priv;
struct backend_funcs backend_funcs;
+ struct pci_id_entry *pci_id;
CARD8 *reg_base;
Bool is_radeon;
+ Bool is_r200;
+ char *busid;
+#ifdef USE_DRI
+ int drmFd;
+#endif /* USE_DRI */
Bool use_fbdev, use_vesa;
} ATICardInfo;
@@ -124,9 +141,96 @@
VesaScreenPrivRec vesa;
#endif
} backend_priv;
+ KaaScreenInfoRec kaa;
+ ATICardInfo *atic;
+
+ Bool using_dri;
+ Bool using_dma;
+ /* If is_24bpp is set, then we are using the accelerator in 8-bit mode due
+ * to it being broken for 24bpp, so coordinates have to be multiplied by 3.
+ */
+ Bool is_24bpp;
int datatype;
int dp_gui_master_cntl;
+
+#ifdef USE_DRI
+ drmSize registerSize;
+ drmHandle registerHandle;
+ drmHandle fbHandle;
+
+ int IsAGP;
+ drmSize gartSize;
+ drmHandle agpMemHandle; /* Handle from drmAgpAlloc */
+ unsigned long gartOffset;
+ unsigned char *AGP; /* Map */
+ int agpMode;
+ drmSize pciSize;
+ drmHandle pciMemHandle;
+
+ /* ring buffer data */
+ unsigned long ringStart; /* Offset into AGP space */
+ drmHandle ringHandle; /* Handle from drmAddMap */
+ drmSize ringMapSize; /* Size of map */
+ int ringSize; /* Size of ring (MB) */
+ unsigned char *ring; /* Map */
+
+ unsigned long ringReadOffset; /* Offset into AGP space */
+ drmHandle ringReadPtrHandle; /* Handle from drmAddMap */
+ drmSize ringReadMapSize; /* Size of map */
+ unsigned char *ringReadPtr; /* Map */
+
+ /* vertex/indirect buffer data */
+ unsigned long bufStart; /* Offset into AGP space */
+ drmHandle bufHandle; /* Handle from drmAddMap */
+ drmSize bufMapSize; /* Size of map */
+ int bufSize; /* Size of buffers (MB) */
+ unsigned char *buf; /* Map */
+ int bufNumBufs; /* Number of buffers */
+ drmBufMapPtr buffers; /* Buffer map */
+
+ /* AGP Texture data */
+ unsigned long gartTexStart; /* Offset into AGP space */
+ drmHandle gartTexHandle; /* Handle from drmAddMap */
+ drmSize gartTexMapSize; /* Size of map */
+ int gartTexSize; /* Size of AGP tex space (MB) */
+ unsigned char *gartTex; /* Map */
+ int log2GARTTexGran;
+
+ int CCEMode; /* CCE mode that server/clients use */
+ int CPMode; /* CP mode that server/clients use */
+ int CCEFifoSize; /* Size of the CCE command FIFO */
+ int DMAusecTimeout; /* CCE timeout in usecs */
+
+ /* DMA 2D accleration */
+ drmBufPtr indirectBuffer;
+ int indirectStart;
+
+ /* DRI screen private data */
+ int fbX;
+ int fbY;
+ int backX;
+ int backY;
+ int depthX;
+ int depthY;
+
+ int frontOffset;
+ int frontPitch;
+ int backOffset;
+ int backPitch;
+ int depthOffset;
+ int depthPitch;
+ int spanOffset;
+ int textureOffset;
+ int textureSize;
+ int log2TexGran;
+
+ int irqEnabled;
+
+ int serverContext;
+
+ DRIInfoPtr pDRIInfo;
+#endif /* USE_DRI */
} ATIScreenInfo;
#define getATIScreenInfo(kd) ((ATIScreenInfo *) ((kd)->screen->driver))
@@ -156,6 +260,14 @@
void
ATIDrawFini(ScreenPtr pScreen);
+#ifdef USE_DRI
+Bool
+ATIDRIScreenInit(ScreenPtr pScreen);
+
+void
+ATIDRICloseScreen(ScreenPtr pScreen);
+#endif /* USE_DRI */
+
extern KdCardFuncs ATIFuncs;
#endif /* _ATI_H_ */
Index: ati_draw.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_draw.c,v
retrieving revision 1.5
retrieving revision 1.5.2.1
diff -u -d -r1.5 -r1.5.2.1
--- ati_draw.c 1 Dec 2003 01:46:38 -0000 1.5
+++ ati_draw.c 1 Dec 2003 22:56:06 -0000 1.5.2.1
@@ -28,6 +28,12 @@
#endif
#include "ati.h"
#include "ati_reg.h"
+#include "ati_draw.h"
+#ifdef USE_DRI
+#include "radeon_common.h"
+#include "r128_common.h"
+#include "ati_sarea.h"
+#endif /* USE_DRI */
CARD8 ATISolidRop[16] = {
/* GXclear */ 0x00, /* 0 */
@@ -68,23 +74,20 @@
};
int copydx, copydy;
-Bool is_radeon;
-/* If is_24bpp is set, then we are using the accelerator in 8-bit mode due
- * to it being broken for 24bpp, so coordinates have to be multiplied by 3.
- */
-Bool is_24bpp;
int fifo_size;
-char *mmio;
-CARD32 bltCmd;
+ATIScreenInfo *accel_atis;
static void
-ATIWaitAvail(int n)
+ATIWaitAvailMMIO(int n)
{
+ ATICardInfo *atic = accel_atis->atic;
+ char *mmio = atic->reg_base;
+
if (fifo_size >= n) {
fifo_size -= n;
return;
}
- if (is_radeon) {
+ if (atic->is_radeon) {
do {
fifo_size = MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
RADEON_RBBM_FIFOCNT_MASK;
@@ -100,9 +103,25 @@
static void
RadeonWaitIdle(void)
{
+ ATIScreenInfo *atis = accel_atis;
+ ATICardInfo *atic = atis->atic;
+ char *mmio = atic->reg_base;
CARD32 temp;
+
+#ifdef USE_DRI
+ if (atis->using_dma) {
+ int ret;
+
+ do {
+ ret = drmCommandNone(atic->drmFd, DRM_RADEON_CP_IDLE);
+ } while (ret == -EBUSY);
+ if (ret != 0)
+ ErrorF("Failed to idle DMA, returned %d\n", ret);
+ }
+#endif /* USE_DRI */
+
/* Wait for the engine to go idle */
- ATIWaitAvail(64);
+ ATIWaitAvailMMIO(64);
while ((MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
RADEON_RBBM_ACTIVE) != 0)
@@ -121,10 +140,25 @@
static void
R128WaitIdle(void)
{
+ ATIScreenInfo *atis = accel_atis;
+ ATICardInfo *atic = atis->atic;
+ char *mmio = atic->reg_base;
CARD32 temp;
int tries;
- ATIWaitAvail(64);
+#ifdef USE_DRI
+ if (atis->using_dma) {
+ int ret;
+
+ do {
+ ret = drmCommandNone(atic->drmFd, DRM_R128_CCE_IDLE);
+ } while (ret == -EBUSY);
+ if (ret != 0)
+ ErrorF("Failed to idle DMA, returned %d\n", ret);
+ }
+#endif /* USE_DRI */
+
+ ATIWaitAvailMMIO(64);
tries = 1000000;
while (tries--) {
@@ -146,170 +180,151 @@
static void
ATIWaitIdle(void)
{
- if (is_radeon)
+ ATIScreenInfo *atis = accel_atis;
+ ATICardInfo *atic = atis->atic;
+
+#ifdef USE_DRI
+ /* Dispatch any accumulated commands first. */
+ if (atis->using_dma && atis->indirectBuffer != NULL)
+ ATIDMAFlushIndirect(0);
+#endif /* USE_DRI */
+
+ if (atic->is_radeon)
RadeonWaitIdle();
else
R128WaitIdle();
}
-static Bool
-ATISetup(PixmapPtr pDst, PixmapPtr pSrc)
+#ifdef USE_DRI
+void ATIDMAStart(ScreenPtr pScreen)
{
- KdScreenPriv(pDst->drawable.pScreen);
+ KdScreenPriv(pScreen);
ATICardInfo(pScreenPriv);
- int dst_offset, dst_pitch, src_offset = 0, src_pitch = 0;
- int bpp = pScreenPriv->screen->fb[0].bitsPerPixel;
-
- mmio = atic->reg_base;
-
- /* No acceleration for other formats (yet) */
- if (pDst->drawable.bitsPerPixel != bpp)
- return FALSE;
-
- dst_pitch = pDst->devKind;
- dst_offset = ((CARD8 *)pDst->devPrivate.ptr -
- pScreenPriv->screen->memory_base);
- if (pSrc != NULL) {
- src_pitch = pSrc->devKind;
- src_offset = ((CARD8 *)pSrc->devPrivate.ptr -
- pScreenPriv->screen->memory_base);
- }
+ ATIScreenInfo(pScreenPriv);
+ int ret;
- ATIWaitAvail((pSrc != NULL) ? 3 : 2);
- if (is_radeon) {
- MMIO_OUT32(mmio, RADEON_REG_DST_PITCH_OFFSET,
- ((dst_pitch >> 6) << 22) | (dst_offset >> 10));
- if (pSrc != NULL) {
- MMIO_OUT32(mmio, RADEON_REG_SRC_PITCH_OFFSET,
- ((src_pitch >> 6) << 22) | (src_offset >> 10));
- }
- } else {
- if (is_24bpp) {
- dst_pitch *= 3;
- src_pitch *= 3;
- }
- /* R128 pitch is in units of 8 pixels, offset in 32 bytes */
- MMIO_OUT32(mmio, RADEON_REG_DST_PITCH_OFFSET,
- ((dst_pitch/bpp) << 21) | (dst_offset >> 5));
- if (pSrc != NULL) {
- MMIO_OUT32(mmio, RADEON_REG_SRC_PITCH_OFFSET,
- ((src_pitch/bpp) << 21) | (src_offset >> 5));
- }
- }
- MMIO_OUT32(mmio, RADEON_REG_DEFAULT_SC_BOTTOM_RIGHT,
- (RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX));
+ if (atic->is_radeon)
+ ret = drmCommandNone(atic->drmFd, DRM_RADEON_CP_START);
+ else
+ ret = drmCommandNone(atic->drmFd, DRM_R128_CCE_START);
- return TRUE;
+ if (ret == 0)
+ atis->using_dma = TRUE;
+ else
+ ErrorF("%s: DMA start returned %d\n", __FUNCTION__, ret);
}
-static Bool
-ATIPrepareSolid(PixmapPtr pPixmap, int alu, Pixel pm, Pixel fg)
+/* Attempts to idle the DMA engine, and stops it. Note that the ioctl is the
+ * same for both R128 and Radeon, so we can just use the name of one of them.
+ */
+void ATIDMAStop(ScreenPtr pScreen)
{
- KdScreenPriv(pPixmap->drawable.pScreen);
+ KdScreenPriv(pScreen);
+ ATICardInfo(pScreenPriv);
ATIScreenInfo(pScreenPriv);
+ drmRadeonCPStop stop;
+ int ret;
- if (is_24bpp) {
- if (pm != 0xffffffff)
- return FALSE;
- /* Solid fills in fake-24bpp mode only work if the pixel color
- * is all the same byte.
- */
- if ((fg & 0xffffff) != (((fg & 0xff) << 16) | ((fg >> 8) &
- 0xffff)))
- return FALSE;
- }
-
- if (!ATISetup(pPixmap, NULL))
- return FALSE;
-
- ATIWaitAvail(4);
- MMIO_OUT32(mmio, RADEON_REG_DP_GUI_MASTER_CNTL,
- atis->dp_gui_master_cntl |
- RADEON_GMC_BRUSH_SOLID_COLOR |
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- (ATISolidRop[alu] << 16));
- MMIO_OUT32(mmio, RADEON_REG_DP_BRUSH_FRGD_CLR, fg);
- MMIO_OUT32(mmio, RADEON_REG_DP_WRITE_MASK, pm);
- MMIO_OUT32(mmio, RADEON_REG_DP_CNTL, RADEON_DST_X_LEFT_TO_RIGHT |
- RADEON_DST_Y_TOP_TO_BOTTOM);
+ stop.flush = 1;
+ stop.idle = 1;
+ ret = drmCommandWrite(atic->drmFd, DRM_RADEON_CP_STOP, &stop,
+ sizeof(drmRadeonCPStop));
- return TRUE;
-}
+ if (ret != 0 && errno == EBUSY) {
+ ErrorF("Failed to idle the DMA engine\n");
-static void
-ATISolid(int x1, int y1, int x2, int y2)
-{
- if (is_24bpp) {
- x1 *= 3;
- x2 *= 3;
+ stop.idle = 0;
+ ret = drmCommandWrite(atic->drmFd, DRM_RADEON_CP_STOP, &stop,
+ sizeof(drmRadeonCPStop));
}
- ATIWaitAvail(2);
- MMIO_OUT32(mmio, RADEON_REG_DST_Y_X, (y1 << 16) | x1);
- MMIO_OUT32(mmio, RADEON_REG_DST_WIDTH_HEIGHT, ((x2 - x1) << 16) |
- (y2 - y1));
+ atis->using_dma = FALSE;
}
-static void
-ATIDoneSolid(void)
+/* The R128 and Radeon Indirect ioctls differ only in the ioctl number */
+void ATIDMADispatchIndirect(Bool discard)
{
+ ATIScreenInfo *atis = accel_atis;
+ ATICardInfo *atic = atis->atic;
+ drmBufPtr buffer = atis->indirectBuffer;
+ drmR128Indirect indirect;
+ int cmd;
+
+ indirect.idx = buffer->idx;
+ indirect.start = atis->indirectStart;
+ indirect.end = buffer->used;
+ indirect.discard = discard;
+ cmd = atic->is_radeon ? DRM_RADEON_INDIRECT : DRM_R128_INDIRECT;
+ drmCommandWriteRead(atic->drmFd, cmd, &indirect,
+ sizeof(drmR128Indirect));
}
-static Bool
-ATIPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int dx, int dy, int alu, Pixel pm)
+/* Flush the indirect buffer to the kernel for submission to the card */
+void ATIDMAFlushIndirect(Bool discard)
{
- KdScreenPriv(pDst->drawable.pScreen);
- ATIScreenInfo(pScreenPriv);
+ ATIScreenInfo *atis = accel_atis;
+ drmBufPtr buffer = atis->indirectBuffer;
- copydx = dx;
- copydy = dy;
+ if (buffer == NULL)
+ return;
+ if ((atis->indirectStart == buffer->used) && !discard)
+ return;
- if (is_24bpp && pm != 0xffffffff)
- return FALSE;
+ ATIDMADispatchIndirect(discard);
- if (!ATISetup(pDst, pSrc))
- return FALSE;
+ if (discard) {
+ atis->indirectBuffer = ATIDMAGetBuffer();
+ atis->indirectStart = 0;
+ } else {
+ /* Start on a double word boundary */
+ atis->indirectStart = buffer->used = (buffer->used + 7) & ~7;
+ }
+}
- ATIWaitAvail(3);
- MMIO_OUT32(mmio, RADEON_REG_DP_GUI_MASTER_CNTL,
- atis->dp_gui_master_cntl |
- RADEON_GMC_BRUSH_SOLID_COLOR |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- (ATIBltRop[alu] << 16) |
- RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_DP_SRC_SOURCE_MEMORY);
- MMIO_OUT32(mmio, RADEON_REG_DP_WRITE_MASK, pm);
- MMIO_OUT32(mmio, RADEON_REG_DP_CNTL,
- (dx >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
- (dy >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0));
+/* Get an indirect buffer for the DMA 2D acceleration commands */
+drmBufPtr ATIDMAGetBuffer()
+{
+ ATIScreenInfo *atis = accel_atis;
+ ATICardInfo *atic = atis->atic;
+ drmDMAReq dma;
+ drmBufPtr buf = NULL;
+ int indx = 0;
+ int size = 0;
+ int ret;
- return TRUE;
+ dma.context = atis->serverContext;
+ dma.send_count = 0;
+ dma.send_list = NULL;
+ dma.send_sizes = NULL;
+ dma.flags = 0;
+ dma.request_count = 1;
+ if (atis->atic->is_radeon)
+ dma.request_size = RADEON_BUFFER_SIZE;
+ else
+ dma.request_size = R128_BUFFER_SIZE;
+ dma.request_list = &indx;
+ dma.request_sizes = &size;
+ dma.granted_count = 0;
+
+ do {
+ ret = drmDMA(atic->drmFd, &dma);
+ } while (ret != 0);
+
+ buf = &atis->buffers->list[indx];
+ buf->used = 0;
+ return buf;
}
-static void
-ATICopy(int srcX, int srcY, int dstX, int dstY, int w, int h)
-{
- if (is_24bpp) {
- srcX *= 3;
- dstX *= 3;
- w *= 3;
- }
+#define USE_DMA
+#include "ati_drawtmp.h"
- if (copydx < 0) {
- srcX += w - 1;
- dstX += w - 1;
- }
+#endif /* USE_DRI */
- if (copydy < 0) {
- srcY += h - 1;
- dstY += h - 1;
- }
+#undef USE_DMA
+#include "ati_drawtmp.h"
- ATIWaitAvail(3);
- MMIO_OUT32(mmio, RADEON_REG_SRC_Y_X, (srcY << 16) | srcX);
- MMIO_OUT32(mmio, RADEON_REG_DST_Y_X, (dstY << 16) | dstX);
- MMIO_OUT32(mmio, RADEON_REG_DST_HEIGHT_WIDTH, (h << 16) | w);
+static void
+ATIDoneSolid(void)
+{
}
static void
@@ -317,20 +332,6 @@
{
}
-static KaaScreenInfoRec ATIKaa = {
- ATIPrepareSolid,
- ATISolid,
- ATIDoneSolid,
-
- ATIPrepareCopy,
- ATICopy,
- ATIDoneCopy,
-
- 0, /* offscreenByteAlign */
- 0, /* offscreenPitch */
- KAA_OFFSCREEN_PIXMAPS, /* flags */
-};
-
Bool
ATIDrawInit(ScreenPtr pScreen)
{
@@ -338,9 +339,6 @@
ATIScreenInfo(pScreenPriv);
ATICardInfo(pScreenPriv);
- is_radeon = atic->is_radeon;
- is_24bpp = FALSE;
-
switch (pScreenPriv->screen->fb[0].depth)
{
case 8:
@@ -354,7 +352,7 @@
break;
case 24:
if (pScreenPriv->screen->fb[0].bitsPerPixel == 24) {
- is_24bpp = TRUE;
+ atis->is_24bpp = TRUE;
atis->datatype = 2;
} else {
atis->datatype = 6;
@@ -366,22 +364,52 @@
return FALSE;
}
+ ErrorF("Screen: %d/%d depth/bpp\n", pScreenPriv->screen->fb[0].depth,
+ pScreenPriv->screen->fb[0].bitsPerPixel);
+#ifdef USE_DRI
+ if (atis->using_dri)
+ ATIDMAStart(pScreen);
+ else {
+ if (ATIDRIScreenInit(pScreen))
+ atis->using_dri = TRUE;
+ }
+#endif /* USE_DRI */
+
atis->dp_gui_master_cntl = (atis->datatype << 8) |
RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_AUX_CLIP_DIS;
- if (is_radeon) {
- ATIKaa.offscreenByteAlign = 1024;
- ATIKaa.offscreenPitch = 1024;
+ memset(&atis->kaa, 0, sizeof(KaaScreenInfoRec));
+#ifdef USE_DRI
+ if (atis->using_dma) {
+ atis->kaa.PrepareSolid = ATIPrepareSolidDMA;
+ atis->kaa.Solid = ATISolidDMA;
+ atis->kaa.PrepareCopy = ATIPrepareCopyDMA;
+ atis->kaa.Copy = ATICopyDMA;
} else {
- ATIKaa.offscreenByteAlign = 8;
+#else
+ {
+#endif /* USE_DRI */
+ atis->kaa.PrepareSolid = ATIPrepareSolidMMIO;
+ atis->kaa.Solid = ATISolidMMIO;
+ atis->kaa.PrepareCopy = ATIPrepareCopyMMIO;
+ atis->kaa.Copy = ATICopyMMIO;
+ }
+ atis->kaa.DoneSolid = ATIDoneSolid;
+ atis->kaa.DoneCopy = ATIDoneCopy;
+ atis->kaa.flags = KAA_OFFSCREEN_PIXMAPS;
+ if (atic->is_radeon) {
+ atis->kaa.offscreenByteAlign = 1024;
+ atis->kaa.offscreenPitch = 1024;
+ } else {
+ atis->kaa.offscreenByteAlign = 8;
/* Workaround for corrupation at 8 and 24bpp. Why? */
if (atis->datatype == 2)
- ATIKaa.offscreenPitch = 16;
+ atis->kaa.offscreenPitch = 16;
else
- ATIKaa.offscreenPitch =
+ atis->kaa.offscreenPitch =
pScreenPriv->screen->fb[0].bitsPerPixel;
}
- if (!kaaDrawInit(pScreen, &ATIKaa))
+ if (!kaaDrawInit(pScreen, &atis->kaa))
return FALSE;
return TRUE;
@@ -401,15 +429,25 @@
void
ATIDrawFini(ScreenPtr pScreen)
{
+#ifdef USE_DRI
+ KdScreenPriv(pScreen);
+ ATIScreenInfo(pScreenPriv);
+
+ if (atis->using_dma)
+ ATIDMAStop(pScreen);
+
+ if (atis->using_dri)
+ ATIDRICloseScreen(pScreen);
+#endif /* USE_DRI */
}
void
ATIDrawSync(ScreenPtr pScreen)
{
KdScreenPriv(pScreen);
- ATICardInfo(pScreenPriv);
+ ATIScreenInfo(pScreenPriv);
- mmio = atic->reg_base;
+ accel_atis = atis;
ATIWaitIdle();
}
Index: ati_reg.h
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_reg.h,v
retrieving revision 1.2
retrieving revision 1.2.2.1
diff -u -d -r1.2 -r1.2.2.1
--- ati_reg.h 20 Nov 2003 07:49:45 -0000 1.2
+++ ati_reg.h 1 Dec 2003 22:56:06 -0000 1.2.2.1
@@ -24,9 +24,24 @@
/* $Header$ */
/* The Radeon register definitions are almost all the same for r128 */
+#define RADEON_REG_BUS_CNTL 0x0030
+# define RADEON_BUS_MASTER_DIS (1 << 6)
+#define RADEON_GEN_INT_CNTL 0x0040
+#define RADEON_REG_AGP_BASE 0x0170
+#define RADEON_REG_AGP_CNTL 0x0174
+# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
+# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
+# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
+# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
+# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
+# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
+# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
+# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_REG_RBBM_STATUS 0x0e40
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
# define RADEON_RBBM_ACTIVE (1 << 31)
+#define RADEON_REG_CP_CSQ_CNTL 0x0740
+# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
#define RADEON_REG_SRC_PITCH_OFFSET 0x1428
#define RADEON_REG_DST_PITCH_OFFSET 0x142c
#define RADEON_REG_SRC_Y_X 0x1434
@@ -61,7 +76,28 @@
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
+#define RADEON_CP_PACKET0 0x00000000
+#define RADEON_CP_PACKET1 0x40000000
+#define RADEON_CP_PACKET2 0x80000000
+
#define R128_REG_PC_NGUI_CTLSTAT 0x0184
# define R128_PC_BUSY (1 << 31)
#define R128_REG_GUI_STAT 0x1740
# define R128_GUI_ACTIVE (1 << 31)
+#define R128_REG_PCI_GART_PAGE 0x017c
+#define R128_REG_PC_NGUI_CTLSTAT 0x0184
+#define R128_REG_BM_CHUNK_0_VAL 0x0a18
+# define R128_BM_PTR_FORCE_TO_PCI (1 << 21)
+# define R128_BM_PM4_RD_FORCE_TO_PCI (1 << 22)
+# define R128_BM_GLOBAL_FORCE_TO_PCI (1 << 23)
+
+# define R128_PM4_NONPM4 (0 << 28)
+# define R128_PM4_192PIO (1 << 28)
+# define R128_PM4_192BM (2 << 28)
+# define R128_PM4_128PIO_64INDBM (3 << 28)
+# define R128_PM4_128BM_64INDBM (4 << 28)
+# define R128_PM4_64PIO_128INDBM (5 << 28)
+# define R128_PM4_64BM_128INDBM (6 << 28)
+# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
+# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
+# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
Index: ati_stub.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_stub.c,v
retrieving revision 1.2
retrieving revision 1.2.2.1
diff -u -d -r1.2 -r1.2.2.1
--- ati_stub.c 1 Dec 2003 04:33:33 -0000 1.2
+++ ati_stub.c 1 Dec 2003 22:56:06 -0000 1.2.2.1
@@ -29,30 +29,17 @@
#include "ati.h"
#include "klinux.h"
-extern struct pci_id_list radeon_id_list[];
-extern struct pci_id_list r128_id_list[];
+extern struct pci_id_entry ati_pci_ids[];
void
InitCard(char *name)
{
+ struct pci_id_entry *id;
KdCardAttr attr;
- int i, j;
-
- for (i = 0; radeon_id_list[i].name != NULL; i++) {
- CARD16 vendor = radeon_id_list[i].vendor;
- CARD16 device = radeon_id_list[i].device;
- j = 0;
- while (LinuxFindPci(vendor, device, j++, &attr))
- KdCardInfoAdd(&ATIFuncs, &attr, 0);
- }
-
- for (i = 0; r128_id_list[i].name != NULL; i++) {
- CARD16 vendor = r128_id_list[i].vendor;
- CARD16 device = r128_id_list[i].device;
-
- j = 0;
- while (LinuxFindPci(vendor, device, j++, &attr))
+ for (id = ati_pci_ids; id->name != NULL; id++) {
+ int j = 0;
+ while (LinuxFindPci(id->vendor, id->device, j++, &attr))
KdCardInfoAdd(&ATIFuncs, &attr, 0);
}
}
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