xserver/hw/kdrive/ati ati_draw.c, 1.24, 1.25 ati_reg.h, 1.10, 1.11 radeon_composite.c, 1.11, 1.12

[Eric Anholt]

Committed by: anholt

Update of /cvs/xserver/xserver/hw/kdrive/ati
In directory gabe:/tmp/cvs-serv22194/hw/kdrive/ati

Modified Files:
	ati_draw.c ati_reg.h radeon_composite.c 
Log Message:
Fix the R200 Render code.  Composite and Trapezoids are now supported
just as well as on R100.


Index: ati_draw.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_draw.c,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -d -r1.24 -r1.25
--- ati_draw.c	12 Sep 2004 23:22:31 -0000	1.24
+++ ati_draw.c	20 Sep 2004 03:12:00 -0000	1.25
@@ -162,14 +162,15 @@
 			    RADEON_TEX1_W_ROUTING_USE_W0);
 			END_DMA();
 		} else {
-			BEGIN_DMA(12);
+			BEGIN_DMA(8);
 			OUT_REG(R200_REG_RE_CNTL, 0);
-			OUT_REG(R200_REG_SE_VTE_CNTL, R200_VTX_XY_FMT);
-			OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
-			OUT_REG(R200_REG_SE_VTX_FMT_1,
-			    (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
-			    (2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
-			OUT_REG(R200_REG_SE_VAP_CNTL, 0);
+			/* XXX: VTX_ST_DENORMALIZED is illegal for the case of
+			 * repeating textures.
+			 */
+			OUT_REG(R200_REG_SE_VTE_CNTL, R200_VTX_ST_DENORMALIZED);
+			OUT_REG(R200_REG_SE_VAP_CNTL,
+			    R200_VAP_FORCE_W_TO_ONE |
+			    R200_VAP_VF_MAX_VTX_NUM);
 			OUT_REG(R200_REG_RE_AUX_SCISSOR_CNTL, 0);
 			END_DMA();
 		}
@@ -789,7 +790,7 @@
 			/*atis->kaa.PrepareTrapezoids = R128PrepareTrapezoids;
 			atis->kaa.Trapezoids = R128Trapezoids;
 			atis->kaa.DoneTrapezoids = R128DoneTrapezoids;*/
-		} else if (atic->is_r100) {
+		} else if (atic->is_r100 || atic->is_r200) {
 			atis->kaa.PrepareTrapezoids = RadeonPrepareTrapezoids;
 			atis->kaa.Trapezoids = RadeonTrapezoids;
 			atis->kaa.DoneTrapezoids = RadeonDoneTrapezoids;

Index: ati_reg.h
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/ati_reg.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- ati_reg.h	19 Sep 2004 10:57:31 -0000	1.10
+++ ati_reg.h	20 Sep 2004 03:12:00 -0000	1.11
@@ -1180,6 +1180,7 @@
 # define R200_VAP_FORCE_W_TO_ONE		0x00010000
 # define R200_VAP_D3D_TEX_DEFAULT		0x00020000
 # define R200_VAP_VF_MAX_VTX_NUM__SHIFT		18
+# define R200_VAP_VF_MAX_VTX_NUM		(9 << 18)
 # define R200_VAP_DX_CLIP_SPACE_DEF		0x00400000
 
 #define R200_REG_SE_VTX_FMT_0			0x2088

Index: radeon_composite.c
===================================================================
RCS file: /cvs/xserver/xserver/hw/kdrive/ati/radeon_composite.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- radeon_composite.c	11 Sep 2004 09:28:19 -0000	1.11
+++ radeon_composite.c	20 Sep 2004 03:12:00 -0000	1.12
@@ -511,7 +511,7 @@
 		is_transform[1] = FALSE;
 	}
 
-	BEGIN_DMA(34);
+	BEGIN_DMA(22);
 	OUT_REG(ATI_REG_WAIT_UNTIL,
 		RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
 
@@ -524,6 +524,11 @@
 	OUT_RING(dst_format | RADEON_ALPHA_BLEND_ENABLE);
 	OUT_RING(dst_offset);
 
+	OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
+	OUT_REG(R200_REG_SE_VTX_FMT_1,
+	    (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
+	    (2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
+
 	OUT_REG(RADEON_REG_RB3D_COLORPITCH, dst_pitch >> pixel_shift);
 
 	/* IN operator: Multiply src by mask components or mask alpha.
@@ -685,6 +690,7 @@
 {
 	KdScreenPriv(pDst->drawable.pScreen);
 	ATIScreenInfo(pScreenPriv);
+	ATICardInfo(pScreenPriv);
 	CARD32 dst_offset, dst_pitch;
 	int pixel_shift;
 	RING_LOCALS;
@@ -701,7 +707,7 @@
 	if (((dst_pitch >> pixel_shift) & 0x7) != 0)
 		ATI_FALLBACK(("Bad destination pitch 0x%x\n", dst_pitch));
 
-	BEGIN_DMA(14);
+	BEGIN_DMA(10);
 	OUT_REG(ATI_REG_WAIT_UNTIL,
 		RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
 
@@ -718,21 +724,36 @@
 	OUT_RING(((pDst->drawable.height - 1) << 16) |
 	    (pDst->drawable.width - 1));
 	OUT_RING(dst_pitch >> pixel_shift);
-
-	/* RADEON_REG_PP_TXCBLEND_0,
-	 * RADEON_REG_PP_TXABLEND_0,
-	 * RADEON_REG_PP_TFACTOR_0
-	 */
-	OUT_RING(DMA_PACKET0(RADEON_REG_PP_TXCBLEND_0, 3));
-	OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
-	    RADEON_COLOR_ARG_C_TFACTOR_ALPHA);
-	OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
-	    RADEON_ALPHA_ARG_C_TFACTOR_ALPHA);
-	OUT_RING(0x01000000);
-
 	OUT_REG(RADEON_REG_RB3D_BLENDCNTL, RadeonBlendOp[PictOpAdd].blend_cntl);
 	END_DMA();
 
+	if (atic->is_r100) {
+		BEGIN_DMA(4);
+		/* RADEON_REG_PP_TXCBLEND_0,
+		 * RADEON_REG_PP_TXABLEND_0,
+		 * RADEON_REG_PP_TFACTOR_0
+		 */
+		OUT_RING(DMA_PACKET0(RADEON_REG_PP_TXCBLEND_0, 3));
+		OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
+		    RADEON_COLOR_ARG_C_TFACTOR_ALPHA);
+		OUT_RING(RADEON_BLEND_CTL_ADD | RADEON_CLAMP_TX |
+		    RADEON_ALPHA_ARG_C_TFACTOR_ALPHA);
+		OUT_RING(0x01000000);
+		END_DMA();
+	} else if (atic->is_r200) {
+		BEGIN_DMA(12);
+		OUT_REG(R200_REG_SE_VTX_FMT_0, R200_VTX_XY);
+		OUT_REG(R200_REG_SE_VTX_FMT_1, 0);
+		OUT_REG(R200_REG_PP_TXCBLEND_0,
+		    R200_TXC_ARG_C_TFACTOR_COLOR);
+		OUT_REG(R200_REG_PP_TXABLEND_0,
+		    R200_TXA_ARG_C_TFACTOR_ALPHA);
+		OUT_REG(R200_REG_PP_TXCBLEND2_0, 0);
+		OUT_REG(R200_REG_PP_TXABLEND2_0, 0);
+		OUT_REG(RADEON_REG_PP_TFACTOR_0, 0x01000000);
+		END_DMA();
+	}
+
 	return TRUE;
 }