dri-devel January 2021

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[PATCH] drm/bridge: ti-sn65dsi86: rename GPIO register bits
by Shawn Guo 12 Jan '21

12 Jan '21

From: Shawn Guo <shawn.guo(a)linaro.org> It renames GPIO register bits to drop 'SN_' prefix, so that they are consistent to other definitions - prefixing register name with 'SN_' but not for bit fields. Signed-off-by: Shawn Guo <shawn.guo(a)linaro.org> --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index f27306c51e4d..8eac9d77eba1 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -63,13 +63,13 @@ #define SN_HPD_DISABLE_REG 0x5C #define HPD_DISABLE BIT(0) #define SN_GPIO_IO_REG 0x5E -#define SN_GPIO_INPUT_SHIFT 4 -#define SN_GPIO_OUTPUT_SHIFT 0 +#define GPIO_INPUT_SHIFT 4 +#define GPIO_OUTPUT_SHIFT 0 #define SN_GPIO_CTRL_REG 0x5F -#define SN_GPIO_MUX_INPUT 0 -#define SN_GPIO_MUX_OUTPUT 1 -#define SN_GPIO_MUX_SPECIAL 2 -#define SN_GPIO_MUX_MASK 0x3 +#define GPIO_MUX_INPUT 0 +#define GPIO_MUX_OUTPUT 1 +#define GPIO_MUX_SPECIAL 2 +#define GPIO_MUX_MASK 0x3 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) #define SN_AUX_ADDR_19_16_REG 0x74 #define SN_AUX_ADDR_15_8_REG 0x75 @@ -1035,7 +1035,7 @@ static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) if (ret) return ret; - return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); + return !!(val & BIT(GPIO_INPUT_SHIFT + offset)); } static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, @@ -1051,8 +1051,8 @@ static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, val &= 1; ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, - BIT(SN_GPIO_OUTPUT_SHIFT + offset), - val << (SN_GPIO_OUTPUT_SHIFT + offset)); + BIT(GPIO_OUTPUT_SHIFT + offset), + val << (GPIO_OUTPUT_SHIFT + offset)); if (ret) dev_warn(pdata->dev, "Failed to set bridge GPIO %u: %d\n", offset, ret); @@ -1069,8 +1069,8 @@ static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, return 0; ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, - SN_GPIO_MUX_MASK << shift, - SN_GPIO_MUX_INPUT << shift); + GPIO_MUX_MASK << shift, + GPIO_MUX_INPUT << shift); if (ret) { set_bit(offset, pdata->gchip_output); return ret; @@ -1103,8 +1103,8 @@ static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, /* Set direction */ ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, - SN_GPIO_MUX_MASK << shift, - SN_GPIO_MUX_OUTPUT << shift); + GPIO_MUX_MASK << shift, + GPIO_MUX_OUTPUT << shift); if (ret) { clear_bit(offset, pdata->gchip_output); pm_runtime_put(pdata->dev); -- 2.17.1

3 3

[PATCH 0/9] Qualcomm DRM DPU fixes
by AngeloGioacchino Del Regno 12 Jan '21

12 Jan '21

This patch series brings some fixes to the Qualcomm DPU driver, aim is to get it prepared for "legacy" SoCs (like MSM8998, SDM630/660) and to finally get command-mode displays working on this driver. The series was tested against MSM8998 (the commit that introduces it to the hw-catalog is not included in this series, as it needs to be cleaned up a little more) and specifically on: - Sony Xperia XZ Premium (MSM8998), 4K dual-dsi LCD display, command-mode - F(x)Tec Pro1 (MSM8998), single-dsi OLED display, video-mode ... And it obviously worked just perfect! AngeloGioacchino Del Regno (9): drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset drm/msm/dpu1: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks drm/msm/dpu1: Add prog_fetch_lines_worst_case to INTF_BLK macro drm/msm/dpu1: Allow specifying features and sblk in DSPP_BLK macro drm/msm/dpu: Disable autorefresh in command mode drm/msm/dpu: Correctly configure vsync tearcheck for command mode drm/msm/dpu: Remove unused call in wait_for_commit_done drm/msm/dpu: Add a function to retrieve the current CTL status drm/msm/dpu: Fix timeout issues on command mode panels .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 91 ++++++++++++++++--- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 39 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 26 ++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 9 +- 7 files changed, 155 insertions(+), 37 deletions(-) -- 2.29.2

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[PULL] drm-intel-next
by Rodrigo Vivi 12 Jan '21

12 Jan '21

Hi Dave and Daniel, A very short collection of patches, mostly with display fixes. Plus GVT. The goal is to get both drm-intel-next and drm-intel-gt-next in sync again through drm-next backports so we can continue with ADL enabling in a topic branch. Please be aware that there's a drm only patch here: commit 7d8ac172d7f1 ("drm: Add function to convert rect in 16.16 fixed format to regular format") Here goes drm-intel-next-2021-01-12: - PSR fixes and improvements for selective fetch (Jose) - GVT build fixed and cleanup (Jani) - RKL display fixes (Lee, Matt) - DSI fix (Hans) - Panel Power and Backlight fixes (Anshuman, Jani) - RPM fix (Chris) - Fix HTI port checking (Jose) - Clean-up in cursor code (Ville) - Once again, trying to use fast+narrow link on eDP (Ville) - DG1 display fix (Matt) Thanks, Rodrigo. The following changes since commit cb3cfbf79aff7decb4e5ee69a7c74864497f61dc: Merge tag 'drm-misc-next-2021-01-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next (2021-01-07 13:40:20 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-12 for you to fetch changes up to cce73665eae238791f4342b29ca54188227717c8: drm/i915/dg1: Update voltage swing tables for DP (2021-01-11 19:20:18 -0800) ---------------------------------------------------------------- - PSR fixes and improvements for selective fetch (Jose) - GVT build fixed and cleanup (Jani) - RKL display fixes (Lee, Matt) - DSI fix (Hans) - Panel Power and Backlight fixes (Anshuman, Jani) - RPM fix (Chris) - Fix HTI port checking (Jose) - Clean-up in cursor code (Ville) - Once again, trying to use fast+narrow link on eDP (Ville) - DG1 display fix (Matt) ---------------------------------------------------------------- Anshuman Gupta (1): drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock} Chris Wilson (1): drm/i915: Disable RPM wakeref assertions during driver shutdown Hans de Goede (1): drm/i915/dsi: Use unconditional msleep for the panel_on_delay when there is no reset-deassert MIPI-sequence Jani Nikula (10): drm/i915/gvt: avoid useless use of inline drm/i915/gvt: make execlist.h self-contained drm/i915/gvt: make fb_decoder.h self-contained drm/i915/gvt: make gtt.h self-contained drm/i915/gvt: make interrupt.h self-contained drm/i915/gvt: make mmio_context.h self-contained drm/i915/gvt: make gvt.h self-contained drm/i915/gvt: make scheduler.h self-contained drm/i915/gvt: make mpt.h self-contained drm/i915/backlight: fix CPU mode backlight takeover on LPT José Roberto de Souza (5): drm: Add function to convert rect in 16.16 fixed format to regular format drm/i915/display/psr: Use plane damage clips to calculate damaged area drm/i915/display: Split and export main surface calculation from skl_check_main_surface() drm/i915/display/psr: Program plane's calculated offset to plane SF register drm/i915: Fix HTI port checking Lee Shawn C (1): drm/i915/rkl: new rkl ddc map for different PCH Matt Roper (2): drm/i915/rkl: Add DP vswing programming tables drm/i915/dg1: Update voltage swing tables for DP Rodrigo Vivi (2): Merge tag 'gvt-next-fixes-2020-12-25' of https://github.com/intel/gvt-linux into drm-intel-next Merge drm/drm-next into drm-intel-next Ville Syrjälä (2): drm/i915: Fix checkpatch warns in cursor code drm/i915: Try to use fast+narrow link on eDP again and fall back to the old max strategy on failure drivers/gpu/drm/i915/Makefile | 10 +- drivers/gpu/drm/i915/display/intel_bios.c | 10 ++ drivers/gpu/drm/i915/display/intel_cursor.c | 6 +- drivers/gpu/drm/i915/display/intel_ddi.c | 79 ++++++++++++- drivers/gpu/drm/i915/display/intel_display.c | 78 ++++++++----- drivers/gpu/drm/i915/display/intel_display.h | 2 + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 83 +++++++++++--- drivers/gpu/drm/i915/display/intel_panel.c | 9 +- drivers/gpu/drm/i915/display/intel_psr.c | 127 ++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 + drivers/gpu/drm/i915/display/vlv_dsi.c | 16 ++- drivers/gpu/drm/i915/gvt/execlist.h | 3 - drivers/gpu/drm/i915/gvt/fb_decoder.h | 6 +- drivers/gpu/drm/i915/gvt/gtt.h | 11 +- drivers/gpu/drm/i915/gvt/gvt.h | 4 + drivers/gpu/drm/i915/gvt/handlers.c | 3 +- drivers/gpu/drm/i915/gvt/interrupt.h | 5 +- drivers/gpu/drm/i915/gvt/mmio_context.h | 11 ++ drivers/gpu/drm/i915/gvt/mpt.h | 2 + drivers/gpu/drm/i915/gvt/scheduler.h | 5 + drivers/gpu/drm/i915/i915_drv.c | 4 + drivers/gpu/drm/i915/i915_reg.h | 3 +- include/drm/drm_rect.h | 13 +++ 24 files changed, 396 insertions(+), 97 deletions(-)

1 0

[RFC PATCH 000/162] DG1 + LMEM enabling
by Matthew Auld 12 Jan '21

12 Jan '21

This series includes a version of Maarten' series[1], which converts more of the driver locking over to dma-resv. On top of this we now implement things like LMEM eviction, which has a dependency on this new locking design. In terms of new uAPI we have gem_create_ext, which offers extensions support for gem_create. For now the only extension we add is giving userspace the ability to optionally provide a priority list of potential placements for the object. The other bit of new uAPI is the query interface for memory regions, which describes the supported memory regions for the device. What this reports can then be fed into gem_create_ext to specify where an object might reside, like device local memory. Note that the class/instance complexity in the uAPI is not very relevant for DG1, but is in preparation for the Xe HP multi-tile architecture with multiple memory regions. The series still includes relocation support, but that's purely for CI, until we have completed all the IGT rework[2] and so will not be merged. Likewise for pread/pwrite, which will also be dropped from DG1+. [1] https://patchwork.freedesktop.org/series/82337/ [2] https://patchwork.freedesktop.org/series/82954/ Abdiel Janulgue (3): drm/i915/query: Expose memory regions through the query uAPI drm/i915: Provide a way to disable PCIe relaxed write ordering drm/i915: Reintroduce mem->reserved Animesh Manna (2): drm/i915/lmem: reset the lmem buffer created by fbdev drm/i915/dsb: Enable lmem for dsb Anshuman Gupta (1): drm/i915/oprom: Basic sanitization Anusha Srivatsa (1): drm/i915/lmem: Bypass aperture when lmem is available Bommu Krishnaiah (1): drm/i915/gem: Update shmem available memory CQ Tang (13): drm/i915/dg1: Fix occasional migration error drm/i915: i915 returns -EBUSY on thread contention drm/i915: setup GPU device lmem region drm/i915: Fix object page offset within a region drm/i915: add i915_gem_object_is_devmem() function drm/i915: finish memory region support for stolen objects. drm/i915: Create stolen memory region from local memory drm/i915/dg1: intel_memory_region_evict() changes for eviction drm/i915/dg1: i915_gem_object_memcpy(..) infrastructure drm/i915/dg1: Eviction logic drm/i915/dg1: Add enable_eviction modparam drm/i915/dg1: Add lmem_size modparam drm/i915: need consider system BO snoop for dgfx Chris Wilson (2): drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h drm/i915/gt: Rename lrc.c to execlists_submission.c Clint Taylor (3): drm/i915/dg1: Read OPROM via SPI controller drm/i915/dg1: Compute MEM Bandwidth using MCHBAR drm/i915/dg1: Double memory bandwidth available Daniele Ceraolo Spurio (5): drm/i915: split gen8+ flush and bb_start emission functions to their own file drm/i915: split wa_bb code to its own file drm/i915: Make intel_init_workaround_bb more compatible with ww locking. drm/i915/guc: put all guc objects in lmem when available drm/i915: WA for zero memory channel Imre Deak (1): drm/i915/dg1: Reserve first 1MB of local memory Kui Wen (1): drm/i915/dg1: Do not check r->sgt.pfn for NULL Lucas De Marchi (2): drm/i915: move eviction to prepare hook drm/i915/dg1: allow pci to auto probe Maarten Lankhorst (60): drm/i915: Pin timeline map after first timeline pin, v5. drm/i915: Move cmd parser pinning to execbuffer drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2. drm/i915: Ensure we hold the object mutex in pin correctly v2 drm/i915: Add gem object locking to madvise. drm/i915: Move HAS_STRUCT_PAGE to obj->flags drm/i915: Rework struct phys attachment handling drm/i915: Convert i915_gem_object_attach_phys() to ww locking, v2. drm/i915: make lockdep slightly happier about execbuf. drm/i915: Disable userptr pread/pwrite support. drm/i915: No longer allow exporting userptr through dma-buf drm/i915: Reject more ioctls for userptr drm/i915: Reject UNSYNCHRONIZED for userptr, v2. drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER. drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v5. drm/i915: Flatten obj->mm.lock drm/i915: Populate logical context during first pin. drm/i915: Make ring submission compatible with obj->mm.lock removal, v2. drm/i915: Handle ww locking in init_status_page drm/i915: Rework clflush to work correctly without obj->mm.lock. drm/i915: Pass ww ctx to intel_pin_to_display_plane drm/i915: Add object locking to vm_fault_cpu drm/i915: Move pinning to inside engine_wa_list_verify() drm/i915: Take reservation lock around i915_vma_pin. drm/i915: Make __engine_unpark() compatible with ww locking v2 drm/i915: Take obj lock around set_domain ioctl drm/i915: Defer pin calls in buffer pool until first use by caller. drm/i915: Fix pread/pwrite to work with new locking rules. drm/i915: Fix workarounds selftest, part 1 drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner. drm/i915: Add ww locking around vm_access() drm/i915: Increase ww locking for perf. drm/i915: Lock ww in ucode objects correctly drm/i915: Add ww locking to dma-buf ops. drm/i915: Add missing ww lock in intel_dsb_prepare. drm/i915: Fix ww locking in shmem_create_from_object drm/i915: Use a single page table lock for each gtt. drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal. drm/i915/selftests: Prepare client blit for obj->mm.lock removal. drm/i915/selftests: Prepare coherency tests for obj->mm.lock removal. drm/i915/selftests: Prepare context tests for obj->mm.lock removal. drm/i915/selftests: Prepare dma-buf tests for obj->mm.lock removal. drm/i915/selftests: Prepare execbuf tests for obj->mm.lock removal. drm/i915/selftests: Prepare mman testcases for obj->mm.lock removal. drm/i915/selftests: Prepare object tests for obj->mm.lock removal. drm/i915/selftests: Prepare object blit tests for obj->mm.lock removal. drm/i915/selftests: Prepare igt_gem_utils for obj->mm.lock removal drm/i915/selftests: Prepare context selftest for obj->mm.lock removal drm/i915/selftests: Prepare hangcheck for obj->mm.lock removal drm/i915/selftests: Prepare execlists for obj->mm.lock removal drm/i915/selftests: Prepare mocs tests for obj->mm.lock removal drm/i915/selftests: Prepare ring submission for obj->mm.lock removal drm/i915/selftests: Prepare timeline tests for obj->mm.lock removal drm/i915/selftests: Prepare i915_request tests for obj->mm.lock removal drm/i915/selftests: Prepare memory region tests for obj->mm.lock removal drm/i915/selftests: Prepare cs engine tests for obj->mm.lock removal drm/i915/selftests: Prepare gtt tests for obj->mm.lock removal drm/i915: Finally remove obj->mm.lock. drm/i915: Keep userpointer bindings if seqcount is unchanged, v2. drm/i915: Implement eviction locking v2 Matt Roper (1): drm/i915/lmem: Fail driver init if LMEM training failed Matthew Auld (19): drm/i915/selftest: also consider non-contiguous objects drm/i915/selftest: assert we get 2M GTT pages drm/i915/selftest: handle local-memory in perf_memcpy HAX drm/i915/lmem: support CPU relocations HAX drm/i915/lmem: support pread and pwrite drm/i915: introduce kernel blitter_context drm/i915/region: support basic eviction drm/i915: support basic object migration drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915: setup the LMEM region drm/i915/gtt: map the PD up front drm/i915/gtt/dgfx: place the PD in LMEM drm/i915/gtt: make flushing conditional drm/i915/gtt/dg1: add PTE_LM plumbing for PPGTT drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT drm/i915: allocate context from LMEM drm/i915: move engine scratch to LMEM drm/i915/lmem: support optional CPU clearing for special internal use drm/i915: drop fake lmem Michael J. Ruhl (2): drm/i915/dmabuf: Disallow LMEM objects from dma-buf drm/i915/dg1: Introduce dmabuf mmap to LMEM Michel Thierry (2): drm/i915/lmem: allocate cmd ring in lmem drm/i915/lmem: allocate HWSP in lmem Mohammed Khajapasha (2): drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete drm/i915: Return error value when bo not in LMEM for discrete Prathap Kumar Valsan (2): drm/i915: Store gt in memory region drm/i915/pm: suspend and restore ppgtt mapping Ramalingam C (6): drm/i915: define intel_partial_pages_for_sg_table drm/i915: create and destroy dummy vma drm/i915: blt copy between objs using pre-created vma windows drm/i915: window_blt_copy is used for swapin and swapout drm/i915: Lmem eviction statistics by category drm/i915/gem/selftest: test and measure window based blt cpy Stuart Summers (1): drm/i915: Allow non-uniform subslices in gen12+ Sudeep Dutt (2): drm/i915/dg1: Track swap in/out stats via debugfs drm/i915/dg1: Measure swap in/out timing stats Thomas Hellström (15): HAX drm/i915: Work around the selftest timeline lock splat workaround drm/i915: Introduce drm_i915_lock_isolated drm/i915: Lock hwsp objects isolated for pinning at create time drm/i915: Prepare for obj->mm.lock removal drm/i915: Avoid some false positives in assert_object_held() drm/i915: Reference contending lock objects drm/i915: Break out dma_resv ww locking utilities to separate files drm/i915: Introduce a for_i915_gem_ww(){} drm/i915: Untangle the vma pages_mutex drm/i915: Add blit functions that can be called from within a WW transaction drm/i915: Delay publishing objects on the eviction lists drm/i915: Perform execbuffer object locking as a separate step drm/i915: Support ww eviction drm/i915: Use a ww transaction in the fault handler drm/i915: Use a ww transaction in i915_gem_object_pin_map_unlocked() Tvrtko Ursulin (4): drm/i915/dg1: Eliminate eviction mutex drm/i915/dg1: Keep engine awake across whole blit drm/i915/dg1: Add dedicated context for blitter eviction drm/i915: Improve accuracy of eviction stats Venkata Ramana Nayana (8): drm/i915: suspend/resume eviction drm/i915: Reset blitter context when unpark engine drm/i915/gt: Allocate default ctx objects in SMEM drm/i915: suspend/resume enable blitter eviction drm/i915: suspend/resume handling of perma-pinned objects drm/i915: Support ww locks in suspend/resume drm/i915/dg1: Fix mapping type for default state object drm/i915/dg1: Fix GPU hang due to shmemfs page drop Venkata Sandeep Dhanalakota (2): drm/i915: Update the helper to set correct mapping drm/i915/lmem: Limit block size to 4G Zbigniew Kempczyński (1): drm/i915: Distinction of memory regions drivers/gpu/drm/i915/Kconfig.debug | 11 + drivers/gpu/drm/i915/Makefile | 7 +- drivers/gpu/drm/i915/display/intel_bios.c | 75 +- drivers/gpu/drm/i915/display/intel_bw.c | 64 +- drivers/gpu/drm/i915/display/intel_display.c | 80 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 9 +- drivers/gpu/drm/i915/display/intel_fbc.c | 20 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 54 +- drivers/gpu/drm/i915/display/intel_opregion.c | 169 ++++ drivers/gpu/drm/i915/display/intel_opregion.h | 31 +- drivers/gpu/drm/i915/display/intel_overlay.c | 34 +- drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_create.c | 398 ++++++++ drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 123 ++- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 52 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 302 +++++- drivers/gpu/drm/i915/gem/i915_gem_fence.c | 95 -- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 254 ++++- drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 22 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 187 ++-- drivers/gpu/drm/i915/gem/i915_gem_mman.h | 11 + drivers/gpu/drm/i915/gem/i915_gem_object.c | 711 +++++++++++++- drivers/gpu/drm/i915/gem/i915_gem_object.h | 206 +++- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 101 +- .../gpu/drm/i915/gem/i915_gem_object_blt.h | 10 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 46 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 140 ++- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 110 +-- drivers/gpu/drm/i915/gem/i915_gem_region.c | 234 ++++- drivers/gpu/drm/i915/gem/i915_gem_region.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 46 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 52 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.h | 6 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 247 +++-- drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 10 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 - drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 870 ++++++----------- .../drm/i915/gem/selftests/huge_gem_object.c | 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 60 +- .../i915/gem/selftests/i915_gem_client_blt.c | 8 +- .../i915/gem/selftests/i915_gem_coherency.c | 18 +- .../drm/i915/gem/selftests/i915_gem_context.c | 21 +- .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +- .../i915/gem/selftests/i915_gem_execbuffer.c | 2 +- .../drm/i915/gem/selftests/i915_gem_mman.c | 33 +- .../drm/i915/gem/selftests/i915_gem_object.c | 2 +- .../i915/gem/selftests/i915_gem_object_blt.c | 172 +++- .../drm/i915/gem/selftests/i915_gem_phys.c | 10 +- .../drm/i915/gem/selftests/igt_gem_utils.c | 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 11 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 393 ++++++++ drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 26 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 91 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 2 + drivers/gpu/drm/i915/gt/intel_context.c | 3 +- drivers/gpu/drm/i915/gt/intel_context.h | 2 + drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 13 +- drivers/gpu/drm/i915/gt/intel_engine.h | 4 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 125 ++- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 14 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 + .../drm/i915/gt/intel_engine_workaround_bb.c | 364 +++++++ .../drm/i915/gt/intel_engine_workaround_bb.h | 14 + ...tel_lrc.c => intel_execlists_submission.c} | 899 +++--------------- .../drm/i915/gt/intel_execlists_submission.h | 66 ++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 93 +- drivers/gpu/drm/i915/gt/intel_gt.c | 14 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c | 47 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool.h | 5 + .../drm/i915/gt/intel_gt_buffer_pool_types.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 105 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 23 +- drivers/gpu/drm/i915/gt/intel_lrc.h | 128 --- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 39 + drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 20 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 + drivers/gpu/drm/i915/gt/intel_ring.c | 24 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 184 ++-- drivers/gpu/drm/i915/gt/intel_sseu.c | 6 +- drivers/gpu/drm/i915/gt/intel_timeline.c | 121 ++- drivers/gpu/drm/i915/gt/intel_timeline.h | 1 + .../gpu/drm/i915/gt/intel_timeline_types.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +- drivers/gpu/drm/i915/gt/mock_engine.c | 24 +- drivers/gpu/drm/i915/gt/selftest_context.c | 5 +- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 4 +- .../{selftest_lrc.c => selftest_execlists.c} | 37 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 5 +- .../drm/i915/gt/selftest_ring_submission.c | 4 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 100 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 101 +- drivers/gpu/drm/i915/gt/shmem_utils.c | 11 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 13 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 4 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c | 18 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 37 +- drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +- drivers/gpu/drm/i915/gvt/mmio_context.h | 2 + drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_active.c | 20 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 104 +- drivers/gpu/drm/i915/i915_debugfs.c | 42 +- drivers/gpu/drm/i915/i915_drv.c | 277 +++++- drivers/gpu/drm/i915/i915_drv.h | 57 +- drivers/gpu/drm/i915/i915_gem.c | 418 +++----- drivers/gpu/drm/i915/i915_gem.h | 12 - drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_gem_ww.c | 93 ++ drivers/gpu/drm/i915/i915_gem_ww.h | 53 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_memcpy.c | 2 +- drivers/gpu/drm/i915/i915_memcpy.h | 2 +- drivers/gpu/drm/i915/i915_mm.c | 2 +- drivers/gpu/drm/i915/i915_params.c | 11 +- drivers/gpu/drm/i915/i915_params.h | 3 +- drivers/gpu/drm/i915/i915_pci.c | 5 +- drivers/gpu/drm/i915/i915_perf.c | 57 +- drivers/gpu/drm/i915/i915_query.c | 62 ++ drivers/gpu/drm/i915/i915_reg.h | 17 + drivers/gpu/drm/i915/i915_selftest.h | 2 + drivers/gpu/drm/i915/i915_vma.c | 154 ++- drivers/gpu/drm/i915/i915_vma.h | 28 +- drivers/gpu/drm/i915/intel_memory_region.c | 229 ++++- drivers/gpu/drm/i915/intel_memory_region.h | 53 +- drivers/gpu/drm/i915/intel_region_lmem.c | 168 ++-- drivers/gpu/drm/i915/intel_region_lmem.h | 3 +- drivers/gpu/drm/i915/intel_uncore.c | 12 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 100 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + drivers/gpu/drm/i915/selftests/i915_perf.c | 3 +- drivers/gpu/drm/i915/selftests/i915_request.c | 10 +- drivers/gpu/drm/i915/selftests/igt_spinner.c | 136 ++- drivers/gpu/drm/i915/selftests/igt_spinner.h | 5 + .../drm/i915/selftests/intel_memory_region.c | 442 ++++++++- drivers/gpu/drm/i915/selftests/mock_region.c | 4 +- include/uapi/drm/i915_drm.h | 118 +++ 148 files changed, 7813 insertions(+), 3312 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.c delete mode 100644 drivers/gpu/drm/i915/gem/i915_gem_fence.c create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.c create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.h create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_workaround_bb.c create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_workaround_bb.h rename drivers/gpu/drm/i915/gt/{intel_lrc.c => intel_execlists_submission.c} (87%) create mode 100644 drivers/gpu/drm/i915/gt/intel_execlists_submission.h delete mode 100644 drivers/gpu/drm/i915/gt/intel_lrc.h rename drivers/gpu/drm/i915/gt/{selftest_lrc.c => selftest_execlists.c} (99%) create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h -- 2.26.2

9 207

[PATCH] drm/ttm: make the pool shrinker lock a mutex
by Christian König 12 Jan '21

12 Jan '21

set_pages_wb() might sleep and so we can't do this in an atomic context. Signed-off-by: Christian König <christian.koenig(a)amd.com> Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov(a)gmail.com> Fixes: d099fc8f540a ("drm/ttm: new TT backend allocation pool v3") --- drivers/gpu/drm/ttm/ttm_pool.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index a00b7ab9c14c..6a6eeba423d1 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -66,7 +66,7 @@ static struct ttm_pool_type global_uncached[MAX_ORDER]; static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER]; static struct ttm_pool_type global_dma32_uncached[MAX_ORDER]; -static spinlock_t shrinker_lock; +static struct mutex shrinker_lock; static struct list_head shrinker_list; static struct shrinker mm_shrinker; @@ -249,9 +249,9 @@ static void ttm_pool_type_init(struct ttm_pool_type *pt, struct ttm_pool *pool, spin_lock_init(&pt->lock); INIT_LIST_HEAD(&pt->pages); - spin_lock(&shrinker_lock); + mutex_lock(&shrinker_lock); list_add_tail(&pt->shrinker_list, &shrinker_list); - spin_unlock(&shrinker_lock); + mutex_unlock(&shrinker_lock); } /* Remove a pool_type from the global shrinker list and free all pages */ @@ -259,9 +259,9 @@ static void ttm_pool_type_fini(struct ttm_pool_type *pt) { struct page *p, *tmp; - spin_lock(&shrinker_lock); + mutex_lock(&shrinker_lock); list_del(&pt->shrinker_list); - spin_unlock(&shrinker_lock); + mutex_unlock(&shrinker_lock); list_for_each_entry_safe(p, tmp, &pt->pages, lru) ttm_pool_free_page(pt->pool, pt->caching, pt->order, p); @@ -302,7 +302,7 @@ static unsigned int ttm_pool_shrink(void) unsigned int num_freed; struct page *p; - spin_lock(&shrinker_lock); + mutex_lock(&shrinker_lock); pt = list_first_entry(&shrinker_list, typeof(*pt), shrinker_list); p = ttm_pool_type_take(pt); @@ -314,7 +314,7 @@ static unsigned int ttm_pool_shrink(void) } list_move_tail(&pt->shrinker_list, &shrinker_list); - spin_unlock(&shrinker_lock); + mutex_unlock(&shrinker_lock); return num_freed; } @@ -564,7 +564,7 @@ int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m) { unsigned int i; - spin_lock(&shrinker_lock); + mutex_lock(&shrinker_lock); seq_puts(m, "\t "); for (i = 0; i < MAX_ORDER; ++i) @@ -600,7 +600,7 @@ int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m) seq_printf(m, "\ntotal\t: %8lu of %8lu\n", atomic_long_read(&allocated_pages), page_pool_size); - spin_unlock(&shrinker_lock); + mutex_unlock(&shrinker_lock); return 0; } @@ -644,7 +644,7 @@ int ttm_pool_mgr_init(unsigned long num_pages) if (!page_pool_size) page_pool_size = num_pages; - spin_lock_init(&shrinker_lock); + mutex_init(&shrinker_lock); INIT_LIST_HEAD(&shrinker_list); for (i = 0; i < MAX_ORDER; ++i) { -- 2.25.1

3 5

[PATCH 0/6] Move struct drm_device.hose to legacy section
by Thomas Zimmermann 12 Jan '21

12 Jan '21

This patchset moves struct drm_device.hose to the section for legacy drivers. As part of this, a number of other changes are applied in order to protect all uses of hose by CONFIG_DRM_LEGACY. Patches 1 to 3 move non-legacy code out put drm_memory.c and add the remaining I/O-memory helpers to the legacy code. Patch 4 addresses CONFIG_DRM_VM, which is only selected by legacy drivers, so drm_vm.c can directly be compiled by CONFIG_DRM_LEGACY. Patch 5 changes radeon to maintain its own copy of the hose field of struct drm_device. Patch 6 makes the hose field legacy. The patchset has been compile-tested w/o CONFIG_DRM_LEGACY enabled. Thomas Zimmermann (6): drm: Inline AGP wrappers into their only callers drm: Implement drm_need_swiotlb() in drm_cache.c drm: Build drm_memory.o only for legacy drivers drm: Merge CONFIG_DRM_VM into CONFIG_DRM_LEGACY drm/radeon: Store PCI controller in struct radeon_device.hose drm: Move struct drm_device.hose to legacy section drivers/gpu/drm/Kconfig | 5 --- drivers/gpu/drm/Makefile | 6 ++-- drivers/gpu/drm/drm_agpsupport.c | 12 +++---- drivers/gpu/drm/drm_cache.c | 32 ++++++++++++++++++ drivers/gpu/drm/drm_file.c | 2 ++ drivers/gpu/drm/drm_legacy.h | 2 +- drivers/gpu/drm/drm_memory.c | 51 ----------------------------- drivers/gpu/drm/radeon/radeon.h | 3 ++ drivers/gpu/drm/radeon/radeon_drv.c | 4 --- drivers/gpu/drm/radeon/radeon_kms.c | 4 +++ drivers/gpu/drm/radeon/radeon_ttm.c | 2 +- include/drm/drm_agpsupport.h | 18 ---------- include/drm/drm_device.h | 9 ++--- 13 files changed, 57 insertions(+), 93 deletions(-) base-commit: cd0df21e28c36de80356344ff8683be2813c6ff2 prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d -- 2.29.2

3 13

[PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs
by Dmitry Osipenko 12 Jan '21

12 Jan '21

Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces power consumption and heating of the Tegra chips. Tegra SoC has multiple hardware units which belong to a core power domain of the SoC and share the core voltage. The voltage must be selected in accordance to a minimum requirement of every core hardware unit. The minimum core voltage requirement depends on: 1. Clock enable state of a hardware unit. 2. Clock frequency. 3. Unit's internal idling/active state. This series is tested on Acer A500 (T20), AC100 (T20), Nexus 7 (T30), Ouya (T30), TK1 (T124) and some others. I also added voltage scaling to the Ventana (T20) and Cardhu (T30) boards which are tested by NVIDIA's CI farm. Tegra30 is now couple degrees cooler on Nexus 7 and stays cool on Ouya (instead of becoming burning hot) while system is idling. It should be possible to improve this further by implementing a more advanced power management features for the kernel drivers. The DVFS support is opt-in for all boards, meaning that older DTBs will continue to work like they did it before this series. It should be possible to easily add the core voltage scaling support for Tegra114+ SoCs based on this grounding work later on, if anyone will want to implement it. Changelog: v2: - Replaced Core voltage regulator with a Core power domain. The voltage control is now done using GENPD API. This was suggested by Ulf Hansson. - Added basic runtime PM and GENPD support to 2d, 3d, host1x and clk drivers. - Added new core-power-domain and clk-device drivers. Some high-freq PLLs and clocks require a higher minimum core voltage and the new clk-device driver manages the voltage for these clocks based on the clock state. - Moved voltage scaling entirely to the new clk-device driver for devices which don't require advanced power management, like PWM for example. - Added devm_tegra_core_dev_init_opp_table() common helper which sets up OPP table for Tegra drivers. - Added resource-managed version for OPP API functions, as it was discussed previously in the comments to v1. - Added new APIs, features and fixed various bugs related to voltage scaling and power management done via GENPD API. Dmitry Osipenko (48): dt-bindings: memory: tegra20: emc: Replace core regulator with power domain dt-bindings: memory: tegra30: emc: Replace core regulator with power domain dt-bindings: memory: tegra124: emc: Replace core regulator with power domain dt-bindings: host1x: Document OPP and power domain properties media: dt: bindings: tegra-vde: Document OPP and power domain properties dt-bindings: clock: tegra: Document clocks sub-node dt-bindings: arm: tegra: Add binding for core power domain regulator: Make regulator_sync_voltage() usable by coupled regulators opp: Add dev_pm_opp_sync_regulators() opp: Add dev_pm_opp_set_voltage() opp: Add dev_pm_opp_find_level_ceil() opp: Add dev_pm_opp_get_required_pstate() opp: Add resource-managed versions of OPP API functions opp: Filter out OPPs based on availability of a required-OPP opp: Support set_opp() customization without requiring to use regulators opp: Handle missing OPP table in dev_pm_opp_xlate_performance_state() opp: Correct debug message in _opp_add_static_v2() opp: Print OPP level in debug message of _opp_add_static_v2() opp: Fix adding OPP entries in a wrong order if rate is unavailable PM: domains: Make set_performance_state() callback optional PM: domains: Add "performance" column to debug summary soc/tegra: pmc: Fix imbalanced clock disabling in error code path soc/tegra: pmc: Pulse resets after removing power clamp soc/tegra: pmc: Ensure that clock rates aren't too high soc/tegra: pmc: Print out domain name when reset fails to acquire soc/tegra: Add devm_tegra_core_dev_init_opp_table() soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default soc/tegra: Introduce core power domain driver soc/tegra: pmc: Link domains to the parent Core domain soc/tegra: regulators: Fix locking up when voltage-spread is out of range soc/tegra: regulators: Support Core domain state syncing clk: tegra: Support runtime PM, power domain and OPP gpu: host1x: Add host1x_channel_stop() gpu: host1x: Support power management drm/tegra: dc: Support OPP and SoC core voltage scaling drm/tegra: gr2d: Correct swapped device-tree compatibles drm/tegra: gr2d: Support OPP and power management drm/tegra: g3d: Support OPP and power management drm/tegra: vic: Stop channel before suspending media: staging: tegra-vde: Support OPP and generic power domain memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree ARM: tegra: acer-a500: Enable core voltage scaling ARM: tegra: ventana: Enable core voltage scaling ARM: tegra: ventana: Support CPU voltage scaling and thermal throttling ARM: tegra: cardhu: Support CPU voltage scaling and thermal throttling .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 + .../bindings/clock/nvidia,tegra20-car.txt | 26 + .../bindings/clock/nvidia,tegra30-car.txt | 26 + .../display/tegra/nvidia,tegra20-host1x.txt | 49 + .../bindings/media/nvidia,tegra-vde.txt | 12 + .../nvidia,tegra124-emc.yaml | 6 +- .../memory-controllers/nvidia,tegra20-emc.txt | 4 +- .../nvidia,tegra30-emc.yaml | 6 +- .../boot/dts/tegra20-acer-a500-picasso.dts | 8 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +- arch/arm/boot/dts/tegra20-harmony.dts | 6 +- arch/arm/boot/dts/tegra20-paz00.dts | 46 +- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 +++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 6 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 6 +- arch/arm/boot/dts/tegra20-trimslice.dts | 12 + arch/arm/boot/dts/tegra20-ventana.dts | 78 +- arch/arm/boot/dts/tegra20.dtsi | 220 +++ .../tegra30-asus-nexus7-grouper-common.dtsi | 4 + arch/arm/boot/dts/tegra30-beaver.dts | 4 + arch/arm/boot/dts/tegra30-cardhu.dtsi | 81 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 20 +- arch/arm/boot/dts/tegra30-ouya.dts | 4 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 358 +++++ drivers/base/power/domain.c | 33 +- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-device.c | 222 +++ drivers/clk/tegra/clk-divider.c | 2 +- drivers/clk/tegra/clk-periph-gate.c | 2 +- drivers/clk/tegra/clk-periph.c | 2 +- drivers/clk/tegra/clk-pll.c | 2 +- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-periph.c | 140 +- drivers/clk/tegra/clk-tegra114.c | 1 + drivers/clk/tegra/clk-tegra124.c | 1 + drivers/clk/tegra/clk-tegra20-emc.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 123 +- drivers/clk/tegra/clk-tegra210.c | 1 + drivers/clk/tegra/clk-tegra30.c | 133 +- drivers/clk/tegra/clk.c | 89 ++ drivers/clk/tegra/clk.h | 7 + drivers/gpu/drm/tegra/dc.c | 66 +- drivers/gpu/drm/tegra/gr2d.c | 77 +- drivers/gpu/drm/tegra/gr3d.c | 264 ++- drivers/gpu/drm/tegra/vic.c | 15 + drivers/gpu/host1x/channel.c | 8 + drivers/gpu/host1x/dev.c | 102 +- drivers/memory/tegra/tegra20-emc.c | 57 +- drivers/memory/tegra/tegra30-emc.c | 57 +- drivers/opp/core.c | 390 ++++- drivers/opp/of.c | 34 +- drivers/opp/opp.h | 2 +- drivers/regulator/core.c | 6 + drivers/soc/tegra/Kconfig | 19 + drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/common.c | 137 ++ drivers/soc/tegra/core-power-domain.c | 125 ++ drivers/soc/tegra/pmc.c | 122 +- drivers/soc/tegra/regulators-tegra20.c | 19 +- drivers/soc/tegra/regulators-tegra30.c | 20 +- drivers/staging/media/tegra-vde/vde.c | 63 +- include/linux/host1x.h | 1 + include/linux/pm_opp.h | 81 + include/soc/tegra/common.h | 41 + 65 files changed, 5458 insertions(+), 403 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml create mode 100644 drivers/clk/tegra/clk-device.c create mode 100644 drivers/soc/tegra/core-power-domain.c -- 2.29.2

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[PULL] drm-misc-fixes
by Thomas Zimmermann 12 Jan '21

12 Jan '21

Hi Dave and Daniel, here's this week's PR for drm-misc-fixes. Best regards Thomas drm-misc-fixes-2021-01-12: * dma-buf: Fix a memory leak in CMAV heap * drm: Fix format check for legacy pageflips * ttm: Pass correct address to dma_mapping_error(); Use mutex in pool shrinker The following changes since commit a73858ef4d5e1d425e171f0f6a52864176a6a979: drm/ttm: unexport ttm_pool_init/fini (2021-01-07 14:25:43 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-01-12 for you to fetch changes up to bb52cb0dec8d2fecdb22843a805131478a180728: drm/ttm: make the pool shrinker lock a mutex (2021-01-12 14:02:08 +0100) ---------------------------------------------------------------- Short summary of fixes pull: * dma-buf: Fix a memory leak in CMAV heap * drm: Fix format check for legacy pageflips * ttm: Pass correct address to dma_mapping_error(); Use mutex in pool shrinker ---------------------------------------------------------------- Bas Nieuwenhuizen (1): drm: Check actual format for legacy pageflip. Christian König (1): drm/ttm: make the pool shrinker lock a mutex Jeremy Cline (1): drm/ttm: Fix address passed to dma_mapping_error() in ttm_pool_map() John Stultz (1): dma-buf: cma_heap: Fix memory leak in CMA heap drivers/dma-buf/heaps/cma_heap.c | 3 +++ drivers/gpu/drm/drm_plane.c | 9 ++++++++- drivers/gpu/drm/ttm/ttm_pool.c | 22 +++++++++++----------- 3 files changed, 22 insertions(+), 12 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer

1 0

[PATCH AUTOSEL 4.19 15/16] drm/msm: Call msm_init_vram before binding the gpu
by Sasha Levin 12 Jan '21

12 Jan '21

From: Craig Tatlor <ctatlor97(a)gmail.com> [ Upstream commit d863f0c7b536288e2bd40cbc01c10465dd226b11 ] vram.size is needed when binding a gpu without an iommu and is defined in msm_init_vram(), so run that before binding it. Signed-off-by: Craig Tatlor <ctatlor97(a)gmail.com> Reviewed-by: Brian Masney <masneyb(a)onstation.org> Tested-by: Alexey Minnekhanov <alexeymin(a)postmarketos.org> Signed-off-by: Rob Clark <robdclark(a)chromium.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/msm/msm_drv.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 3ba3ae9749bec..81de5e1659551 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -483,14 +483,14 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) drm_mode_config_init(ddev); - /* Bind all our sub-components: */ - ret = component_bind_all(dev, ddev); + ret = msm_init_vram(ddev); if (ret) goto err_destroy_mdss; - ret = msm_init_vram(ddev); + /* Bind all our sub-components: */ + ret = component_bind_all(dev, ddev); if (ret) - goto err_msm_uninit; + goto err_destroy_mdss; if (!dev->dma_parms) { dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), -- 2.27.0

1 0

[PATCH AUTOSEL 5.4 27/28] drm/msm: Call msm_init_vram before binding the gpu
by Sasha Levin 12 Jan '21

12 Jan '21

From: Craig Tatlor <ctatlor97(a)gmail.com> [ Upstream commit d863f0c7b536288e2bd40cbc01c10465dd226b11 ] vram.size is needed when binding a gpu without an iommu and is defined in msm_init_vram(), so run that before binding it. Signed-off-by: Craig Tatlor <ctatlor97(a)gmail.com> Reviewed-by: Brian Masney <masneyb(a)onstation.org> Tested-by: Alexey Minnekhanov <alexeymin(a)postmarketos.org> Signed-off-by: Rob Clark <robdclark(a)chromium.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/msm/msm_drv.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 108632a1f2438..8d9d86c76a4e9 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -432,14 +432,14 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) drm_mode_config_init(ddev); - /* Bind all our sub-components: */ - ret = component_bind_all(dev, ddev); + ret = msm_init_vram(ddev); if (ret) goto err_destroy_mdss; - ret = msm_init_vram(ddev); + /* Bind all our sub-components: */ + ret = component_bind_all(dev, ddev); if (ret) - goto err_msm_uninit; + goto err_destroy_mdss; if (!dev->dma_parms) { dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), -- 2.27.0

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dri-devel January 2021