dri-devel December 2021

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720 discussions

[PATCH v3] drm/dp: Add Additional DP2 Headers
by Fangzhi Zuo 03 Feb '22

03 Feb '22

Include FEC, DSC, Link Training related headers. Change since v2 - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT Signed-off-by: Fangzhi Zuo <Jerry.Zuo(a)amd.com> --- This patch is based on top of the other DP2.0 work in "drm/dp: add LTTPR DP 2.0 DPCD addresses" --- include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..a1df35aa6e68 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -453,6 +453,7 @@ struct drm_panel; # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ @@ -537,6 +538,9 @@ struct drm_panel; #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 +/* DFP Capability Extension */ +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -688,6 +692,7 @@ struct drm_panel; #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ # define DP_DECOMPRESSION_EN (1 << 0) +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE BIT(0) @@ -743,6 +748,7 @@ struct drm_panel; # define DP_RECEIVE_PORT_0_STATUS (1 << 0) # define DP_RECEIVE_PORT_1_STATUS (1 << 1) # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ #define DP_ADJUST_REQUEST_LANE0_1 0x206 #define DP_ADJUST_REQUEST_LANE2_3 0x207 @@ -865,6 +871,8 @@ struct drm_panel; # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 # define DP_PHY_TEST_PATTERN_CP2520 0x5 +#define DP_PHY_SQUARE_PATTERN 0x249 + #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 @@ -1109,6 +1117,18 @@ struct drm_panel; #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 + +/* DSC Extended Capability Branch Total DSC Resources */ +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +# define DP_DSC_DECODER_COUNT_SHIFT 5 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 + /* Protocol Converter Extension */ /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ #define DP_CEC_TUNNELING_CAPABILITY 0x3000 -- 2.25.1

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[PATCH v3 0/2] drm/panel: Add support for LG.Philips SW43101 DSI video mode panel
by Yassine Oudjana 03 Feb '22

03 Feb '22

This adds a driver for the LG.Philips SW43101 FHD (1080x1920) 58Hz OLED DSI video mode panel, found on the Xiaomi Mi Note 2. Changes since v2: - Make the DT schema patch first in the series. - Use backlight_get_brightness where needed. - Remove 0xff mask from return value in sw43101_bl_get_brightness. - Constify struct backlight_properties props in sw43101_create_backlight. Changes since v1: - Add regulator support. - Add MAINTAINERS entry. - Dual-license DT binding. Yassine Oudjana (2): dt-bindings: display: Add DT schema for LG.Philips SW43101 drm/panel: Add driver for LG.Philips SW43101 DSI video mode panel .../display/panel/lgphilips,sw43101.yaml | 75 ++++ MAINTAINERS | 6 + drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-lgphilips-sw43101.c | 358 ++++++++++++++++++ 5 files changed, 450 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/lgphilips,sw43101.yaml create mode 100644 drivers/gpu/drm/panel/panel-lgphilips-sw43101.c -- 2.33.1

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[PATCH v6 0/6] drm: sun4i: dsi: Bridge support
by Jagan Teki 02 Feb '22

02 Feb '22

This series add bridge support for Allwinner DSI controller. In addition to previous version, this series add bridge support only not doing any bridge conversion at the moment. Previous version changes [1]. Patch 1: Drop the DRM bind race while attaching bridges Patch 2: Move component_add into sun6i_dsi_attach Patch 3: Add Bridge driver Patch 4: Add mode_set API Patch 5: Enable DSI Panel Patch 6: Enable DSI Bridge Patch 7: Enable DSI Bridge (I2C) [1] https://patchwork.kernel.org/project/dri-devel/cover/20211122065223.88059-1… Any inputs? Jagan. Jagan Teki (6): drm: sun4i: dsi: Drop DRM bind race with bridge attach drm: sun4i: dsi: Add component only once DSI device attached drm: sun4i: dsi: Add bridge support [DO NOT MERGE] ARM: dts: sun8i: bananapi-m2m: Enable iS070WV20-CT16 DSI Panel [DO NOT MERGE] ARM: dts: sun8i: bananapi-m2m: Enable ICN6211 DSI Bridge [DO NOT MERGE] ARM: dts: sun8i: bananapi-m2m: Enable DLPC3433 Bridge (I2C) .../boot/dts/sun8i-r16-bananapi-m2m-i2c.dts | 69 +++++++ .../boot/dts/sun8i-r16-bananapi-m2m-panel.dts | 41 ++++ arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 64 ++++++ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 187 ++++++++---------- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 10 +- 5 files changed, 256 insertions(+), 115 deletions(-) -- 2.25.1

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[Bug 214801] New: polaris11 (rx560) regression
by bugzilla-daemon＠bugzilla.kernel.org 01 Feb '22

01 Feb '22

https://bugzilla.kernel.org/show_bug.cgi?id=214801 Bug ID: 214801 Summary: polaris11 (rx560) regression Product: Drivers Version: 2.5 Kernel Version: 5.14.14 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: roxmail(a)list.ru Regression: No Created attachment 299307 --> https://bugzilla.kernel.org/attachment.cgi?id=299307&action=edit dmesg After a long using 4.19.122, i am trying to move for a newer kernel (my xhci greatly improved since), currently it is 5.14.14 and there are noticeable slowdown. For a numbers the Unigine Heaven Benchmark 4.0 (linux OpenGL) was used. 4.19.122: FPS: 43.9 Score: 1105 Min FPS: 15.2 Max FPS: 90.7 5.14.14: FPS: 31.4 Score: 790 Min FPS: 22.4 Max FPS: 60.1 And there are flickering artifacts visible while benchmarking with newer kernel. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

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[PARCH v2 0/7] drm/msm/dpu: merge dpu_core_irq into dpu_hw_interrupts
by Dmitry Baryshkov 01 Feb '22

01 Feb '22

This patch series reworks DPU's irq handling code by merging dpu_core_irq into dpu_hw_intr, reworking/dropping irq-related helpers and wrappers, etc. Changes since v1: - Rework callbacks registration code to allow just single callback per interrupt. This removes need to do any memory allocation in reg/unreg code and simplifies handling of interrupts. The following changes since commit 7e0230fd096c03e9662e66150f951075dd16e496: drm/msm/mdp5: provide dynamic bandwidth management (2021-06-17 09:51:44 -0700) are available in the Git repository at: https://git.linaro.org/people/dmitry.baryshkov/kernel.git dpu-irq-simplify-5 for you to fetch changes up to b2ae835c61b2065037c55b4596e16053484f4904: drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx (2021-06-18 01:12:04 +0300) ---------------------------------------------------------------- Dmitry Baryshkov (7): drm/msm/dpu: squash dpu_core_irq into dpu_hw_interrupts drm/msm/dpu: don't clear IRQ register twice drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr drm/msm/dpu: allow just single IRQ callback drm/msm/dpu: remove extra wrappers around dpu_core_irq drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 256 -------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 30 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 111 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 66 +----- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 99 ++++---- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 56 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 264 +++++++++++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 96 +------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 27 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 25 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 51 ++-- 12 files changed, 334 insertions(+), 748 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c

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[PATCH] dma-resv: some doc polish for iterators
by Daniel Vetter 31 Jan '22

31 Jan '22

Hammer it a bit more in that iterators can be restarted and when that matters, plus suggest to prefer the locked version whenver. Also delete the two leftover kerneldoc for static functions plus sprinkle some more links while at it. Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- drivers/dma-buf/dma-resv.c | 26 ++++++++++++-------------- include/linux/dma-resv.h | 13 ++++++++++++- 2 files changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 9eb2baa387d4..1453b664c405 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -323,12 +323,6 @@ void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) } EXPORT_SYMBOL(dma_resv_add_excl_fence); -/** - * dma_resv_iter_restart_unlocked - restart the unlocked iterator - * @cursor: The dma_resv_iter object to restart - * - * Restart the unlocked iteration by initializing the cursor object. - */ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) { cursor->seq = read_seqcount_begin(&cursor->obj->seq); @@ -344,14 +338,6 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) cursor->is_restarted = true; } -/** - * dma_resv_iter_walk_unlocked - walk over fences in a dma_resv obj - * @cursor: cursor to record the current position - * - * Return all the fences in the dma_resv object which are not yet signaled. - * The returned fence has an extra local reference so will stay alive. - * If a concurrent modify is detected the whole iteration is started over again. - */ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) { struct dma_resv *obj = cursor->obj; @@ -387,6 +373,12 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj. * @cursor: the cursor with the current position * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_first() whenver possible. + * * Returns the first fence from an unlocked dma_resv obj. */ struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) @@ -406,6 +398,10 @@ EXPORT_SYMBOL(dma_resv_iter_first_unlocked); * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj. * @cursor: the cursor with the current position * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_next() whenver possible. + * * Returns the next fence from an unlocked dma_resv obj. */ struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) @@ -431,6 +427,8 @@ EXPORT_SYMBOL(dma_resv_iter_next_unlocked); * dma_resv_iter_first - first fence from a locked dma_resv object * @cursor: cursor to record the current position * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * * Return the first fence in the dma_resv object while holding the * &dma_resv.lock. */ diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h index dbd235ab447f..ebe908592ac3 100644 --- a/include/linux/dma-resv.h +++ b/include/linux/dma-resv.h @@ -153,6 +153,13 @@ struct dma_resv { * struct dma_resv_iter - current position into the dma_resv fences * * Don't touch this directly in the driver, use the accessor function instead. + * + * IMPORTANT + * + * When using the lockless iterators like dma_resv_iter_next_unlocked() or + * dma_resv_for_each_fence_unlocked() beware that the iterator can be restarted. + * Code which accumulates statistics or similar needs to check for this with + * dma_resv_iter_is_restarted(). */ struct dma_resv_iter { /** @obj: The dma_resv object we iterate over */ @@ -243,7 +250,11 @@ static inline bool dma_resv_iter_is_restarted(struct dma_resv_iter *cursor) * &dma_resv.lock and using RCU instead. The cursor needs to be initialized * with dma_resv_iter_begin() and cleaned up with dma_resv_iter_end(). Inside * the iterator a reference to the dma_fence is held and the RCU lock dropped. - * When the dma_resv is modified the iteration starts over again. + * + * Beware that the iterator can be restarted when the struct dma_resv for + * @cursor is modified. Code which accumulates statistics or similar needs to + * check for this with dma_resv_iter_is_restarted(). For this reason prefer the + * lock iterator dma_resv_for_each_fence() whenever possible. */ #define dma_resv_for_each_fence_unlocked(cursor, fence) \ for (fence = dma_resv_iter_first_unlocked(cursor); \ -- 2.33.0

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[PATCH v5 0/4] arm: dts: qcom: sc7280: Add display DT nodes for sc7280
by Sankeerth Billakanti 31 Jan '22

31 Jan '22

Add display devicetree support for sc7280 platform. Krishna Manikandan (1): arm64: dts: qcom: sc7280: add display dt nodes Kuogee Hsieh (1): arm64: dts: qcom: sc7280: Add Display Port node Rajeev Nandan (1): arm64: dts: qcom: sc7280: Add DSI display nodes Sankeerth Billakanti (1): arm64: dts: qcom: sc7280: add edp display dt nodes arch/arm64/boot/dts/qcom/sc7280.dtsi | 390 ++++++++++++++++++++++++++++++++++- 1 file changed, 388 insertions(+), 2 deletions(-) -- 2.7.4

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[PATCH v4 4/4] arm64: dts: qcom: sc7280: Add Display Port node
by Sankeerth Billakanti 31 Jan '22

31 Jan '22

From: Kuogee Hsieh <khsieh(a)codeaurora.org> Signed-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> Reviewed-by: Stephen Boyd <swboyd(a)chromium.org> Signed-off-by: Sankeerth Billakanti <quic_sbillaka(a)quicinc.com> --- Changes in v4: - Add the patch to display DT change series (Bjorn Andersson) - Remove the trailing whitespaces arch/arm64/boot/dts/qcom/sc7280.dtsi | 90 +++++++++++++++++++++++++++++++++++- 1 file changed, 88 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5ad500e..0b2ffd5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2693,8 +2693,8 @@ <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>, + <&dp_phy 0>, + <&dp_phy 1>, <&edp_phy 0>, <&edp_phy 1>; clock-names = "bi_tcxo", @@ -2791,6 +2791,13 @@ remote-endpoint = <&edp_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -3002,6 +3009,79 @@ status = "disabled"; }; + + msm_dp: displayport-controller@ae90000 { + compatible = "qcom,sc7280-dp"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; pdc: interrupt-controller@b220000 { @@ -3104,6 +3184,12 @@ bias-pull-up; }; + dp_hot_plug_det: dp-hot-plug-det { + pins = "gpio47"; + function = "dp_hot"; + bias-disable; + }; + qspi_clk: qspi-clk { pins = "gpio14"; function = "qspi_clk"; -- 2.7.4

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[PATCH v4 1/4] arm64: dts: qcom: sc7280: add display dt nodes
by Sankeerth Billakanti 31 Jan '22

31 Jan '22

From: Krishna Manikandan <quic_mkrishn(a)quicinc.com> Add mdss and mdp DT nodes for sc7280. Signed-off-by: Krishna Manikandan <quic_mkrishn(a)quicinc.com> Reported-by: kernel test robot <lkp(a)intel.com> Reviewed-by: Stephen Boyd <swboyd(a)chromium.org> Reported-by: kernel test robot <lkp(a)intel.com> Signed-off-by: Sankeerth Billakanti <quic_sbillaka(a)quicinc.com> --- Changes in v4: None Changes in v3: None Changes in v2: - Rename display dt nodes (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) arch/arm64/boot/dts/qcom/sc7280.dtsi | 90 ++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 365a2e0..a4536b6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2704,6 +2704,96 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sc7280-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0 0x0ae01000 0 0x8f030>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + status = "disabled"; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-506666667 { + opp-hz = /bits/ 64 <506666667>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- 2.7.4

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[Bug 214197] New: [Asus G713QY] RX6800M not usable after exiting Vulkan application
by bugzilla-daemon＠bugzilla.kernel.org 30 Jan '22

30 Jan '22

https://bugzilla.kernel.org/show_bug.cgi?id=214197 Bug ID: 214197 Summary: [Asus G713QY] RX6800M not usable after exiting Vulkan application Product: Drivers Version: 2.5 Kernel Version: 5.13.13 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: velemas(a)gmail.com Regression: No Asus ROG Strix G17 Advantage Edition (G713QY) has hybrid-graphics with dGPU RX6800M. After exiting any Vulkan application, it becomes unusable. Vulkaninfo sees dGPU before Vulkan app and does not see RX6800M after. After Vulkan app close, dmesg reports: [ 154.385749] amdgpu 0000:03:00.0: amdgpu: RAS: optional ras ta ucode is not available [ 154.401405] amdgpu 0000:03:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available [ 154.401409] amdgpu 0000:03:00.0: amdgpu: SMU is resuming... [ 159.038150] amdgpu 0000:03:00.0: amdgpu: message: RunDcBtc (54) param: 0x00000000 is timeout (no response) [ 159.038154] amdgpu 0000:03:00.0: amdgpu: Failed to setup smc hw! [ 159.038156] [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <smu> failed -62 [ 159.038220] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_resume failed (-62). Using amdgpu.runpm=0 parameter fixes the issue. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

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