dri-devel April 2021

dri-devel@lists.freedesktop.org

317 participants
715 discussions

[PATCH 0/2] drm/tegra: Fix device/module refs for DP
by Lyude Paul 14 May '21

14 May '21

This patch series fixes a regression that was introduced by one of the changes I made to when Tegra registers its AUX adapters, along with fixing some reference leaks that I found along the way. !!!NOTE!!! There's one thing I'm not entirely sure about, which is the use of module references (e.g. try_module_get()) here. If I'm understanding how this code worked previously: since the get_device call in tegra_sor_probe() was previously the i2c adapter for the AUX channel - which itself is initialized in drm_dp_aux_register() - then I -think- that the module owner for the DDC adapter would likely have been drm_kms_helper. With these changes, if I'm understanding things correctly we're now just grabbing a module reference for ourselves - something which might not be the best idea? If anyone could confirm if I need to fix this or not that'd be appreciated, along with reviews of course :P Lyude Paul (2): drm/tegra: Get ref for DP AUX channel, not its ddc adapter drm/tegra: Fix DP AUX channel reference leaks drivers/gpu/drm/tegra/sor.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) -- 2.30.2

2 5

[PATCH v15 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings
by Krishna Manikandan 14 May '21

14 May '21

MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings. Signed-off-by: Krishna Manikandan <mkrishn(a)codeaurora.org> Changes in v2: - Changed dpu to DPU (Sam Ravnborg) - Fixed indentation issues (Sam Ravnborg) - Added empty line between different properties (Sam Ravnborg) - Replaced reference txt files with their corresponding yaml files (Sam Ravnborg) - Modified the file to use "|" only when it is necessary (Sam Ravnborg) Changes in v3: - Corrected the license used (Rob Herring) - Added maxItems for properties (Rob Herring) - Dropped generic descriptions (Rob Herring) - Added ranges property (Rob Herring) - Corrected the indendation (Rob Herring) - Added additionalProperties (Rob Herring) - Split dsi file into two, one for dsi controller and another one for dsi phy per target (Rob Herring) - Corrected description for pinctrl-names (Rob Herring) - Corrected the examples used in yaml file (Rob Herring) - Delete dsi.txt and dpu.txt (Rob Herring) Changes in v4: - Move schema up by one level (Rob Herring) - Add patternProperties for mdp node (Rob Herring) - Corrected description of some properties (Rob Herring) Changes in v5: - Correct the indentation (Rob Herring) - Remove unnecessary description from properties (Rob Herring) - Correct the number of interconnect entries (Rob Herring) - Add interconnect names for sc7180 (Rob Herring) - Add description for ports (Rob Herring) - Remove common properties (Rob Herring) - Add unevalutatedProperties (Rob Herring) - Reference existing dsi controller yaml in the common dsi controller file (Rob Herring) - Correct the description of clock names to include only the clocks that are required (Rob Herring) - Remove properties which are already covered under the common binding (Rob Herring) - Add dsi phy supply nodes which are required for sc7180 and sdm845 targets (Rob Herring) - Add type ref for syscon-sfpb (Rob Herring) Changes in v6: - Fixed errors during dt_binding_check (Rob Herring) - Add maxItems for phys and phys-names (Rob Herring) - Use unevaluatedProperties wherever required (Rob Herring) - Removed interrupt controller from required properties for dsi controller (Rob Herring) - Add constraints for dsi-phy reg-names based on the compatible phy version (Rob Herring) - Add constraints for dsi-phy supply nodes based on the compatible phy version (Rob Herring) Changes in v7: - Add default value for qcom,mdss-mdp-transfer-time-us (Rob Herring) - Modify the schema for data-lanes (Rob Herring) - Split the phy schema into separate schemas based on the phy version (Rob Herring) Changes in v8: - Resolve merge conflicts with latest dsi.txt file - Include dp yaml change also in the same series Changes in v9: - Combine target specific dsi controller yaml files to a single yaml file (Rob Herring) - Combine target specific dsi phy yaml files into a single yaml file (Rob Herring) - Use unevaluatedProperties and additionalProperties wherever required - Remove duplicate properties from common yaml files Changes in v10: - Split the patch into separate patches for DPU, DSI and PHY (Stephen Boyd) - Drop unnecessary fullstop (Stephen Boyd) - Add newline whereever required (Stephen Boyd) - Add description for clock used (Stephen Boyd) - Modify the description for interconnect entries (Stephen Boyd) - Drop assigned clock entries as it a generic property (Stephen Boyd) - Correct the definition for interrupts (Stephen Boyd) - Drop clock names from required properties (Stephen Boyd) - Drop labels for display nodes from example (Stephen Boyd) - Drop flags from interrupts entries (Stephen Boyd) Changes in v11: - Drop maxItems for clocks (Stephen Boyd) Changes in v12: - Add description for register property (Stephen Boyd) - Add maxItems for interrupts (Stephen Boyd) - Add description for iommus property (Stephen Boyd) - Add description for interconnects (Stephen Boyd) - Change display node name to display_controller (Stephen Boyd) Changes in v13: - Add maxItems for reg property (Stephen Boyd) - Add ranges property in example (Stephen Boyd) - Modify description for iommus property (Stephen Boyd) - Add Dp bindings for ports in the same patch (Stephen Boyd) - Remove soc from examples and change address and size cells accordingly (Stephen Boyd) - Add reference for ports Changes in v14: - Modify title for SC7180 and SDM845 yaml files (Stephen Boyd) - Add required list for display-controller node (Stephen Boyd) - Rename mdss node name to display-subsytem (Stephen Boyd) --- .../bindings/display/msm/dpu-sc7180.yaml | 215 +++++++++++++++++++++ .../bindings/display/msm/dpu-sdm845.yaml | 196 +++++++++++++++++++ .../devicetree/bindings/display/msm/dpu.txt | 141 -------------- 3 files changed, 411 insertions(+), 141 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml new file mode 100644 index 0000000..36531a5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SC7180 target + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7180 target. + +properties: + compatible: + items: + - const: qcom,sc7180-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + + interconnects: + items: + - description: Interconnect path specifying the port ids for data bus + + interconnect-names: + const: mdp0-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sc7180-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display ahb clock + - description: Display rotator clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: iface + - const: rot + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/port + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + + port@1: + type: object + description: DPU_INTF2 (DSI2) + port@2: + type: object + description: DPU_INTF0 (DP) + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: true + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7180.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7180-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x800 0x2>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7180-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml new file mode 100644 index 0000000..c744559 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SDM845 target + +maintainers: + - Krishna Manikandan <mkrishn(a)codeaurora.org> + +description: | + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SDM845 target. + +properties: + compatible: + items: + - const: qcom,sdm845-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + + ranges: true + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + items: + - const: qcom,sdm845-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/port + type: object + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + type: object + description: DPU_INTF1 (DSI1) + + port@1: + type: object + description: DPU_INTF2 (DSI2) + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: true + +examples: +- | + #include <dt-bindings/clock/qcom,dispcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt deleted file mode 100644 index 551ae26..0000000 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ /dev/null @@ -1,141 +0,0 @@ -Qualcomm Technologies, Inc. DPU KMS - -Description: - -Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates -sub-blocks like DPU display controller, DSI and DP interfaces etc. -The DPU display controller is found in SDM845 SoC. - -MDSS: -Required properties: -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" -- reg: physical base address and length of contoller's registers. -- reg-names: register region names. The following region is required: - * "mdss" -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required: - * "iface" - * "bus" - * "core" -- interrupts: interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- iommus: phandle of iommu device node. -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. -- interconnects : interconnect path specifier for MDSS according to - Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be - 2 paths corresponding to 2 AXI ports. -- interconnect-names : MDSS will have 2 port names to differentiate between the - 2 interconnect paths defined with interconnect specifier. - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -MDP: -Required properties: -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" -- reg: physical base address and length of controller's registers. -- reg-names : register region names. The following region is required: - * "mdp" - * "vbif" -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required. - * "bus" - * "iface" - * "core" - * "vsync" -- interrupts: interrupt line from DPU to MDSS. -- ports: contains the list of output ports from DPU device. These ports connect - to interfaces that are external to the DPU hardware, such as DSI, DP etc. - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - Port 0 -> DPU_INTF1 (DSI1) - Port 1 -> DPU_INTF2 (DSI2) - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -Example: - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - - power-domains = <&clock_dispcc 0>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>, - <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>; - - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_iommu 0>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xae00000 0xb2008>; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <0 0 300000000 19200000>; - - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - }; -- 2.7.4

3 10

linux-next: manual merge of the drm-intel tree with the drm tree
by Stephen Rothwell 14 May '21

14 May '21

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/display/intel_sprite.c between commit: 92f1d09ca4ed ("drm: Switch to %p4cc format modifier") from the drm tree and commit: 46d12f911821 ("drm/i915: migrate skl planes code new file (v5)") from the drm-intel tree. I fixed it up (I used the latter version of the file and applied the following patch) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. From: Stephen Rothwell <sfr(a)canb.auug.org.au> Date: Wed, 17 Mar 2021 14:05:42 +1100 Subject: [PATCH] merge fix for "drm: Switch to %p4cc format modifier" Signed-off-by: Stephen Rothwell <sfr(a)canb.auug.org.au> --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 1f335cb09149..45ceff436bf7 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1120,7 +1120,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; - struct drm_format_name_buf format_name; if (!fb) return 0; @@ -1168,9 +1167,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: drm_dbg_kms(&dev_priv->drm, - "Unsupported pixel format %s for 90/270!\n", - drm_get_format_name(fb->format->format, - &format_name)); + "Unsupported pixel format %p4cc for 90/270!\n", + &fb->format->format); return -EINVAL; default: break; -- 2.30.0 -- Cheers, Stephen Rothwell

2 4

[PATCH v1 1/1] video: ssd1307fb: Drop OF dependency
by Andy Shevchenko 14 May '21

14 May '21

After the commit 72915994e028 ("video: ssd1307fb: Make use of device properties") driver does not depend on OF, drop unneeded dependency. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- drivers/video/fbdev/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 4f02db65dede..7506b5949eb0 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -2209,7 +2209,6 @@ config FB_SIMPLE config FB_SSD1307 tristate "Solomon SSD1307 framebuffer support" depends on FB && I2C - depends on OF depends on GPIOLIB || COMPILE_TEST select FB_SYS_FOPS select FB_SYS_FILLRECT -- 2.30.2

2 2

[PATCH -next] drm/mediatek: Fix PM reference leak in mtk_crtc_ddp_hw_init()
by Wang Li 13 May '21

13 May '21

pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to putting operation will result in reference leak here. Fix it by replacing it with pm_runtime_resume_and_get to keep usage counter balanced. Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Wang Li <wangli74(a)huawei.com> --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 54ab3a324752..f1954242d8f6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -259,7 +259,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) drm_connector_list_iter_end(&conn_iter); } - ret = pm_runtime_get_sync(crtc->dev->dev); + ret = pm_runtime_resume_and_get(crtc->dev->dev); if (ret < 0) { DRM_ERROR("Failed to enable power domain: %d\n", ret); return ret; -- 2.17.1

2 2

16 bpc fixed point (RGBA16) framebuffer support for core and AMD.
by Mario Kleiner 13 May '21

13 May '21

Hi, this patch series adds the fourcc's for 16 bit fixed point unorm framebuffers to the core, and then an implementation for AMD gpu's with DisplayCore. This is intended to allow for pageflipping to, and direct scanout of, Vulkan swapchain images in the format VK_FORMAT_R16G16B16A16_UNORM. I have patched AMD's GPUOpen amdvlk OSS driver to enable this format for swapchains, mapping to DRM_FORMAT_XBGR16161616: Link: https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecba… My main motivation for this is squeezing every bit of precision out of the hardware for scientific and medical research applications, where fp16 in the unorm range is limited to ~11 bpc effective linear precision in the upper half [0.5;1.0] of the unorm range, although the hardware could do at least 12 bpc. It has been successfully tested on AMD RavenRidge (DCN-1), and with Polaris11 (DCE-11.2). Up to two displays were active on RavenRidge (DP 2560x1440@144Hz + HDMI 2560x1440@120Hz), the maximum supported on my hw, both running at 10 bpc DP output depth. Up to three displays were active on the Polaris (DP 2560x1440@144Hz + 2560x1440@100Hz USB-C DP-altMode-to-HDMI converter + eDP 2880x1800@60Hz Apple Retina panel), all running at 10 bpc output depth. No malfunctions, visual artifacts or other oddities were observed (apart from an adventureous mess of cables and adapters on my desk), suggesting it works. I used my automatic photometer measurement procedure to verify the effective output precision of 10 bpc DP native signal + spatial dithering in the gpu as enabled by the amdgpu driver. Results show the expected 12 bpc precision i hoped for -- the current upper limit for AMD display hw afaik. So it seems to work in the way i hoped :). Some open questions wrt. AMD DC, to be addressed in this patch series, or follow up patches if neccessary: - For the atomic check for plane scaling, the current patch will apply the same hw limits as for other rgb fixed point fb's, e.g., for 8 bpc rgb8. Is this correct? Or would we need to use the fp16 limits, because this is also a 64 bpp format? Or something new entirely? - I haven't added the new fourcc to the DCC tables yet. Should i? - I had to change an assert for DCE to allow 36bpp linebuffers (patch 4/5). It looks to me as if that assert was inconsistent with other places in the driver where COLOR_DEPTH121212 is supported, and looking at the code, the change seems harmless. At least on DCE-11.2 the change didn't cause any noticeable (by myself) or measurable (by my equipment) problems on any of the 3 connected displays. - Related to that change, while i needed to increase lb pixelsize to 36bpp to get > 10 bpc effective precision on DCN, i didn't need to do that on DCE. Also no change of lb pixelsize was needed on either DCN or DCe to get > 10 bpc precision for fp16 framebuffers, so something seems to behave differently for floating point 16 vs. fixed point 16. This all seems to suggest one could leave lb pixelsize at the old 30 bpp value on at least DCE-11.2 and still get the > 10 bpc precision if one wanted to avoid the changes of patch 4/5. Thanks, -mario

3 19

[PATCH v3 0/5] mediatek: hdmi: add MT8167 configuration
by Neil Armstrong 13 May '21

13 May '21

The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock, and is not validated and supported for HDMI modes out of HDMI CEA modes. To achieve this: - switch the mediatek HDMI bindings to YAML - add the MT8167 compatible - add a boolean to discard the non-CEA modes - add a value to specify mac TMDS supported clock - add a conf entry for the MT8167 compatible Changes since v4: - fixed bindings Neil Armstrong (5): dt-bindings: display: mediatek,hdmi: Convert to use graph schema dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings gpu/drm: mediatek: hdmi: add check for CEA modes only gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock gpu/drm: mediatek: hdmi: add MT8167 configuration .../display/mediatek/mediatek,cec.yaml | 52 +++++++ .../display/mediatek/mediatek,hdmi-ddc.yaml | 58 ++++++++ .../display/mediatek/mediatek,hdmi.txt | 136 ------------------ .../display/mediatek/mediatek,hdmi.yaml | 133 +++++++++++++++++ drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +++ 5 files changed, 260 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml -- 2.25.1

3 11

[PATCH v2] drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors are connected
by Kai-Heng Feng 11 May '21

11 May '21

Screen flickers rapidly when two 4K 60Hz monitors are in use. This issue doesn't happen when one monitor is 4K 60Hz (pixelclock 594MHz) and another one is 4K 30Hz (pixelclock 297MHz). The issue is gone after setting "power_dpm_force_performance_level" to "high". Following the indication, we found that the issue occurs when sclk is too low. So resolve the issue by disabling sclk switching when there are two monitors requires high pixelclock (> 297MHz). v2: - Only apply the fix to Oland. Signed-off-by: Kai-Heng Feng <kai.heng.feng(a)canonical.com> --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_pm.c | 8 ++++++++ drivers/gpu/drm/radeon/si_dpm.c | 3 +++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 42281fce552e6..56ed5634cebef 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1549,6 +1549,7 @@ struct radeon_dpm { void *priv; u32 new_active_crtcs; int new_active_crtc_count; + int high_pixelclock_count; u32 current_active_crtcs; int current_active_crtc_count; bool single_display; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 0c1950f4e146f..3861c0b98fcf3 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1767,6 +1767,7 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) struct drm_device *ddev = rdev->ddev; struct drm_crtc *crtc; struct radeon_crtc *radeon_crtc; + struct radeon_connector *radeon_connector; if (!rdev->pm.dpm_enabled) return; @@ -1776,6 +1777,7 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) /* update active crtc counts */ rdev->pm.dpm.new_active_crtcs = 0; rdev->pm.dpm.new_active_crtc_count = 0; + rdev->pm.dpm.high_pixelclock_count = 0; if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { @@ -1783,6 +1785,12 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) if (crtc->enabled) { rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); rdev->pm.dpm.new_active_crtc_count++; + if (!radeon_crtc->connector) + continue; + + radeon_connector = to_radeon_connector(radeon_crtc->connector); + if (radeon_connector->pixelclock_for_modeset > 297000) + rdev->pm.dpm.high_pixelclock_count++; } } } diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 9186095518047..3cc2b96a7f368 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -2979,6 +2979,9 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, (rdev->pdev->device == 0x6605)) { max_sclk = 75000; } + + if (rdev->pm.dpm.high_pixelclock_count > 1) + disable_sclk_switching = true; } if (rps->vce_active) { -- 2.30.2

2 2

Re: [RFC] Add BPF_PROG_TYPE_CGROUP_IOCTL
by Daniel Vetter 11 May '21

11 May '21

Adding gpu folks. On Tue, Nov 03, 2020 at 03:28:05PM -0800, Alexei Starovoitov wrote: > On Tue, Nov 03, 2020 at 05:57:47PM -0500, Kenny Ho wrote: > > On Tue, Nov 3, 2020 at 4:04 PM Alexei Starovoitov > > <alexei.starovoitov(a)gmail.com> wrote: > > > > > > On Tue, Nov 03, 2020 at 02:19:22PM -0500, Kenny Ho wrote: > > > > On Tue, Nov 3, 2020 at 12:43 AM Alexei Starovoitov > > > > <alexei.starovoitov(a)gmail.com> wrote: > > > > > On Mon, Nov 2, 2020 at 9:39 PM Kenny Ho <y2kenny(a)gmail.com> wrote: > > > > > > Sounds like either bpf_lsm needs to be made aware of cgv2 (which would > > > be a great thing to have regardless) or cgroup-bpf needs a drm/gpu specific hook. > > > I think generic ioctl hook is too broad for this use case. > > > I suspect drm/gpu internal state would be easier to access inside > > > bpf program if the hook is next to gpu/drm. At ioctl level there is 'file'. > > > It's probably too abstract for the things you want to do. > > > Like how VRAM/shader/etc can be accessed through file? > > > Probably possible through a bunch of lookups and dereferences, but > > > if the hook is custom to GPU that info is likely readily available. > > > Then such cgroup-bpf check would be suitable in execution paths where > > > ioctl-based hook would be too slow. > > Just to clarify, when you say drm specific hook, did you mean just a > > unique attach_type or a unique prog_type+attach_type combination? (I > > am still a bit fuzzy on when a new prog type is needed vs a new attach > > type. I think prog type is associated with a unique type of context > > that the bpf prog will get but I could be missing some nuances.) > > > > When I was thinking of doing an ioctl wide hook, the file would be the > > device file and the thinking was to have a helper function provided by > > device drivers to further disambiguate. For our (AMD's) driver, we > > have a bunch of ioctls for set/get/create/destroy > > (https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/amdkfd/k…) > > so the bpf prog can make the decision after the disambiguation. For > > example, we have an ioctl called "kfd_ioctl_set_cu_mask." You can > > Thanks for the pointer. > That's one monster ioctl. So much copy_from_user. > BPF prog would need to be sleepable to able to examine the args in such depth. > After quick glance at the code I would put a new hook into > kfd_ioctl() right before > retcode = func(filep, process, kdata); > At this point kdata is already copied from user space > and usize, that is cmd specific, is known. > So bpf prog wouldn't need to copy that data again. > That will save one copy. > To drill into details of kfd_ioctl_set_cu_mask() the prog would > need to be sleepable to do second copy_from_user of cu_mask. > At least it's not that big. > Yes, the attachment point will be amd driver specific, > but the program doesn't need to be. > It can be generic tracing prog that is agumented to use BTF. > Something like writeable tracepoint with BTF support would do. > So on the bpf side there will be minimal amount of changes. > And in the driver you'll add one or few writeable tracepoints > and the result of the tracepoint will gate > retcode = func(filep, process, kdata); > call in kfd_ioctl(). > The writeable tracepoint would need to be cgroup-bpf based. > So that's the only tricky part. BPF infra doesn't have > cgroup+tracepoint scheme. It's probably going to be useful > in other cases like this. See trace_nbd_send_request. Yeah I think this proposal doesn't work: - inspecting ioctl arguments that need copying outside of the driver/subsystem doing that copying is fundamentally racy - there's been a pile of cgroups proposal to manage gpus at the drm subsystem level, some by Kenny, and frankly this at least looks a bit like a quick hack to sidestep the consensus process for that. So once we push this into drivers it's not going to be a bpf hook anymore I think. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 21

[Bug 51381] New: [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting, when disabled via vgaswitcheroo
by bugzilla-daemon＠bugzilla.kernel.org 11 May '21

11 May '21

https://bugzilla.kernel.org/show_bug.cgi?id=51381 Summary: [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting, when disabled via vgaswitcheroo Product: Drivers Version: 2.5 Kernel Version: Linux version 3.6.9-1-ARCH (tobias@T-POWA-LX) (gcc version 4.7.2 (GCC) ) #1 SMP PREEMPT Tue Dec 4 08:04:10 CET 2012 Platform: All OS/Version: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) AssignedTo: drivers_video-dri(a)kernel-bugs.osdl.org ReportedBy: a(a)anrd.net Regression: Yes Created an attachment (id=88591) --> (https://bugzilla.kernel.org/attachment.cgi?id=88591) journald log After updating from 3.6.6 to 3.6.9 my laptop with Intel graphics and ATI HD 5650 will not resume from suspend. I use vgaswitcheroo to disable the ATI card at boot. On resume the computer almost hangs (I can press power button and wait 5 minutes for a proper shutdown, but no other interaction is possible). It logs a lot of messages saying: [drm:atom_op_jump] *ERROR* atombios stuck in loop for more than 5secs aborting [drm:atom_execute_table_locked] *ERROR* atombios stuck executing D098 (len 72, WS 0, PS 0) @ 0xD0C7 Steps to reproduce: echo "OFF" > /sys/kernel/debug/vgaswitcheroo/switch [suspend and resume] Actual results: Almost freeze. Expected results: Resume and work as normal. Log is attached, but if you need anything else just ask. -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are watching the assignee of the bug.

1 62

← Newer
1
...
13
14
15
16
17
18
19
...
72
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel April 2021