dri-devel August 2021

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Radeon NI: GIT kernel with the nislands_smc commit doesn't boot on a Freescale P5040 board and P.A.Semi Nemo board
by Christian Zigotzky 08 Nov '21

08 Nov '21

Hello, The Nemo board (A-EON AmigaOne X1000) [1] and the FSL P5040 Cyrus+ board (A-EON AmigaOne X5000) [2] with installed AMD Radeon HD6970 NI graphics cards (Cayman XT) [3] don't boot with the latest git kernel anymore after the commit "drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE branch" [4]. This git kernel boots in a virtual e5500 QEMU machine with a VirtIO-GPU [5]. I bisected today [6]. Result: drm/radeon/nislands_smc.h: Replace one-element array with flexible-array member in struct NISLANDS_SMC_SWSTATE branch (434fb1e7444a2efc3a4ebd950c7f771ebfcffa31) [4] is the first bad commit. I was able to revert this commit [7] and after a new compiling, the kernel boots without any problems on my AmigaOnes. After that I created a patch for reverting this commit for new git test kernels. [3] The kernel compiles and boots with this patch on my AmigaOnes. Please find attached the kernel config files. Please check the first bad commit. Thanks, Christian [1] https://en.wikipedia.org/wiki/AmigaOne_X1000 [2] http://wiki.amiga.org/index.php?title=X5000 [3] https://forum.hyperion-entertainment.com/viewtopic.php?f=35&t=4377 [4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… [5] qemu-system-ppc64 -M ppce500 -cpu e5500 -m 1024 -kernel uImage -drive format=raw,file=MintPPC32-X5000.img,index=0,if=virtio -netdev user,id=mynet0 -device virtio-net-pci,netdev=mynet0 -append "rw root=/dev/vda" -device virtio-vga -usb -device usb-ehci,id=ehci -device usb-tablet -device virtio-keyboard-pci -smp 4 -vnc :1 [6] https://forum.hyperion-entertainment.com/viewtopic.php?p=53074#p53074 [7] git revert 434fb1e7444a2efc3a4ebd950c7f771ebfcffa3

5 10

[PATCH] dma-buf/poll: Get a file reference for outstanding fence callbacks
by Michel Dänzer 04 Nov '21

04 Nov '21

From: Michel Dänzer <mdaenzer(a)redhat.com> This makes sure we don't hit the BUG_ON(dmabuf->cb_in.active || dmabuf->cb_out.active); in dma_buf_release, which could be triggered by user space closing the dma-buf file description while there are outstanding fence callbacks from dma_buf_poll. Cc: stable(a)vger.kernel.org Signed-off-by: Michel Dänzer <mdaenzer(a)redhat.com> --- drivers/dma-buf/dma-buf.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 6c520c9bd93c..ec25498a971f 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -65,12 +65,9 @@ static void dma_buf_release(struct dentry *dentry) BUG_ON(dmabuf->vmapping_counter); /* - * Any fences that a dma-buf poll can wait on should be signaled - * before releasing dma-buf. This is the responsibility of each - * driver that uses the reservation objects. - * - * If you hit this BUG() it means someone dropped their ref to the - * dma-buf while still having pending operation to the buffer. + * If you hit this BUG() it could mean: + * * There's a file reference imbalance in dma_buf_poll / dma_buf_poll_cb or somewhere else + * * dmabuf->cb_in/out.active are non-0 despite no pending fence callback */ BUG_ON(dmabuf->cb_in.active || dmabuf->cb_out.active); @@ -196,6 +193,7 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) static void dma_buf_poll_cb(struct dma_fence *fence, struct dma_fence_cb *cb) { struct dma_buf_poll_cb_t *dcb = (struct dma_buf_poll_cb_t *)cb; + struct dma_buf *dmabuf = container_of(dcb->poll, struct dma_buf, poll); unsigned long flags; spin_lock_irqsave(&dcb->poll->lock, flags); @@ -203,6 +201,8 @@ static void dma_buf_poll_cb(struct dma_fence *fence, struct dma_fence_cb *cb) dcb->active = 0; spin_unlock_irqrestore(&dcb->poll->lock, flags); dma_fence_put(fence); + /* Paired with get_file in dma_buf_poll */ + fput(dmabuf->file); } static bool dma_buf_poll_shared(struct dma_resv *resv, @@ -278,6 +278,9 @@ static __poll_t dma_buf_poll(struct file *file, poll_table *poll) spin_unlock_irq(&dmabuf->poll.lock); if (events & EPOLLOUT) { + /* Paired with fput in dma_buf_poll_cb */ + get_file(dmabuf->file); + if (!dma_buf_poll_shared(resv, dcb) && !dma_buf_poll_excl(resv, dcb)) /* No callback queued, wake up any other waiters */ @@ -299,6 +302,9 @@ static __poll_t dma_buf_poll(struct file *file, poll_table *poll) spin_unlock_irq(&dmabuf->poll.lock); if (events & EPOLLIN) { + /* Paired with fput in dma_buf_poll_cb */ + get_file(dmabuf->file); + if (!dma_buf_poll_excl(resv, dcb)) /* No callback queued, wake up any other waiters */ dma_buf_poll_cb(NULL, &dcb->cb); -- 2.32.0

4 7

[Bug 214029] New: [NAVI] Several memory leaks in amdgpu and ttm
by bugzilla-daemon＠bugzilla.kernel.org 04 Nov '21

04 Nov '21

https://bugzilla.kernel.org/show_bug.cgi?id=214029 Bug ID: 214029 Summary: [NAVI] Several memory leaks in amdgpu and ttm Product: Drivers Version: 2.5 Kernel Version: 5.14-rc5 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: erhard_f(a)mailbox.org CC: daniel(a)ffwll.ch Regression: No Created attachment 298265 --> https://bugzilla.kernel.org/attachment.cgi?id=298265&action=edit kernel dmesg (kernel 5.14-rc5, AMD FX-8370) Getting this on kernel 5.14-rc5 with my Radeon RX 5500. unreferenced object 0xffff888169af1b40 (size 216): comm "lightdm-gtk-gre", pid 662, jiffies 4294902381 (age 13444.937s) hex dump (first 32 bytes): d0 1b af 69 81 88 ff ff 60 cb b9 c0 ff ff ff ff ...i....`....... 80 73 48 e1 13 00 00 00 58 7d c1 0b 00 c9 ff ff .sH.....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff888263377700 (size 72): comm "sdma0", pid 345, jiffies 4294902381 (age 13444.937s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ f2 a0 4c e1 13 00 00 00 58 28 9b c9 81 88 ff ff ..L.....X(...... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff88811314b9c0 (size 216): comm "mate-session-ch", pid 768, jiffies 4294905408 (age 13434.854s) hex dump (first 32 bytes): 50 ba 14 13 81 88 ff ff 60 cb b9 c0 ff ff ff ff P.......`....... dc 7a c1 3a 16 00 00 00 58 7d c1 0b 00 c9 ff ff .z.:....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff888167ffc340 (size 72): comm "sdma0", pid 345, jiffies 4294905408 (age 13434.854s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ ac b5 c5 3a 16 00 00 00 58 e4 a7 01 81 88 ff ff ...:....X....... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff888113b6d240 (size 216): comm "mate-screensave", pid 57770, jiffies 4295052030 (age 12946.214s) hex dump (first 32 bytes): d0 d2 b6 13 81 88 ff ff 60 cb b9 c0 ff ff ff ff ........`....... a2 85 ff 05 88 00 00 00 58 7d c1 0b 00 c9 ff ff ........X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff8881c85d6e80 (size 72): comm "sdma0", pid 345, jiffies 4295052030 (age 12946.217s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 0c a0 03 06 88 00 00 00 58 34 14 75 82 88 ff ff ........X4.u.... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff888119b78940 (size 216): comm "mate-screensave", pid 98610, jiffies 4295149755 (age 12620.510s) hex dump (first 32 bytes): d0 89 b7 19 81 88 ff ff 60 cb b9 c0 ff ff ff ff ........`....... 08 db 28 de d3 00 00 00 58 7d c1 0b 00 c9 ff ff ..(.....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff8882589af700 (size 72): comm "sdma0", pid 345, jiffies 4295149755 (age 12620.514s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 17 3c 2d de d3 00 00 00 58 b4 df 67 81 88 ff ff .<-.....X..g.... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff8881274ccac0 (size 216): comm "mate-screensave", pid 98731, jiffies 4295150087 (age 12619.460s) hex dump (first 32 bytes): 50 cb 4c 27 81 88 ff ff 60 cb b9 c0 ff ff ff ff P.L'....`....... 7e bc 18 20 d4 00 00 00 58 7d c1 0b 00 c9 ff ff ~.. ....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff888255796940 (size 72): comm "sdma0", pid 345, jiffies 4295150087 (age 12619.464s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 0f be 1c 20 d4 00 00 00 58 70 a1 be 81 88 ff ff ... ....Xp...... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff88823ef75540 (size 216): comm "glxinfo", pid 173188, jiffies 4298442862 (age 1643.630s) hex dump (first 32 bytes): d0 55 f7 3e 82 88 ff ff 60 cb b9 c0 ff ff ff ff .U.>....`....... d7 bb 9c a7 cf 0a 00 00 58 7d c1 0b 00 c9 ff ff ........X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff88826dfee1c0 (size 72): comm "sdma0", pid 345, jiffies 4298442862 (age 1643.630s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 91 e3 a0 a7 cf 0a 00 00 58 04 01 14 81 88 ff ff ........X....... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff88823ef756c0 (size 216): comm "glxinfo:sh0", pid 173194, jiffies 4298442879 (age 1643.620s) hex dump (first 32 bytes): 50 57 f7 3e 82 88 ff ff 60 cb b9 c0 ff ff ff ff PW.>....`....... 3a 18 f8 aa cf 0a 00 00 58 7d c1 0b 00 c9 ff ff :.......X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff8882a950cb80 (size 72): comm "sdma0", pid 345, jiffies 4298442879 (age 1643.620s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 27 7b fc aa cf 0a 00 00 58 cc ec 19 81 88 ff ff '{......X....... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff888227171840 (size 216): comm "glxinfo", pid 173188, jiffies 4298442879 (age 1643.620s) hex dump (first 32 bytes): d0 18 17 27 82 88 ff ff 60 cb b9 c0 ff ff ff ff ...'....`....... f0 c7 0c ab cf 0a 00 00 58 7d c1 0b 00 c9 ff ff ........X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff8882a950cac0 (size 72): comm "sdma0", pid 345, jiffies 4298442879 (age 1643.620s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ f1 fe 10 ab cf 0a 00 00 58 9c ec 19 81 88 ff ff ........X....... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff88816aaca940 (size 216): comm "glxinfo", pid 173247, jiffies 4298445099 (age 1636.294s) hex dump (first 32 bytes): d0 a9 ac 6a 81 88 ff ff 60 cb b9 c0 ff ff ff ff ...j....`....... 4d 52 2f 64 d1 0a 00 00 58 7d c1 0b 00 c9 ff ff MR/d....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff88825fe8d700 (size 72): comm "sdma0", pid 345, jiffies 4298445099 (age 1636.294s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 63 72 33 64 d1 0a 00 00 58 64 7b 47 81 88 ff ff cr3d....Xd{G.... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff8881433c2940 (size 216): comm "glxinfo:sh0", pid 173253, jiffies 4298445116 (age 1636.240s) hex dump (first 32 bytes): d0 29 3c 43 81 88 ff ff 60 cb b9 c0 ff ff ff ff .)<C....`....... 1b 8a 79 67 d1 0a 00 00 58 7d c1 0b 00 c9 ff ff ..yg....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff88825fe8d580 (size 72): comm "sdma0", pid 345, jiffies 4298445116 (age 1636.240s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ 99 20 7e 67 d1 0a 00 00 58 a8 28 8b 82 88 ff ff . ~g....X.(..... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 unreferenced object 0xffff8881433c24c0 (size 216): comm "glxinfo", pid 173247, jiffies 4298445116 (age 1636.314s) hex dump (first 32 bytes): 50 25 3c 43 81 88 ff ff 60 cb b9 c0 ff ff ff ff P%<C....`....... 57 37 94 67 d1 0a 00 00 58 7d c1 0b 00 c9 ff ff W7.g....X}...... backtrace: [<ffffffffc0b9914f>] drm_sched_fence_create+0x1f/0x1d0 [gpu_sched] [<ffffffffc0b944de>] drm_sched_job_init+0x10e/0x240 [gpu_sched] [<ffffffffc138dd37>] amdgpu_job_submit+0x27/0x2d0 [amdgpu] [<ffffffffc0f7ae6e>] amdgpu_copy_buffer+0x49e/0x700 [amdgpu] [<ffffffffc0f7b6ca>] amdgpu_ttm_copy_mem_to_mem+0x5fa/0xf00 [amdgpu] [<ffffffffc0f7ce06>] amdgpu_bo_move+0x356/0x2180 [amdgpu] [<ffffffffc0a79897>] ttm_bo_handle_move_mem+0x1c7/0x620 [ttm] [<ffffffffc0a7d297>] ttm_bo_validate+0x2c7/0x450 [ttm] [<ffffffffc0f83444>] amdgpu_bo_fault_reserve_notify+0x2a4/0x640 [amdgpu] [<ffffffffc0f93313>] amdgpu_gem_fault+0x123/0x2d0 [amdgpu] [<ffffffffab55c3b3>] __do_fault+0xf3/0x3e0 [<ffffffffab56e5ab>] __handle_mm_fault+0x1bcb/0x2ac0 [<ffffffffab56f5ca>] handle_mm_fault+0x12a/0x490 [<ffffffffab0908b9>] do_user_addr_fault+0x259/0xb70 [<ffffffffac7b6935>] exc_page_fault+0x55/0xb0 [<ffffffffac800acb>] asm_exc_page_fault+0x1b/0x20 unreferenced object 0xffff8881dbf6b340 (size 72): comm "sdma0", pid 345, jiffies 4298445116 (age 1636.314s) hex dump (first 32 bytes): f0 f3 5c 69 81 88 ff ff 80 8a cf c1 ff ff ff ff ..\i............ f9 60 98 67 d1 0a 00 00 58 b4 28 8b 82 88 ff ff .`.g....X.(..... backtrace: [<ffffffffc0f70521>] amdgpu_fence_emit+0x91/0x790 [amdgpu] [<ffffffffc0fdd4bb>] amdgpu_ib_schedule+0x8cb/0x12f0 [amdgpu] [<ffffffffc138d09e>] amdgpu_job_run+0x35e/0x790 [amdgpu] [<ffffffffc0b9792e>] drm_sched_main+0x64e/0xc60 [gpu_sched] [<ffffffffab12fda2>] kthread+0x342/0x410 [<ffffffffab0030d2>] ret_from_fork+0x22/0x30 $ inxi -bZ System: Kernel: 5.14.0-rc5-bdver2 x86_64 bits: 64 Desktop: MATE 1.24.1 Distro: Gentoo Base System release 2.7 Machine: Type: Desktop System: Gigabyte product: N/A v: N/A serial: <superuser/root required> Mobo: Gigabyte model: 970-GAMING v: x.x serial: <superuser/root required> UEFI: American Megatrends v: F2 date: 04/06/2016 CPU: Info: 8-Core AMD FX-8370 [MCP] speed: 1727 MHz min/max: 1400/4000 MHz Graphics: Device-1: Advanced Micro Devices [AMD/ATI] Navi 14 [Radeon RX 5500/5500M / Pro 5500M] driver: amdgpu v: kernel Display: x11 server: X.Org 1.20.11 driver: amdgpu,ati unloaded: fbdev,modesetting,radeon resolution: 1920x1080~60Hz OpenGL: renderer: Radeon RX 5500 XT (NAVI14 DRM 3.42.0 5.14.0-rc5-bdver2 LLVM 12.0.1) v: 4.6 Mesa 21.1.4 Network: Device-1: Qualcomm Atheros Killer E2400 Gigabit Ethernet driver: alx $ lspci 00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD9x0/RX980 Host Bridge (rev 02) 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD/ATI] RD890S/RD990 I/O Memory Management Unit (IOMMU) 00:02.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 PCI to PCI bridge (PCI Express GFX port 0) 00:04.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 PCI to PCI bridge (PCI Express GPP Port 0) 00:06.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 PCI to PCI bridge (PCI Express GPP Port 2) 00:09.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 PCI to PCI bridge (PCI Express GPP Port 4) 00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) 00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller (rev 42) 00:14.2 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) (rev 40) 00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) 00:14.4 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to PCI Bridge (rev 40) 00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 00:15.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB700/SB800/SB900 PCI to PCI bridge (PCIE port 0) 00:16.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:16.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 01:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Upstream Port of PCI Express Switch (rev c5) 02:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch 03:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 14 [Radeon RX 5500/5500M / Pro 5500M] (rev c5) 03:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 HDMI Audio 04:00.0 USB controller: Renesas Technology Corp. uPD720201 USB 3.0 Host Controller (rev 03) 05:00.0 Non-Volatile memory controller: Shenzhen Longsys Electronics Co., Ltd. Device 2263 (rev 03) 06:00.0 USB controller: ASMedia Technology Inc. ASM1143 USB 3.1 Host Controller 08:00.0 Ethernet controller: Qualcomm Atheros Killer E2400 Gigabit Ethernet Controller (rev 10) # lspci -vv -s 03:00.0 03:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 14 [Radeon RX 5500/5500M / Pro 5500M] (rev c5) (prog-if 00 [VGA controller]) Subsystem: ASRock Incorporation Navi 14 [Radeon RX 5500/5500M / Pro 5500M] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 65 IOMMU group: 17 Region 0: Memory at c0000000 (64-bit, prefetchable) [size=256M] Region 2: Memory at d0000000 (64-bit, prefetchable) [size=2M] Region 4: I/O ports at e000 [size=256] Region 5: Memory at fe500000 (32-bit, non-prefetchable) [size=512K] Expansion ROM at 000c0000 [disabled] [size=128K] Capabilities: [48] Vendor Specific Information: Len=08 <?> Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L0s L1, Exit Latency L0s <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 16GT/s (ok), Width x16 (ok) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+ 10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1 EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- FRS- AtomicOpsCap: 32bit+ 64bit+ 128bitCAS- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, AtomicOpsCtl: ReqEn- LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS- LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+ EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest- Retimer- 2Retimers- CrosslinkRes: unsupported Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee01004 Data: 0025 Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- HeaderLog: 00000000 00000000 00000000 00000000 Capabilities: [200 v1] Physical Resizable BAR BAR 0: current size: 256MB, supported: 256MB 512MB 1GB 2GB 4GB 8GB BAR 2: current size: 2MB, supported: 2MB 4MB 8MB 16MB 32MB 64MB 128MB 256MB Capabilities: [240 v1] Power Budgeting <?> Capabilities: [270 v1] Secondary PCI Express LnkCtl3: LnkEquIntrruptEn- PerformEqu- LaneErrStat: 0 Capabilities: [2a0 v1] Access Control Services ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Capabilities: [2b0 v1] Address Translation Service (ATS) ATSCap: Invalidate Queue Depth: 00 ATSCtl: Enable-, Smallest Translation Unit: 00 Capabilities: [2c0 v1] Page Request Interface (PRI) PRICtl: Enable- Reset- PRISta: RF- UPRGI- Stopped+ Page Request Capacity: 00000100, Page Request Allocation: 00000000 Capabilities: [2d0 v1] Process Address Space ID (PASID) PASIDCap: Exec+ Priv+, Max PASID Width: 10 PASIDCtl: Enable- Exec- Priv- Capabilities: [320 v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Capabilities: [400 v1] Data Link Feature <?> Capabilities: [410 v1] Physical Layer 16.0 GT/s <?> Capabilities: [440 v1] Lane Margining at the Receiver <?> Kernel driver in use: amdgpu Kernel modules: amdgpu -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 29

[PATCH v11 0/4] Add MIPI rx DPI support
by Xin Ji 04 Nov '21

04 Nov '21

Hi all, this patch series implement MIPI rx DPI feature. Please help to review. This is the v11 version, rebase all patches on the latest code. Any mistakes, please let me know, I'll fix it in the next series. Change history: v11: Fix Rob Herring comment - Move swing register description in property. - Remove additional property. v10: Fix Rob Herring and Laurent Pinchart comments - Add more description about lane swing configuration in commit message. v9: Fix Neil Amstrong comment - use macro define 'V4L2_FWNODE_BUS_TYPE_PARALLEL' instead of fixing value. v8: Fix Laurent Pinchart comment - Expand the commit message. v7: - Rebase DT on the latest branch 'drm-misc-next'. - Remove HDCP patch. v6: Fix kernel robot compile warning v5: Fix Rob Herring, Hsin-Yi, Robert Foss comments - Rebase code on the branch 'drm-misc-next', refer video-interfaces.yaml - Seprate HDCP function to a new patch - Fix driver not correctly get 'bus-type' 'data-lanes' - Add audio HDMI codec function support v4: Fix Rob Herring comment - Rebase code on the branch 'drm-misc-next' - Change 'analogix,hdcp-support' type to boolean v3: Fix Rob Herring, Dan Carpenter, Nicolas comment - Split the patch, fix not correct return data - Fix several coding format - Split DP tx swing register setting to two property - Add HDCP support vender flag - remove 'analogix,swing-setting' and 'analogix,mipi-dpi-in' property v2: Fix Rob Herring comment - Fix yamllint warnings/errors in analogix,anx7625.yaml - Fix kernel robot compile warning v1: initial MIPI rx DPI feature support Xin Ji (4): dt-bindings:drm/bridge:anx7625:add vendor define drm/bridge: anx7625: fix not correct return value drm/bridge: anx7625: add MIPI DPI input feature drm/bridge: anx7625: add HDMI audio function .../display/bridge/analogix,anx7625.yaml | 65 ++- drivers/gpu/drm/bridge/analogix/anx7625.c | 458 ++++++++++++++++-- drivers/gpu/drm/bridge/analogix/anx7625.h | 23 +- 3 files changed, 491 insertions(+), 55 deletions(-) -- 2.25.1

4 14

[PATCH 0/4] Unregister mst connectors when hotplug
by Wayne Lin 02 Nov '21

02 Nov '21

By patches below, we change to clean up resources of a mst connector and put port's malloc_kref when we start to destroy a connector. * 09b974e8983 drm/amd/amdgpu_dm/mst: Remove ->destroy_connector() callback * 72dc0f51591 drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector However, find out that mst connectors won't reach connector destroy flow after hot unplug and hence will cause no more resources for new added connectors. Thus, this patch set is trying to solve observed registration/unregistration problem of mst connectors. Wayne Lin (4): drm/dp_mst: Put malloc_kref of vcpi pointing port when disable MST drm/dp_mst: Only create connector for connected end device drm/dp_mst: Put connector of disconnected end device when handling CSN drm/dp_mst: Release disconnected connectors when resume drivers/gpu/drm/drm_dp_mst_topology.c | 39 ++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) -- 2.17.1

3 25

[Bug 204987] New: general protection fault in amdgpu_dm_atomic_commit_tail (Vega64)
by bugzilla-daemon＠bugzilla.kernel.org 02 Nov '21

02 Nov '21

https://bugzilla.kernel.org/show_bug.cgi?id=204987 Bug ID: 204987 Summary: general protection fault in amdgpu_dm_atomic_commit_tail (Vega64) Product: Drivers Version: 2.5 Kernel Version: 5.3.1 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: steinex(a)nognu.de Regression: No drm.debug=0x54 log uploaded here due to attachment size limit: https://nognu.de/p/1569355650 This is on 5.3.1 with this patch series applied: https://patchwork.freedesktop.org/series/64505/ It happens between ~5 and ~45 minutes after the system is booted into X. There is no obvious pattern what triggers it. -- You are receiving this mail because: You are watching the assignee of the bug.

1 7

linux-next: build warning after merge of the drm tree
by Stephen Rothwell 28 Oct '21

28 Oct '21

Hi all, After merging the drm tree, today's linux-next build (x86_64 allmodconfig) produced this warning: WARNING: unmet direct dependencies detected for DRM_I915_WERROR Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && !COMPILE_TEST [=y] Selected by [m]: - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && EXPERT [=y] && DRM_I915 [=m] WARNING: unmet direct dependencies detected for DRM_I915_WERROR Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && !COMPILE_TEST [=y] Selected by [m]: - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && EXPERT [=y] && DRM_I915 [=m] WARNING: unmet direct dependencies detected for DRM_I915_WERROR Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && !COMPILE_TEST [=y] Selected by [m]: - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && EXPERT [=y] && DRM_I915 [=m] Maybe introduced by commit 4f86975f539d ("drm/i915: Add DEBUG_GEM to the recommended CI config") -- Cheers, Stephen Rothwell

3 7

[PATCH 00/47] GuC submission support
by Matthew Brost 27 Oct '21

27 Oct '21

As discussed in [1], [2] we are enabling GuC submission support in the i915. This is a subset of the patches in step 5 described in [1], basically it is absolute to enable CI with GuC submission on gen11+ platforms. This series itself will likely be broken down into smaller patch sets to merge. Likely into CTBs changes, basic submission, virtual engines, and resets. A following series will address the missing patches remaining from [1]. Locally tested on TGL machine and basic tests seem to be passing. Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> [1] https://patchwork.freedesktop.org/series/89844/ [2] https://patchwork.freedesktop.org/series/91417/ Daniele Ceraolo Spurio (1): drm/i915/guc: Unblock GuC submission on Gen11+ John Harrison (10): drm/i915/guc: Module load failure test for CT buffer creation drm/i915: Track 'serial' counts for virtual engines drm/i915/guc: Provide mmio list to be saved/restored on engine reset drm/i915/guc: Don't complain about reset races drm/i915/guc: Enable GuC engine reset drm/i915/guc: Fix for error capture after full GPU reset with GuC drm/i915/guc: Hook GuC scheduling policies up drm/i915/guc: Connect reset modparam updates to GuC policy flags drm/i915/guc: Include scheduling policies in the debugfs state dump drm/i915/guc: Add golden context to GuC ADS Matthew Brost (36): drm/i915/guc: Relax CTB response timeout drm/i915/guc: Improve error message for unsolicited CT response drm/i915/guc: Increase size of CTB buffers drm/i915/guc: Add non blocking CTB send function drm/i915/guc: Add stall timer to non blocking CTB send function drm/i915/guc: Optimize CTB writes and reads drm/i915/guc: Add new GuC interface defines and structures drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor drm/i915/guc: Add lrc descriptor context lookup array drm/i915/guc: Implement GuC submission tasklet drm/i915/guc: Add bypass tasklet submission path to GuC drm/i915/guc: Implement GuC context operations for new inteface drm/i915/guc: Insert fence on context when deregistering drm/i915/guc: Defer context unpin until scheduling is disabled drm/i915/guc: Disable engine barriers with GuC during unpin drm/i915/guc: Extend deregistration fence to schedule disable drm/i915: Disable preempt busywait when using GuC scheduling drm/i915/guc: Ensure request ordering via completion fences drm/i915/guc: Disable semaphores when using GuC scheduling drm/i915/guc: Ensure G2H response has space in buffer drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC drm/i915/guc: Update GuC debugfs to support new GuC drm/i915/guc: Add several request trace points drm/i915: Add intel_context tracing drm/i915/guc: GuC virtual engines drm/i915: Hold reference to intel_context over life of i915_request drm/i915/guc: Disable bonding extension with GuC submission drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs drm/i915/guc: Reset implementation for new GuC interface drm/i915: Reset GPU immediately if submission is disabled drm/i915/guc: Add disable interrupts to guc sanitize drm/i915/guc: Suspend/resume implementation for new interface drm/i915/guc: Handle context reset notification drm/i915/guc: Handle engine reset failure notification drm/i915/guc: Enable the timer expired interrupt for GuC drm/i915/guc: Capture error state on context reset drivers/gpu/drm/i915/gem/i915_gem_context.c | 30 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 41 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.h | 14 +- .../gpu/drm/i915/gt/intel_breadcrumbs_types.h | 7 + drivers/gpu/drm/i915/gt/intel_context.c | 41 +- drivers/gpu/drm/i915/gt/intel_context.h | 31 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 49 + drivers/gpu/drm/i915/gt/intel_engine.h | 72 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 182 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 71 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.h | 4 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 +- .../drm/i915/gt/intel_execlists_submission.c | 234 +- .../drm/i915/gt/intel_execlists_submission.h | 11 - drivers/gpu/drm/i915/gt/intel_gt.c | 21 + drivers/gpu/drm/i915/gt/intel_gt.h | 2 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +- drivers/gpu/drm/i915/gt/intel_gt_requests.c | 22 +- drivers/gpu/drm/i915/gt/intel_gt_requests.h | 9 +- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 - drivers/gpu/drm/i915/gt/intel_reset.c | 20 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 28 + drivers/gpu/drm/i915/gt/intel_rps.c | 4 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 46 +- .../gpu/drm/i915/gt/intel_workarounds_types.h | 1 + drivers/gpu/drm/i915/gt/mock_engine.c | 41 +- drivers/gpu/drm/i915/gt/selftest_context.c | 10 + drivers/gpu/drm/i915/gt/selftest_execlists.c | 20 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 15 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 82 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 106 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 460 +++- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 318 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 22 +- .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 25 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 88 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2197 +++++++++++++++-- .../gpu/drm/i915/gt/uc/intel_guc_submission.h | 17 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 102 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 11 + drivers/gpu/drm/i915/i915_debugfs.c | 2 + drivers/gpu/drm/i915/i915_debugfs_params.c | 31 + drivers/gpu/drm/i915/i915_gem_evict.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 25 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/i915_request.c | 159 +- drivers/gpu/drm/i915/i915_request.h | 21 + drivers/gpu/drm/i915/i915_scheduler.c | 6 + drivers/gpu/drm/i915/i915_scheduler.h | 6 + drivers/gpu/drm/i915/i915_scheduler_types.h | 5 + drivers/gpu/drm/i915/i915_trace.h | 197 +- .../gpu/drm/i915/selftests/igt_live_test.c | 2 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- 57 files changed, 4159 insertions(+), 787 deletions(-) -- 2.28.0

9 165

[PATCH 00/30] drm/i915/gem: ioctl clean-ups (v9)
by Jason Ekstrand 22 Oct '21

22 Oct '21

Overview: --------- This patch series attempts to clean up some of the IOCTL mess we've created over the last few years. The most egregious bit being context mutability. In summary, this series: 1. Drops two never-used context params: RINGSIZE and NO_ZEROMAP 2. Drops the entire CONTEXT_CLONE API 3. Implements SINGLE_TIMELINE with a syncobj instead of actually sharing intel_timeline between engines. 4. Adds a few sanity restrictions to the balancing/bonding API. 5. Implements a proto-ctx mechanism so that the engine set and VM can only be set early on in the lifetime of a context, before anything ever executes on it. This effectively makes the VM and engine set immutable. This series has been tested with IGT as well as the Iris, ANV, and the Intel media driver doing an 8K decode (this uses bonding/balancing). I've also done quite a bit of git archeology to ensure that nothing in here will break anything that's already shipped at some point in history. It's possible I've missed something, but I've dug quite a bit. Details and motivation: ----------------------- In very broad strokes, there's an effort going on right now within Intel to try and clean up and simplify i915 anywhere we can. We obviously don't want to break any shipping userspace but, as can be seen by this series, there's a lot i915 theoretically supports which userspace doesn't actually need. Some of this, like the two context params used here, were simply oversights where we went through the usual API review process and merged the i915 bits but the userspace bits never landed for some reason. Not all are so innocent, however. For instance, there's an entire context cloning API which allows one to create a context with certain parameters "cloned" from some other context. This entire API has never been used by any userspace except IGT and there were never patches to any other userspace to use it. It never should have landed. Also, when we added support for setting explicit engine sets and sharing VMs across contexts, people decided to do so via SET_CONTEXT_PARAM. While this allowed them to re-use existing API, it did so at the cost of making those states mutable which leads to a plethora of potential race conditions. There were even IGT tests merged to cover some of theses: - gem_vm_create@async-destroy and gem_vm_create@destroy-race which test swapping out the VM on a running context. - gem_ctx_persistence@replace* which test whether a client can escape a non-persistent context by submitting a hanging batch and then swapping out the engine set before the hang is detected. - api_intel_bb@bb-with-vm which tests the that intel_bb_assign_vm works properly. This API is never used by any other IGT test. There is also an entire deferred flush and set state framework in i915_gem_cotnext.c which exists for safely swapping out the VM while there is work in-flight on a context. So, clearly people knew that this API was inherently racy and difficult to implement but they landed it anyway. Why? The best explanation I've been given is because it makes the API more "unified" or "symmetric" for this stuff to go through SET_CONTEXT_PARAM. It's not because any userspace actually wants to be able to swap out the VM or the set of engines on a running context. That would be utterly insane. This patch series cleans up this particular mess by introducing the concept of a i915_gem_proto_context data structure which contains context creation information. When you initially call GEM_CONTEXT_CREATE, a proto-context in created instead of an actual context. Then, the first time something is done on the context besides SET_CONTEXT_PARAM, an actual context is created. This allows us to keep the old drivers which use SET_CONTEXT_PARAM to set up the engine set (see also media) while ensuring that, once you have an i915_gem_context, the VM and the engine set are immutable state. Eventually, there are more clean-ups I'd like to do on top of this which should make working with contexts inside i915 simpler and safer: 1. Move the GEM handle -> vma LUT from i915_gem_context into either i915_ppgtt or drm_i915_file_private depending on whether or not the hardware has a full PPGTT. 2. Move the delayed context destruction code into intel_context or a per-engine wrapper struct rather than i915_gem_context. 3. Get rid of the separation between context close and context destroy 4. Get rid of the RCU on i915_gem_context However, these should probably be done as a separate patch series as this one is already starting to get longish, especially if you consider the 89 IGT patches that go along with it. Test-with: 20210707210215.351483-1-jason(a)jlekstrand.net Jason Ekstrand (30): drm/i915: Drop I915_CONTEXT_PARAM_RINGSIZE drm/i915: Stop storing the ring size in the ring pointer (v3) drm/i915: Drop I915_CONTEXT_PARAM_NO_ZEROMAP drm/i915/gem: Set the watchdog timeout directly in intel_context_set_gem (v2) drm/i915/gem: Return void from context_apply_all drm/i915: Drop the CONTEXT_CLONE API (v2) drm/i915: Implement SINGLE_TIMELINE with a syncobj (v4) drm/i915: Drop getparam support for I915_CONTEXT_PARAM_ENGINES drm/i915/gem: Disallow bonding of virtual engines (v3) drm/i915/gem: Remove engine auto-magic with FENCE_SUBMIT (v2) drm/i915/request: Remove the hook from await_execution drm/i915/gem: Disallow creating contexts with too many engines drm/i915: Stop manually RCU banging in reset_stats_ioctl (v2) drm/i915/gem: Add a separate validate_priority helper drm/i915: Add gem/i915_gem_context.h to the docs drm/i915/gem: Add an intermediate proto_context struct (v5) drm/i915/gem: Rework error handling in default_engines drm/i915/gem: Optionally set SSEU in intel_context_set_gem drm/i915: Add an i915_gem_vm_lookup helper drm/i915/gem: Make an alignment check more sensible drm/i915/gem: Use the proto-context to handle create parameters (v5) drm/i915/gem: Return an error ptr from context_lookup drm/i915/gt: Drop i915_address_space::file (v2) drm/i915/gem: Delay context creation (v3) drm/i915/gem: Don't allow changing the VM on running contexts (v4) drm/i915/gem: Don't allow changing the engine set on running contexts (v3) drm/i915/selftests: Take a VM in kernel_context() i915/gem/selftests: Assign the VM at context creation in igt_shared_ctx_exec drm/i915/gem: Roll all of context creation together drm/i915: Finalize contexts in GEM_CONTEXT_CREATE on version 13+ Documentation/gpu/i915.rst | 2 + drivers/gpu/drm/i915/Makefile | 1 - drivers/gpu/drm/i915/gem/i915_gem_context.c | 2926 ++++++++--------- drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 196 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 31 +- .../drm/i915/gem/selftests/i915_gem_context.c | 127 +- .../gpu/drm/i915/gem/selftests/mock_context.c | 67 +- .../gpu/drm/i915/gem/selftests/mock_context.h | 4 +- drivers/gpu/drm/i915/gt/intel_context.c | 3 +- drivers/gpu/drm/i915/gt/intel_context.h | 5 - drivers/gpu/drm/i915/gt/intel_context_param.c | 63 - drivers/gpu/drm/i915/gt/intel_context_param.h | 6 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 - .../drm/i915/gt/intel_execlists_submission.c | 114 - .../drm/i915/gt/intel_execlists_submission.h | 8 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 11 - drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 3 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 251 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 82 +- drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_request.c | 42 +- drivers/gpu/drm/i915/i915_request.h | 4 +- .../drm/i915/selftests/i915_mock_selftests.h | 1 - drivers/gpu/drm/i915/selftests/mock_gtt.c | 1 - include/uapi/drm/i915_drm.h | 40 +- 33 files changed, 1681 insertions(+), 2340 deletions(-) delete mode 100644 drivers/gpu/drm/i915/gt/intel_context_param.c -- 2.31.1

3 32

[PATCH] drm/rockchip: Implement mmap as GEM object function
by Thomas Zimmermann 21 Oct '21

21 Oct '21

Moving the driver-specific mmap code into a GEM object function allows for using DRM helpers for various mmap callbacks. The respective rockchip functions are being removed. The file_operations structure fops is now being created by the helper macro DEFINE_DRM_GEM_FOPS(). Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 +----- drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +- drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 44 +++++-------------- drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 7 --- 4 files changed, 15 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index b730b8d5d949..2e3ab573a817 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -208,16 +208,7 @@ static void rockchip_drm_unbind(struct device *dev) drm_dev_put(drm_dev); } -static const struct file_operations rockchip_drm_driver_fops = { - .owner = THIS_MODULE, - .open = drm_open, - .mmap = rockchip_gem_mmap, - .poll = drm_poll, - .read = drm_read, - .unlocked_ioctl = drm_ioctl, - .compat_ioctl = drm_compat_ioctl, - .release = drm_release, -}; +DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops); static const struct drm_driver rockchip_drm_driver = { .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, @@ -226,7 +217,7 @@ static const struct drm_driver rockchip_drm_driver = { .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, - .gem_prime_mmap = rockchip_gem_mmap_buf, + .gem_prime_mmap = drm_gem_prime_mmap, .fops = &rockchip_drm_driver_fops, .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c index 2fdc455c4ad7..d8418dd39d0e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c @@ -7,6 +7,7 @@ #include <drm/drm.h> #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> +#include <drm/drm_prime.h> #include <drm/drm_probe_helper.h> #include "rockchip_drm_drv.h" @@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info, struct drm_fb_helper *helper = info->par; struct rockchip_drm_private *private = to_drm_private(helper); - return rockchip_gem_mmap_buf(private->fbdev_bo, vma); + return drm_gem_prime_mmap(private->fbdev_bo, vma); } static const struct fb_ops rockchip_drm_fbdev_ops = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index 7971f57436dd..63eb73b624aa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, int ret; struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); + /* + * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the + * whole buffer from the start. + */ + vma->vm_pgoff = 0; + /* * We allocated a struct page table for rk_obj, so clear * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). */ + vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; vma->vm_flags &= ~VM_PFNMAP; + vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + if (rk_obj->pages) ret = rockchip_drm_gem_object_mmap_iommu(obj, vma); else @@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, return ret; } -int rockchip_gem_mmap_buf(struct drm_gem_object *obj, - struct vm_area_struct *vma) -{ - int ret; - - ret = drm_gem_mmap_obj(obj, obj->size, vma); - if (ret) - return ret; - - return rockchip_drm_gem_object_mmap(obj, vma); -} - -/* drm driver mmap file operations */ -int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma) -{ - struct drm_gem_object *obj; - int ret; - - ret = drm_gem_mmap(filp, vma); - if (ret) - return ret; - - /* - * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the - * whole buffer from the start. - */ - vma->vm_pgoff = 0; - - obj = vma->vm_private_data; - - return rockchip_drm_gem_object_mmap(obj, vma); -} - static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) { drm_gem_object_release(&rk_obj->base); @@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = { .get_sg_table = rockchip_gem_prime_get_sg_table, .vmap = rockchip_gem_prime_vmap, .vunmap = rockchip_gem_prime_vunmap, + .mmap = rockchip_drm_gem_object_mmap, .vm_ops = &drm_gem_cma_vm_ops, }; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h index 5a70a56cd406..47c1861eece0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h @@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev, int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map); void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map); -/* drm driver mmap file operations */ -int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma); - -/* mmap a gem object to userspace. */ -int rockchip_gem_mmap_buf(struct drm_gem_object *obj, - struct vm_area_struct *vma); - struct rockchip_gem_object * rockchip_gem_create_object(struct drm_device *drm, unsigned int size, bool alloc_kmap); -- 2.32.0

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dri-devel August 2021