dri-devel May 2022

dri-devel@lists.freedesktop.org

344 participants
736 discussions

[PULL] drm-intel-fixes
by Joonas Lahtinen 12 May '22

12 May '22

Hi Dave & Daniel, One fix for memory corruption under heavy load (#5732, Cc: stable). Regards, Joonas *** drm-intel-fixes-2022-05-12: Fix for #5732: (Cc stable) kernel memory corruption when running a lot of OpenCL tests in parallel The following changes since commit c5eb0a61238dd6faf37f58c9ce61c9980aaffd7a: Linux 5.18-rc6 (2022-05-08 13:54:17 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2022-05-12 for you to fetch changes up to 3220c3b2115102bb35f8f07d90d2989a3f5eb452: drm/i915: Fix race in __i915_vma_remove_closed (2022-05-09 10:36:49 +0300) ---------------------------------------------------------------- Fix for #5732: (Cc stable) kernel memory corruption when running a lot of OpenCL tests in parallel ---------------------------------------------------------------- Karol Herbst (1): drm/i915: Fix race in __i915_vma_remove_closed drivers/gpu/drm/i915/i915_vma.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-)

1 0

drm/mediatek: fixup crtc event null pointer issue
by Yongqiang Niu 12 May '22

12 May '22

base linux v5.17-rc1 Yongqiang Niu (1): drm/mediatek: fixup crtc event null pointer issue drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.25.1

4 5

[PATCH 0/2] Prune unsupported modes as per HDMI2.1 spec
by Ankit Nautiyal 12 May '22

12 May '22

Modes like 4K100, 4K120, 8K50, 8K60 need FRL and/or DSC from source. Since FRL and DSC are not currently supported natively by intel platforms (are supported only via DP-HDMI2.1 PCONs), these modes must be pruned as per spec. Currently these modes are not getting pruned as we check the TMDS clock, which passes some of these with YCbCr420 format and with lower bpc. This causes failures during compliance test (e.g. HFR1-67). This patch prunes the modes, if FRL, DSC not supported, or the support requirement not met as per the spec. Although the spec mentions 4K100, 4K120, 8K50, and 8K60 video timings, I have used the check for clock >= 2376 MHz (or 1188 MHz with 420 format), instead of using individual VICs. While at it, fix a bug while parsing the compressed bpc supported from edid. Ankit Nautiyal (2): drm/edid: Fix minimum bpc supported with DSC1.2 for HDMI sink drm/i915/hdmi: Prune unsupported modes as per HDMI2.1 spec drivers/gpu/drm/drm_edid.c | 3 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 48 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) -- 2.25.1

3 4

[pull] amdgpu, amdkfd drm-next-5.19
by Alex Deucher 12 May '22

12 May '22

Hi Dave, Daniel, New stuff for 5.19. Mostly new IP block support. The following changes since commit 3da2c38231a4c62dafdbd762a199cfacaccd0533: drm/amdgpu: Free user pages if amdgpu_cs_parser_bos failed (2022-04-28 17:49:04 -0400) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.19-2022-05-11 for you to fetch changes up to 81c5495910e81c2cadcb9118ca0c8803ab3bde61: drm/amdgpu: Remove duplicated argument in vcn_v4_0 (2022-05-10 17:53:13 -0400) ---------------------------------------------------------------- amd-drm-next-5.19-2022-05-11: amdgpu: - OPTC updates - NBIO 4.3 support - IH 6.0 support - GPUVM TLB flush fix - HDP 6.0 support - LTTPR fixes - HDP 5.2 support - NBIO 7.7 support - SMUIO 13.x updates - DP2 fixes - GMC 11.0 support - PSP 13.x updates - SMU 13.x updates - VCN RAS support - GC 11.0 support - SDMA 6.0 support - VCN 4.0 support - Misc code cleanups - DCN CONFIG cleanup - RAS fixes amdkfd: - GC 11.0 support ---------------------------------------------------------------- Alan Liu (1): drm/amd/display: do not disable an invalid irq source in hdp finish Alex Deucher (15): drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init drm/amdgpu/psp: drop load/unload/init_shared_buf wrappers drm/amdgpu/psp: fix memory leak in terminate functions drm/amdgpu/psp: move shared buffer frees into single function drm/amdgpu/discovery: handle AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO in SMU drm/amdkfd: add helper to generate cache info from gfx config drm/amdgpu/discovery: add MES11 support drm/amdgpu/gfx11: remove some register fields that no longer exist Revert "drm/amdgpu: disable runpm if we are the primary adapter" Revert "fbdev: fbmem: add a helper to determine if an aperture is used by a fw fb" drm/amdgpu/discovery: set flag for GC 11.0.1 drm/amdgpu: simplify nv and soc21 read_register functions drm/amdgpu: make smu_v13_0_7_check_fw_status() static drm/amdgpu/mes: fix format specifier for size_t Revert "drm/amd/pm: keep the BACO feature enabled for suspend" Alex Hung (7): drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dce drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in gpio drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in irq drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN for z10 drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dm drm/amd/display: remove unnecessary else by CONFIG_DRM_AMD_DC_DCN Alice Wong (3): drm/amdgpu/psp: deallocate memory when psp_load_fw failed drm/amdgpu/ucode: Remove firmware load type check in amdgpu_ucode_free_bo drm/amdgpu/psp: Return failure when firmware failed to load in SRIOV Andrey Grodzovsky (2): drm/amd/psp: Add C2P registers to mp_13_0_2 header drm/amdgpu/psp: Add VBIOS flash handler Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.115.0 Aric Cyr (3): drm/amd/display: Clean up pixel format types drm/amd/display: 3.2.184 drm/amd/display: 3.2.185 Chengming Gui (8): drm/amd/amdgpu: adjust the fw load type list drm/amd/amdgpu: add more fw load type to fit new ASICs drm/amdgpu/discovery: add SMUIO_13_0_8 func support drm/amdgpu/psp13: add support for MP0 13.0.7 drm/amdgpu/discovery: add psp13 support for PSP 13.0.7 drm/amd/pm: add SMU_13_0_7 PMFW headers drm/amdgpu/swsmu: add smu 13.0.7 firmware drm/amd/pm: add SMU_13_0_7 ppt_funcs for SMU_13_0_7 Christian König (1): drm/amdgpu: nuke dynamic gfx scratch reg allocation Dan Carpenter (1): drm/amdgpu/gfx11: unlock on error in gfx_v11_0_kiq_resume() Danijel Slivka (1): amdgpu/pm: Disallow managing power profiles on SRIOV for Sienna Cichlid Elena Sakhnovitch (2): drm/amdgpu: Remove trailing space drm/amd/pm: Disable fan control if not supported Eric Bernstein (1): drm/amd/display: Add new DSC interface to disconnect from pipe Eric Huang (2): drm/amdkfd: add asic support for SDMA 6.0.2 drm/amdkfd: add asic support for GC 11.0.2 Evan Quan (38): drm/amd/pm: enable pp_dpm_vclk/dclk sysfs interface support for SMU 13.0.0 drm/amd/pm: move bootup values retrieving to ->sw_init drm/amd/pm: correct the way for retrieving bootup clocks drm/amd/pm: update the hw initialization sequence around pptable setup drm/amdgpu: enable pptable ucode loading drm/amd/pm: enable SCPM support for SMU drm/amd/pm: correct SMU OverridePcieParameters related settings drm/amd/pm: enable the support for retrieving combo pptable drm/amd/smu: Update SMU13 support for SMU 13.0.0 drm/amdgpu/soc21: enable ATHUB and MMHUB PG drm/amdgpu: add FGCG support drm/amdgpu: enable GFX CGCG/CGLS for GC11.0.0 drm/amdgpu: enable fgcg for soc21 drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 drm/amd/pm: enable ac/dc switching for SMU 13.0.0 drm/amd/pm: enable power profile setting for SMU 13.0.0 drm/amd/pm: enable RunDcBtc support for SMU 13.0.0 drm/amd/pm: enable ppfeature mask setting for SMU 13.0.0 drm/amd/pm: enable PMLOG support for SMU 13.0.0 drm/amd/pm: enable df cstate feature for SMU 13.0.0 drm/amdgpu: enable more GFX clockgating features for GC 11.0.0 drm/amd/pm: support more DPM features for SMU 13.0.0 drm/amd/pm: enable deep sleep features control for SMU 13.0.0 drm/amd/pm: enable gfx ulv feature control for SMU 13.0.0 drm/amd/pm: enable more dpm features to pair with PMFW 78.31.0 drm/amdgpu: enable MGCG and LS for ATHUB 3.0 drm/amdgpu: enable MGCG and LS for MMHUB 3.0 drm/amdgpu: enable clock gating for IH 6.0 drm/amdgpu: enable clock gating for HDP 6.0 drm/amd/pm: enable lclk dpm/ds and BACO features for SMU 13.0.0 drm/amd/pm: enable BACO support for SMU 13.0.0 drm/amd/pm: enable UCLK DPM for SMU 13.0.0 drm/amd/pm: correct the check for current link status drm/amd/pm: correct the way for retrieving current uclk frequency drm/amd/pm: correct the way for retrieving current fclk frequency drm/amd/pm: enable FCLK DPM support for SMU 13.0.0 drm/amd/pm: disable the gfxoff feature temporarily for SMU 13.0.0 drm/amd/pm: suppress compile warning about possible unaligned accesses Evgenii Krasnikov (2): Revert "drm/amd/display: Reset cached PSR parameters after hibernate" drm/amd/display: Reset cached PSR parameters after hibernate Flora Cui (18): drm/amdgpu: add soc21 support for GC 11.0.2 drm/amdgpu/discovery: add soc21 support for GC 11.0.2 drm/amdgpu: add support for ATHUB 3.0.2 drm/amdgpu/discovery: add ih6 support for IH 6.0.2 drm/amdgpu/discovery: add smu13 support for MP1 13.0.7 drm/amdgpu/discovery: add nbio 4.3 support for NBIO 4.3.1 drm/amdgpu/discovery: add hdp6 support for HDP 6.0.1 drm/amdgpu: add UMC 8.11.0 support drm/amdgpu: add GMC11 support for GC 11.0.2 drm/amdgpu/discovery: add gmc11 support for GC 11.0.2 drm/amdgpu: add sdma 6.0.2 firware support drm/amdgpu/discovery: add sdma6 support for SDMA 6.0.2 drm/amdgpu: add mes 11 firmware for mes 11.0.2 drm/amdgpu/discovery: add mes11 support for GC 11.0.2 drm/amdgpu: add gc v11_0_2 imu firmware drm/amdgpu: add initial GC 11.0.2 support drm/amdgpu/discovery: add gfx11 support for GC 11.0.2 drm/amdgpu/discovery: set family for GC 11.0.2 Graham Sider (3): drm/amdgpu: Disable SDMA WPTR_POLL_ENABLE for sdma_v6_0 drm/amdkfd: Update event_interrupt_isr_v11 return drm/amdgpu: Implement get_vmid_pasid_mapping for gfx11 Harry Wentland (1): drm/amd/display: Avoid reading audio pattern past AUDIO_CHANNELS_COUNT Hawking Zhang (22): drm/amdgpu: add nbio v4_3_0 ip headers v6 drm/amdgpu: add osssys v6_0_0 ip headers v4 drm/amdgpu: add hdp v6_0_0 ip headers v4 drm/amdgpu: add smuio v13_0_6 ip headers v4 drm/amdgpu: add smuio v13_0_6 support drm/amdgpu: init smuio v13_0_6 callbacks drm/amdgpu: support print psp v2_0 hdr debug information drm/amdgpu: add athub v3_0_0 ip headers v6 drm/amdgpu: add mmhub v3_0_0 ip headers v6 drm/amdgpu: add updated smu_info structures drm/amdgpu: query core refclk from bios for smu v13 drm/amdgpu: add GC v11_0_0 family id drm/amdgpu: add soc21 chip enum header v8 drm/amdgpu: add gfx11 clearstate header drm/amdgpu: add gfx11 mqd structures drm/amdgpu: add init support for GFX11 (v2) drm/amdgpu: enable GENERIC0_INT for gfx/compute pipes drm/amdgpu: add sdma v6_0_0 pkt header v3 drm/amdgpu: add mmhub v3_0_2 ip headers drm/amdgpu: add mmhub v3_0_2 ip callback functions drm/amdgpu: split mmhub v3_0_2 callbacks from mmhub v3_0 drm/amdgpu: add lsdma v6_0_0 ip headers Huang Rui (18): drm/amdgpu: add nbio v7_7_0 ip headers drm/amdgpu: add hdp v5_2_1 ip headers drm/amdgpu: add mmhub support for MMHUB 3.0.1 drm/amdgpu: add soc21 common ip block support for GC 11.0.1 drm/amdgpu/discovery: enable soc21 common for GC 11.0.1 drm/amdgpu: add gmc v11 support for GC 11.0.1 drm/amdgpu/discovery: enable gmc v11 for GC 11.0.1 drm/amdgpu/discovery: enable ih v6 for OSS 6.0.1 drm/amdgpu: add sdma support for sdma 6.0.1 drm/amdgpu/discovery: enable sdma v6 for SDMA 6.0.1 drm/amdgpu: add GC 11.0.1 family id drm/amdgpu: set GC 11.0.1 family drm/amdgpu: add gfx support for GC 11.0.1 drm/amdgpu: add GC v11.0.1 into mes v11 drm/amdkfd: add GC 11.0.1 KFD support drm/amdgpu: enable imu firmware for GC 11.0.1 drm/amdgpu/discovery: enable gfx v11 for GC 11.0.1 drm/amdgpu/discovery: enable mes support for GC v11.0.1 Jack Xiao (77): drm/amdgpu: save the setting of VM_CONTEXT_CNTL drm/amdgpu: define MQD abstract layer for hw ip drm/amdgpu: add helper function to initialize mqd from ring v4 drm/amdgpu: add the per-context meta data v3 drm/amdgpu: add mes ctx data in amdgpu_ring drm/amdgpu: define ring structure to access rptr/wptr/fence drm/amdgpu: use ring structure to access rptr/wptr v2 drm/amdgpu: initialize/finalize the ring for mes queue drm/amdgpu: assign the cpu/gpu address of fence from ring drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2 drm/amdgpu/gfx10: use per ctx CSA for ce metadata drm/amdgpu/gfx10: use per ctx CSA for de metadata drm/amdgpu/gfx10: associate mes queue id with fence v2 drm/amdgpu/gfx10: inherit vmid from mqd drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2 drm/amdgpu/gmc10: skip emitting pasid mapping packet drm/amdgpu: use the whole doorbell space for mes drm/amdgpu: update mes process/gang/queue definitions drm/amdgpu: add mes_kiq module parameter v2 drm/amdgpu: allocate doorbell index for mes kiq drm/amdgpu/mes: extend mes framework to support multiple mes pipes drm/amdgpu/gfx10: add mes queue fence handling drm/amdgpu/gfx10: add mes support for gfx ib test drm/amdgpu: don't use kiq to flush gpu tlb if mes enabled drm/amdgpu/sdma: use per-ctx sdma csa address for mes sdma queue drm/amdgpu/sdma5.2: initialize sdma mqd drm/amdgpu/sdma5.2: associate mes queue id with fence drm/amdgpu/sdma5.2: add mes queue fence handling drm/amdgpu/sdma5.2: add mes support for sdma ring test drm/amdgpu/sdma5.2: add mes support for sdma ib test drm/amdgpu/sdma5: initialize sdma mqd drm/amdgpu/sdma5: associate mes queue id with fence drm/amdgpu/sdma5: add mes queue fence handling drm/amdgpu/sdma5: add mes support for sdma ring test drm/amdgpu/sdma5: add mes support for sdma ib test drm/amdgpu/mes: add mes kiq callback drm/amdgpu: add mes kiq frontdoor loading support drm/amdgpu: enable mes kiq N-1 test on sienna cichlid drm/amdgpu/mes: manage mes doorbell allocation drm/amdgpu: add mes queue id mask v2 drm/amdgpu/mes: initialize/finalize common mes structure v2 drm/amdgpu/mes: relocate status_fence slot allocation drm/amdgpu/mes10.1: call general mes initialization drm/amdgpu/mes10.1: add delay after mes engine enable drm/amdgpu/mes10.1: implement the suspend/resume routine drm/amdgpu/mes: implement creating mes process v2 drm/amdgpu/mes: implement destroying mes process drm/amdgpu/mes: implement adding mes gang drm/amdgpu/mes: implement removing mes gang drm/amdgpu/mes: implement suspending all gangs drm/amdgpu/mes: implement resuming all gangs drm/amdgpu/mes: initialize mqd from queue properties drm/amdgpu/mes: implement adding mes queue drm/amdgpu/mes: implement removing mes queue drm/amdgpu/mes: add helper function to convert ring to queue property drm/amdgpu/mes: add helper function to get the ctx meta data offset drm/amdgpu/mes: use ring for kernel queue submission drm/amdgpu/mes: implement removing mes ring drm/amdgpu/mes: add helper functions to alloc/free ctx metadata drm/amdgpu: skip kfd routines when mes enabled drm/amdgpu: skip some checking for mes queue ib submission drm/amdgpu: skip kiq ib tests if mes enabled drm/amdgpu: skip gds switch for mes queue drm/amdgpu: kiq takes charge of all queues drm/amdgpu/mes: map ctx metadata for mes self test drm/amdgpu/mes: create gang and queues for mes self test drm/amdgpu/mes: add ring/ib test for mes self test drm/amdgpu/mes: implement mes self test drm/amdgpu/mes10.1: add mes self test in late init drm/amdgpu/mes: fix vm csa update issue drm/amdgpu/mes: disable mes sdma queue test drm/amdgpu: add new CP_MES ucode ids drm/amdgpu: correct cp doorbell range drm/amdgpu: add mes unmap legacy queue routine drm/amdgpu/mes11: initiate mes v11 support drm/amdgpu/gfx10: enable kiq to map mes ring drm/amdgpu/gfx11: enable kiq to map mes ring James Zhu (18): drm/amdgpu: move out asic specific definition from common header drm/amdgpu: add irq sources for vcn v4_0 drm/amdgpu/jpeg: add jpeg support for VCN4_0_0 drm/amdgpu/jpeg: enable JPEG PG and CG for VCN4_0_0 drm/amdgpu/vcn: enable vcn4 dpg mode drm/amdgpu: add vcn_4_0_0 video codec query drm/amdgpu/discovery: add VCN 4.0 Support drm/amdgpu: add VCN4_0_4 firmware drm/amdgpu/jpeg: enable JPEG CG for VCN4_0_4 drm/amdgpu/jpeg: enable JPEG PG for VCN4_0_4 drm/amdgpu/vcn: enable VCN CG for VCN4_0_4 drm/amdgpu/vcn: enable VCN PG for VCN4_0_4 drm/amdgpu/vcn: enable VCN DPG mode for VCN4_0_4 drm/amdgpu/discovery: enable vcn/jpeg v4_0_4 drm/amdgpu/vcn: add common vcn sofware ring decode drm/amdgpu/vcn3: replace ip based software ring decode with common vcn software ring decode drm/amdgpu/vcn4: replace ip based software ring decode with common vcn software ring decode drm/amdgpu/vcn: include header for vcn_dec_sw_ring_emit_fence Jimmy Kizito (1): drm/amd/display: Add Connection Manager boot option. Josip Pavic (2): drm/amd/display: move definition of dc_flip_addrs struct drm/amd/display: do not wait for vblank during pipe programming Kenneth Feng (23): drm/amd/pm: support power on/off vcn/jpeg in smu v13_0_7 drm/amd/pm: add features to smu_v13_0_7 drm/amd/pm: add mvdd and vddio scaling in smu_v13_0_7 drm/amd/pm: enable link dpm and link ds on smu_v13_0_7 drm/amd/pm: enable mp0,vcn,dcn dpm on smu_v13_0_7 drm/amd/pm: enable fclk,vcn ds and df cstate for smu_v13_0_7 drm/amd/pm: enable platform features for smu_v13_0_7 drm/amd/pm: add SCPM support in smu v13_0_7 drm/amd/pm: update the features for smu_v13_0_7 drm/amd/pm: pp_dpm_* interface for smu_v13_0_7 drm/amd/pm:add UMD Pstate clock settings for smu_v13_0_7 drm/amd/pm: enable pp_dpm_vclk/dclk interface for smu_v13_0_7 drm/amd/pm: port the fan interface to smu_v13_0_7 drm/amd/pm: add the pg_flag for athub and mmhub pg on smu_v13_0_7 drm/amd/soc21: enable mmhub and athub power gating drm/amd/pm: enable gfx ds for smu_v13_0_7 drm/amd/pm: enable gfx pcc and soc cg on smu_v13_0_7 drm/amd/pm: pp_dpm_sclk change for smu_v13_0_7 drm/amd/pm: enable workload type change on smu_v13_0_7 drm/amd/pm: change the soft pptable id for smu_v13_0_7 drm/amd/pm: report preDS gfxclk on smu_v13_0_7 drm/amd/pm: disable ac/dc on smu_v13_0_7 drm/amd/pm: enable gfxoff control on smu_v13_0_7 Lee, Alvin (1): drm/amd/display: Make OPTC3 function accessible to other DCN Leo Liu (4): drm/amdgpu: add vcn 4_0_0 header files v7 drm/amdgpu: make software ring functions reuseable for newer VCN drm/amdgpu: add VCN4 ip block support drm/amdgpu: enable VCN4 PG and CG for VCN4_0_0 Likun Gao (47): drm/amdgpu/discovery: add soc21 common Support drm/amdgpu/discovery: add NBIO 4.3 Support drm/amd/smu: Increace dpm level count only for smu v13.0.2 drm/amdgpu/discovery: add IH v6 drm/amdgpu: add hdp version 6 functions drm/amdgpu/discovery: add HDP v6 drm/amdgpu: extend PSP GFX FW type drm/amdgpu: add support for spl fw load on psp v13 drm/amdgpu: support psp v13_0_0 microcode init drm/amdgpu: rework psp firmware name drm/amdgpu: add tracking for the enablement of SCPM drm/amdgpu/discovery: Enable PSP for PSP 13.0.0 drm/amdgpu/discovery: add GMC 11.0 Support drm/amd/pm: fix NULL pointer issue of amdgpu_smu_stb_debug_fs_init drm/amd/smu: add smu v13_0 header files drm/amdgpu/discovery: Enable SMU for SMU 13.0.0 drm/amdgpu/discovery: Set GC family for GC 11.0 IP drm/amdgpu: add gfx firmware header v2_0 drm/amdgpu: support rlc v2_3 ucode struct drm/amdgpu: add rlc TOC header file for soc21 (v2) drm/amdgpu: add imu fw structure drm/amdgpu: add mes kiq PSP GFX FW type drm/amdgpu: support RLCP firmware front door load drm/amdgpu: support RLCV firmware front door load drm/amdgpu: support for new SDMA front door load drm/amdgpu: support IMU front door load drm/amdgpu: add convert for new gfx type drm/amdgpu: init SDMA v6 microcode with PSP load type drm/amdgpu: extend the show ucode name function drm/amdgpu/gfx: refine fw hdr check fuction drm/amdgpu: fix the fw size for sdma drm/amdgpu: renovate sdma fw struct drm/amdgpu: support RS64 CP fw front door load drm/amdgpu: support imu for gfx11 drm/amdgpu/discovery: add GFX 11.0 Support drm/amdgpu: update rlc ram for gc v11_0_2 drm/amdgpu: enable cgcg and cgls for GC 11_0_2 drm/amd/pm: add get enable mask function for smu v13_0_7 drm/amdgpu/psp: Add vbflash sysfs interface support drm/amdgpu: add sysfs to shows psp vbflash status drm/amdgpu: add lsdma block drm/amdgpu: support mem copy for LSDMA drm/amdgpu: support fill mem for LSDMA drm/amdgpu: add LSDMA block for LSDMA v6.0.0 drm/amdgpu: add LSDMA block for LSDMA v6.0.2 drm/amdgpu: support memory power gating for lsdma drm/amdgpu: support memory power gating for lsdma 6.0.2 Michael Strauss (1): drm/amd/display: Refactor LTTPR cap retrieval Mike Lothian (3): drm/amdgpu/gfx11: Add missing break drm/amdgpu/gfx10: Avoid uninitialised variable 'index' drm/amdgpu/gfx11: Avoid uninitialised variable 'index' Minghao Chi (4): drm/amdgpu: simplify the return expression of iceland_ih_hw_init drm/amdgpu: simplify the return expression of navi10_ih_hw_init() drm/amdgpu: simplify the return expression drm/amdgpu: simplify the return expression of vega10_ih_hw_init() Mohammad Zafar Ziya (2): drm/amdgpu/jpeg: add jpeg ras poison consumption handling drm/amdgpu/vcn: Add vcn ras poison consumption event handling Mukul Joshi (3): drm/amdgpu: Enable KFD with MES enabled drm/amdgpu/mes: Update the doorbell function signatures drm/amdkfd: Add KFD support for soc21 v3 Philip Yang (2): drm/amdgpu: Free user pages if kvmalloc_array fails drm/amdgpu: vm flush needed after updating PDEs Richard Gong (1): drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems Sonny Jiang (1): drm/amdgpu: Enable vcn v4_0_4 sram Stanley Yang (3): drm/amdgpu: add soc21 ih clientid definition drm/amdgpu: add initial support for sdma v6.0 drm/amdgpu/discovery: add SDMA v6_0 ip block Stanley.Yang (2): drm/amdgpu: add nbio v4_3_0 ip block v2 drm/amdgpu: add ih v6_0 ip block v2 Stylon Wang (1): Revert "drm/amd/display: Fix DCN3 B0 DP Alt Mapping" Sung Joon Kim (1): drm/amd/display: Fix null pointer exception while load amdgpu Tao Zhou (2): drm/amdgpu: enable RAS IH for poison consumption drm/amdgpu: refine RAS poison consumption handler Tianci.Yin (4): drm/amdgpu: add athub v3_0 ip block drm/amdgpu: add gfxhub v3_0 ip block drm/amdgpu: add mmhub v3_0 ip block drm/amdgpu: add gmc v11_0 ip block (v3) Tse, Kaitlyn (1): drm/amd/display: Remove outdated register for dcn3+ Wan Jiabing (1): drm/amdgpu: Remove duplicated argument in vcn_v4_0 Wenhui Sheng (1): drm/amdgpu: add irq src id for GFX11 Wenjing Liu (1): drm/amd/display: do not calculate DP2.0 SST payload when link is off Xiaojian Du (8): drm/amdgpu: handle asics with 1 SDMA instance drm/amdgpu: skip the new gc doorbell function for some asics drm/amdgpu: add pcie port function helpers for SOC21 drm/amdgpu: add the files of NBIO v7.7 block drm/admgpu/discovery: add NBIO v7.7 into the IP discovery list drm/amdgpu: add the files of HDP v5.2 block drm/amdgpu/discovery: add HDP v5.2.1 into the IP discovery list drm/amdgpu/discovery: add PSP v13.0.4 into the IP discovery list Yang Li (2): drm/amdgpu/gfx11: remove unneeded semicolon drm/amdkfd: Return true/false (not 1/0) from bool functions Yang Wang (1): drm/amd/pm: enable pmlog support for smu_v13_0_7 Yiqing Yao (1): drm/amdgpu: flush delete wq after wait fence pengfuyuan (1): gpu/drm/radeon: Fix spelling typo in comments drivers/gpu/drm/amd/amdgpu/Makefile | 35 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 37 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c | 625 + drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 61 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 115 +- drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 40 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 47 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 36 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h | 51 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 18 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 - drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c | 91 + drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h | 46 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1227 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 252 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h | 121 + drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 631 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 30 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 47 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 193 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 22 + drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 45 + drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 24 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 226 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 72 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 45 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 23 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +- drivers/gpu/drm/amd/amdgpu/athub_v3_0.c | 98 + drivers/gpu/drm/amd/amdgpu/athub_v3_0.h | 30 + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +- drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h | 988 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 448 +- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6437 + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h | 29 + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 62 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 80 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 44 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 51 +- drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 + drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 2 + drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 511 + drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.h | 29 + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 973 + drivers/gpu/drm/amd/amdgpu/gmc_v11_0.h | 30 + drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c | 45 + drivers/gpu/drm/amd/amdgpu/hdp_v5_2.h | 31 + drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c | 142 + drivers/gpu/drm/amd/amdgpu/hdp_v6_0.h | 31 + drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 7 +- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 745 + drivers/gpu/drm/amd/amdgpu/ih_v6_0.h | 28 + drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 367 + drivers/gpu/drm/amd/amdgpu/imu_v11_0.h | 30 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 20 +- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 609 + drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h | 29 + drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c | 121 + drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.h | 31 + drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 630 +- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1182 + drivers/gpu/drm/amd/amdgpu/mes_v11_0.h | 29 + drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 2 + drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 + drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 661 + drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.h | 28 + drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 571 + drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.h | 28 + drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 7 +- drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 368 + drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h | 32 + drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 241 + drivers/gpu/drm/amd/amdgpu/nbio_v7_7.h | 33 + drivers/gpu/drm/amd/amdgpu/nv.c | 13 +- drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 30 + drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 114 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 16 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 28 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 169 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 171 +- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1689 + drivers/gpu/drm/amd/amdgpu/sdma_v6_0.h | 30 + drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h | 5664 + drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 +- drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.c | 41 + drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.h | 30 + drivers/gpu/drm/amd/amdgpu/soc21.c | 111 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c | 86 + drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.h | 44 + drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 15 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 24 +- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 96 +- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1874 + drivers/gpu/drm/amd/amdgpu/vcn_v4_0.h | 29 + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 7 +- drivers/gpu/drm/amd/amdgpu/vi.c | 17 +- drivers/gpu/drm/amd/amdkfd/Makefile | 3 + drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 82 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 38 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 299 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 5 + .../drm/amd/amdkfd/kfd_device_queue_manager_v11.c | 81 + drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 56 +- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c | 384 + drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 8 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 10 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 508 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 13 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 19 + .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 21 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 +- drivers/gpu/drm/amd/amdkfd/soc15_int.h | 3 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 - .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 - .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 - .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 6 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 - .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 - .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 4 - drivers/gpu/drm/amd/display/dc/Makefile | 2 - .../amd/display/dc/bios/command_table_helper2.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 41 +- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 181 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c | 2 - drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 31 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 12 - drivers/gpu/drm/amd/display/dc/dc.h | 51 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 19 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 2 + .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 15 +- .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 12 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 10 - .../drm/amd/display/dc/dce/dce_stream_encoder.c | 21 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 - drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 11 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 - drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 5 - drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 2 +- .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 6 - drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 - drivers/gpu/drm/amd/display/dc/gpio/Makefile | 3 +- .../amd/display/dc/gpio/dcn30/hw_factory_dcn30.c | 2 - .../amd/display/dc/gpio/dcn30/hw_factory_dcn30.h | 2 - .../amd/display/dc/gpio/dcn30/hw_translate_dcn30.c | 2 - .../amd/display/dc/gpio/dcn30/hw_translate_dcn30.h | 2 - drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 - drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 4 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 17 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h | 1 + drivers/gpu/drm/amd/display/dc/irq/Makefile | 3 +- .../amd/display/dc/irq/dcn30/irq_service_dcn30.c | 3 - .../amd/display/dc/irq/dcn30/irq_service_dcn30.h | 3 - drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 - drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 36 +- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 + .../drm/amd/display/include/link_service_types.h | 6 + drivers/gpu/drm/amd/include/amd_shared.h | 3 + .../include/asic_reg/athub/athub_3_0_0_offset.h | 259 + .../include/asic_reg/athub/athub_3_0_0_sh_mask.h | 1246 + .../amd/include/asic_reg/hdp/hdp_5_2_1_offset.h | 217 + .../amd/include/asic_reg/hdp/hdp_5_2_1_sh_mask.h | 684 + .../amd/include/asic_reg/hdp/hdp_6_0_0_offset.h | 209 + .../amd/include/asic_reg/hdp/hdp_6_0_0_sh_mask.h | 646 + .../include/asic_reg/lsdma/lsdma_6_0_0_offset.h | 391 + .../include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h | 1439 + .../include/asic_reg/mmhub/mmhub_3_0_0_offset.h | 1529 + .../include/asic_reg/mmhub/mmhub_3_0_0_sh_mask.h | 7478 + .../include/asic_reg/mmhub/mmhub_3_0_2_offset.h | 1425 + .../include/asic_reg/mmhub/mmhub_3_0_2_sh_mask.h | 7228 + .../drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h | 48 + .../amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h | 72 + .../amd/include/asic_reg/nbio/nbio_4_3_0_offset.h | 17379 ++ .../amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h | 82049 ++++++++++ .../amd/include/asic_reg/nbio/nbio_7_7_0_offset.h | 29654 ++++ .../amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h | 154403 ++++++++++++++++++ .../amd/include/asic_reg/oss/osssys_6_0_0_offset.h | 263 + .../include/asic_reg/oss/osssys_6_0_0_sh_mask.h | 969 + .../include/asic_reg/smuio/smuio_13_0_6_offset.h | 517 + .../include/asic_reg/smuio/smuio_13_0_6_sh_mask.h | 1178 + .../amd/include/asic_reg/vcn/vcn_4_0_0_offset.h | 1610 + .../amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h | 8055 + drivers/gpu/drm/amd/include/atomfirmware.h | 124 + .../amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h | 77 + .../drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h | 4 + .../drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h | 41 + drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 1 + drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 + .../gpu/drm/amd/{amdgpu => include}/mes_api_def.h | 167 +- drivers/gpu/drm/amd/include/mes_v11_api_def.h | 579 + drivers/gpu/drm/amd/include/soc15_hw_ip.h | 1 + drivers/gpu/drm/amd/include/soc15_ih_clientid.h | 27 + drivers/gpu/drm/amd/include/soc21_enum.h | 22477 +++ drivers/gpu/drm/amd/include/v11_structs.h | 1189 + drivers/gpu/drm/amd/pm/amdgpu_pm.c | 24 +- drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 203 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 128 +- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 18 +- .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 1544 + .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 1562 + .../amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h | 141 + .../amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h | 134 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 2 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 49 +- .../gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 200 + .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 17 +- drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h | 8 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 590 +- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1617 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.h | 28 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1514 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.h | 28 + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 24 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 + drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 + drivers/gpu/drm/radeon/atombios.h | 6 +- drivers/video/fbdev/core/fbmem.c | 47 - include/linux/fb.h | 1 - include/uapi/drm/amdgpu_drm.h | 2 + 240 files changed, 382132 insertions(+), 1990 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v3_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v3_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c create mode 100644 drivers/gpu/drm/amd/amdgpu/hdp_v5_2.h create mode 100644 drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/hdp_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/ih_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/imu_v11_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/imu_v11_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v11_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.h create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_7.h create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.c create mode 100644 drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_2_1_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_2_1_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_6_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_6_0_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_6_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_6_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h rename drivers/gpu/drm/amd/{amdgpu => include}/mes_api_def.h (68%) create mode 100644 drivers/gpu/drm/amd/include/mes_v11_api_def.h create mode 100644 drivers/gpu/drm/amd/include/soc21_enum.h create mode 100644 drivers/gpu/drm/amd/include/v11_structs.h create mode 100644 drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.h create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.h

1 0

[PATCH] drm/msm/dpu: remove NULL-ness check in dpu_hw_intr_destroy
by Dmitry Baryshkov 12 May '22

12 May '22

There is no need to check that kfree() argument is not NULL. Remove extra check and call kfree() unconditionally. Reported-by: kernel test robot <lkp(a)intel.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index fa4f99034a08..915250b7f122 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -433,8 +433,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) { - if (intr) - kfree(intr); + kfree(intr); } int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx, -- 2.35.1

3 2

[PATCH] drm/msm/dpu: add DRM_MODE_ROTATE_180 back to supported rotations
by Abhinav Kumar 12 May '22

12 May '22

DRM_MODE_ROTATE_180 was previously marked as supported even for devices not supporting inline rotation. This is true because the SSPPs can always flip the image. After inline rotation support changes, this bit was removed and kms_rotation_crc IGT test starts skipping now whereas it was previously passing. Restore DRM_MODE_ROTATE_180 bit to the supported rotations list. Fixes: dabfdd89eaa92 ("add inline rotation support for sc7280") Signed-off-by: Abhinav Kumar <quic_abhinavk(a)quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 9d2f0364d2c7..5b5aef249390 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1577,7 +1577,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE)); - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) supported_rotations |= DRM_MODE_ROTATE_MASK; -- 2.35.1

4 3

[PATCH 0/2] drm/msm/dsi: switch msm/dsi to DRM_PANEL_BRIDGE
by Dmitry Baryshkov 11 May '22

11 May '22

Currently the DSI driver has two separate paths: one if the next device in a chain is a bridge and another one if the panel is connected directly to the DSI host. The later functionality is already suppurted by the panel-bridge driver, which wraps drm panel into the drm bridge instance. Using it will remove the need for special handling of drm_panel and drm_connector inside the DSI driver. With these patches in all cases the DSI driver will see the chain bridges which either support bridge-connector or allocate the connector on their own. ---------------------------------------------------------------- Dmitry Baryshkov (2): drm/msm/dsi: move DSI host powerup to modeset time drm/msm/dsi: switch to DRM_PANEL_BRIDGE drivers/gpu/drm/msm/dsi/dsi.c | 32 +--- drivers/gpu/drm/msm/dsi/dsi.h | 10 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 20 +-- drivers/gpu/drm/msm/dsi/dsi_manager.c | 296 ++++++---------------------------- 4 files changed, 61 insertions(+), 297 deletions(-)

4 14

[PATCH v2] Revert "drm/msm/dsi: move DSI host powerup to modeset time"
by Douglas Anderson 11 May '22

11 May '22

This reverts commit 7d8e9a90509f1bd1d193a0c93cb8d1dbad9049fb. The patch causes sc7180 Chromebooks that use the parade-ps8640 bridge chip to fail to turn the display back on after it turns off. Let's revert to get these devices back to a working state. It seems like the DSI powerup problem is somewhat common and probably we should land something more general like Dave Stevenson's series [1] that would give more flexibility. [1] https://lore.kernel.org/r/cover.1646406653.git.dave.stevenson@raspberrypi.c… Fixes: 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset time") Signed-off-by: Douglas Anderson <dianders(a)chromium.org> --- Changes in v2: - Remove the mud from my face. drivers/gpu/drm/msm/dsi/dsi_manager.c | 43 ++++++++------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 50b987658b1f..8d51711a3417 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -315,12 +315,13 @@ dsi_mgr_connector_best_encoder(struct drm_connector *connector) return msm_dsi_get_encoder(msm_dsi); } -static void dsi_mgr_bridge_power_on(struct drm_bridge *bridge) +static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge); struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); struct mipi_dsi_host *host = msm_dsi->host; + struct drm_panel *panel = msm_dsi->panel; struct msm_dsi_phy_shared_timings phy_shared_timings[DSI_MAX]; bool is_bonded_dsi = IS_BONDED_DSI(); int ret; @@ -361,34 +362,6 @@ static void dsi_mgr_bridge_power_on(struct drm_bridge *bridge) if (is_bonded_dsi && msm_dsi1) msm_dsi_host_enable_irq(msm_dsi1->host); - return; - -host1_on_fail: - msm_dsi_host_power_off(host); -host_on_fail: - dsi_mgr_phy_disable(id); -phy_en_fail: - return; -} - -static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) -{ - int id = dsi_mgr_bridge_get_id(bridge); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); - struct mipi_dsi_host *host = msm_dsi->host; - struct drm_panel *panel = msm_dsi->panel; - bool is_bonded_dsi = IS_BONDED_DSI(); - int ret; - - DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - - /* Do nothing with the host if it is slave-DSI in case of bonded DSI */ - if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id)) - return; - /* Always call panel functions once, because even for dual panels, * there is only one drm_panel instance. */ @@ -423,7 +396,17 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) if (panel) drm_panel_unprepare(panel); panel_prep_fail: + msm_dsi_host_disable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_disable_irq(msm_dsi1->host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_power_off(msm_dsi1->host); +host1_on_fail: + msm_dsi_host_power_off(host); +host_on_fail: + dsi_mgr_phy_disable(id); +phy_en_fail: return; } @@ -569,8 +552,6 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge, msm_dsi_host_set_display_mode(host, adjusted_mode); if (is_bonded_dsi && other_dsi) msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode); - - dsi_mgr_bridge_power_on(bridge); } static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, -- 2.36.0.550.gb090851708-goog

2 1

[PATCH v4] drm/msm/dp: Always clear mask bits to disable interrupts at dp_ctrl_reset_irq_ctrl()
by Kuogee Hsieh 11 May '22

11 May '22

dp_catalog_ctrl_reset() will software reset DP controller. But it will not reset programmable registers to default value. DP driver still have to clear mask bits to interrupt status registers to disable interrupts after software reset of controller. This patch removes the enable flag condition checking to always clear mask bits of interrupt status registers to disable interrupts if enable flag is false. This patch also will fix the potential problem happen at system suspend where dp_ctrl_reset_irq_ctrl() was called to try to disable HPD related irqs but the irq is still unmasked unexpectedly and can come in while system are suspending. This leads to bus hangs if the irq is handled after we power down the DP hardware because we run the irq handler and access a device register assuming that no irq could ever come in if we powered down the device. We don't know when the irq will be handled though, so it's possible the irq is pending from before we disable the irq in the hardware. Changes in v2: -- add more details commit text Changes in v3: -- add synchrons_irq() -- add atomic_t suspended Changes in v4: -- correct Fixes's commit ID Fixes: 989ebe7bc446 ("drm/msm/dp: do not initialize phy until plugin interrupt received") Signed-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 9 +++++++-- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index af7a80c..f3e333e 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1389,8 +1389,13 @@ void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable) dp_catalog_ctrl_reset(ctrl->catalog); - if (enable) - dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); + /* + * all dp controller programmable registers will not + * be reset to default value after DP_SW_RESET + * therefore interrupt mask bits have to be updated + * to enable/disable interrupts + */ + dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); } void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c388323..c34dbfc 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -98,6 +98,8 @@ struct dp_display_private { struct dp_ctrl *ctrl; struct dp_debug *debug; + atomic_t suspended; + struct dp_usbpd_cb usbpd_cb; struct dp_display_mode dp_mode; struct msm_dp dp_display; @@ -187,6 +189,11 @@ static int dp_add_event(struct dp_display_private *dp_priv, u32 event, int pndx; spin_lock_irqsave(&dp_priv->event_lock, flag); + if (atomic_read(&dp_priv->suspended)) { + spin_unlock_irqrestore(&dp_priv->event_lock, flag); + return -EPERM; + } + pndx = dp_priv->event_pndx + 1; pndx %= DP_EVENT_Q_MAX; if (pndx == dp_priv->event_gndx) { @@ -454,6 +461,13 @@ static void dp_display_host_deinit(struct dp_display_private *dp) dp->dp_display.connector_type, dp->core_initialized, dp->phy_initialized); + if (!dp->core_initialized) { + DRM_DEBUG_DP("DP core not initialized\n"); + return; + } + + synchronize_irq(dp->irq); + dp_ctrl_reset_irq_ctrl(dp->ctrl, false); dp_aux_deinit(dp->aux); dp_power_deinit(dp->power); @@ -1362,6 +1376,8 @@ static int dp_pm_resume(struct device *dev) dp->dp_display.connector_type, dp->core_initialized, dp->phy_initialized, dp_display->power_on); + atomic_set(&dp->suspended, 0); + /* start from disconnected state */ dp->hpd_state = ST_DISCONNECTED; @@ -1431,6 +1447,8 @@ static int dp_pm_suspend(struct device *dev) dp->dp_display.connector_type, dp->core_initialized, dp->phy_initialized, dp_display->power_on); + atomic_inc(&dp->suspended); + /* mainlink enabled */ if (dp_power_clk_status(dp->power, DP_CTRL_PM)) dp_ctrl_off_link_stream(dp->ctrl); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

2 2

[PATCH] Revert "FROMGIT: drm/msm/dsi: move DSI host powerup to modeset time"
by Douglas Anderson 11 May '22

11 May '22

This reverts commit c7e4a2a72e696aa6aed2c8b651279f491bb096fe. The patch causes sc7180 Chromebooks that use the parade-ps8640 bridge chip to fail to turn the display back on after it turns off. Let's revert to get these devices back to a working state. It seems like the DSI powerup problem is somewhat common and probably we should land something more general like Dave Stevenson's series [1] that would give more flexibility. [1] https://lore.kernel.org/r/cover.1646406653.git.dave.stevenson@raspberrypi.c… Fixes: c7e4a2a72e69 ("FROMGIT: drm/msm/dsi: move DSI host powerup to modeset time") Signed-off-by: Douglas Anderson <dianders(a)chromium.org> --- drivers/gpu/drm/msm/dsi/dsi_manager.c | 43 ++++++++------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 50b987658b1f..8d51711a3417 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -315,12 +315,13 @@ dsi_mgr_connector_best_encoder(struct drm_connector *connector) return msm_dsi_get_encoder(msm_dsi); } -static void dsi_mgr_bridge_power_on(struct drm_bridge *bridge) +static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge); struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); struct mipi_dsi_host *host = msm_dsi->host; + struct drm_panel *panel = msm_dsi->panel; struct msm_dsi_phy_shared_timings phy_shared_timings[DSI_MAX]; bool is_bonded_dsi = IS_BONDED_DSI(); int ret; @@ -361,34 +362,6 @@ static void dsi_mgr_bridge_power_on(struct drm_bridge *bridge) if (is_bonded_dsi && msm_dsi1) msm_dsi_host_enable_irq(msm_dsi1->host); - return; - -host1_on_fail: - msm_dsi_host_power_off(host); -host_on_fail: - dsi_mgr_phy_disable(id); -phy_en_fail: - return; -} - -static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) -{ - int id = dsi_mgr_bridge_get_id(bridge); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); - struct mipi_dsi_host *host = msm_dsi->host; - struct drm_panel *panel = msm_dsi->panel; - bool is_bonded_dsi = IS_BONDED_DSI(); - int ret; - - DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - - /* Do nothing with the host if it is slave-DSI in case of bonded DSI */ - if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id)) - return; - /* Always call panel functions once, because even for dual panels, * there is only one drm_panel instance. */ @@ -423,7 +396,17 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) if (panel) drm_panel_unprepare(panel); panel_prep_fail: + msm_dsi_host_disable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_disable_irq(msm_dsi1->host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_power_off(msm_dsi1->host); +host1_on_fail: + msm_dsi_host_power_off(host); +host_on_fail: + dsi_mgr_phy_disable(id); +phy_en_fail: return; } @@ -569,8 +552,6 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge, msm_dsi_host_set_display_mode(host, adjusted_mode); if (is_bonded_dsi && other_dsi) msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode); - - dsi_mgr_bridge_power_on(bridge); } static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, -- 2.36.0.550.gb090851708-goog

2 1

← Newer
1
...
48
49
50
51
52
53
54
...
74
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel May 2022