On 12/8/21 13:59, Matthew Auld wrote:
On Wed, 8 Dec 2021 at 12:43, Thomas Hellström (Intel) thomas_os@shipmail.org wrote:
Hi,
On 12/7/21 17:51, Ramalingam C wrote:
From: Stuart Summers stuart.summers@intel.com
Add a new platform flag, has_64k_pages, for platforms supporting base page sizes of 64k.
Signed-off-by: Stuart Summers stuart.summers@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com
drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 85bb8d3107f0..6132163e1cb3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_MSLICES(dev_priv) \ (INTEL_INFO(dev_priv)->has_mslices)
+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
Could we please have some documentation of the exact meaning of this flag. Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?
Something like: "Set if the device requires 64K GTT page sizes or larger for device local memory access. Also implies that we require or at least support the compact PT layout for the ppGTT when using 64K GTT pages."
Sounds great.
Thanks,
Thomas