Normal DP suspend operation contains two steps, display off followed by dp suspend, to complete system wide suspending cycle if display is up at that time. In this case, DP phy will be powered off at display off. However there is an exception case that depending on the timing of dongle plug in during system wide suspending, sometimes display off procedure may be skipped and dp suspend was called directly. In this case, dp phy is stay at powered on (phy->power_count = 1) so that at next resume dp driver crash at main link clock enable due to phy is not physically powered on. This patch will call dp_ctrl_off_link_stream() to tear down main link and power off phy at dp_pm_suspend() if main link had been brought up.
Changes in V2: -- stashed changes into dp_ctrl.c -- add is_phy_on to monitor phy state
Changes in V3: -- delete is_phy_on -- call dp_ctrl_off_link_stream() from dp_pm_suspend()
Changes in V4: -- delete changes made at dp_power.c -- move main link status checking to dp_pm_suspend
Changes in V5: -- correct commit id at Fixes tag
Fixes: 8dbde399044b ("drm/msm/dp: handle irq_hpd with sink_count = 0 correctly) Signed-off-by: Kuogee Hsieh khsieh@codeaurora.org Tested-by: Stephen Boyd swboyd@chromium.org Reviewed-by: Stephen Boyd swboyd@chromium.org --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 ++++++---- drivers/gpu/drm/msm/dp/dp_display.c | 7 ++++++- 2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index dbd8943..caf71fa 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1827,10 +1827,12 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
- ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); - if (ret) { - DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); - return ret; + if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) { + ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); + if (ret) { + DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); + return ret; + } }
ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index cdec0a3..9c59def 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1327,8 +1327,13 @@ static int dp_pm_suspend(struct device *dev)
mutex_lock(&dp->event_mutex);
- if (dp->core_initialized == true) + if (dp->core_initialized == true) { + /* mainlink enabled */ + if (dp_power_clk_status(dp->power, DP_CTRL_PM)) + dp_ctrl_off_link_stream(dp->ctrl); + dp_display_host_deinit(dp); + }
dp->hpd_state = ST_SUSPENDED;