Hi, Nancy:
On Wed, 2021-08-18 at 17:18 +0800, Nancy.Lin wrote:
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of the ovl_adaptor component.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com
[snip]
+#define MDP_RDMA_EN 0x000 +#define FLD_ROT_ENABLE REG_FLD(1, 0)
I would like the bitwise definition has one more indent than the byte definition.
+#define MDP_RDMA_RESET 0x008
+#define MDP_RDMA_CON 0x020 +#define FLD_OUTPUT_10B REG_FLD(1, 5) +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+#define MDP_RDMA_GMCIF_CON 0x028 +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18) +#define FLD_PRE_ULTRA_EN REG_FLD(2, 16) +#define FLD_ULTRA_EN REG_FLD(2, 12) +#define FLD_RD_REQ_TYPE REG_FLD(4, 4) +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7 +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3) +#define FLD_COMMAND_DIV REG_FLD(1, 0)
+#define MDP_RDMA_SRC_CON 0x030 +#define FLD_OUTPUT_ARGB REG_FLD(1, 25) +#define FLD_BIT_NUMBER REG_FLD(2, 18) +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17) +#define FLD_SWAP REG_FLD(1, 14) +#define FLD_SRC_FORMAT REG_FLD(4, 0)
+#define MDP_RDMA_COMP_CON 0x038 +#define FLD_AFBC_EN REG_FLD(1, 22) +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21) +#define FLD_UFBDC_EN REG_FLD(1, 12)
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068 +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+#define MDP_RDMA_MF_SRC_SIZE 0x070 +#define FLD_MF_SRC_H REG_FLD(15, 16) +#define FLD_MF_SRC_W REG_FLD(15, 0)
+#define MDP_RDMA_MF_CLIP_SIZE 0x078 +#define FLD_MF_CLIP_H REG_FLD(15, 16) +#define FLD_MF_CLIP_W REG_FLD(15, 0)
+#define MDP_RDMA_TARGET_LINE 0x0a0 +#define FLD_LINE_THRESHOLD REG_FLD(15, 17) +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+#define MDP_RDMA_SRC_OFFSET_0 0x118 +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+#define MDP_RDMA_TRANSFORM_0 0x200 +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23) +#define FLD_TRANS_EN REG_FLD(1, 16)
+#define MDP_RDMA_UTRA_H_CON_0 0x248 +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+#define MDP_RDMA_UTRA_L_CON_0 0x250 +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+#define MDP_RDMA_SRC_BASE_0 0xf00 +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+#define RDMA_INPUT_SWAP BIT(14) +#define RDMA_INPUT_10BIT BIT(18)
[snip]
+static void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
struct cmdq_client_reg *cmdq_base)+{
- unsigned int pre_ultra_h = 156;
- unsigned int pre_ultra_l = 104;
Give the reason why this value. You could refer to merge [1].
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210819022327.130...
- unsigned int reg_mask;
- unsigned int reg_val;
- unsigned int reg;
- reg = MDP_RDMA_GMCIF_CON;
- reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, VAL_RD_REQ_TYPE_BURST_8_ACCESS) |
REG_FLD_VAL(FLD_COMMAND_DIV, 1) |REG_FLD_VAL(FLD_EXT_PREULTRA_EN, 1) |REG_FLD_VAL(FLD_ULTRA_EN, 0) |REG_FLD_VAL(FLD_PRE_ULTRA_EN, 1) |REG_FLD_VAL(FLD_EXT_ULTRA_EN, 1);- reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
REG_FLD_MASK(FLD_COMMAND_DIV) |REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |REG_FLD_MASK(FLD_ULTRA_EN) |REG_FLD_MASK(FLD_PRE_ULTRA_EN) |REG_FLD_MASK(FLD_EXT_ULTRA_EN);- mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
#define FLD_COMMAND_DIV BIT(0) #define FLD_EXT_PREULTRA_EN BIT(3) #define FLD_RD_REQ_TYPE GENMASK(7, 4) #define FLD_ULTRA_EN GENMASK(13, 12) #define FLD_PRE_ULTRA_EN GENMASK(17, 16) #define FLD_PRE_ULTRA_EN_ENABLE 1 #define FLD_EXT_ULTRA_EN BIT(18)
mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | FLD_PRE_ULTRA_EN_ENABLE << 16 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 | FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, cmdq_base, base, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN | FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE | FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
- reg = MDP_RDMA_UTRA_H_CON_0;
- reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, pre_ultra_h);
- reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
- mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
- reg = MDP_RDMA_UTRA_L_CON_0;
- reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, pre_ultra_l);
- reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
- mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
[snip]
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h new file mode 100644 index 000000000000..50fa6e18d244 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/*
- Copyright (c) 2021 MediaTek Inc.
- */
+#ifndef __MTK_MDP_RDMA_H__ +#define __MTK_MDP_RDMA_H__
+enum mtk_mdp_rdma_profile {
- RDMA_CSC_RGB_TO_JPEG = 0,
- RDMA_CSC_RGB_TO_FULL709 = 1,
- RDMA_CSC_RGB_TO_BT601 = 2,
- RDMA_CSC_RGB_TO_BT709 = 3,
- RDMA_CSC_JPEG_TO_RGB = 4,
- RDMA_CSC_FULL709_TO_RGB = 5,
- RDMA_CSC_BT601_TO_RGB = 6,
- RDMA_CSC_BT709_TO_RGB = 7,
- RDMA_CSC_JPEG_TO_BT601 = 8,
- RDMA_CSC_JPEG_TO_BT709 = 9,
- RDMA_CSC_BT601_TO_JPEG = 10,
- RDMA_CSC_BT709_TO_BT601 = 11,
- RDMA_CSC_BT601_TO_BT709 = 12
+};
+struct mtk_mdp_rdma_cfg {
- enum mtk_mdp_rdma_profile profile;
- unsigned int source_width;
source_width is useless, so remove.
Regards, CK.
- unsigned int pitch;
- unsigned int addr0;
- unsigned int width;
- unsigned int height;
- unsigned int x_left;
- unsigned int y_top;
- bool csc_enable;
- int fmt;
+};
+#endif // __MTK_MDP_RDMA_H__