Window properties are programmed through a shared aperture and have to happen atomically. Also we do the read-update-write dance on some of the shared regs. To make sure that different functions don't stumble over each other protect the register access with a mutex.
Signed-off-by: Lucas Stach dev@lynxeye.de --- We could probably make this a bit more fine grained, but this would add some complexity and I don't really see a win there for now. --- drivers/gpu/drm/tegra/dc.c | 13 +++++++++++++ drivers/gpu/drm/tegra/drm.h | 1 + 2 Dateien geändert, 14 Zeilen hinzugefügt(+)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 54683e4..b256574 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -171,6 +171,8 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc, return err; }
+ mutex_lock(&dc->regs_mutex); + /* program display mode */ tegra_dc_set_timings(dc, mode);
@@ -269,6 +271,8 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc, tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY); tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN);
+ mutex_unlock(&dc->regs_mutex); + return 0; }
@@ -287,6 +291,8 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc) else syncpt = SYNCPT_VBLANK0;
+ mutex_lock(&dc->regs_mutex); + /* initialize display controller */ tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); @@ -320,6 +326,8 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc)
value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); + + mutex_unlock(&dc->regs_mutex); }
static void tegra_crtc_commit(struct drm_crtc *crtc) @@ -330,6 +338,8 @@ static void tegra_crtc_commit(struct drm_crtc *crtc)
update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+ mutex_lock(&dc->regs_mutex); + tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE); @@ -341,6 +351,8 @@ static void tegra_crtc_commit(struct drm_crtc *crtc) tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL); + + mutex_unlock(&dc->regs_mutex); }
static void tegra_crtc_load_lut(struct drm_crtc *crtc) @@ -747,6 +759,7 @@ static int tegra_dc_probe(struct platform_device *pdev) return -ENOMEM;
INIT_LIST_HEAD(&dc->list); + mutex_init(&dc->regs_mutex); dc->dev = &pdev->dev;
dc->clk = devm_clk_get(&pdev->dev, NULL); diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 3a843a7..eae1f56 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -84,6 +84,7 @@ struct tegra_dc {
struct clk *clk;
+ struct mutex regs_mutex; void __iomem *regs; int irq;